hw/arm/aspeed_soc.c

   1 /*
   2  * ASPEED SoC family
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  * Jeremy Kerr <jk@ozlabs.org>
   6  *
   7  * Copyright 2016 IBM Corp.
   8  *
   9  * This code is licensed under the GPL version 2 or later.  See
  10  * the COPYING file in the top-level directory.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qapi/error.h"
  15 #include "qemu-common.h"
  16 #include "cpu.h"
  17 #include "exec/address-spaces.h"
  18 #include "hw/arm/aspeed_soc.h"
  19 #include "hw/char/serial.h"
  20 #include "qemu/log.h"
  21 #include "hw/i2c/aspeed_i2c.h"
  22 #include "net/net.h"
  23
  24 #define ASPEED_SOC_UART_5_BASE      0x00184000
  25 #define ASPEED_SOC_IOMEM_SIZE       0x00200000
  26 #define ASPEED_SOC_IOMEM_BASE       0x1E600000
  27 #define ASPEED_SOC_FMC_BASE         0x1E620000
  28 #define ASPEED_SOC_SPI_BASE         0x1E630000
  29 #define ASPEED_SOC_SPI2_BASE        0x1E631000
  30 #define ASPEED_SOC_VIC_BASE         0x1E6C0000
  31 #define ASPEED_SOC_SDMC_BASE        0x1E6E0000
  32 #define ASPEED_SOC_SCU_BASE         0x1E6E2000
  33 #define ASPEED_SOC_SRAM_BASE        0x1E720000
  34 #define ASPEED_SOC_TIMER_BASE       0x1E782000
  35 #define ASPEED_SOC_WDT_BASE         0x1E785000
  36 #define ASPEED_SOC_I2C_BASE         0x1E78A000
  37 #define ASPEED_SOC_ETH1_BASE        0x1E660000
  38 #define ASPEED_SOC_ETH2_BASE        0x1E680000
  39
  40 static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
  41 static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
  42
  43 #define AST2400_SDRAM_BASE       0x40000000
  44 #define AST2500_SDRAM_BASE       0x80000000
  45
  46 static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE };
  47 static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
  48
  49 static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE,
  50                                                        ASPEED_SOC_SPI2_BASE};
  51 static const char *aspeed_soc_ast2500_typenames[] = {
  52     "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
  53
  54 static const AspeedSoCInfo aspeed_socs[] = {
  55     {
  56         .name         = "ast2400-a0",
  57         .cpu_model    = "arm926",
  58         .silicon_rev  = AST2400_A0_SILICON_REV,
  59         .sdram_base   = AST2400_SDRAM_BASE,
  60         .sram_size    = 0x8000,
  61         .spis_num     = 1,
  62         .spi_bases    = aspeed_soc_ast2400_spi_bases,
  63         .fmc_typename = "aspeed.smc.fmc",
  64         .spi_typename = aspeed_soc_ast2400_typenames,
  65     }, {
  66         .name         = "ast2400-a1",
  67         .cpu_model    = "arm926",
  68         .silicon_rev  = AST2400_A1_SILICON_REV,
  69         .sdram_base   = AST2400_SDRAM_BASE,
  70         .sram_size    = 0x8000,
  71         .spis_num     = 1,
  72         .spi_bases    = aspeed_soc_ast2400_spi_bases,
  73         .fmc_typename = "aspeed.smc.fmc",
  74         .spi_typename = aspeed_soc_ast2400_typenames,
  75     }, {
  76         .name         = "ast2400",
  77         .cpu_model    = "arm926",
  78         .silicon_rev  = AST2400_A0_SILICON_REV,
  79         .sdram_base   = AST2400_SDRAM_BASE,
  80         .sram_size    = 0x8000,
  81         .spis_num     = 1,
  82         .spi_bases    = aspeed_soc_ast2400_spi_bases,
  83         .fmc_typename = "aspeed.smc.fmc",
  84         .spi_typename = aspeed_soc_ast2400_typenames,
  85     }, {
  86         .name         = "ast2500-a1",
  87         .cpu_model    = "arm1176",
  88         .silicon_rev  = AST2500_A1_SILICON_REV,
  89         .sdram_base   = AST2500_SDRAM_BASE,
  90         .sram_size    = 0x9000,
  91         .spis_num     = 2,
  92         .spi_bases    = aspeed_soc_ast2500_spi_bases,
  93         .fmc_typename = "aspeed.smc.ast2500-fmc",
  94         .spi_typename = aspeed_soc_ast2500_typenames,
  95     },
  96 };
  97
  98 /*
  99  * IO handlers: simply catch any reads/writes to IO addresses that aren't
 100  * handled by a device mapping.
 101  */
 102
 103 static uint64_t aspeed_soc_io_read(void *p, hwaddr offset, unsigned size)
 104 {
 105     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
 106                   __func__, offset, size);
 107     return 0;
 108 }
 109
 110 static void aspeed_soc_io_write(void *opaque, hwaddr offset, uint64_t value,
 111                 unsigned size)
 112 {
 113     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
 114                   __func__, offset, value, size);
 115 }
 116
 117 static const MemoryRegionOps aspeed_soc_io_ops = {
 118     .read = aspeed_soc_io_read,
 119     .write = aspeed_soc_io_write,
 120     .endianness = DEVICE_LITTLE_ENDIAN,
 121 };
 122
 123 static void aspeed_soc_init(Object *obj)
 124 {
 125     AspeedSoCState *s = ASPEED_SOC(obj);
 126     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 127     char *cpu_typename;
 128     int i;
 129
 130     cpu_typename = g_strdup_printf("%s-" TYPE_ARM_CPU, sc->info->cpu_model);
 131     object_initialize(&s->cpu, sizeof(s->cpu), cpu_typename);
 132     object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
 133     g_free(cpu_typename);
 134
 135     object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
 136     object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
 137     qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default());
 138
 139     object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
 140     object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);
 141     qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());
 142
 143     object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
 144     object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL);
 145     qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default());
 146
 147     object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU);
 148     object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL);
 149     qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
 150     qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
 151                          sc->info->silicon_rev);
 152     object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
 153                               "hw-strap1", &error_abort);
 154     object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
 155                               "hw-strap2", &error_abort);
 156
 157     object_initialize(&s->fmc, sizeof(s->fmc), sc->info->fmc_typename);
 158     object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL);
 159     qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default());
 160     object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
 161                               &error_abort);
 162
 163     for (i = 0; i < sc->info->spis_num; i++) {
 164         object_initialize(&s->spi[i], sizeof(s->spi[i]),
 165                           sc->info->spi_typename[i]);
 166         object_property_add_child(obj, "spi[*]", OBJECT(&s->spi[i]), NULL);
 167         qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
 168     }
 169
 170     object_initialize(&s->sdmc, sizeof(s->sdmc), TYPE_ASPEED_SDMC);
 171     object_property_add_child(obj, "sdmc", OBJECT(&s->sdmc), NULL);
 172     qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default());
 173     qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
 174                          sc->info->silicon_rev);
 175     object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
 176                               "ram-size", &error_abort);
 177
 178     object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ASPEED_WDT);
 179     object_property_add_child(obj, "wdt", OBJECT(&s->wdt), NULL);
 180     qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default());
 181
 182     object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC100);
 183     object_property_add_child(obj, "ftgmac100", OBJECT(&s->ftgmac100), NULL);
 184     qdev_set_parent_bus(DEVICE(&s->ftgmac100), sysbus_get_default());
 185 }
 186
 187 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
 188 {
 189     int i;
 190     AspeedSoCState *s = ASPEED_SOC(dev);
 191     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 192     Error *err = NULL, *local_err = NULL;
 193
 194     /* IO space */
 195     memory_region_init_io(&s->iomem, NULL, &aspeed_soc_io_ops, NULL,
 196             "aspeed_soc.io", ASPEED_SOC_IOMEM_SIZE);
 197     memory_region_add_subregion_overlap(get_system_memory(),
 198                                         ASPEED_SOC_IOMEM_BASE, &s->iomem, -1);
 199
 200     /* CPU */
 201     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
 202     if (err) {
 203         error_propagate(errp, err);
 204         return;
 205     }
 206
 207     /* SRAM */
 208     memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
 209                            sc->info->sram_size, &err);
 210     if (err) {
 211         error_propagate(errp, err);
 212         return;
 213     }
 214     vmstate_register_ram_global(&s->sram);
 215     memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE,
 216                                 &s->sram);
 217
 218     /* VIC */
 219     object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
 220     if (err) {
 221         error_propagate(errp, err);
 222         return;
 223     }
 224     sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE);
 225     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
 226                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
 227     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
 228                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
 229
 230     /* Timer */
 231     object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
 232     if (err) {
 233         error_propagate(errp, err);
 234         return;
 235     }
 236     sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);
 237     for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
 238         qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
 239         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
 240     }
 241
 242     /* SCU */
 243     object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
 244     if (err) {
 245         error_propagate(errp, err);
 246         return;
 247     }
 248     sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);
 249
 250     /* UART - attach an 8250 to the IO space as our UART5 */
 251     if (serial_hds[0]) {
 252         qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
 253         serial_mm_init(&s->iomem, ASPEED_SOC_UART_5_BASE, 2,
 254                        uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);
 255     }
 256
 257     /* I2C */
 258     object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
 259     if (err) {
 260         error_propagate(errp, err);
 261         return;
 262     }
 263     sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);
 264     sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
 265                        qdev_get_gpio_in(DEVICE(&s->vic), 12));
 266
 267     /* FMC, The number of CS is set at the board level */
 268     object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
 269     if (err) {
 270         error_propagate(errp, err);
 271         return;
 272     }
 273     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE);
 274     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
 275                     s->fmc.ctrl->flash_window_base);
 276     sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
 277                        qdev_get_gpio_in(DEVICE(&s->vic), 19));
 278
 279     /* SPI */
 280     for (i = 0; i < sc->info->spis_num; i++) {
 281         object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
 282         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
 283                                  &local_err);
 284         error_propagate(&err, local_err);
 285         if (err) {
 286             error_propagate(errp, err);
 287             return;
 288         }
 289         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, sc->info->spi_bases[i]);
 290         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
 291                         s->spi[i].ctrl->flash_window_base);
 292     }
 293
 294     /* SDMC - SDRAM Memory Controller */
 295     object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
 296     if (err) {
 297         error_propagate(errp, err);
 298         return;
 299     }
 300     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
 301
 302     /* Watch dog */
 303     object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);
 304     if (err) {
 305         error_propagate(errp, err);
 306         return;
 307     }
 308     sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, ASPEED_SOC_WDT_BASE);
 309
 310     /* Net */
 311     qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]);
 312     object_property_set_bool(OBJECT(&s->ftgmac100), true, "aspeed", &err);
 313     object_property_set_bool(OBJECT(&s->ftgmac100), true, "realized",
 314                              &local_err);
 315     error_propagate(&err, local_err);
 316     if (err) {
 317         error_propagate(errp, err);
 318         return;
 319     }
 320     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, ASPEED_SOC_ETH1_BASE);
 321     sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0,
 322                        qdev_get_gpio_in(DEVICE(&s->vic), 2));
 323 }
 324
 325 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 326 {
 327     DeviceClass *dc = DEVICE_CLASS(oc);
 328     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
 329
 330     sc->info = (AspeedSoCInfo *) data;
 331     dc->realize = aspeed_soc_realize;
 332 }
 333
 334 static const TypeInfo aspeed_soc_type_info = {
 335     .name           = TYPE_ASPEED_SOC,
 336     .parent         = TYPE_DEVICE,
 337     .instance_init  = aspeed_soc_init,
 338     .instance_size  = sizeof(AspeedSoCState),
 339     .class_size     = sizeof(AspeedSoCClass),
 340     .abstract       = true,
 341 };
 342
 343 static void aspeed_soc_register_types(void)
 344 {
 345     int i;
 346
 347     type_register_static(&aspeed_soc_type_info);
 348     for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {
 349         TypeInfo ti = {
 350             .name       = aspeed_socs[i].name,
 351             .parent     = TYPE_ASPEED_SOC,
 352             .class_init = aspeed_soc_class_init,
 353             .class_data = (void *) &aspeed_socs[i],
 354         };
 355         type_register(&ti);
 356     }
 357 }
 358
 359 type_init(aspeed_soc_register_types)