4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
10 #include "qemu/units.h"
11 #include "target/arm/idau.h"
14 #include "internals.h"
15 #include "exec/gdbstub.h"
16 #include "exec/helper-proto.h"
17 #include "qemu/host-utils.h"
18 #include "qemu/main-loop.h"
19 #include "qemu/bitops.h"
20 #include "qemu/crc32c.h"
21 #include "qemu/qemu-print.h"
22 #include "exec/exec-all.h"
23 #include <zlib.h> /* For crc32 */
25 #include "hw/semihosting/semihost.h"
26 #include "sysemu/cpus.h"
27 #include "sysemu/cpu-timers.h"
28 #include "sysemu/kvm.h"
29 #include "sysemu/tcg.h"
30 #include "qemu/range.h"
31 #include "qapi/qapi-commands-machine-target.h"
32 #include "qapi/error.h"
33 #include "qemu/guest-random.h"
36 #include "exec/cpu_ldst.h"
37 #include "hw/semihosting/common-semi.h"
40 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
42 #ifndef CONFIG_USER_ONLY
44 static bool get_phys_addr_lpae(CPUARMState
*env
, uint64_t address
,
45 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
47 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
48 target_ulong
*page_size_ptr
,
49 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
50 __attribute__((nonnull
));
53 static void switch_mode(CPUARMState
*env
, int mode
);
54 static int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
);
56 static int vfp_gdb_get_reg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
58 ARMCPU
*cpu
= env_archcpu(env
);
59 int nregs
= cpu_isar_feature(aa32_simd_r32
, cpu
) ? 32 : 16;
61 /* VFP data registers are always little-endian. */
63 return gdb_get_reg64(buf
, *aa32_vfp_dreg(env
, reg
));
65 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
66 /* Aliases for Q regs. */
69 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
70 return gdb_get_reg128(buf
, q
[0], q
[1]);
73 switch (reg
- nregs
) {
74 case 0: return gdb_get_reg32(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); break;
75 case 1: return gdb_get_reg32(buf
, vfp_get_fpscr(env
)); break;
76 case 2: return gdb_get_reg32(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); break;
81 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
83 ARMCPU
*cpu
= env_archcpu(env
);
84 int nregs
= cpu_isar_feature(aa32_simd_r32
, cpu
) ? 32 : 16;
87 *aa32_vfp_dreg(env
, reg
) = ldq_le_p(buf
);
90 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
93 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
95 q
[1] = ldq_le_p(buf
+ 8);
99 switch (reg
- nregs
) {
100 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
101 case 1: vfp_set_fpscr(env
, ldl_p(buf
)); return 4;
102 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
107 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
112 /* 128 bit FP register - quads are in LE order */
113 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
114 return gdb_get_reg128(buf
, q
[1], q
[0]);
118 return gdb_get_reg32(buf
, vfp_get_fpsr(env
));
121 return gdb_get_reg32(buf
,vfp_get_fpcr(env
));
127 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
131 /* 128 bit FP register */
133 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
134 q
[0] = ldq_le_p(buf
);
135 q
[1] = ldq_le_p(buf
+ 8);
140 vfp_set_fpsr(env
, ldl_p(buf
));
144 vfp_set_fpcr(env
, ldl_p(buf
));
151 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
153 assert(ri
->fieldoffset
);
154 if (cpreg_field_is_64bit(ri
)) {
155 return CPREG_FIELD64(env
, ri
);
157 return CPREG_FIELD32(env
, ri
);
161 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
164 assert(ri
->fieldoffset
);
165 if (cpreg_field_is_64bit(ri
)) {
166 CPREG_FIELD64(env
, ri
) = value
;
168 CPREG_FIELD32(env
, ri
) = value
;
172 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
174 return (char *)env
+ ri
->fieldoffset
;
177 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
179 /* Raw read of a coprocessor register (as needed for migration, etc). */
180 if (ri
->type
& ARM_CP_CONST
) {
181 return ri
->resetvalue
;
182 } else if (ri
->raw_readfn
) {
183 return ri
->raw_readfn(env
, ri
);
184 } else if (ri
->readfn
) {
185 return ri
->readfn(env
, ri
);
187 return raw_read(env
, ri
);
191 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
194 /* Raw write of a coprocessor register (as needed for migration, etc).
195 * Note that constant registers are treated as write-ignored; the
196 * caller should check for success by whether a readback gives the
199 if (ri
->type
& ARM_CP_CONST
) {
201 } else if (ri
->raw_writefn
) {
202 ri
->raw_writefn(env
, ri
, v
);
203 } else if (ri
->writefn
) {
204 ri
->writefn(env
, ri
, v
);
206 raw_write(env
, ri
, v
);
211 * arm_get/set_gdb_*: get/set a gdb register
212 * @env: the CPU state
213 * @buf: a buffer to copy to/from
214 * @reg: register number (offset from start of group)
216 * We return the number of bytes copied
219 static int arm_gdb_get_sysreg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
221 ARMCPU
*cpu
= env_archcpu(env
);
222 const ARMCPRegInfo
*ri
;
225 key
= cpu
->dyn_sysreg_xml
.data
.cpregs
.keys
[reg
];
226 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
228 if (cpreg_field_is_64bit(ri
)) {
229 return gdb_get_reg64(buf
, (uint64_t)read_raw_cp_reg(env
, ri
));
231 return gdb_get_reg32(buf
, (uint32_t)read_raw_cp_reg(env
, ri
));
237 static int arm_gdb_set_sysreg(CPUARMState
*env
, uint8_t *buf
, int reg
)
242 #ifdef TARGET_AARCH64
243 static int arm_gdb_get_svereg(CPUARMState
*env
, GByteArray
*buf
, int reg
)
245 ARMCPU
*cpu
= env_archcpu(env
);
248 /* The first 32 registers are the zregs */
252 for (vq
= 0; vq
< cpu
->sve_max_vq
; vq
++) {
253 len
+= gdb_get_reg128(buf
,
254 env
->vfp
.zregs
[reg
].d
[vq
* 2 + 1],
255 env
->vfp
.zregs
[reg
].d
[vq
* 2]);
260 return gdb_get_reg32(buf
, vfp_get_fpsr(env
));
262 return gdb_get_reg32(buf
, vfp_get_fpcr(env
));
263 /* then 16 predicates and the ffr */
268 for (vq
= 0; vq
< cpu
->sve_max_vq
; vq
= vq
+ 4) {
269 len
+= gdb_get_reg64(buf
, env
->vfp
.pregs
[preg
].p
[vq
/ 4]);
276 * We report in Vector Granules (VG) which is 64bit in a Z reg
277 * while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
279 int vq
= sve_zcr_len_for_el(env
, arm_current_el(env
)) + 1;
280 return gdb_get_reg64(buf
, vq
* 2);
283 /* gdbstub asked for something out our range */
284 qemu_log_mask(LOG_UNIMP
, "%s: out of range register %d", __func__
, reg
);
291 static int arm_gdb_set_svereg(CPUARMState
*env
, uint8_t *buf
, int reg
)
293 ARMCPU
*cpu
= env_archcpu(env
);
295 /* The first 32 registers are the zregs */
297 /* The first 32 registers are the zregs */
301 uint64_t *p
= (uint64_t *) buf
;
302 for (vq
= 0; vq
< cpu
->sve_max_vq
; vq
++) {
303 env
->vfp
.zregs
[reg
].d
[vq
* 2 + 1] = *p
++;
304 env
->vfp
.zregs
[reg
].d
[vq
* 2] = *p
++;
310 vfp_set_fpsr(env
, *(uint32_t *)buf
);
313 vfp_set_fpcr(env
, *(uint32_t *)buf
);
319 uint64_t *p
= (uint64_t *) buf
;
320 for (vq
= 0; vq
< cpu
->sve_max_vq
; vq
= vq
+ 4) {
321 env
->vfp
.pregs
[preg
].p
[vq
/ 4] = *p
++;
327 /* cannot set vg via gdbstub */
330 /* gdbstub asked for something out our range */
336 #endif /* TARGET_AARCH64 */
338 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
340 /* Return true if the regdef would cause an assertion if you called
341 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
342 * program bug for it not to have the NO_RAW flag).
343 * NB that returning false here doesn't necessarily mean that calling
344 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
345 * read/write access functions which are safe for raw use" from "has
346 * read/write access functions which have side effects but has forgotten
347 * to provide raw access functions".
348 * The tests here line up with the conditions in read/write_raw_cp_reg()
349 * and assertions in raw_read()/raw_write().
351 if ((ri
->type
& ARM_CP_CONST
) ||
353 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
359 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
361 /* Write the coprocessor state from cpu->env to the (index,value) list. */
365 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
366 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
367 const ARMCPRegInfo
*ri
;
370 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
375 if (ri
->type
& ARM_CP_NO_RAW
) {
379 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
382 * Only sync if the previous list->cpustate sync succeeded.
383 * Rather than tracking the success/failure state for every
384 * item in the list, we just recheck "does the raw write we must
385 * have made in write_list_to_cpustate() read back OK" here.
387 uint64_t oldval
= cpu
->cpreg_values
[i
];
389 if (oldval
== newval
) {
393 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
394 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
398 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
400 cpu
->cpreg_values
[i
] = newval
;
405 bool write_list_to_cpustate(ARMCPU
*cpu
)
410 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
411 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
412 uint64_t v
= cpu
->cpreg_values
[i
];
413 const ARMCPRegInfo
*ri
;
415 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
420 if (ri
->type
& ARM_CP_NO_RAW
) {
423 /* Write value and confirm it reads back as written
424 * (to catch read-only registers and partially read-only
425 * registers where the incoming migration value doesn't match)
427 write_raw_cp_reg(&cpu
->env
, ri
, v
);
428 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
435 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
437 ARMCPU
*cpu
= opaque
;
439 const ARMCPRegInfo
*ri
;
441 regidx
= *(uint32_t *)key
;
442 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
444 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
445 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
446 /* The value array need not be initialized at this point */
447 cpu
->cpreg_array_len
++;
451 static void count_cpreg(gpointer key
, gpointer opaque
)
453 ARMCPU
*cpu
= opaque
;
455 const ARMCPRegInfo
*ri
;
457 regidx
= *(uint32_t *)key
;
458 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
460 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
461 cpu
->cpreg_array_len
++;
465 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
467 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
468 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
479 void init_cpreg_list(ARMCPU
*cpu
)
481 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
482 * Note that we require cpreg_tuples[] to be sorted by key ID.
487 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
488 keys
= g_list_sort(keys
, cpreg_key_compare
);
490 cpu
->cpreg_array_len
= 0;
492 g_list_foreach(keys
, count_cpreg
, cpu
);
494 arraylen
= cpu
->cpreg_array_len
;
495 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
496 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
497 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
498 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
499 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
500 cpu
->cpreg_array_len
= 0;
502 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
504 assert(cpu
->cpreg_array_len
== arraylen
);
510 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
512 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
513 const ARMCPRegInfo
*ri
,
516 if (!is_a64(env
) && arm_current_el(env
) == 3 &&
517 arm_is_secure_below_el3(env
)) {
518 return CP_ACCESS_TRAP_UNCATEGORIZED
;
523 /* Some secure-only AArch32 registers trap to EL3 if used from
524 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
525 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
526 * We assume that the .access field is set to PL1_RW.
528 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
529 const ARMCPRegInfo
*ri
,
532 if (arm_current_el(env
) == 3) {
535 if (arm_is_secure_below_el3(env
)) {
536 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
537 return CP_ACCESS_TRAP_EL2
;
539 return CP_ACCESS_TRAP_EL3
;
541 /* This will be EL1 NS and EL2 NS, which just UNDEF */
542 return CP_ACCESS_TRAP_UNCATEGORIZED
;
545 static uint64_t arm_mdcr_el2_eff(CPUARMState
*env
)
547 return arm_is_el2_enabled(env
) ? env
->cp15
.mdcr_el2
: 0;
550 /* Check for traps to "powerdown debug" registers, which are controlled
553 static CPAccessResult
access_tdosa(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
556 int el
= arm_current_el(env
);
557 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
558 bool mdcr_el2_tdosa
= (mdcr_el2
& MDCR_TDOSA
) || (mdcr_el2
& MDCR_TDE
) ||
559 (arm_hcr_el2_eff(env
) & HCR_TGE
);
561 if (el
< 2 && mdcr_el2_tdosa
) {
562 return CP_ACCESS_TRAP_EL2
;
564 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDOSA
)) {
565 return CP_ACCESS_TRAP_EL3
;
570 /* Check for traps to "debug ROM" registers, which are controlled
571 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
573 static CPAccessResult
access_tdra(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
576 int el
= arm_current_el(env
);
577 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
578 bool mdcr_el2_tdra
= (mdcr_el2
& MDCR_TDRA
) || (mdcr_el2
& MDCR_TDE
) ||
579 (arm_hcr_el2_eff(env
) & HCR_TGE
);
581 if (el
< 2 && mdcr_el2_tdra
) {
582 return CP_ACCESS_TRAP_EL2
;
584 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
585 return CP_ACCESS_TRAP_EL3
;
590 /* Check for traps to general debug registers, which are controlled
591 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
593 static CPAccessResult
access_tda(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
596 int el
= arm_current_el(env
);
597 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
598 bool mdcr_el2_tda
= (mdcr_el2
& MDCR_TDA
) || (mdcr_el2
& MDCR_TDE
) ||
599 (arm_hcr_el2_eff(env
) & HCR_TGE
);
601 if (el
< 2 && mdcr_el2_tda
) {
602 return CP_ACCESS_TRAP_EL2
;
604 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
605 return CP_ACCESS_TRAP_EL3
;
610 /* Check for traps to performance monitor registers, which are controlled
611 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
613 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
616 int el
= arm_current_el(env
);
617 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
619 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
620 return CP_ACCESS_TRAP_EL2
;
622 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
623 return CP_ACCESS_TRAP_EL3
;
628 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
629 static CPAccessResult
access_tvm_trvm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
632 if (arm_current_el(env
) == 1) {
633 uint64_t trap
= isread
? HCR_TRVM
: HCR_TVM
;
634 if (arm_hcr_el2_eff(env
) & trap
) {
635 return CP_ACCESS_TRAP_EL2
;
641 /* Check for traps from EL1 due to HCR_EL2.TSW. */
642 static CPAccessResult
access_tsw(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
645 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TSW
)) {
646 return CP_ACCESS_TRAP_EL2
;
651 /* Check for traps from EL1 due to HCR_EL2.TACR. */
652 static CPAccessResult
access_tacr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
655 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TACR
)) {
656 return CP_ACCESS_TRAP_EL2
;
661 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
662 static CPAccessResult
access_ttlb(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
665 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TTLB
)) {
666 return CP_ACCESS_TRAP_EL2
;
671 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
673 ARMCPU
*cpu
= env_archcpu(env
);
675 raw_write(env
, ri
, value
);
676 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
679 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
681 ARMCPU
*cpu
= env_archcpu(env
);
683 if (raw_read(env
, ri
) != value
) {
684 /* Unlike real hardware the qemu TLB uses virtual addresses,
685 * not modified virtual addresses, so this causes a TLB flush.
688 raw_write(env
, ri
, value
);
692 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
695 ARMCPU
*cpu
= env_archcpu(env
);
697 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
698 && !extended_addresses_enabled(env
)) {
699 /* For VMSA (when not using the LPAE long descriptor page table
700 * format) this register includes the ASID, so do a TLB flush.
701 * For PMSA it is purely a process ID and no action is needed.
705 raw_write(env
, ri
, value
);
708 /* IS variants of TLB operations must affect all cores */
709 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
712 CPUState
*cs
= env_cpu(env
);
714 tlb_flush_all_cpus_synced(cs
);
717 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
720 CPUState
*cs
= env_cpu(env
);
722 tlb_flush_all_cpus_synced(cs
);
725 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
728 CPUState
*cs
= env_cpu(env
);
730 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
733 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
736 CPUState
*cs
= env_cpu(env
);
738 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
742 * Non-IS variants of TLB operations are upgraded to
743 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
744 * force broadcast of these operations.
746 static bool tlb_force_broadcast(CPUARMState
*env
)
748 return arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_FB
);
751 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
754 /* Invalidate all (TLBIALL) */
755 CPUState
*cs
= env_cpu(env
);
757 if (tlb_force_broadcast(env
)) {
758 tlb_flush_all_cpus_synced(cs
);
764 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
767 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
768 CPUState
*cs
= env_cpu(env
);
770 value
&= TARGET_PAGE_MASK
;
771 if (tlb_force_broadcast(env
)) {
772 tlb_flush_page_all_cpus_synced(cs
, value
);
774 tlb_flush_page(cs
, value
);
778 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
781 /* Invalidate by ASID (TLBIASID) */
782 CPUState
*cs
= env_cpu(env
);
784 if (tlb_force_broadcast(env
)) {
785 tlb_flush_all_cpus_synced(cs
);
791 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
794 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
795 CPUState
*cs
= env_cpu(env
);
797 value
&= TARGET_PAGE_MASK
;
798 if (tlb_force_broadcast(env
)) {
799 tlb_flush_page_all_cpus_synced(cs
, value
);
801 tlb_flush_page(cs
, value
);
805 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
808 CPUState
*cs
= env_cpu(env
);
810 tlb_flush_by_mmuidx(cs
,
812 ARMMMUIdxBit_E10_1_PAN
|
816 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
819 CPUState
*cs
= env_cpu(env
);
821 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
823 ARMMMUIdxBit_E10_1_PAN
|
828 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
831 CPUState
*cs
= env_cpu(env
);
833 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
836 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
839 CPUState
*cs
= env_cpu(env
);
841 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
844 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
847 CPUState
*cs
= env_cpu(env
);
848 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
850 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
853 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
856 CPUState
*cs
= env_cpu(env
);
857 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
859 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
863 static const ARMCPRegInfo cp_reginfo
[] = {
864 /* Define the secure and non-secure FCSE identifier CP registers
865 * separately because there is no secure bank in V8 (no _EL3). This allows
866 * the secure register to be properly reset and migrated. There is also no
867 * v8 EL1 version of the register so the non-secure instance stands alone.
870 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
871 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
872 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
873 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
874 { .name
= "FCSEIDR_S",
875 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
876 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
877 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
878 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
879 /* Define the secure and non-secure context identifier CP registers
880 * separately because there is no secure bank in V8 (no _EL3). This allows
881 * the secure register to be properly reset and migrated. In the
882 * non-secure case, the 32-bit register will have reset and migration
883 * disabled during registration as it is handled by the 64-bit instance.
885 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
886 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
887 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
888 .secure
= ARM_CP_SECSTATE_NS
,
889 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
890 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
891 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
892 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
893 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
894 .secure
= ARM_CP_SECSTATE_S
,
895 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
896 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
900 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
901 /* NB: Some of these registers exist in v8 but with more precise
902 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
904 /* MMU Domain access control / MPU write buffer control */
906 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
907 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
908 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
909 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
910 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
911 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
912 * For v6 and v5, these mappings are overly broad.
914 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
915 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
916 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
917 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
918 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
919 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
920 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
921 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
922 /* Cache maintenance ops; some of this space may be overridden later. */
923 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
924 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
925 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
929 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
930 /* Not all pre-v6 cores implemented this WFI, so this is slightly
933 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
934 .access
= PL1_W
, .type
= ARM_CP_WFI
},
938 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
939 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
940 * is UNPREDICTABLE; we choose to NOP as most implementations do).
942 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
943 .access
= PL1_W
, .type
= ARM_CP_WFI
},
944 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
945 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
946 * OMAPCP will override this space.
948 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
949 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
951 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
952 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
954 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
955 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
956 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
958 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
959 * implementing it as RAZ means the "debug architecture version" bits
960 * will read as a reserved value, which should cause Linux to not try
961 * to use the debug hardware.
963 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
964 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
965 /* MMU TLB control. Note that the wildcarding means we cover not just
966 * the unified TLB ops but also the dside/iside/inner-shareable variants.
968 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
969 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
970 .type
= ARM_CP_NO_RAW
},
971 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
972 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
973 .type
= ARM_CP_NO_RAW
},
974 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
975 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
976 .type
= ARM_CP_NO_RAW
},
977 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
978 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
979 .type
= ARM_CP_NO_RAW
},
980 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
981 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
982 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
983 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
987 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
992 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
993 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
994 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
995 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
996 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
998 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
999 /* VFP coprocessor: cp10 & cp11 [23:20] */
1000 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
1002 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
1003 /* ASEDIS [31] bit is RAO/WI */
1007 /* VFPv3 and upwards with NEON implement 32 double precision
1008 * registers (D0-D31).
1010 if (!cpu_isar_feature(aa32_simd_r32
, env_archcpu(env
))) {
1011 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
1019 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
1020 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
1022 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
1023 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
1024 value
&= ~(0xf << 20);
1025 value
|= env
->cp15
.cpacr_el1
& (0xf << 20);
1028 env
->cp15
.cpacr_el1
= value
;
1031 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1034 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
1035 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
1037 uint64_t value
= env
->cp15
.cpacr_el1
;
1039 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
1040 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
1041 value
&= ~(0xf << 20);
1047 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1049 /* Call cpacr_write() so that we reset with the correct RAO bits set
1050 * for our CPU features.
1052 cpacr_write(env
, ri
, 0);
1055 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1058 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1059 /* Check if CPACR accesses are to be trapped to EL2 */
1060 if (arm_current_el(env
) == 1 && arm_is_el2_enabled(env
) &&
1061 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
)) {
1062 return CP_ACCESS_TRAP_EL2
;
1063 /* Check if CPACR accesses are to be trapped to EL3 */
1064 } else if (arm_current_el(env
) < 3 &&
1065 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
1066 return CP_ACCESS_TRAP_EL3
;
1070 return CP_ACCESS_OK
;
1073 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1076 /* Check if CPTR accesses are set to trap to EL3 */
1077 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
1078 return CP_ACCESS_TRAP_EL3
;
1081 return CP_ACCESS_OK
;
1084 static const ARMCPRegInfo v6_cp_reginfo
[] = {
1085 /* prefetch by MVA in v6, NOP in v7 */
1086 { .name
= "MVA_prefetch",
1087 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
1088 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1089 /* We need to break the TB after ISB to execute self-modifying code
1090 * correctly and also to take any pending interrupts immediately.
1091 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
1093 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
1094 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
1095 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
1096 .access
= PL0_W
, .type
= ARM_CP_NOP
},
1097 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
1098 .access
= PL0_W
, .type
= ARM_CP_NOP
},
1099 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
1100 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
1101 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
1102 offsetof(CPUARMState
, cp15
.ifar_ns
) },
1104 /* Watchpoint Fault Address Register : should actually only be present
1105 * for 1136, 1176, 11MPCore.
1107 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
1108 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
1109 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
1110 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
1111 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
1112 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
1116 /* Definitions for the PMU registers */
1117 #define PMCRN_MASK 0xf800
1118 #define PMCRN_SHIFT 11
1127 * Mask of PMCR bits writeable by guest (not including WO bits like C, P,
1128 * which can be written as 1 to trigger behaviour but which stay RAZ).
1130 #define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
1132 #define PMXEVTYPER_P 0x80000000
1133 #define PMXEVTYPER_U 0x40000000
1134 #define PMXEVTYPER_NSK 0x20000000
1135 #define PMXEVTYPER_NSU 0x10000000
1136 #define PMXEVTYPER_NSH 0x08000000
1137 #define PMXEVTYPER_M 0x04000000
1138 #define PMXEVTYPER_MT 0x02000000
1139 #define PMXEVTYPER_EVTCOUNT 0x0000ffff
1140 #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
1141 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
1142 PMXEVTYPER_M | PMXEVTYPER_MT | \
1143 PMXEVTYPER_EVTCOUNT)
1145 #define PMCCFILTR 0xf8000000
1146 #define PMCCFILTR_M PMXEVTYPER_M
1147 #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
1149 static inline uint32_t pmu_num_counters(CPUARMState
*env
)
1151 return (env
->cp15
.c9_pmcr
& PMCRN_MASK
) >> PMCRN_SHIFT
;
1154 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
1155 static inline uint64_t pmu_counter_mask(CPUARMState
*env
)
1157 return (1 << 31) | ((1 << pmu_num_counters(env
)) - 1);
1160 typedef struct pm_event
{
1161 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
1162 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
1163 bool (*supported
)(CPUARMState
*);
1165 * Retrieve the current count of the underlying event. The programmed
1166 * counters hold a difference from the return value from this function
1168 uint64_t (*get_count
)(CPUARMState
*);
1170 * Return how many nanoseconds it will take (at a minimum) for count events
1171 * to occur. A negative value indicates the counter will never overflow, or
1172 * that the counter has otherwise arranged for the overflow bit to be set
1173 * and the PMU interrupt to be raised on overflow.
1175 int64_t (*ns_per_count
)(uint64_t);
1178 static bool event_always_supported(CPUARMState
*env
)
1183 static uint64_t swinc_get_count(CPUARMState
*env
)
1186 * SW_INCR events are written directly to the pmevcntr's by writes to
1187 * PMSWINC, so there is no underlying count maintained by the PMU itself
1192 static int64_t swinc_ns_per(uint64_t ignored
)
1198 * Return the underlying cycle count for the PMU cycle counters. If we're in
1199 * usermode, simply return 0.
1201 static uint64_t cycles_get_count(CPUARMState
*env
)
1203 #ifndef CONFIG_USER_ONLY
1204 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1205 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1207 return cpu_get_host_ticks();
1211 #ifndef CONFIG_USER_ONLY
1212 static int64_t cycles_ns_per(uint64_t cycles
)
1214 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
1217 static bool instructions_supported(CPUARMState
*env
)
1219 return icount_enabled() == 1; /* Precise instruction counting */
1222 static uint64_t instructions_get_count(CPUARMState
*env
)
1224 return (uint64_t)icount_get_raw();
1227 static int64_t instructions_ns_per(uint64_t icount
)
1229 return icount_to_ns((int64_t)icount
);
1233 static bool pmu_8_1_events_supported(CPUARMState
*env
)
1235 /* For events which are supported in any v8.1 PMU */
1236 return cpu_isar_feature(any_pmu_8_1
, env_archcpu(env
));
1239 static bool pmu_8_4_events_supported(CPUARMState
*env
)
1241 /* For events which are supported in any v8.1 PMU */
1242 return cpu_isar_feature(any_pmu_8_4
, env_archcpu(env
));
1245 static uint64_t zero_event_get_count(CPUARMState
*env
)
1247 /* For events which on QEMU never fire, so their count is always zero */
1251 static int64_t zero_event_ns_per(uint64_t cycles
)
1253 /* An event which never fires can never overflow */
1257 static const pm_event pm_events
[] = {
1258 { .number
= 0x000, /* SW_INCR */
1259 .supported
= event_always_supported
,
1260 .get_count
= swinc_get_count
,
1261 .ns_per_count
= swinc_ns_per
,
1263 #ifndef CONFIG_USER_ONLY
1264 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
1265 .supported
= instructions_supported
,
1266 .get_count
= instructions_get_count
,
1267 .ns_per_count
= instructions_ns_per
,
1269 { .number
= 0x011, /* CPU_CYCLES, Cycle */
1270 .supported
= event_always_supported
,
1271 .get_count
= cycles_get_count
,
1272 .ns_per_count
= cycles_ns_per
,
1275 { .number
= 0x023, /* STALL_FRONTEND */
1276 .supported
= pmu_8_1_events_supported
,
1277 .get_count
= zero_event_get_count
,
1278 .ns_per_count
= zero_event_ns_per
,
1280 { .number
= 0x024, /* STALL_BACKEND */
1281 .supported
= pmu_8_1_events_supported
,
1282 .get_count
= zero_event_get_count
,
1283 .ns_per_count
= zero_event_ns_per
,
1285 { .number
= 0x03c, /* STALL */
1286 .supported
= pmu_8_4_events_supported
,
1287 .get_count
= zero_event_get_count
,
1288 .ns_per_count
= zero_event_ns_per
,
1293 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1294 * events (i.e. the statistical profiling extension), this implementation
1295 * should first be updated to something sparse instead of the current
1296 * supported_event_map[] array.
1298 #define MAX_EVENT_ID 0x3c
1299 #define UNSUPPORTED_EVENT UINT16_MAX
1300 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1303 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1304 * of ARM event numbers to indices in our pm_events array.
1306 * Note: Events in the 0x40XX range are not currently supported.
1308 void pmu_init(ARMCPU
*cpu
)
1313 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1316 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1317 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1322 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1323 const pm_event
*cnt
= &pm_events
[i
];
1324 assert(cnt
->number
<= MAX_EVENT_ID
);
1325 /* We do not currently support events in the 0x40xx range */
1326 assert(cnt
->number
<= 0x3f);
1328 if (cnt
->supported(&cpu
->env
)) {
1329 supported_event_map
[cnt
->number
] = i
;
1330 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1331 if (cnt
->number
& 0x20) {
1332 cpu
->pmceid1
|= event_mask
;
1334 cpu
->pmceid0
|= event_mask
;
1341 * Check at runtime whether a PMU event is supported for the current machine
1343 static bool event_supported(uint16_t number
)
1345 if (number
> MAX_EVENT_ID
) {
1348 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1351 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1354 /* Performance monitor registers user accessibility is controlled
1355 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1356 * trapping to EL2 or EL3 for other accesses.
1358 int el
= arm_current_el(env
);
1359 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1361 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1362 return CP_ACCESS_TRAP
;
1364 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
1365 return CP_ACCESS_TRAP_EL2
;
1367 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1368 return CP_ACCESS_TRAP_EL3
;
1371 return CP_ACCESS_OK
;
1374 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1375 const ARMCPRegInfo
*ri
,
1378 /* ER: event counter read trap control */
1379 if (arm_feature(env
, ARM_FEATURE_V8
)
1380 && arm_current_el(env
) == 0
1381 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1383 return CP_ACCESS_OK
;
1386 return pmreg_access(env
, ri
, isread
);
1389 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1390 const ARMCPRegInfo
*ri
,
1393 /* SW: software increment write trap control */
1394 if (arm_feature(env
, ARM_FEATURE_V8
)
1395 && arm_current_el(env
) == 0
1396 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1398 return CP_ACCESS_OK
;
1401 return pmreg_access(env
, ri
, isread
);
1404 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1405 const ARMCPRegInfo
*ri
,
1408 /* ER: event counter read trap control */
1409 if (arm_feature(env
, ARM_FEATURE_V8
)
1410 && arm_current_el(env
) == 0
1411 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1412 return CP_ACCESS_OK
;
1415 return pmreg_access(env
, ri
, isread
);
1418 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1419 const ARMCPRegInfo
*ri
,
1422 /* CR: cycle counter read trap control */
1423 if (arm_feature(env
, ARM_FEATURE_V8
)
1424 && arm_current_el(env
) == 0
1425 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1427 return CP_ACCESS_OK
;
1430 return pmreg_access(env
, ri
, isread
);
1433 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using
1434 * the current EL, security state, and register configuration.
1436 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1439 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1440 bool enabled
, prohibited
, filtered
;
1441 bool secure
= arm_is_secure(env
);
1442 int el
= arm_current_el(env
);
1443 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1444 uint8_t hpmn
= mdcr_el2
& MDCR_HPMN
;
1446 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1450 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1451 (counter
< hpmn
|| counter
== 31)) {
1452 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1454 e
= mdcr_el2
& MDCR_HPME
;
1456 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1459 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1460 prohibited
= mdcr_el2
& MDCR_HPMD
;
1465 prohibited
= arm_feature(env
, ARM_FEATURE_EL3
) &&
1466 !(env
->cp15
.mdcr_el3
& MDCR_SPME
);
1469 if (prohibited
&& counter
== 31) {
1470 prohibited
= env
->cp15
.c9_pmcr
& PMCRDP
;
1473 if (counter
== 31) {
1474 filter
= env
->cp15
.pmccfiltr_el0
;
1476 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1479 p
= filter
& PMXEVTYPER_P
;
1480 u
= filter
& PMXEVTYPER_U
;
1481 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1482 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1483 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1484 m
= arm_el_is_aa64(env
, 1) &&
1485 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1488 filtered
= secure
? u
: u
!= nsu
;
1489 } else if (el
== 1) {
1490 filtered
= secure
? p
: p
!= nsk
;
1491 } else if (el
== 2) {
1497 if (counter
!= 31) {
1499 * If not checking PMCCNTR, ensure the counter is setup to an event we
1502 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1503 if (!event_supported(event
)) {
1508 return enabled
&& !prohibited
&& !filtered
;
1511 static void pmu_update_irq(CPUARMState
*env
)
1513 ARMCPU
*cpu
= env_archcpu(env
);
1514 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1515 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1519 * Ensure c15_ccnt is the guest-visible count so that operations such as
1520 * enabling/disabling the counter or filtering, modifying the count itself,
1521 * etc. can be done logically. This is essentially a no-op if the counter is
1522 * not enabled at the time of the call.
1524 static void pmccntr_op_start(CPUARMState
*env
)
1526 uint64_t cycles
= cycles_get_count(env
);
1528 if (pmu_counter_enabled(env
, 31)) {
1529 uint64_t eff_cycles
= cycles
;
1530 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1531 /* Increment once every 64 processor clock cycles */
1535 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1537 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1538 1ull << 63 : 1ull << 31;
1539 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1540 env
->cp15
.c9_pmovsr
|= (1 << 31);
1541 pmu_update_irq(env
);
1544 env
->cp15
.c15_ccnt
= new_pmccntr
;
1546 env
->cp15
.c15_ccnt_delta
= cycles
;
1550 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1551 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1554 static void pmccntr_op_finish(CPUARMState
*env
)
1556 if (pmu_counter_enabled(env
, 31)) {
1557 #ifndef CONFIG_USER_ONLY
1558 /* Calculate when the counter will next overflow */
1559 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1560 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1561 remaining_cycles
= (uint32_t)remaining_cycles
;
1563 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1565 if (overflow_in
> 0) {
1566 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1568 ARMCPU
*cpu
= env_archcpu(env
);
1569 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1573 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1574 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1575 /* Increment once every 64 processor clock cycles */
1578 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1582 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1585 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1587 if (event_supported(event
)) {
1588 uint16_t event_idx
= supported_event_map
[event
];
1589 count
= pm_events
[event_idx
].get_count(env
);
1592 if (pmu_counter_enabled(env
, counter
)) {
1593 uint32_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1595 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& INT32_MIN
) {
1596 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1597 pmu_update_irq(env
);
1599 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1601 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1604 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1606 if (pmu_counter_enabled(env
, counter
)) {
1607 #ifndef CONFIG_USER_ONLY
1608 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1609 uint16_t event_idx
= supported_event_map
[event
];
1610 uint64_t delta
= UINT32_MAX
-
1611 (uint32_t)env
->cp15
.c14_pmevcntr
[counter
] + 1;
1612 int64_t overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1614 if (overflow_in
> 0) {
1615 int64_t overflow_at
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1617 ARMCPU
*cpu
= env_archcpu(env
);
1618 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1622 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1623 env
->cp15
.c14_pmevcntr
[counter
];
1627 void pmu_op_start(CPUARMState
*env
)
1630 pmccntr_op_start(env
);
1631 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1632 pmevcntr_op_start(env
, i
);
1636 void pmu_op_finish(CPUARMState
*env
)
1639 pmccntr_op_finish(env
);
1640 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1641 pmevcntr_op_finish(env
, i
);
1645 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1647 pmu_op_start(&cpu
->env
);
1650 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1652 pmu_op_finish(&cpu
->env
);
1655 void arm_pmu_timer_cb(void *opaque
)
1657 ARMCPU
*cpu
= opaque
;
1660 * Update all the counter values based on the current underlying counts,
1661 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1662 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1663 * counter may expire.
1665 pmu_op_start(&cpu
->env
);
1666 pmu_op_finish(&cpu
->env
);
1669 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1674 if (value
& PMCRC
) {
1675 /* The counter has been reset */
1676 env
->cp15
.c15_ccnt
= 0;
1679 if (value
& PMCRP
) {
1681 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1682 env
->cp15
.c14_pmevcntr
[i
] = 0;
1686 env
->cp15
.c9_pmcr
&= ~PMCR_WRITEABLE_MASK
;
1687 env
->cp15
.c9_pmcr
|= (value
& PMCR_WRITEABLE_MASK
);
1692 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1696 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1697 /* Increment a counter's count iff: */
1698 if ((value
& (1 << i
)) && /* counter's bit is set */
1699 /* counter is enabled and not filtered */
1700 pmu_counter_enabled(env
, i
) &&
1701 /* counter is SW_INCR */
1702 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1703 pmevcntr_op_start(env
, i
);
1706 * Detect if this write causes an overflow since we can't predict
1707 * PMSWINC overflows like we can for other events
1709 uint32_t new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1711 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& INT32_MIN
) {
1712 env
->cp15
.c9_pmovsr
|= (1 << i
);
1713 pmu_update_irq(env
);
1716 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1718 pmevcntr_op_finish(env
, i
);
1723 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1726 pmccntr_op_start(env
);
1727 ret
= env
->cp15
.c15_ccnt
;
1728 pmccntr_op_finish(env
);
1732 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1735 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1736 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1737 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1740 env
->cp15
.c9_pmselr
= value
& 0x1f;
1743 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1746 pmccntr_op_start(env
);
1747 env
->cp15
.c15_ccnt
= value
;
1748 pmccntr_op_finish(env
);
1751 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1754 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1756 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1759 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1762 pmccntr_op_start(env
);
1763 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1764 pmccntr_op_finish(env
);
1767 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1770 pmccntr_op_start(env
);
1771 /* M is not accessible from AArch32 */
1772 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1773 (value
& PMCCFILTR
);
1774 pmccntr_op_finish(env
);
1777 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1779 /* M is not visible in AArch32 */
1780 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1783 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1786 value
&= pmu_counter_mask(env
);
1787 env
->cp15
.c9_pmcnten
|= value
;
1790 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1793 value
&= pmu_counter_mask(env
);
1794 env
->cp15
.c9_pmcnten
&= ~value
;
1797 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1800 value
&= pmu_counter_mask(env
);
1801 env
->cp15
.c9_pmovsr
&= ~value
;
1802 pmu_update_irq(env
);
1805 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1808 value
&= pmu_counter_mask(env
);
1809 env
->cp15
.c9_pmovsr
|= value
;
1810 pmu_update_irq(env
);
1813 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1814 uint64_t value
, const uint8_t counter
)
1816 if (counter
== 31) {
1817 pmccfiltr_write(env
, ri
, value
);
1818 } else if (counter
< pmu_num_counters(env
)) {
1819 pmevcntr_op_start(env
, counter
);
1822 * If this counter's event type is changing, store the current
1823 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1824 * pmevcntr_op_finish has the correct baseline when it converts back to
1827 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1828 PMXEVTYPER_EVTCOUNT
;
1829 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1830 if (old_event
!= new_event
) {
1832 if (event_supported(new_event
)) {
1833 uint16_t event_idx
= supported_event_map
[new_event
];
1834 count
= pm_events
[event_idx
].get_count(env
);
1836 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1839 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1840 pmevcntr_op_finish(env
, counter
);
1842 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1843 * PMSELR value is equal to or greater than the number of implemented
1844 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1848 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1849 const uint8_t counter
)
1851 if (counter
== 31) {
1852 return env
->cp15
.pmccfiltr_el0
;
1853 } else if (counter
< pmu_num_counters(env
)) {
1854 return env
->cp15
.c14_pmevtyper
[counter
];
1857 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1858 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1864 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1867 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1868 pmevtyper_write(env
, ri
, value
, counter
);
1871 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1874 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1875 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1878 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1879 * pmu_op_finish calls when loading saved state for a migration. Because
1880 * we're potentially updating the type of event here, the value written to
1881 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1882 * different counter type. Therefore, we need to set this value to the
1883 * current count for the counter type we're writing so that pmu_op_finish
1884 * has the correct count for its calculation.
1886 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1887 if (event_supported(event
)) {
1888 uint16_t event_idx
= supported_event_map
[event
];
1889 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1890 pm_events
[event_idx
].get_count(env
);
1894 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1896 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1897 return pmevtyper_read(env
, ri
, counter
);
1900 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1903 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1906 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1908 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1911 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1912 uint64_t value
, uint8_t counter
)
1914 if (counter
< pmu_num_counters(env
)) {
1915 pmevcntr_op_start(env
, counter
);
1916 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1917 pmevcntr_op_finish(env
, counter
);
1920 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1921 * are CONSTRAINED UNPREDICTABLE.
1925 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1928 if (counter
< pmu_num_counters(env
)) {
1930 pmevcntr_op_start(env
, counter
);
1931 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1932 pmevcntr_op_finish(env
, counter
);
1935 /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1936 * are CONSTRAINED UNPREDICTABLE. */
1941 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1944 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1945 pmevcntr_write(env
, ri
, value
, counter
);
1948 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1950 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1951 return pmevcntr_read(env
, ri
, counter
);
1954 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1957 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1958 assert(counter
< pmu_num_counters(env
));
1959 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1960 pmevcntr_write(env
, ri
, value
, counter
);
1963 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1965 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1966 assert(counter
< pmu_num_counters(env
));
1967 return env
->cp15
.c14_pmevcntr
[counter
];
1970 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1973 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1976 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1978 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1981 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1984 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1985 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1987 env
->cp15
.c9_pmuserenr
= value
& 1;
1991 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1994 /* We have no event counters so only the C bit can be changed */
1995 value
&= pmu_counter_mask(env
);
1996 env
->cp15
.c9_pminten
|= value
;
1997 pmu_update_irq(env
);
2000 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2003 value
&= pmu_counter_mask(env
);
2004 env
->cp15
.c9_pminten
&= ~value
;
2005 pmu_update_irq(env
);
2008 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2011 /* Note that even though the AArch64 view of this register has bits
2012 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
2013 * architectural requirements for bits which are RES0 only in some
2014 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
2015 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
2017 raw_write(env
, ri
, value
& ~0x1FULL
);
2020 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2022 /* Begin with base v8.0 state. */
2023 uint32_t valid_mask
= 0x3fff;
2024 ARMCPU
*cpu
= env_archcpu(env
);
2026 if (ri
->state
== ARM_CP_STATE_AA64
) {
2027 value
|= SCR_FW
| SCR_AW
; /* these two bits are RES1. */
2028 valid_mask
&= ~SCR_NET
;
2030 if (cpu_isar_feature(aa64_lor
, cpu
)) {
2031 valid_mask
|= SCR_TLOR
;
2033 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
2034 valid_mask
|= SCR_API
| SCR_APK
;
2036 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
2037 valid_mask
|= SCR_EEL2
;
2039 if (cpu_isar_feature(aa64_mte
, cpu
)) {
2040 valid_mask
|= SCR_ATA
;
2043 valid_mask
&= ~(SCR_RW
| SCR_ST
);
2046 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
2047 valid_mask
&= ~SCR_HCE
;
2049 /* On ARMv7, SMD (or SCD as it is called in v7) is only
2050 * supported if EL2 exists. The bit is UNK/SBZP when
2051 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
2052 * when EL2 is unavailable.
2053 * On ARMv8, this bit is always available.
2055 if (arm_feature(env
, ARM_FEATURE_V7
) &&
2056 !arm_feature(env
, ARM_FEATURE_V8
)) {
2057 valid_mask
&= ~SCR_SMD
;
2061 /* Clear all-context RES0 bits. */
2062 value
&= valid_mask
;
2063 raw_write(env
, ri
, value
);
2066 static CPAccessResult
access_aa64_tid2(CPUARMState
*env
,
2067 const ARMCPRegInfo
*ri
,
2070 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID2
)) {
2071 return CP_ACCESS_TRAP_EL2
;
2074 return CP_ACCESS_OK
;
2077 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2079 ARMCPU
*cpu
= env_archcpu(env
);
2081 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
2084 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
2085 ri
->secure
& ARM_CP_SECSTATE_S
);
2087 return cpu
->ccsidr
[index
];
2090 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2093 raw_write(env
, ri
, value
& 0xf);
2096 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2098 CPUState
*cs
= env_cpu(env
);
2099 bool el1
= arm_current_el(env
) == 1;
2100 uint64_t hcr_el2
= el1
? arm_hcr_el2_eff(env
) : 0;
2103 if (hcr_el2
& HCR_IMO
) {
2104 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
2108 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
2113 if (hcr_el2
& HCR_FMO
) {
2114 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
2118 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
2123 /* External aborts are not possible in QEMU so A bit is always clear */
2127 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2130 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
2131 return CP_ACCESS_TRAP_EL2
;
2134 return CP_ACCESS_OK
;
2137 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2140 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2141 return access_aa64_tid1(env
, ri
, isread
);
2144 return CP_ACCESS_OK
;
2147 static const ARMCPRegInfo v7_cp_reginfo
[] = {
2148 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
2149 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
2150 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2151 /* Performance monitors are implementation defined in v7,
2152 * but with an ARM recommended set of registers, which we
2155 * Performance registers fall into three categories:
2156 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2157 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2158 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2159 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2160 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2162 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
2163 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2164 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2165 .writefn
= pmcntenset_write
,
2166 .accessfn
= pmreg_access
,
2167 .raw_writefn
= raw_write
},
2168 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
2169 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
2170 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2171 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
2172 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
2173 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
2175 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2176 .accessfn
= pmreg_access
,
2177 .writefn
= pmcntenclr_write
,
2178 .type
= ARM_CP_ALIAS
},
2179 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2180 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
2181 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2182 .type
= ARM_CP_ALIAS
,
2183 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
2184 .writefn
= pmcntenclr_write
},
2185 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
2186 .access
= PL0_RW
, .type
= ARM_CP_IO
,
2187 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2188 .accessfn
= pmreg_access
,
2189 .writefn
= pmovsr_write
,
2190 .raw_writefn
= raw_write
},
2191 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2192 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
2193 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2194 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2195 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2196 .writefn
= pmovsr_write
,
2197 .raw_writefn
= raw_write
},
2198 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
2199 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2200 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2201 .writefn
= pmswinc_write
},
2202 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
2203 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
2204 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2205 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2206 .writefn
= pmswinc_write
},
2207 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
2208 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2209 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
2210 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
2211 .raw_writefn
= raw_write
},
2212 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
2213 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
2214 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
2215 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
2216 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
2217 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
2218 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2219 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
2220 .accessfn
= pmreg_access_ccntr
},
2221 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2222 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
2223 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
2225 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
2226 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
2227 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
2228 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
2229 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
2230 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2231 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2233 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2234 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2235 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2236 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2238 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2240 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2241 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2242 .accessfn
= pmreg_access
,
2243 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2244 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2245 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2246 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2247 .accessfn
= pmreg_access
,
2248 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2249 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2250 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2251 .accessfn
= pmreg_access_xevcntr
,
2252 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2253 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2254 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2255 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2256 .accessfn
= pmreg_access_xevcntr
,
2257 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2258 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2259 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2260 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2262 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2263 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2264 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2265 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2266 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2268 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2269 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2270 .access
= PL1_RW
, .accessfn
= access_tpm
,
2271 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2272 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2274 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2275 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2276 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2277 .access
= PL1_RW
, .accessfn
= access_tpm
,
2279 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2280 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2281 .resetvalue
= 0x0 },
2282 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2283 .access
= PL1_RW
, .accessfn
= access_tpm
,
2284 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2285 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2286 .writefn
= pmintenclr_write
, },
2287 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2288 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2289 .access
= PL1_RW
, .accessfn
= access_tpm
,
2290 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2291 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2292 .writefn
= pmintenclr_write
},
2293 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2294 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2296 .accessfn
= access_aa64_tid2
,
2297 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2298 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2299 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2301 .accessfn
= access_aa64_tid2
,
2302 .writefn
= csselr_write
, .resetvalue
= 0,
2303 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2304 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2305 /* Auxiliary ID register: this actually has an IMPDEF value but for now
2306 * just RAZ for all cores:
2308 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2309 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2310 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2311 .accessfn
= access_aa64_tid1
,
2313 /* Auxiliary fault status registers: these also are IMPDEF, and we
2314 * choose to RAZ/WI for all cores.
2316 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2317 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2318 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2319 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2320 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2321 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2322 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2323 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2324 /* MAIR can just read-as-written because we don't implement caches
2325 * and so don't need to care about memory attributes.
2327 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2328 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2329 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2330 .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2332 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2333 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2334 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2336 /* For non-long-descriptor page tables these are PRRR and NMRR;
2337 * regardless they still act as reads-as-written for QEMU.
2339 /* MAIR0/1 are defined separately from their 64-bit counterpart which
2340 * allows them to assign the correct fieldoffset based on the endianness
2341 * handled in the field definitions.
2343 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2344 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2345 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2346 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2347 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2348 .resetfn
= arm_cp_reset_ignore
},
2349 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2350 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1,
2351 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2352 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2353 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2354 .resetfn
= arm_cp_reset_ignore
},
2355 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2356 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2357 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2358 /* 32 bit ITLB invalidates */
2359 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2360 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2361 .writefn
= tlbiall_write
},
2362 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2363 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2364 .writefn
= tlbimva_write
},
2365 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2366 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2367 .writefn
= tlbiasid_write
},
2368 /* 32 bit DTLB invalidates */
2369 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2370 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2371 .writefn
= tlbiall_write
},
2372 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2373 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2374 .writefn
= tlbimva_write
},
2375 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2376 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2377 .writefn
= tlbiasid_write
},
2378 /* 32 bit TLB invalidates */
2379 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2380 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2381 .writefn
= tlbiall_write
},
2382 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2383 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2384 .writefn
= tlbimva_write
},
2385 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2386 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2387 .writefn
= tlbiasid_write
},
2388 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2389 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2390 .writefn
= tlbimvaa_write
},
2394 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2395 /* 32 bit TLB invalidates, Inner Shareable */
2396 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2397 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2398 .writefn
= tlbiall_is_write
},
2399 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2400 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2401 .writefn
= tlbimva_is_write
},
2402 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2403 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2404 .writefn
= tlbiasid_is_write
},
2405 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2406 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2407 .writefn
= tlbimvaa_is_write
},
2411 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2412 /* PMOVSSET is not implemented in v7 before v7ve */
2413 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2414 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2415 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2416 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2417 .writefn
= pmovsset_write
,
2418 .raw_writefn
= raw_write
},
2419 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2420 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2421 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2422 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2423 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2424 .writefn
= pmovsset_write
,
2425 .raw_writefn
= raw_write
},
2429 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2436 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2439 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2440 return CP_ACCESS_TRAP
;
2442 return CP_ACCESS_OK
;
2445 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2446 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2447 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2449 .writefn
= teecr_write
},
2450 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2451 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2452 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2456 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2457 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2458 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2460 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2461 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2463 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2464 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2465 .resetfn
= arm_cp_reset_ignore
},
2466 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2467 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2468 .access
= PL0_R
|PL1_W
,
2469 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2471 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2472 .access
= PL0_R
|PL1_W
,
2473 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2474 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2475 .resetfn
= arm_cp_reset_ignore
},
2476 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2477 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2479 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2480 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2482 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2483 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2488 #ifndef CONFIG_USER_ONLY
2490 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2493 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2494 * Writable only at the highest implemented exception level.
2496 int el
= arm_current_el(env
);
2502 hcr
= arm_hcr_el2_eff(env
);
2503 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2504 cntkctl
= env
->cp15
.cnthctl_el2
;
2506 cntkctl
= env
->cp15
.c14_cntkctl
;
2508 if (!extract32(cntkctl
, 0, 2)) {
2509 return CP_ACCESS_TRAP
;
2513 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2514 arm_is_secure_below_el3(env
)) {
2515 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2516 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2524 if (!isread
&& el
< arm_highest_el(env
)) {
2525 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2528 return CP_ACCESS_OK
;
2531 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2534 unsigned int cur_el
= arm_current_el(env
);
2535 bool has_el2
= arm_is_el2_enabled(env
);
2536 uint64_t hcr
= arm_hcr_el2_eff(env
);
2540 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2541 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2542 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2543 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2546 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2547 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2548 return CP_ACCESS_TRAP
;
2551 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
2552 if (hcr
& HCR_E2H
) {
2553 if (timeridx
== GTIMER_PHYS
&&
2554 !extract32(env
->cp15
.cnthctl_el2
, 10, 1)) {
2555 return CP_ACCESS_TRAP_EL2
;
2558 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2559 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2560 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2561 return CP_ACCESS_TRAP_EL2
;
2567 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2568 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2570 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2571 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2572 return CP_ACCESS_TRAP_EL2
;
2576 return CP_ACCESS_OK
;
2579 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2582 unsigned int cur_el
= arm_current_el(env
);
2583 bool has_el2
= arm_is_el2_enabled(env
);
2584 uint64_t hcr
= arm_hcr_el2_eff(env
);
2588 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2589 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2590 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2591 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2595 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2596 * EL0 if EL0[PV]TEN is zero.
2598 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2599 return CP_ACCESS_TRAP
;
2604 if (has_el2
&& timeridx
== GTIMER_PHYS
) {
2605 if (hcr
& HCR_E2H
) {
2606 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2607 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2608 return CP_ACCESS_TRAP_EL2
;
2611 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2612 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2613 return CP_ACCESS_TRAP_EL2
;
2619 return CP_ACCESS_OK
;
2622 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2623 const ARMCPRegInfo
*ri
,
2626 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2629 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2630 const ARMCPRegInfo
*ri
,
2633 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2636 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2639 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2642 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2645 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2648 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2649 const ARMCPRegInfo
*ri
,
2652 /* The AArch64 register view of the secure physical timer is
2653 * always accessible from EL3, and configurably accessible from
2656 switch (arm_current_el(env
)) {
2658 if (!arm_is_secure(env
)) {
2659 return CP_ACCESS_TRAP
;
2661 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2662 return CP_ACCESS_TRAP_EL3
;
2664 return CP_ACCESS_OK
;
2667 return CP_ACCESS_TRAP
;
2669 return CP_ACCESS_OK
;
2671 g_assert_not_reached();
2675 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2677 ARMCPU
*cpu
= env_archcpu(env
);
2679 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2682 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2684 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2687 /* Timer enabled: calculate and set current ISTATUS, irq, and
2688 * reset timer to when ISTATUS next has to change
2690 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2691 cpu
->env
.cp15
.cntvoff_el2
: 0;
2692 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2693 /* Note that this must be unsigned 64 bit arithmetic: */
2694 int istatus
= count
- offset
>= gt
->cval
;
2698 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2700 irqstate
= (istatus
&& !(gt
->ctl
& 2));
2701 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2704 /* Next transition is when count rolls back over to zero */
2705 nexttick
= UINT64_MAX
;
2707 /* Next transition is when we hit cval */
2708 nexttick
= gt
->cval
+ offset
;
2710 /* Note that the desired next expiry time might be beyond the
2711 * signed-64-bit range of a QEMUTimer -- in this case we just
2712 * set the timer for as far in the future as possible. When the
2713 * timer expires we will reset the timer for any remaining period.
2715 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2716 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2718 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2720 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
2722 /* Timer disabled: ISTATUS and timer output always clear */
2724 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
2725 timer_del(cpu
->gt_timer
[timeridx
]);
2726 trace_arm_gt_recalc_disabled(timeridx
);
2730 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2733 ARMCPU
*cpu
= env_archcpu(env
);
2735 timer_del(cpu
->gt_timer
[timeridx
]);
2738 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2740 return gt_get_countervalue(env
);
2743 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2747 switch (arm_current_el(env
)) {
2749 hcr
= arm_hcr_el2_eff(env
);
2750 if (hcr
& HCR_E2H
) {
2755 hcr
= arm_hcr_el2_eff(env
);
2756 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2762 return env
->cp15
.cntvoff_el2
;
2765 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2767 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2770 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2774 trace_arm_gt_cval_write(timeridx
, value
);
2775 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2776 gt_recalc_timer(env_archcpu(env
), timeridx
);
2779 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2782 uint64_t offset
= 0;
2786 case GTIMER_HYPVIRT
:
2787 offset
= gt_virt_cnt_offset(env
);
2791 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2792 (gt_get_countervalue(env
) - offset
));
2795 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2799 uint64_t offset
= 0;
2803 case GTIMER_HYPVIRT
:
2804 offset
= gt_virt_cnt_offset(env
);
2808 trace_arm_gt_tval_write(timeridx
, value
);
2809 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2810 sextract64(value
, 0, 32);
2811 gt_recalc_timer(env_archcpu(env
), timeridx
);
2814 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2818 ARMCPU
*cpu
= env_archcpu(env
);
2819 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2821 trace_arm_gt_ctl_write(timeridx
, value
);
2822 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2823 if ((oldval
^ value
) & 1) {
2824 /* Enable toggled */
2825 gt_recalc_timer(cpu
, timeridx
);
2826 } else if ((oldval
^ value
) & 2) {
2827 /* IMASK toggled: don't need to recalculate,
2828 * just set the interrupt line based on ISTATUS
2830 int irqstate
= (oldval
& 4) && !(value
& 2);
2832 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
2833 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2837 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2839 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2842 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2845 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2848 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2850 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2853 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2856 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2859 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2862 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2865 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2867 switch (arm_mmu_idx(env
)) {
2868 case ARMMMUIdx_E20_0
:
2869 case ARMMMUIdx_E20_2
:
2870 case ARMMMUIdx_E20_2_PAN
:
2871 case ARMMMUIdx_SE20_0
:
2872 case ARMMMUIdx_SE20_2
:
2873 case ARMMMUIdx_SE20_2_PAN
:
2880 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2882 switch (arm_mmu_idx(env
)) {
2883 case ARMMMUIdx_E20_0
:
2884 case ARMMMUIdx_E20_2
:
2885 case ARMMMUIdx_E20_2_PAN
:
2886 case ARMMMUIdx_SE20_0
:
2887 case ARMMMUIdx_SE20_2
:
2888 case ARMMMUIdx_SE20_2_PAN
:
2889 return GTIMER_HYPVIRT
;
2895 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2896 const ARMCPRegInfo
*ri
)
2898 int timeridx
= gt_phys_redir_timeridx(env
);
2899 return env
->cp15
.c14_timer
[timeridx
].cval
;
2902 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2905 int timeridx
= gt_phys_redir_timeridx(env
);
2906 gt_cval_write(env
, ri
, timeridx
, value
);
2909 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2910 const ARMCPRegInfo
*ri
)
2912 int timeridx
= gt_phys_redir_timeridx(env
);
2913 return gt_tval_read(env
, ri
, timeridx
);
2916 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2919 int timeridx
= gt_phys_redir_timeridx(env
);
2920 gt_tval_write(env
, ri
, timeridx
, value
);
2923 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2924 const ARMCPRegInfo
*ri
)
2926 int timeridx
= gt_phys_redir_timeridx(env
);
2927 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2930 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2933 int timeridx
= gt_phys_redir_timeridx(env
);
2934 gt_ctl_write(env
, ri
, timeridx
, value
);
2937 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2939 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2942 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2945 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2948 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2950 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2953 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2956 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2959 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2962 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2965 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2968 ARMCPU
*cpu
= env_archcpu(env
);
2970 trace_arm_gt_cntvoff_write(value
);
2971 raw_write(env
, ri
, value
);
2972 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2975 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
2976 const ARMCPRegInfo
*ri
)
2978 int timeridx
= gt_virt_redir_timeridx(env
);
2979 return env
->cp15
.c14_timer
[timeridx
].cval
;
2982 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2985 int timeridx
= gt_virt_redir_timeridx(env
);
2986 gt_cval_write(env
, ri
, timeridx
, value
);
2989 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
2990 const ARMCPRegInfo
*ri
)
2992 int timeridx
= gt_virt_redir_timeridx(env
);
2993 return gt_tval_read(env
, ri
, timeridx
);
2996 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2999 int timeridx
= gt_virt_redir_timeridx(env
);
3000 gt_tval_write(env
, ri
, timeridx
, value
);
3003 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
3004 const ARMCPRegInfo
*ri
)
3006 int timeridx
= gt_virt_redir_timeridx(env
);
3007 return env
->cp15
.c14_timer
[timeridx
].ctl
;
3010 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3013 int timeridx
= gt_virt_redir_timeridx(env
);
3014 gt_ctl_write(env
, ri
, timeridx
, value
);
3017 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3019 gt_timer_reset(env
, ri
, GTIMER_HYP
);
3022 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3025 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
3028 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3030 return gt_tval_read(env
, ri
, GTIMER_HYP
);
3033 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3036 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
3039 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3042 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
3045 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3047 gt_timer_reset(env
, ri
, GTIMER_SEC
);
3050 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3053 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
3056 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3058 return gt_tval_read(env
, ri
, GTIMER_SEC
);
3061 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3064 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
3067 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3070 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
3073 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3075 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
3078 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3081 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3084 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3086 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
3089 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3092 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3095 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3098 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3101 void arm_gt_ptimer_cb(void *opaque
)
3103 ARMCPU
*cpu
= opaque
;
3105 gt_recalc_timer(cpu
, GTIMER_PHYS
);
3108 void arm_gt_vtimer_cb(void *opaque
)
3110 ARMCPU
*cpu
= opaque
;
3112 gt_recalc_timer(cpu
, GTIMER_VIRT
);
3115 void arm_gt_htimer_cb(void *opaque
)
3117 ARMCPU
*cpu
= opaque
;
3119 gt_recalc_timer(cpu
, GTIMER_HYP
);
3122 void arm_gt_stimer_cb(void *opaque
)
3124 ARMCPU
*cpu
= opaque
;
3126 gt_recalc_timer(cpu
, GTIMER_SEC
);
3129 void arm_gt_hvtimer_cb(void *opaque
)
3131 ARMCPU
*cpu
= opaque
;
3133 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
3136 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
3138 ARMCPU
*cpu
= env_archcpu(env
);
3140 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
3143 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3144 /* Note that CNTFRQ is purely reads-as-written for the benefit
3145 * of software; writing it doesn't actually change the timer frequency.
3146 * Our reset value matches the fixed frequency we implement the timer at.
3148 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
3149 .type
= ARM_CP_ALIAS
,
3150 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3151 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
3153 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3154 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3155 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3156 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3157 .resetfn
= arm_gt_cntfrq_reset
,
3159 /* overall control: mostly access permissions */
3160 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
3161 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
3163 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
3166 /* per-timer control */
3167 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3168 .secure
= ARM_CP_SECSTATE_NS
,
3169 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3170 .accessfn
= gt_ptimer_access
,
3171 .fieldoffset
= offsetoflow32(CPUARMState
,
3172 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3173 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3174 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3176 { .name
= "CNTP_CTL_S",
3177 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3178 .secure
= ARM_CP_SECSTATE_S
,
3179 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3180 .accessfn
= gt_ptimer_access
,
3181 .fieldoffset
= offsetoflow32(CPUARMState
,
3182 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3183 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3185 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3186 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
3187 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3188 .accessfn
= gt_ptimer_access
,
3189 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3191 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3192 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3194 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
3195 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3196 .accessfn
= gt_vtimer_access
,
3197 .fieldoffset
= offsetoflow32(CPUARMState
,
3198 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3199 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3200 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3202 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3203 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
3204 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3205 .accessfn
= gt_vtimer_access
,
3206 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3208 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3209 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3211 /* TimerValue views: a 32 bit downcounting view of the underlying state */
3212 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3213 .secure
= ARM_CP_SECSTATE_NS
,
3214 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3215 .accessfn
= gt_ptimer_access
,
3216 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3218 { .name
= "CNTP_TVAL_S",
3219 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3220 .secure
= ARM_CP_SECSTATE_S
,
3221 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3222 .accessfn
= gt_ptimer_access
,
3223 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
3225 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3226 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
3227 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3228 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
3229 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3231 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
3232 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3233 .accessfn
= gt_vtimer_access
,
3234 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3236 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3237 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
3238 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3239 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
3240 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3242 /* The counter itself */
3243 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
3244 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3245 .accessfn
= gt_pct_access
,
3246 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3248 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
3249 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
3250 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3251 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3253 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
3254 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3255 .accessfn
= gt_vct_access
,
3256 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3258 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3259 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3260 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3261 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3263 /* Comparison value, indicating when the timer goes off */
3264 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
3265 .secure
= ARM_CP_SECSTATE_NS
,
3267 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3268 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3269 .accessfn
= gt_ptimer_access
,
3270 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3271 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3273 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
3274 .secure
= ARM_CP_SECSTATE_S
,
3276 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3277 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3278 .accessfn
= gt_ptimer_access
,
3279 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3281 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3282 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
3285 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3286 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
3287 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3288 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3290 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
3292 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3293 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3294 .accessfn
= gt_vtimer_access
,
3295 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3296 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3298 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3299 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
3302 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3303 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
3304 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3305 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3307 /* Secure timer -- this is actually restricted to only EL3
3308 * and configurably Secure-EL1 via the accessfn.
3310 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3311 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3312 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3313 .accessfn
= gt_stimer_access
,
3314 .readfn
= gt_sec_tval_read
,
3315 .writefn
= gt_sec_tval_write
,
3316 .resetfn
= gt_sec_timer_reset
,
3318 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3319 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3320 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3321 .accessfn
= gt_stimer_access
,
3322 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3324 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3326 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3327 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3328 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3329 .accessfn
= gt_stimer_access
,
3330 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3331 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3336 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3339 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3340 return CP_ACCESS_TRAP
;
3342 return CP_ACCESS_OK
;
3347 /* In user-mode most of the generic timer registers are inaccessible
3348 * however modern kernels (4.12+) allow access to cntvct_el0
3351 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3353 ARMCPU
*cpu
= env_archcpu(env
);
3355 /* Currently we have no support for QEMUTimer in linux-user so we
3356 * can't call gt_get_countervalue(env), instead we directly
3357 * call the lower level functions.
3359 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3362 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3363 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3364 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3365 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3366 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3367 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3369 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3370 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3371 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3372 .readfn
= gt_virt_cnt_read
,
3379 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3381 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3382 raw_write(env
, ri
, value
);
3383 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3384 raw_write(env
, ri
, value
& 0xfffff6ff);
3386 raw_write(env
, ri
, value
& 0xfffff1ff);
3390 #ifndef CONFIG_USER_ONLY
3391 /* get_phys_addr() isn't present for user-mode-only targets */
3393 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3397 /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in
3398 * Secure EL1 (which can only happen if EL3 is AArch64).
3399 * They are simply UNDEF if executed from NS EL1.
3400 * They function normally from EL2 or EL3.
3402 if (arm_current_el(env
) == 1) {
3403 if (arm_is_secure_below_el3(env
)) {
3404 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
3405 return CP_ACCESS_TRAP_UNCATEGORIZED_EL2
;
3407 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
3409 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3412 return CP_ACCESS_OK
;
3416 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3417 MMUAccessType access_type
, ARMMMUIdx mmu_idx
)
3420 target_ulong page_size
;
3424 bool format64
= false;
3425 MemTxAttrs attrs
= {};
3426 ARMMMUFaultInfo fi
= {};
3427 ARMCacheAttrs cacheattrs
= {};
3429 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
, &phys_addr
, &attrs
,
3430 &prot
, &page_size
, &fi
, &cacheattrs
);
3434 * Some kinds of translation fault must cause exceptions rather
3435 * than being reported in the PAR.
3437 int current_el
= arm_current_el(env
);
3439 uint32_t syn
, fsr
, fsc
;
3440 bool take_exc
= false;
3442 if (fi
.s1ptw
&& current_el
== 1
3443 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3445 * Synchronous stage 2 fault on an access made as part of the
3446 * translation table walk for AT S1E0* or AT S1E1* insn
3447 * executed from NS EL1. If this is a synchronous external abort
3448 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3449 * to EL3. Otherwise the fault is taken as an exception to EL2,
3450 * and HPFAR_EL2 holds the faulting IPA.
3452 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3453 (env
->cp15
.scr_el3
& SCR_EA
)) {
3456 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3457 if (arm_is_secure_below_el3(env
) && fi
.s1ns
) {
3458 env
->cp15
.hpfar_el2
|= HPFAR_NS
;
3463 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3465 * Synchronous external aborts during a translation table walk
3466 * are taken as Data Abort exceptions.
3469 if (current_el
== 3) {
3475 target_el
= exception_target_el(env
);
3481 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3482 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3483 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3484 fsr
= arm_fi_to_lfsc(&fi
);
3485 fsc
= extract32(fsr
, 0, 6);
3487 fsr
= arm_fi_to_sfsc(&fi
);
3491 * Report exception with ESR indicating a fault due to a
3492 * translation table walk for a cache maintenance instruction.
3494 syn
= syn_data_abort_no_iss(current_el
== target_el
, 0,
3495 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3496 env
->exception
.vaddress
= value
;
3497 env
->exception
.fsr
= fsr
;
3498 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3504 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3507 * * TTBCR.EAE determines whether the result is returned using the
3508 * 32-bit or the 64-bit PAR format
3509 * * Instructions executed in Hyp mode always use the 64bit format
3511 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3512 * * The Non-secure TTBCR.EAE bit is set to 1
3513 * * The implementation includes EL2, and the value of HCR.VM is 1
3515 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3517 * ATS1Hx always uses the 64bit format.
3519 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3521 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3522 if (mmu_idx
== ARMMMUIdx_E10_0
||
3523 mmu_idx
== ARMMMUIdx_E10_1
||
3524 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3525 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3527 format64
|= arm_current_el(env
) == 2;
3533 /* Create a 64-bit PAR */
3534 par64
= (1 << 11); /* LPAE bit always set */
3536 par64
|= phys_addr
& ~0xfffULL
;
3537 if (!attrs
.secure
) {
3538 par64
|= (1 << 9); /* NS */
3540 par64
|= (uint64_t)cacheattrs
.attrs
<< 56; /* ATTR */
3541 par64
|= cacheattrs
.shareability
<< 7; /* SH */
3543 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3546 par64
|= (fsr
& 0x3f) << 1; /* FS */
3548 par64
|= (1 << 9); /* S */
3551 par64
|= (1 << 8); /* PTW */
3555 /* fsr is a DFSR/IFSR value for the short descriptor
3556 * translation table format (with WnR always clear).
3557 * Convert it to a 32-bit PAR.
3560 /* We do not set any attribute bits in the PAR */
3561 if (page_size
== (1 << 24)
3562 && arm_feature(env
, ARM_FEATURE_V7
)) {
3563 par64
= (phys_addr
& 0xff000000) | (1 << 1);
3565 par64
= phys_addr
& 0xfffff000;
3567 if (!attrs
.secure
) {
3568 par64
|= (1 << 9); /* NS */
3571 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3573 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3574 ((fsr
& 0xf) << 1) | 1;
3579 #endif /* CONFIG_TCG */
3581 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3584 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3587 int el
= arm_current_el(env
);
3588 bool secure
= arm_is_secure_below_el3(env
);
3590 switch (ri
->opc2
& 6) {
3592 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3595 mmu_idx
= ARMMMUIdx_SE3
;
3598 g_assert(!secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3601 if (ri
->crm
== 9 && (env
->uncached_cpsr
& CPSR_PAN
)) {
3602 mmu_idx
= (secure
? ARMMMUIdx_Stage1_SE1_PAN
3603 : ARMMMUIdx_Stage1_E1_PAN
);
3605 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE1
: ARMMMUIdx_Stage1_E1
;
3609 g_assert_not_reached();
3613 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3616 mmu_idx
= ARMMMUIdx_SE10_0
;
3619 g_assert(!secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3620 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3623 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE0
: ARMMMUIdx_Stage1_E0
;
3626 g_assert_not_reached();
3630 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3631 mmu_idx
= ARMMMUIdx_E10_1
;
3634 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3635 mmu_idx
= ARMMMUIdx_E10_0
;
3638 g_assert_not_reached();
3641 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
3643 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3645 /* Handled by hardware accelerator. */
3646 g_assert_not_reached();
3647 #endif /* CONFIG_TCG */
3650 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3654 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3657 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
);
3659 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3661 /* Handled by hardware accelerator. */
3662 g_assert_not_reached();
3663 #endif /* CONFIG_TCG */
3666 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3669 if (arm_current_el(env
) == 3 &&
3670 !(env
->cp15
.scr_el3
& (SCR_NS
| SCR_EEL2
))) {
3671 return CP_ACCESS_TRAP
;
3673 return CP_ACCESS_OK
;
3676 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3680 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3682 int secure
= arm_is_secure_below_el3(env
);
3684 switch (ri
->opc2
& 6) {
3687 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3688 if (ri
->crm
== 9 && (env
->pstate
& PSTATE_PAN
)) {
3689 mmu_idx
= (secure
? ARMMMUIdx_Stage1_SE1_PAN
3690 : ARMMMUIdx_Stage1_E1_PAN
);
3692 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE1
: ARMMMUIdx_Stage1_E1
;
3695 case 4: /* AT S1E2R, AT S1E2W */
3696 mmu_idx
= secure
? ARMMMUIdx_SE2
: ARMMMUIdx_E2
;
3698 case 6: /* AT S1E3R, AT S1E3W */
3699 mmu_idx
= ARMMMUIdx_SE3
;
3702 g_assert_not_reached();
3705 case 2: /* AT S1E0R, AT S1E0W */
3706 mmu_idx
= secure
? ARMMMUIdx_Stage1_SE0
: ARMMMUIdx_Stage1_E0
;
3708 case 4: /* AT S12E1R, AT S12E1W */
3709 mmu_idx
= secure
? ARMMMUIdx_SE10_1
: ARMMMUIdx_E10_1
;
3711 case 6: /* AT S12E0R, AT S12E0W */
3712 mmu_idx
= secure
? ARMMMUIdx_SE10_0
: ARMMMUIdx_E10_0
;
3715 g_assert_not_reached();
3718 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
3720 /* Handled by hardware accelerator. */
3721 g_assert_not_reached();
3722 #endif /* CONFIG_TCG */
3726 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
3727 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
3728 .access
= PL1_RW
, .resetvalue
= 0,
3729 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
3730 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
3731 .writefn
= par_write
},
3732 #ifndef CONFIG_USER_ONLY
3733 /* This underdecoding is safe because the reginfo is NO_RAW. */
3734 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
3735 .access
= PL1_W
, .accessfn
= ats_access
,
3736 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
3741 /* Return basic MPU access permission bits. */
3742 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3749 for (i
= 0; i
< 16; i
+= 2) {
3750 ret
|= (val
>> i
) & mask
;
3756 /* Pad basic MPU access permission bits to extended format. */
3757 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3764 for (i
= 0; i
< 16; i
+= 2) {
3765 ret
|= (val
& mask
) << i
;
3771 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3774 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3777 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3779 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3782 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3785 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3788 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3790 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3793 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3795 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3801 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3805 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3808 ARMCPU
*cpu
= env_archcpu(env
);
3809 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3815 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3816 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3820 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3823 ARMCPU
*cpu
= env_archcpu(env
);
3824 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3826 if (value
>= nrgs
) {
3827 qemu_log_mask(LOG_GUEST_ERROR
,
3828 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3829 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3833 raw_write(env
, ri
, value
);
3836 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
3837 /* Reset for all these registers is handled in arm_cpu_reset(),
3838 * because the PMSAv7 is also used by M-profile CPUs, which do
3839 * not register cpregs but still need the state to be reset.
3841 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
3842 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3843 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
3844 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3845 .resetfn
= arm_cp_reset_ignore
},
3846 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
3847 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3848 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
3849 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3850 .resetfn
= arm_cp_reset_ignore
},
3851 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
3852 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
3853 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
3854 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
3855 .resetfn
= arm_cp_reset_ignore
},
3856 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
3858 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
3859 .writefn
= pmsav7_rgnr_write
,
3860 .resetfn
= arm_cp_reset_ignore
},
3864 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
3865 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
3866 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3867 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3868 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
3869 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
3870 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
3871 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3872 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
3873 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
3875 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
3877 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
3879 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
3881 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
3883 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
3884 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
3886 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
3887 /* Protection region base and size registers */
3888 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
3889 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3890 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
3891 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
3892 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3893 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
3894 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
3895 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3896 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
3897 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
3898 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3899 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
3900 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
3901 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3902 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
3903 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
3904 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3905 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
3906 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
3907 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3908 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
3909 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
3910 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
3911 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
3915 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3918 TCR
*tcr
= raw_ptr(env
, ri
);
3919 int maskshift
= extract32(value
, 0, 3);
3921 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
3922 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
3923 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
3924 * using Long-desciptor translation table format */
3925 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
3926 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3927 /* In an implementation that includes the Security Extensions
3928 * TTBCR has additional fields PD0 [4] and PD1 [5] for
3929 * Short-descriptor translation table format.
3931 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
3937 /* Update the masks corresponding to the TCR bank being written
3938 * Note that we always calculate mask and base_mask, but
3939 * they are only used for short-descriptor tables (ie if EAE is 0);
3940 * for long-descriptor tables the TCR fields are used differently
3941 * and the mask and base_mask values are meaningless.
3943 tcr
->raw_tcr
= value
;
3944 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
3945 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
3948 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3951 ARMCPU
*cpu
= env_archcpu(env
);
3952 TCR
*tcr
= raw_ptr(env
, ri
);
3954 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3955 /* With LPAE the TTBCR could result in a change of ASID
3956 * via the TTBCR.A1 bit, so do a TLB flush.
3958 tlb_flush(CPU(cpu
));
3960 /* Preserve the high half of TCR_EL1, set via TTBCR2. */
3961 value
= deposit64(tcr
->raw_tcr
, 0, 32, value
);
3962 vmsa_ttbcr_raw_write(env
, ri
, value
);
3965 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3967 TCR
*tcr
= raw_ptr(env
, ri
);
3969 /* Reset both the TCR as well as the masks corresponding to the bank of
3970 * the TCR being reset.
3974 tcr
->base_mask
= 0xffffc000u
;
3977 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3980 ARMCPU
*cpu
= env_archcpu(env
);
3981 TCR
*tcr
= raw_ptr(env
, ri
);
3983 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
3984 tlb_flush(CPU(cpu
));
3985 tcr
->raw_tcr
= value
;
3988 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3991 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
3992 if (cpreg_field_is_64bit(ri
) &&
3993 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
3994 ARMCPU
*cpu
= env_archcpu(env
);
3995 tlb_flush(CPU(cpu
));
3997 raw_write(env
, ri
, value
);
4000 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4004 * If we are running with E2&0 regime, then an ASID is active.
4005 * Flush if that might be changing. Note we're not checking
4006 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
4007 * holds the active ASID, only checking the field that might.
4009 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
4010 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
4011 uint16_t mask
= ARMMMUIdxBit_E20_2
|
4012 ARMMMUIdxBit_E20_2_PAN
|
4015 if (arm_is_secure_below_el3(env
)) {
4016 mask
>>= ARM_MMU_IDX_A_NS
;
4019 tlb_flush_by_mmuidx(env_cpu(env
), mask
);
4021 raw_write(env
, ri
, value
);
4024 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4027 ARMCPU
*cpu
= env_archcpu(env
);
4028 CPUState
*cs
= CPU(cpu
);
4031 * A change in VMID to the stage2 page table (Stage2) invalidates
4032 * the combined stage 1&2 tlbs (EL10_1 and EL10_0).
4034 if (raw_read(env
, ri
) != value
) {
4035 uint16_t mask
= ARMMMUIdxBit_E10_1
|
4036 ARMMMUIdxBit_E10_1_PAN
|
4039 if (arm_is_secure_below_el3(env
)) {
4040 mask
>>= ARM_MMU_IDX_A_NS
;
4043 tlb_flush_by_mmuidx(cs
, mask
);
4044 raw_write(env
, ri
, value
);
4048 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
4049 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4050 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .type
= ARM_CP_ALIAS
,
4051 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
4052 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
4053 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4054 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4055 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
4056 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
4057 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
4058 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4059 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
4060 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
4061 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
4062 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
4063 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4064 .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
4069 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
4070 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
4071 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
4072 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4073 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
4074 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
4075 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
4076 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4077 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
4078 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4079 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
4080 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
4081 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
4082 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4083 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
4084 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4085 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
4086 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
4087 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4088 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4089 .writefn
= vmsa_tcr_el12_write
,
4090 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
4091 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
4092 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4093 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4094 .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
4095 .raw_writefn
= vmsa_ttbcr_raw_write
,
4096 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
4097 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
4101 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
4102 * qemu tlbs nor adjusting cached masks.
4104 static const ARMCPRegInfo ttbcr2_reginfo
= {
4105 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
4106 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4107 .type
= ARM_CP_ALIAS
,
4108 .bank_fieldoffsets
= { offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
4109 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]) },
4112 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4115 env
->cp15
.c15_ticonfig
= value
& 0xe7;
4116 /* The OS_TYPE bit in this register changes the reported CPUID! */
4117 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
4118 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
4121 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4124 env
->cp15
.c15_threadid
= value
& 0xffff;
4127 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4130 /* Wait-for-interrupt (deprecated) */
4131 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
4134 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4137 /* On OMAP there are registers indicating the max/min index of dcache lines
4138 * containing a dirty line; cache flush operations have to reset these.
4140 env
->cp15
.c15_i_max
= 0x000;
4141 env
->cp15
.c15_i_min
= 0xff0;
4144 static const ARMCPRegInfo omap_cp_reginfo
[] = {
4145 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
4146 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
4147 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
4149 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
4150 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4151 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
4153 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
4154 .writefn
= omap_ticonfig_write
},
4155 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
4157 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
4158 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
4159 .access
= PL1_RW
, .resetvalue
= 0xff0,
4160 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
4161 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
4163 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
4164 .writefn
= omap_threadid_write
},
4165 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
4166 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4167 .type
= ARM_CP_NO_RAW
,
4168 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
4169 /* TODO: Peripheral port remap register:
4170 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
4171 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
4174 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
4175 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
4176 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
4177 .writefn
= omap_cachemaint_write
},
4178 { .name
= "C9", .cp
= 15, .crn
= 9,
4179 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
4180 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
4184 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4187 env
->cp15
.c15_cpar
= value
& 0x3fff;
4190 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
4191 { .name
= "XSCALE_CPAR",
4192 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4193 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
4194 .writefn
= xscale_cpar_write
, },
4195 { .name
= "XSCALE_AUXCR",
4196 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
4197 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
4199 /* XScale specific cache-lockdown: since we have no cache we NOP these
4200 * and hope the guest does not really rely on cache behaviour.
4202 { .name
= "XSCALE_LOCK_ICACHE_LINE",
4203 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
4204 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4205 { .name
= "XSCALE_UNLOCK_ICACHE",
4206 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
4207 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4208 { .name
= "XSCALE_DCACHE_LOCK",
4209 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
4210 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4211 { .name
= "XSCALE_UNLOCK_DCACHE",
4212 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
4213 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4217 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
4218 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
4219 * implementation of this implementation-defined space.
4220 * Ideally this should eventually disappear in favour of actually
4221 * implementing the correct behaviour for all cores.
4223 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
4224 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4226 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
4231 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
4232 /* Cache status: RAZ because we have no cache so it's always clean */
4233 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
4234 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4239 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
4240 /* We never have a a block transfer operation in progress */
4241 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
4242 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4244 /* The cache ops themselves: these all NOP for QEMU */
4245 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
4246 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4247 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
4248 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4249 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
4250 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4251 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
4252 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4253 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
4254 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4255 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
4256 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
4260 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
4261 /* The cache test-and-clean instructions always return (1 << 30)
4262 * to indicate that there are no dirty cache lines.
4264 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
4265 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4266 .resetvalue
= (1 << 30) },
4267 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
4268 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4269 .resetvalue
= (1 << 30) },
4273 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
4274 /* Ignore ReadBuffer accesses */
4275 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
4276 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4277 .access
= PL1_RW
, .resetvalue
= 0,
4278 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
4282 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4284 unsigned int cur_el
= arm_current_el(env
);
4286 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4287 return env
->cp15
.vpidr_el2
;
4289 return raw_read(env
, ri
);
4292 static uint64_t mpidr_read_val(CPUARMState
*env
)
4294 ARMCPU
*cpu
= env_archcpu(env
);
4295 uint64_t mpidr
= cpu
->mp_affinity
;
4297 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
4298 mpidr
|= (1U << 31);
4299 /* Cores which are uniprocessor (non-coherent)
4300 * but still implement the MP extensions set
4301 * bit 30. (For instance, Cortex-R5).
4303 if (cpu
->mp_is_up
) {
4304 mpidr
|= (1u << 30);
4310 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4312 unsigned int cur_el
= arm_current_el(env
);
4314 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4315 return env
->cp15
.vmpidr_el2
;
4317 return mpidr_read_val(env
);
4320 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4322 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4323 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4324 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4325 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4326 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4327 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4328 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4329 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4330 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4331 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4332 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4333 offsetof(CPUARMState
, cp15
.par_ns
)} },
4334 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4335 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4336 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4337 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4338 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4339 .writefn
= vmsa_ttbr_write
, },
4340 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4341 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4342 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4343 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4344 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4345 .writefn
= vmsa_ttbr_write
, },
4349 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4351 return vfp_get_fpcr(env
);
4354 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4357 vfp_set_fpcr(env
, value
);
4360 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4362 return vfp_get_fpsr(env
);
4365 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4368 vfp_set_fpsr(env
, value
);
4371 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4374 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4375 return CP_ACCESS_TRAP
;
4377 return CP_ACCESS_OK
;
4380 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4383 env
->daif
= value
& PSTATE_DAIF
;
4386 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4388 return env
->pstate
& PSTATE_PAN
;
4391 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4394 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4397 static const ARMCPRegInfo pan_reginfo
= {
4398 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4399 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4400 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4401 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4404 static uint64_t aa64_uao_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4406 return env
->pstate
& PSTATE_UAO
;
4409 static void aa64_uao_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4412 env
->pstate
= (env
->pstate
& ~PSTATE_UAO
) | (value
& PSTATE_UAO
);
4415 static const ARMCPRegInfo uao_reginfo
= {
4416 .name
= "UAO", .state
= ARM_CP_STATE_AA64
,
4417 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 4,
4418 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4419 .readfn
= aa64_uao_read
, .writefn
= aa64_uao_write
4422 static CPAccessResult
aa64_cacheop_poc_access(CPUARMState
*env
,
4423 const ARMCPRegInfo
*ri
,
4426 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4427 switch (arm_current_el(env
)) {
4429 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4430 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4431 return CP_ACCESS_TRAP
;
4435 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4436 if (arm_hcr_el2_eff(env
) & HCR_TPCP
) {
4437 return CP_ACCESS_TRAP_EL2
;
4441 return CP_ACCESS_OK
;
4444 static CPAccessResult
aa64_cacheop_pou_access(CPUARMState
*env
,
4445 const ARMCPRegInfo
*ri
,
4448 /* Cache invalidate/clean to Point of Unification... */
4449 switch (arm_current_el(env
)) {
4451 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4452 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4453 return CP_ACCESS_TRAP
;
4457 /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */
4458 if (arm_hcr_el2_eff(env
) & HCR_TPU
) {
4459 return CP_ACCESS_TRAP_EL2
;
4463 return CP_ACCESS_OK
;
4466 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4467 * Page D4-1736 (DDI0487A.b)
4470 static int vae1_tlbmask(CPUARMState
*env
)
4472 uint64_t hcr
= arm_hcr_el2_eff(env
);
4475 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4476 mask
= ARMMMUIdxBit_E20_2
|
4477 ARMMMUIdxBit_E20_2_PAN
|
4480 mask
= ARMMMUIdxBit_E10_1
|
4481 ARMMMUIdxBit_E10_1_PAN
|
4485 if (arm_is_secure_below_el3(env
)) {
4486 mask
>>= ARM_MMU_IDX_A_NS
;
4492 /* Return 56 if TBI is enabled, 64 otherwise. */
4493 static int tlbbits_for_regime(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
4496 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
4497 int tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
4498 int select
= extract64(addr
, 55, 1);
4500 return (tbi
>> select
) & 1 ? 56 : 64;
4503 static int vae1_tlbbits(CPUARMState
*env
, uint64_t addr
)
4505 uint64_t hcr
= arm_hcr_el2_eff(env
);
4508 /* Only the regime of the mmu_idx below is significant. */
4509 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4510 mmu_idx
= ARMMMUIdx_E20_0
;
4512 mmu_idx
= ARMMMUIdx_E10_0
;
4515 if (arm_is_secure_below_el3(env
)) {
4516 mmu_idx
&= ~ARM_MMU_IDX_A_NS
;
4519 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4522 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4525 CPUState
*cs
= env_cpu(env
);
4526 int mask
= vae1_tlbmask(env
);
4528 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4531 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4534 CPUState
*cs
= env_cpu(env
);
4535 int mask
= vae1_tlbmask(env
);
4537 if (tlb_force_broadcast(env
)) {
4538 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4540 tlb_flush_by_mmuidx(cs
, mask
);
4544 static int alle1_tlbmask(CPUARMState
*env
)
4547 * Note that the 'ALL' scope must invalidate both stage 1 and
4548 * stage 2 translations, whereas most other scopes only invalidate
4549 * stage 1 translations.
4551 if (arm_is_secure_below_el3(env
)) {
4552 return ARMMMUIdxBit_SE10_1
|
4553 ARMMMUIdxBit_SE10_1_PAN
|
4554 ARMMMUIdxBit_SE10_0
;
4556 return ARMMMUIdxBit_E10_1
|
4557 ARMMMUIdxBit_E10_1_PAN
|
4562 static int e2_tlbmask(CPUARMState
*env
)
4564 if (arm_is_secure_below_el3(env
)) {
4565 return ARMMMUIdxBit_SE20_0
|
4566 ARMMMUIdxBit_SE20_2
|
4567 ARMMMUIdxBit_SE20_2_PAN
|
4570 return ARMMMUIdxBit_E20_0
|
4571 ARMMMUIdxBit_E20_2
|
4572 ARMMMUIdxBit_E20_2_PAN
|
4577 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4580 CPUState
*cs
= env_cpu(env
);
4581 int mask
= alle1_tlbmask(env
);
4583 tlb_flush_by_mmuidx(cs
, mask
);
4586 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4589 CPUState
*cs
= env_cpu(env
);
4590 int mask
= e2_tlbmask(env
);
4592 tlb_flush_by_mmuidx(cs
, mask
);
4595 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4598 ARMCPU
*cpu
= env_archcpu(env
);
4599 CPUState
*cs
= CPU(cpu
);
4601 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_SE3
);
4604 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4607 CPUState
*cs
= env_cpu(env
);
4608 int mask
= alle1_tlbmask(env
);
4610 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4613 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4616 CPUState
*cs
= env_cpu(env
);
4617 int mask
= e2_tlbmask(env
);
4619 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4622 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4625 CPUState
*cs
= env_cpu(env
);
4627 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_SE3
);
4630 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4633 /* Invalidate by VA, EL2
4634 * Currently handles both VAE2 and VALE2, since we don't support
4635 * flush-last-level-only.
4637 CPUState
*cs
= env_cpu(env
);
4638 int mask
= e2_tlbmask(env
);
4639 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4641 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4644 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4647 /* Invalidate by VA, EL3
4648 * Currently handles both VAE3 and VALE3, since we don't support
4649 * flush-last-level-only.
4651 ARMCPU
*cpu
= env_archcpu(env
);
4652 CPUState
*cs
= CPU(cpu
);
4653 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4655 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_SE3
);
4658 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4661 CPUState
*cs
= env_cpu(env
);
4662 int mask
= vae1_tlbmask(env
);
4663 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4664 int bits
= vae1_tlbbits(env
, pageaddr
);
4666 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4669 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4672 /* Invalidate by VA, EL1&0 (AArch64 version).
4673 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4674 * since we don't support flush-for-specific-ASID-only or
4675 * flush-last-level-only.
4677 CPUState
*cs
= env_cpu(env
);
4678 int mask
= vae1_tlbmask(env
);
4679 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4680 int bits
= vae1_tlbbits(env
, pageaddr
);
4682 if (tlb_force_broadcast(env
)) {
4683 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4685 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4689 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4692 CPUState
*cs
= env_cpu(env
);
4693 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4694 bool secure
= arm_is_secure_below_el3(env
);
4695 int mask
= secure
? ARMMMUIdxBit_SE2
: ARMMMUIdxBit_E2
;
4696 int bits
= tlbbits_for_regime(env
, secure
? ARMMMUIdx_E2
: ARMMMUIdx_SE2
,
4699 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4702 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4705 CPUState
*cs
= env_cpu(env
);
4706 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4707 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_SE3
, pageaddr
);
4709 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4710 ARMMMUIdxBit_SE3
, bits
);
4713 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4716 int cur_el
= arm_current_el(env
);
4719 uint64_t hcr
= arm_hcr_el2_eff(env
);
4722 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4723 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
4724 return CP_ACCESS_TRAP_EL2
;
4727 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
4728 return CP_ACCESS_TRAP
;
4730 if (hcr
& HCR_TDZ
) {
4731 return CP_ACCESS_TRAP_EL2
;
4734 } else if (hcr
& HCR_TDZ
) {
4735 return CP_ACCESS_TRAP_EL2
;
4738 return CP_ACCESS_OK
;
4741 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4743 ARMCPU
*cpu
= env_archcpu(env
);
4744 int dzp_bit
= 1 << 4;
4746 /* DZP indicates whether DC ZVA access is allowed */
4747 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
4750 return cpu
->dcz_blocksize
| dzp_bit
;
4753 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4756 if (!(env
->pstate
& PSTATE_SP
)) {
4757 /* Access to SP_EL0 is undefined if it's being used as
4758 * the stack pointer.
4760 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4762 return CP_ACCESS_OK
;
4765 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4767 return env
->pstate
& PSTATE_SP
;
4770 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
4772 update_spsel(env
, val
);
4775 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4778 ARMCPU
*cpu
= env_archcpu(env
);
4780 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
4781 /* M bit is RAZ/WI for PMSA with no MPU implemented */
4785 /* ??? Lots of these bits are not implemented. */
4787 if (ri
->state
== ARM_CP_STATE_AA64
&& !cpu_isar_feature(aa64_mte
, cpu
)) {
4788 if (ri
->opc1
== 6) { /* SCTLR_EL3 */
4789 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF
| SCTLR_ATA
);
4791 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF0
| SCTLR_TCF
|
4792 SCTLR_ATA0
| SCTLR_ATA
);
4796 if (raw_read(env
, ri
) == value
) {
4797 /* Skip the TLB flush if nothing actually changed; Linux likes
4798 * to do a lot of pointless SCTLR writes.
4803 raw_write(env
, ri
, value
);
4805 /* This may enable/disable the MMU, so do a TLB flush. */
4806 tlb_flush(CPU(cpu
));
4808 if (ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
4810 * Normally we would always end the TB on an SCTLR write; see the
4811 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
4812 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
4813 * of hflags from the translator, so do it here.
4815 arm_rebuild_hflags(env
);
4819 static CPAccessResult
fpexc32_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4822 if ((env
->cp15
.cptr_el
[2] & CPTR_TFP
) && arm_current_el(env
) == 2) {
4823 return CP_ACCESS_TRAP_FP_EL2
;
4825 if (env
->cp15
.cptr_el
[3] & CPTR_TFP
) {
4826 return CP_ACCESS_TRAP_FP_EL3
;
4828 return CP_ACCESS_OK
;
4831 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4834 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
4837 static const ARMCPRegInfo v8_cp_reginfo
[] = {
4838 /* Minimal set of EL0-visible registers. This will need to be expanded
4839 * significantly for system emulation of AArch64 CPUs.
4841 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
4842 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
4843 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
4844 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
4845 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
4846 .type
= ARM_CP_NO_RAW
,
4847 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
4848 .fieldoffset
= offsetof(CPUARMState
, daif
),
4849 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
4850 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
4851 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
4852 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4853 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
4854 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
4855 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
4856 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
4857 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
4858 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
4859 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
4860 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
4861 .readfn
= aa64_dczid_read
},
4862 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
4863 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
4864 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
4865 #ifndef CONFIG_USER_ONLY
4866 /* Avoid overhead of an access check that always passes in user-mode */
4867 .accessfn
= aa64_zva_access
,
4870 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
4871 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
4872 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
4873 /* Cache ops: all NOPs since we don't emulate caches */
4874 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
4875 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
4876 .access
= PL1_W
, .type
= ARM_CP_NOP
,
4877 .accessfn
= aa64_cacheop_pou_access
},
4878 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
4879 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
4880 .access
= PL1_W
, .type
= ARM_CP_NOP
,
4881 .accessfn
= aa64_cacheop_pou_access
},
4882 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
4883 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
4884 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4885 .accessfn
= aa64_cacheop_pou_access
},
4886 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
4887 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
4888 .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
,
4889 .type
= ARM_CP_NOP
},
4890 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
4891 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
4892 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4893 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
4894 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
4895 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4896 .accessfn
= aa64_cacheop_poc_access
},
4897 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
4898 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
4899 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4900 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
4901 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
4902 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4903 .accessfn
= aa64_cacheop_pou_access
},
4904 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
4905 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
4906 .access
= PL0_W
, .type
= ARM_CP_NOP
,
4907 .accessfn
= aa64_cacheop_poc_access
},
4908 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
4909 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
4910 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
4911 /* TLBI operations */
4912 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
4913 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
4914 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4915 .writefn
= tlbi_aa64_vmalle1is_write
},
4916 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
4917 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
4918 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4919 .writefn
= tlbi_aa64_vae1is_write
},
4920 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
4921 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
4922 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4923 .writefn
= tlbi_aa64_vmalle1is_write
},
4924 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
4925 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
4926 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4927 .writefn
= tlbi_aa64_vae1is_write
},
4928 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
4929 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
4930 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4931 .writefn
= tlbi_aa64_vae1is_write
},
4932 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
4933 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
4934 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4935 .writefn
= tlbi_aa64_vae1is_write
},
4936 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
4937 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
4938 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4939 .writefn
= tlbi_aa64_vmalle1_write
},
4940 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
4941 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
4942 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4943 .writefn
= tlbi_aa64_vae1_write
},
4944 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
4945 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
4946 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4947 .writefn
= tlbi_aa64_vmalle1_write
},
4948 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
4949 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
4950 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4951 .writefn
= tlbi_aa64_vae1_write
},
4952 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
4953 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
4954 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4955 .writefn
= tlbi_aa64_vae1_write
},
4956 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
4957 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
4958 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
4959 .writefn
= tlbi_aa64_vae1_write
},
4960 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
4961 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
4962 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4963 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
4964 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
4965 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4966 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
4967 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
4968 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4969 .writefn
= tlbi_aa64_alle1is_write
},
4970 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
4971 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
4972 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4973 .writefn
= tlbi_aa64_alle1is_write
},
4974 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
4975 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
4976 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4977 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
4978 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
4979 .access
= PL2_W
, .type
= ARM_CP_NOP
},
4980 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
4981 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
4982 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4983 .writefn
= tlbi_aa64_alle1_write
},
4984 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
4985 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
4986 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
4987 .writefn
= tlbi_aa64_alle1is_write
},
4988 #ifndef CONFIG_USER_ONLY
4989 /* 64 bit address translation operations */
4990 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
4991 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
4992 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4993 .writefn
= ats_write64
},
4994 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
4995 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
4996 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
4997 .writefn
= ats_write64
},
4998 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
4999 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
5000 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5001 .writefn
= ats_write64
},
5002 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
5003 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
5004 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5005 .writefn
= ats_write64
},
5006 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
5007 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
5008 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5009 .writefn
= ats_write64
},
5010 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
5011 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
5012 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5013 .writefn
= ats_write64
},
5014 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
5015 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
5016 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5017 .writefn
= ats_write64
},
5018 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
5019 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
5020 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5021 .writefn
= ats_write64
},
5022 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
5023 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
5024 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
5025 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5026 .writefn
= ats_write64
},
5027 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
5028 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
5029 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5030 .writefn
= ats_write64
},
5031 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
5032 .type
= ARM_CP_ALIAS
,
5033 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
5034 .access
= PL1_RW
, .resetvalue
= 0,
5035 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
5036 .writefn
= par_write
},
5038 /* TLB invalidate last level of translation table walk */
5039 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5040 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5041 .writefn
= tlbimva_is_write
},
5042 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5043 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5044 .writefn
= tlbimvaa_is_write
},
5045 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5046 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5047 .writefn
= tlbimva_write
},
5048 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5049 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5050 .writefn
= tlbimvaa_write
},
5051 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5052 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5053 .writefn
= tlbimva_hyp_write
},
5054 { .name
= "TLBIMVALHIS",
5055 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5056 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5057 .writefn
= tlbimva_hyp_is_write
},
5058 { .name
= "TLBIIPAS2",
5059 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5060 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5061 { .name
= "TLBIIPAS2IS",
5062 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5063 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5064 { .name
= "TLBIIPAS2L",
5065 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5066 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5067 { .name
= "TLBIIPAS2LIS",
5068 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5069 .type
= ARM_CP_NOP
, .access
= PL2_W
},
5070 /* 32 bit cache operations */
5071 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5072 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5073 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
5074 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5075 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5076 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5077 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
5078 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5079 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
5080 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5081 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
5082 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5083 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5084 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5085 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5086 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5087 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
5088 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5089 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5090 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5091 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
5092 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_pou_access
},
5093 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
5094 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5095 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5096 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5097 /* MMU Domain access control / MPU write buffer control */
5098 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
5099 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
5100 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5101 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
5102 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
5103 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
5104 .type
= ARM_CP_ALIAS
,
5105 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
5107 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
5108 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
5109 .type
= ARM_CP_ALIAS
,
5110 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
5112 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
5113 /* We rely on the access checks not allowing the guest to write to the
5114 * state field when SPSel indicates that it's being used as the stack
5117 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
5118 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
5119 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
5120 .type
= ARM_CP_ALIAS
,
5121 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
5122 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
5123 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
5124 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5125 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
5126 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
5127 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
5128 .type
= ARM_CP_NO_RAW
,
5129 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
5130 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
5131 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
5132 .type
= ARM_CP_ALIAS
,
5133 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]),
5134 .access
= PL2_RW
, .accessfn
= fpexc32_access
},
5135 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
5136 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
5137 .access
= PL2_RW
, .resetvalue
= 0,
5138 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5139 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
5140 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
5141 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
5142 .access
= PL2_RW
, .resetvalue
= 0,
5143 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
5144 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
5145 .type
= ARM_CP_ALIAS
,
5146 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
5148 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
5149 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
5150 .type
= ARM_CP_ALIAS
,
5151 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
5153 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
5154 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
5155 .type
= ARM_CP_ALIAS
,
5156 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
5158 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
5159 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
5160 .type
= ARM_CP_ALIAS
,
5161 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
5163 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
5164 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
5165 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
5167 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
5168 { .name
= "SDCR", .type
= ARM_CP_ALIAS
,
5169 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
5170 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5171 .writefn
= sdcr_write
,
5172 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
5176 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
5177 static const ARMCPRegInfo el3_no_el2_cp_reginfo
[] = {
5178 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5179 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
5181 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
5182 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5183 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5185 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5186 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
5187 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
5188 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5189 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
5190 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
5192 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5193 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5194 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
5195 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5196 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5197 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
5198 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5200 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
5201 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
5202 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5203 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5204 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
5205 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5207 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
5208 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
5209 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5211 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
5212 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
5213 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5215 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
5216 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
5217 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5219 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5220 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
5221 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5222 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5223 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5224 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5225 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5226 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
5227 .cp
= 15, .opc1
= 6, .crm
= 2,
5228 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5229 .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
5230 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5231 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
5232 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5233 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5234 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
5235 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5236 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5237 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
5238 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5239 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
5240 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
5241 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5242 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
5243 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
5245 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5246 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
5247 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5248 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
5249 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
5250 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5251 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
5252 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
5254 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
5255 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
5256 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5257 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
5258 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
5260 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
5261 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
5262 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5263 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5264 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
5265 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5266 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5267 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
5268 .access
= PL2_RW
, .accessfn
= access_tda
,
5269 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5270 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5271 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5272 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5273 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5274 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5275 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
5276 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5277 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5278 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
5279 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5280 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
5281 .type
= ARM_CP_CONST
,
5282 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
5283 .access
= PL2_RW
, .resetvalue
= 0 },
5287 /* Ditto, but for registers which exist in ARMv8 but not v7 */
5288 static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo
[] = {
5289 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
5290 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
5292 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5296 static void do_hcr_write(CPUARMState
*env
, uint64_t value
, uint64_t valid_mask
)
5298 ARMCPU
*cpu
= env_archcpu(env
);
5300 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5301 valid_mask
|= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5303 valid_mask
|= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5306 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5307 valid_mask
&= ~HCR_HCD
;
5308 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5309 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5310 * However, if we're using the SMC PSCI conduit then QEMU is
5311 * effectively acting like EL3 firmware and so the guest at
5312 * EL2 should retain the ability to prevent EL1 from being
5313 * able to make SMC calls into the ersatz firmware, so in
5314 * that case HCR.TSC should be read/write.
5316 valid_mask
&= ~HCR_TSC
;
5319 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5320 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5321 valid_mask
|= HCR_E2H
;
5323 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5324 valid_mask
|= HCR_TLOR
;
5326 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5327 valid_mask
|= HCR_API
| HCR_APK
;
5329 if (cpu_isar_feature(aa64_mte
, cpu
)) {
5330 valid_mask
|= HCR_ATA
| HCR_DCT
| HCR_TID5
;
5334 /* Clear RES0 bits. */
5335 value
&= valid_mask
;
5338 * These bits change the MMU setup:
5339 * HCR_VM enables stage 2 translation
5340 * HCR_PTW forbids certain page-table setups
5341 * HCR_DC disables stage1 and enables stage2 translation
5342 * HCR_DCT enables tagging on (disabled) stage1 translation
5344 if ((env
->cp15
.hcr_el2
^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
| HCR_DCT
)) {
5345 tlb_flush(CPU(cpu
));
5347 env
->cp15
.hcr_el2
= value
;
5350 * Updates to VI and VF require us to update the status of
5351 * virtual interrupts, which are the logical OR of these bits
5352 * and the state of the input lines from the GIC. (This requires
5353 * that we have the iothread lock, which is done by marking the
5354 * reginfo structs as ARM_CP_IO.)
5355 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5356 * possible for it to be taken immediately, because VIRQ and
5357 * VFIQ are masked unless running at EL0 or EL1, and HCR
5358 * can only be written at EL2.
5360 g_assert(qemu_mutex_iothread_locked());
5361 arm_cpu_update_virq(cpu
);
5362 arm_cpu_update_vfiq(cpu
);
5365 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5367 do_hcr_write(env
, value
, 0);
5370 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5373 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5374 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
5375 do_hcr_write(env
, value
, MAKE_64BIT_MASK(0, 32));
5378 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5381 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5382 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
5383 do_hcr_write(env
, value
, MAKE_64BIT_MASK(32, 32));
5387 * Return the effective value of HCR_EL2.
5388 * Bits that are not included here:
5389 * RW (read from SCR_EL3.RW as needed)
5391 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
5393 uint64_t ret
= env
->cp15
.hcr_el2
;
5395 if (!arm_is_el2_enabled(env
)) {
5397 * "This register has no effect if EL2 is not enabled in the
5398 * current Security state". This is ARMv8.4-SecEL2 speak for
5399 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5401 * Prior to that, the language was "In an implementation that
5402 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5403 * as if this field is 0 for all purposes other than a direct
5404 * read or write access of HCR_EL2". With lots of enumeration
5405 * on a per-field basis. In current QEMU, this is condition
5406 * is arm_is_secure_below_el3.
5408 * Since the v8.4 language applies to the entire register, and
5409 * appears to be backward compatible, use that.
5415 * For a cpu that supports both aarch64 and aarch32, we can set bits
5416 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5417 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5419 if (!arm_el_is_aa64(env
, 2)) {
5420 uint64_t aa32_valid
;
5423 * These bits are up-to-date as of ARMv8.6.
5424 * For HCR, it's easiest to list just the 2 bits that are invalid.
5425 * For HCR2, list those that are valid.
5427 aa32_valid
= MAKE_64BIT_MASK(0, 32) & ~(HCR_RW
| HCR_TDZ
);
5428 aa32_valid
|= (HCR_CD
| HCR_ID
| HCR_TERR
| HCR_TEA
| HCR_MIOCNCE
|
5429 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_TTLBIS
);
5433 if (ret
& HCR_TGE
) {
5434 /* These bits are up-to-date as of ARMv8.6. */
5435 if (ret
& HCR_E2H
) {
5436 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
5437 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
5438 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
5439 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
|
5440 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_ENSCXT
|
5441 HCR_TTLBIS
| HCR_TTLBOS
| HCR_TID5
);
5443 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
5445 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
5446 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
5447 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
5454 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5458 * For A-profile AArch32 EL3, if NSACR.CP10
5459 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5461 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5462 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5463 value
&= ~(0x3 << 10);
5464 value
|= env
->cp15
.cptr_el
[2] & (0x3 << 10);
5466 env
->cp15
.cptr_el
[2] = value
;
5469 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5472 * For A-profile AArch32 EL3, if NSACR.CP10
5473 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5475 uint64_t value
= env
->cp15
.cptr_el
[2];
5477 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
5478 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
5484 static const ARMCPRegInfo el2_cp_reginfo
[] = {
5485 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
5487 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5488 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5489 .writefn
= hcr_write
},
5490 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
5491 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5492 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
5493 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
5494 .writefn
= hcr_writelow
},
5495 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
5496 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
5497 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5498 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
5499 .type
= ARM_CP_ALIAS
,
5500 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
5502 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
5503 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
5504 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
5505 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
5506 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5507 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
5508 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
5509 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
5510 .type
= ARM_CP_ALIAS
,
5511 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
5513 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
5514 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
5515 .type
= ARM_CP_ALIAS
,
5516 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
5518 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
5519 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
5520 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
5521 .access
= PL2_RW
, .writefn
= vbar_write
,
5522 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
5524 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
5525 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
5526 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
5527 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
5528 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5529 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
5530 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5531 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
5532 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
5533 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5534 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
5535 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
5537 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
5538 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
5539 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
5540 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
5541 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
5542 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
5543 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5545 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
5546 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
5547 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
5548 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5550 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
5551 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
5552 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5554 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
5555 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
5556 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5558 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5559 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
5560 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
5561 /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */
5562 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
5563 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
5564 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5565 .type
= ARM_CP_ALIAS
,
5566 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5567 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5568 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
5569 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
5571 /* no .writefn needed as this can't cause an ASID change;
5572 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
5574 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
5575 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
5576 .cp
= 15, .opc1
= 6, .crm
= 2,
5577 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5578 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5579 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
5580 .writefn
= vttbr_write
},
5581 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5582 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
5583 .access
= PL2_RW
, .writefn
= vttbr_write
,
5584 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
5585 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5586 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
5587 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
5588 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
5589 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5590 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
5591 .access
= PL2_RW
, .resetvalue
= 0,
5592 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
5593 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
5594 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
5595 .access
= PL2_RW
, .resetvalue
= 0, .writefn
= vmsa_tcr_ttbr_el2_write
,
5596 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5597 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
5598 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
5599 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
5600 { .name
= "TLBIALLNSNH",
5601 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5602 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5603 .writefn
= tlbiall_nsnh_write
},
5604 { .name
= "TLBIALLNSNHIS",
5605 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5606 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5607 .writefn
= tlbiall_nsnh_is_write
},
5608 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5609 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5610 .writefn
= tlbiall_hyp_write
},
5611 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5612 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5613 .writefn
= tlbiall_hyp_is_write
},
5614 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5615 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5616 .writefn
= tlbimva_hyp_write
},
5617 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5618 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5619 .writefn
= tlbimva_hyp_is_write
},
5620 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
5621 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
5622 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5623 .writefn
= tlbi_aa64_alle2_write
},
5624 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
5625 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
5626 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5627 .writefn
= tlbi_aa64_vae2_write
},
5628 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
5629 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5630 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5631 .writefn
= tlbi_aa64_vae2_write
},
5632 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
5633 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
5634 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5635 .writefn
= tlbi_aa64_alle2is_write
},
5636 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
5637 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
5638 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5639 .writefn
= tlbi_aa64_vae2is_write
},
5640 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
5641 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5642 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5643 .writefn
= tlbi_aa64_vae2is_write
},
5644 #ifndef CONFIG_USER_ONLY
5645 /* Unlike the other EL2-related AT operations, these must
5646 * UNDEF from EL3 if EL2 is not implemented, which is why we
5647 * define them here rather than with the rest of the AT ops.
5649 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
5650 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5651 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5652 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
, .writefn
= ats_write64
},
5653 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
5654 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5655 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
5656 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
, .writefn
= ats_write64
},
5657 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
5658 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
5659 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
5660 * to behave as if SCR.NS was 1.
5662 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
5664 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5665 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
5667 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
5668 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5669 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
5670 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
5671 * reset values as IMPDEF. We choose to reset to 3 to comply with
5672 * both ARMv7 and ARMv8.
5674 .access
= PL2_RW
, .resetvalue
= 3,
5675 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
5676 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
5677 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
5678 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
5679 .writefn
= gt_cntvoff_write
,
5680 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5681 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
5682 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
5683 .writefn
= gt_cntvoff_write
,
5684 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
5685 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
5686 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
5687 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5688 .type
= ARM_CP_IO
, .access
= PL2_RW
,
5689 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5690 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
5691 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
5692 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
5693 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
5694 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
5695 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
5696 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
5697 .resetfn
= gt_hyp_timer_reset
,
5698 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
5699 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
5701 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
5703 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
5705 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
5707 /* The only field of MDCR_EL2 that has a defined architectural reset value
5708 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
5709 * don't implement any PMU event counters, so using zero as a reset
5710 * value for MDCR_EL2 is okay
5712 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
5713 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
5714 .access
= PL2_RW
, .resetvalue
= 0,
5715 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
), },
5716 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
5717 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5718 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
5719 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5720 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
5721 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
5723 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
5724 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
5725 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
5727 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
5731 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
5732 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
5733 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5734 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
5736 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
5737 .writefn
= hcr_writehigh
},
5741 static CPAccessResult
sel2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5744 if (arm_current_el(env
) == 3 || arm_is_secure_below_el3(env
)) {
5745 return CP_ACCESS_OK
;
5747 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5750 static const ARMCPRegInfo el2_sec_cp_reginfo
[] = {
5751 { .name
= "VSTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
5752 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 0,
5753 .access
= PL2_RW
, .accessfn
= sel2_access
,
5754 .fieldoffset
= offsetof(CPUARMState
, cp15
.vsttbr_el2
) },
5755 { .name
= "VSTCR_EL2", .state
= ARM_CP_STATE_AA64
,
5756 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 2,
5757 .access
= PL2_RW
, .accessfn
= sel2_access
,
5758 .fieldoffset
= offsetof(CPUARMState
, cp15
.vstcr_el2
) },
5762 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5765 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
5766 * At Secure EL1 it traps to EL3 or EL2.
5768 if (arm_current_el(env
) == 3) {
5769 return CP_ACCESS_OK
;
5771 if (arm_is_secure_below_el3(env
)) {
5772 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
5773 return CP_ACCESS_TRAP_EL2
;
5775 return CP_ACCESS_TRAP_EL3
;
5777 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
5779 return CP_ACCESS_OK
;
5781 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5784 static const ARMCPRegInfo el3_cp_reginfo
[] = {
5785 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
5786 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
5787 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
5788 .resetvalue
= 0, .writefn
= scr_write
},
5789 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
5790 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
5791 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5792 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
5793 .writefn
= scr_write
},
5794 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
5795 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
5796 .access
= PL3_RW
, .resetvalue
= 0,
5797 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
5799 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
5800 .access
= PL3_RW
, .resetvalue
= 0,
5801 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
5802 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
5803 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5804 .writefn
= vbar_write
, .resetvalue
= 0,
5805 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
5806 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
5807 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
5808 .access
= PL3_RW
, .resetvalue
= 0,
5809 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
5810 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
5811 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
5813 /* no .writefn needed as this can't cause an ASID change;
5814 * we must provide a .raw_writefn and .resetfn because we handle
5815 * reset and migration for the AArch32 TTBCR(S), which might be
5816 * using mask and base_mask.
5818 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
5819 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
5820 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
5821 .type
= ARM_CP_ALIAS
,
5822 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
5824 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
5825 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
5826 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
5827 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
5828 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
5829 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
5830 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
5831 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
5832 .type
= ARM_CP_ALIAS
,
5833 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
5835 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
5836 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
5837 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
5838 .access
= PL3_RW
, .writefn
= vbar_write
,
5839 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
5841 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
5842 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
5843 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
5844 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
5845 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
5846 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
5847 .access
= PL3_RW
, .resetvalue
= 0,
5848 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
5849 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
5850 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
5851 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5853 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
5854 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
5855 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5857 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
5858 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
5859 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5861 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
5862 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
5863 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5864 .writefn
= tlbi_aa64_alle3is_write
},
5865 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
5866 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
5867 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5868 .writefn
= tlbi_aa64_vae3is_write
},
5869 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
5870 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
5871 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5872 .writefn
= tlbi_aa64_vae3is_write
},
5873 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
5874 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
5875 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5876 .writefn
= tlbi_aa64_alle3_write
},
5877 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
5878 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
5879 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5880 .writefn
= tlbi_aa64_vae3_write
},
5881 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
5882 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
5883 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
5884 .writefn
= tlbi_aa64_vae3_write
},
5888 #ifndef CONFIG_USER_ONLY
5889 /* Test if system register redirection is to occur in the current state. */
5890 static bool redirect_for_e2h(CPUARMState
*env
)
5892 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
5895 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5899 if (redirect_for_e2h(env
)) {
5900 /* Switch to the saved EL2 version of the register. */
5902 readfn
= ri
->readfn
;
5904 readfn
= ri
->orig_readfn
;
5906 if (readfn
== NULL
) {
5909 return readfn(env
, ri
);
5912 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5917 if (redirect_for_e2h(env
)) {
5918 /* Switch to the saved EL2 version of the register. */
5920 writefn
= ri
->writefn
;
5922 writefn
= ri
->orig_writefn
;
5924 if (writefn
== NULL
) {
5925 writefn
= raw_write
;
5927 writefn(env
, ri
, value
);
5930 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
5933 uint32_t src_key
, dst_key
, new_key
;
5934 const char *src_name
, *dst_name
, *new_name
;
5935 bool (*feature
)(const ARMISARegisters
*id
);
5938 #define K(op0, op1, crn, crm, op2) \
5939 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
5941 static const struct E2HAlias aliases
[] = {
5942 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
5943 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
5944 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
5945 "CPACR", "CPTR_EL2", "CPACR_EL12" },
5946 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
5947 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
5948 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
5949 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
5950 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
5951 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
5952 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
5953 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
5954 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
5955 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
5956 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
5957 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
5958 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
5959 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
5960 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
5961 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
5962 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
5963 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
5964 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
5965 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
5966 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
5967 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
5968 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
5969 "VBAR", "VBAR_EL2", "VBAR_EL12" },
5970 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
5971 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
5972 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
5973 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
5976 * Note that redirection of ZCR is mentioned in the description
5977 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
5978 * not in the summary table.
5980 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
5981 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
5983 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
5984 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte
},
5986 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
5987 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
5993 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
5994 const struct E2HAlias
*a
= &aliases
[i
];
5995 ARMCPRegInfo
*src_reg
, *dst_reg
;
5997 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
6001 src_reg
= g_hash_table_lookup(cpu
->cp_regs
, &a
->src_key
);
6002 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
, &a
->dst_key
);
6003 g_assert(src_reg
!= NULL
);
6004 g_assert(dst_reg
!= NULL
);
6006 /* Cross-compare names to detect typos in the keys. */
6007 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
6008 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
6010 /* None of the core system registers use opaque; we will. */
6011 g_assert(src_reg
->opaque
== NULL
);
6013 /* Create alias before redirection so we dup the right data. */
6015 ARMCPRegInfo
*new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
6016 uint32_t *new_key
= g_memdup(&a
->new_key
, sizeof(uint32_t));
6019 new_reg
->name
= a
->new_name
;
6020 new_reg
->type
|= ARM_CP_ALIAS
;
6021 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
6022 new_reg
->access
&= PL2_RW
| PL3_RW
;
6024 ok
= g_hash_table_insert(cpu
->cp_regs
, new_key
, new_reg
);
6028 src_reg
->opaque
= dst_reg
;
6029 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
6030 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
6031 if (!src_reg
->raw_readfn
) {
6032 src_reg
->raw_readfn
= raw_read
;
6034 if (!src_reg
->raw_writefn
) {
6035 src_reg
->raw_writefn
= raw_write
;
6037 src_reg
->readfn
= el2_e2h_read
;
6038 src_reg
->writefn
= el2_e2h_write
;
6043 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6046 int cur_el
= arm_current_el(env
);
6049 uint64_t hcr
= arm_hcr_el2_eff(env
);
6052 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
6053 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
6054 return CP_ACCESS_TRAP_EL2
;
6057 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
6058 return CP_ACCESS_TRAP
;
6060 if (hcr
& HCR_TID2
) {
6061 return CP_ACCESS_TRAP_EL2
;
6064 } else if (hcr
& HCR_TID2
) {
6065 return CP_ACCESS_TRAP_EL2
;
6069 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
6070 return CP_ACCESS_TRAP_EL2
;
6073 return CP_ACCESS_OK
;
6076 static void oslar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6079 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
6080 * read via a bit in OSLSR_EL1.
6084 if (ri
->state
== ARM_CP_STATE_AA32
) {
6085 oslock
= (value
== 0xC5ACCE55);
6090 env
->cp15
.oslsr_el1
= deposit32(env
->cp15
.oslsr_el1
, 1, 1, oslock
);
6093 static const ARMCPRegInfo debug_cp_reginfo
[] = {
6094 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
6095 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
6096 * unlike DBGDRAR it is never accessible from EL0.
6097 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
6100 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
6101 .access
= PL0_R
, .accessfn
= access_tdra
,
6102 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6103 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
6104 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
6105 .access
= PL1_R
, .accessfn
= access_tdra
,
6106 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6107 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
6108 .access
= PL0_R
, .accessfn
= access_tdra
,
6109 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6110 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
6111 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
6112 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
6113 .access
= PL1_RW
, .accessfn
= access_tda
,
6114 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
6116 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
6117 * We don't implement the configurable EL0 access.
6119 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_BOTH
,
6120 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
6121 .type
= ARM_CP_ALIAS
,
6122 .access
= PL1_R
, .accessfn
= access_tda
,
6123 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
6124 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
6125 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
6126 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
6127 .accessfn
= access_tdosa
,
6128 .writefn
= oslar_write
},
6129 { .name
= "OSLSR_EL1", .state
= ARM_CP_STATE_BOTH
,
6130 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 4,
6131 .access
= PL1_R
, .resetvalue
= 10,
6132 .accessfn
= access_tdosa
,
6133 .fieldoffset
= offsetof(CPUARMState
, cp15
.oslsr_el1
) },
6134 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
6135 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
6136 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
6137 .access
= PL1_RW
, .accessfn
= access_tdosa
,
6138 .type
= ARM_CP_NOP
},
6139 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
6140 * implement vector catch debug events yet.
6143 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
6144 .access
= PL1_RW
, .accessfn
= access_tda
,
6145 .type
= ARM_CP_NOP
},
6146 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
6147 * to save and restore a 32-bit guest's DBGVCR)
6149 { .name
= "DBGVCR32_EL2", .state
= ARM_CP_STATE_AA64
,
6150 .opc0
= 2, .opc1
= 4, .crn
= 0, .crm
= 7, .opc2
= 0,
6151 .access
= PL2_RW
, .accessfn
= access_tda
,
6152 .type
= ARM_CP_NOP
},
6153 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
6154 * Channel but Linux may try to access this register. The 32-bit
6155 * alias is DBGDCCINT.
6157 { .name
= "MDCCINT_EL1", .state
= ARM_CP_STATE_BOTH
,
6158 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
6159 .access
= PL1_RW
, .accessfn
= access_tda
,
6160 .type
= ARM_CP_NOP
},
6164 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
6165 /* 64 bit access versions of the (dummy) debug registers */
6166 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
6167 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
6168 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
6169 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
6173 /* Return the exception level to which exceptions should be taken
6174 * via SVEAccessTrap. If an exception should be routed through
6175 * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
6176 * take care of raising that exception.
6177 * C.f. the ARM pseudocode function CheckSVEEnabled.
6179 int sve_exception_el(CPUARMState
*env
, int el
)
6181 #ifndef CONFIG_USER_ONLY
6182 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
6184 if (el
<= 1 && (hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
6185 bool disabled
= false;
6187 /* The CPACR.ZEN controls traps to EL1:
6188 * 0, 2 : trap EL0 and EL1 accesses
6189 * 1 : trap only EL0 accesses
6190 * 3 : trap no accesses
6192 if (!extract32(env
->cp15
.cpacr_el1
, 16, 1)) {
6194 } else if (!extract32(env
->cp15
.cpacr_el1
, 17, 1)) {
6199 return hcr_el2
& HCR_TGE
? 2 : 1;
6202 /* Check CPACR.FPEN. */
6203 if (!extract32(env
->cp15
.cpacr_el1
, 20, 1)) {
6205 } else if (!extract32(env
->cp15
.cpacr_el1
, 21, 1)) {
6213 /* CPTR_EL2. Since TZ and TFP are positive,
6214 * they will be zero when EL2 is not present.
6216 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6217 if (env
->cp15
.cptr_el
[2] & CPTR_TZ
) {
6220 if (env
->cp15
.cptr_el
[2] & CPTR_TFP
) {
6225 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6226 if (arm_feature(env
, ARM_FEATURE_EL3
)
6227 && !(env
->cp15
.cptr_el
[3] & CPTR_EZ
)) {
6234 static uint32_t sve_zcr_get_valid_len(ARMCPU
*cpu
, uint32_t start_len
)
6238 end_len
= start_len
&= 0xf;
6239 if (!test_bit(start_len
, cpu
->sve_vq_map
)) {
6240 end_len
= find_last_bit(cpu
->sve_vq_map
, start_len
);
6241 assert(end_len
< start_len
);
6247 * Given that SVE is enabled, return the vector length for EL.
6249 uint32_t sve_zcr_len_for_el(CPUARMState
*env
, int el
)
6251 ARMCPU
*cpu
= env_archcpu(env
);
6252 uint32_t zcr_len
= cpu
->sve_max_vq
- 1;
6255 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[1]);
6257 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
6258 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[2]);
6260 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6261 zcr_len
= MIN(zcr_len
, 0xf & (uint32_t)env
->vfp
.zcr_el
[3]);
6264 return sve_zcr_get_valid_len(cpu
, zcr_len
);
6267 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6270 int cur_el
= arm_current_el(env
);
6271 int old_len
= sve_zcr_len_for_el(env
, cur_el
);
6274 /* Bits other than [3:0] are RAZ/WI. */
6275 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
6276 raw_write(env
, ri
, value
& 0xf);
6279 * Because we arrived here, we know both FP and SVE are enabled;
6280 * otherwise we would have trapped access to the ZCR_ELn register.
6282 new_len
= sve_zcr_len_for_el(env
, cur_el
);
6283 if (new_len
< old_len
) {
6284 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6288 static const ARMCPRegInfo zcr_el1_reginfo
= {
6289 .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
6290 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
6291 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
6292 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
6293 .writefn
= zcr_write
, .raw_writefn
= raw_write
6296 static const ARMCPRegInfo zcr_el2_reginfo
= {
6297 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
6298 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
6299 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
6300 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
6301 .writefn
= zcr_write
, .raw_writefn
= raw_write
6304 static const ARMCPRegInfo zcr_no_el2_reginfo
= {
6305 .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
6306 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
6307 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
6308 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
6311 static const ARMCPRegInfo zcr_el3_reginfo
= {
6312 .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
6313 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
6314 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
6315 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
6316 .writefn
= zcr_write
, .raw_writefn
= raw_write
6319 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
6321 CPUARMState
*env
= &cpu
->env
;
6323 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
6324 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
6326 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
6328 if (env
->cpu_watchpoint
[n
]) {
6329 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
6330 env
->cpu_watchpoint
[n
] = NULL
;
6333 if (!extract64(wcr
, 0, 1)) {
6334 /* E bit clear : watchpoint disabled */
6338 switch (extract64(wcr
, 3, 2)) {
6340 /* LSC 00 is reserved and must behave as if the wp is disabled */
6343 flags
|= BP_MEM_READ
;
6346 flags
|= BP_MEM_WRITE
;
6349 flags
|= BP_MEM_ACCESS
;
6353 /* Attempts to use both MASK and BAS fields simultaneously are
6354 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
6355 * thus generating a watchpoint for every byte in the masked region.
6357 mask
= extract64(wcr
, 24, 4);
6358 if (mask
== 1 || mask
== 2) {
6359 /* Reserved values of MASK; we must act as if the mask value was
6360 * some non-reserved value, or as if the watchpoint were disabled.
6361 * We choose the latter.
6365 /* Watchpoint covers an aligned area up to 2GB in size */
6367 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
6368 * whether the watchpoint fires when the unmasked bits match; we opt
6369 * to generate the exceptions.
6373 /* Watchpoint covers bytes defined by the byte address select bits */
6374 int bas
= extract64(wcr
, 5, 8);
6377 if (extract64(wvr
, 2, 1)) {
6378 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
6379 * ignored, and BAS[3:0] define which bytes to watch.
6385 /* This must act as if the watchpoint is disabled */
6389 /* The BAS bits are supposed to be programmed to indicate a contiguous
6390 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
6391 * we fire for each byte in the word/doubleword addressed by the WVR.
6392 * We choose to ignore any non-zero bits after the first range of 1s.
6394 basstart
= ctz32(bas
);
6395 len
= cto32(bas
>> basstart
);
6399 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
6400 &env
->cpu_watchpoint
[n
]);
6403 void hw_watchpoint_update_all(ARMCPU
*cpu
)
6406 CPUARMState
*env
= &cpu
->env
;
6408 /* Completely clear out existing QEMU watchpoints and our array, to
6409 * avoid possible stale entries following migration load.
6411 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
6412 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
6414 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
6415 hw_watchpoint_update(cpu
, i
);
6419 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6422 ARMCPU
*cpu
= env_archcpu(env
);
6425 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
6426 * register reads and behaves as if values written are sign extended.
6427 * Bits [1:0] are RES0.
6429 value
= sextract64(value
, 0, 49) & ~3ULL;
6431 raw_write(env
, ri
, value
);
6432 hw_watchpoint_update(cpu
, i
);
6435 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6438 ARMCPU
*cpu
= env_archcpu(env
);
6441 raw_write(env
, ri
, value
);
6442 hw_watchpoint_update(cpu
, i
);
6445 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
6447 CPUARMState
*env
= &cpu
->env
;
6448 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
6449 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
6454 if (env
->cpu_breakpoint
[n
]) {
6455 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
6456 env
->cpu_breakpoint
[n
] = NULL
;
6459 if (!extract64(bcr
, 0, 1)) {
6460 /* E bit clear : watchpoint disabled */
6464 bt
= extract64(bcr
, 20, 4);
6467 case 4: /* unlinked address mismatch (reserved if AArch64) */
6468 case 5: /* linked address mismatch (reserved if AArch64) */
6469 qemu_log_mask(LOG_UNIMP
,
6470 "arm: address mismatch breakpoint types not implemented\n");
6472 case 0: /* unlinked address match */
6473 case 1: /* linked address match */
6475 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
6476 * we behave as if the register was sign extended. Bits [1:0] are
6477 * RES0. The BAS field is used to allow setting breakpoints on 16
6478 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
6479 * a bp will fire if the addresses covered by the bp and the addresses
6480 * covered by the insn overlap but the insn doesn't start at the
6481 * start of the bp address range. We choose to require the insn and
6482 * the bp to have the same address. The constraints on writing to
6483 * BAS enforced in dbgbcr_write mean we have only four cases:
6484 * 0b0000 => no breakpoint
6485 * 0b0011 => breakpoint on addr
6486 * 0b1100 => breakpoint on addr + 2
6487 * 0b1111 => breakpoint on addr
6488 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
6490 int bas
= extract64(bcr
, 5, 4);
6491 addr
= sextract64(bvr
, 0, 49) & ~3ULL;
6500 case 2: /* unlinked context ID match */
6501 case 8: /* unlinked VMID match (reserved if no EL2) */
6502 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
6503 qemu_log_mask(LOG_UNIMP
,
6504 "arm: unlinked context breakpoint types not implemented\n");
6506 case 9: /* linked VMID match (reserved if no EL2) */
6507 case 11: /* linked context ID and VMID match (reserved if no EL2) */
6508 case 3: /* linked context ID match */
6510 /* We must generate no events for Linked context matches (unless
6511 * they are linked to by some other bp/wp, which is handled in
6512 * updates for the linking bp/wp). We choose to also generate no events
6513 * for reserved values.
6518 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
6521 void hw_breakpoint_update_all(ARMCPU
*cpu
)
6524 CPUARMState
*env
= &cpu
->env
;
6526 /* Completely clear out existing QEMU breakpoints and our array, to
6527 * avoid possible stale entries following migration load.
6529 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
6530 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
6532 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
6533 hw_breakpoint_update(cpu
, i
);
6537 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6540 ARMCPU
*cpu
= env_archcpu(env
);
6543 raw_write(env
, ri
, value
);
6544 hw_breakpoint_update(cpu
, i
);
6547 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6550 ARMCPU
*cpu
= env_archcpu(env
);
6553 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
6556 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
6557 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
6559 raw_write(env
, ri
, value
);
6560 hw_breakpoint_update(cpu
, i
);
6563 static void define_debug_regs(ARMCPU
*cpu
)
6565 /* Define v7 and v8 architectural debug registers.
6566 * These are just dummy implementations for now.
6569 int wrps
, brps
, ctx_cmps
;
6572 * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot
6573 * use AArch32. Given that bit 15 is RES1, if the value is 0 then
6574 * the register must not exist for this cpu.
6576 if (cpu
->isar
.dbgdidr
!= 0) {
6577 ARMCPRegInfo dbgdidr
= {
6578 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0,
6579 .opc1
= 0, .opc2
= 0,
6580 .access
= PL0_R
, .accessfn
= access_tda
,
6581 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->isar
.dbgdidr
,
6583 define_one_arm_cp_reg(cpu
, &dbgdidr
);
6586 /* Note that all these register fields hold "number of Xs minus 1". */
6587 brps
= arm_num_brps(cpu
);
6588 wrps
= arm_num_wrps(cpu
);
6589 ctx_cmps
= arm_num_ctx_cmps(cpu
);
6591 assert(ctx_cmps
<= brps
);
6593 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
6595 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
6596 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
6599 for (i
= 0; i
< brps
; i
++) {
6600 ARMCPRegInfo dbgregs
[] = {
6601 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
6602 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
6603 .access
= PL1_RW
, .accessfn
= access_tda
,
6604 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
6605 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
6607 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
6608 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
6609 .access
= PL1_RW
, .accessfn
= access_tda
,
6610 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
6611 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
6615 define_arm_cp_regs(cpu
, dbgregs
);
6618 for (i
= 0; i
< wrps
; i
++) {
6619 ARMCPRegInfo dbgregs
[] = {
6620 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
6621 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
6622 .access
= PL1_RW
, .accessfn
= access_tda
,
6623 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
6624 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
6626 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
6627 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
6628 .access
= PL1_RW
, .accessfn
= access_tda
,
6629 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
6630 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
6634 define_arm_cp_regs(cpu
, dbgregs
);
6638 static void define_pmu_regs(ARMCPU
*cpu
)
6641 * v7 performance monitor control register: same implementor
6642 * field as main ID register, and we implement four counters in
6643 * addition to the cycle count register.
6645 unsigned int i
, pmcrn
= 4;
6646 ARMCPRegInfo pmcr
= {
6647 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
6649 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6650 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
6651 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
6652 .raw_writefn
= raw_write
,
6654 ARMCPRegInfo pmcr64
= {
6655 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
6656 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
6657 .access
= PL0_RW
, .accessfn
= pmreg_access
,
6659 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
6660 .resetvalue
= (cpu
->midr
& 0xff000000) | (pmcrn
<< PMCRN_SHIFT
) |
6662 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
6664 define_one_arm_cp_reg(cpu
, &pmcr
);
6665 define_one_arm_cp_reg(cpu
, &pmcr64
);
6666 for (i
= 0; i
< pmcrn
; i
++) {
6667 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
6668 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
6669 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
6670 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
6671 ARMCPRegInfo pmev_regs
[] = {
6672 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
6673 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6674 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6675 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6676 .accessfn
= pmreg_access
},
6677 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
6678 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
6679 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6681 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
6682 .raw_readfn
= pmevcntr_rawread
,
6683 .raw_writefn
= pmevcntr_rawwrite
},
6684 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
6685 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
6686 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
6687 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6688 .accessfn
= pmreg_access
},
6689 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
6690 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
6691 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
6693 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
6694 .raw_writefn
= pmevtyper_rawwrite
},
6697 define_arm_cp_regs(cpu
, pmev_regs
);
6698 g_free(pmevcntr_name
);
6699 g_free(pmevcntr_el0_name
);
6700 g_free(pmevtyper_name
);
6701 g_free(pmevtyper_el0_name
);
6703 if (cpu_isar_feature(aa32_pmu_8_1
, cpu
)) {
6704 ARMCPRegInfo v81_pmu_regs
[] = {
6705 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
6706 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
6707 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6708 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
6709 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
6710 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
6711 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6712 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
6715 define_arm_cp_regs(cpu
, v81_pmu_regs
);
6717 if (cpu_isar_feature(any_pmu_8_4
, cpu
)) {
6718 static const ARMCPRegInfo v84_pmmir
= {
6719 .name
= "PMMIR_EL1", .state
= ARM_CP_STATE_BOTH
,
6720 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 6,
6721 .access
= PL1_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
6724 define_one_arm_cp_reg(cpu
, &v84_pmmir
);
6728 /* We don't know until after realize whether there's a GICv3
6729 * attached, and that is what registers the gicv3 sysregs.
6730 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
6733 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6735 ARMCPU
*cpu
= env_archcpu(env
);
6736 uint64_t pfr1
= cpu
->isar
.id_pfr1
;
6738 if (env
->gicv3state
) {
6744 #ifndef CONFIG_USER_ONLY
6745 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6747 ARMCPU
*cpu
= env_archcpu(env
);
6748 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
6750 if (env
->gicv3state
) {
6757 /* Shared logic between LORID and the rest of the LOR* registers.
6758 * Secure state exclusion has already been dealt with.
6760 static CPAccessResult
access_lor_ns(CPUARMState
*env
,
6761 const ARMCPRegInfo
*ri
, bool isread
)
6763 int el
= arm_current_el(env
);
6765 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
6766 return CP_ACCESS_TRAP_EL2
;
6768 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
6769 return CP_ACCESS_TRAP_EL3
;
6771 return CP_ACCESS_OK
;
6774 static CPAccessResult
access_lor_other(CPUARMState
*env
,
6775 const ARMCPRegInfo
*ri
, bool isread
)
6777 if (arm_is_secure_below_el3(env
)) {
6778 /* Access denied in secure mode. */
6779 return CP_ACCESS_TRAP
;
6781 return access_lor_ns(env
, ri
, isread
);
6785 * A trivial implementation of ARMv8.1-LOR leaves all of these
6786 * registers fixed at 0, which indicates that there are zero
6787 * supported Limited Ordering regions.
6789 static const ARMCPRegInfo lor_reginfo
[] = {
6790 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
6791 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
6792 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6793 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6794 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
6795 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
6796 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6797 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6798 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
6799 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
6800 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6801 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6802 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
6803 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
6804 .access
= PL1_RW
, .accessfn
= access_lor_other
,
6805 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6806 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
6807 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
6808 .access
= PL1_R
, .accessfn
= access_lor_ns
,
6809 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6813 #ifdef TARGET_AARCH64
6814 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6817 int el
= arm_current_el(env
);
6820 arm_feature(env
, ARM_FEATURE_EL2
) &&
6821 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
6822 return CP_ACCESS_TRAP_EL2
;
6825 arm_feature(env
, ARM_FEATURE_EL3
) &&
6826 !(env
->cp15
.scr_el3
& SCR_APK
)) {
6827 return CP_ACCESS_TRAP_EL3
;
6829 return CP_ACCESS_OK
;
6832 static const ARMCPRegInfo pauth_reginfo
[] = {
6833 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6834 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
6835 .access
= PL1_RW
, .accessfn
= access_pauth
,
6836 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
6837 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6838 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
6839 .access
= PL1_RW
, .accessfn
= access_pauth
,
6840 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
6841 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6842 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
6843 .access
= PL1_RW
, .accessfn
= access_pauth
,
6844 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
6845 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6846 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
6847 .access
= PL1_RW
, .accessfn
= access_pauth
,
6848 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
6849 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6850 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
6851 .access
= PL1_RW
, .accessfn
= access_pauth
,
6852 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
6853 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6854 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
6855 .access
= PL1_RW
, .accessfn
= access_pauth
,
6856 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
6857 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6858 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
6859 .access
= PL1_RW
, .accessfn
= access_pauth
,
6860 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
6861 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6862 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
6863 .access
= PL1_RW
, .accessfn
= access_pauth
,
6864 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
6865 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
6866 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
6867 .access
= PL1_RW
, .accessfn
= access_pauth
,
6868 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
6869 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
6870 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
6871 .access
= PL1_RW
, .accessfn
= access_pauth
,
6872 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
6876 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6881 /* Success sets NZCV = 0000. */
6882 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
6884 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
6886 * ??? Failed, for unknown reasons in the crypto subsystem.
6887 * The best we can do is log the reason and return the
6888 * timed-out indication to the guest. There is no reason
6889 * we know to expect this failure to be transitory, so the
6890 * guest may well hang retrying the operation.
6892 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
6893 ri
->name
, error_get_pretty(err
));
6896 env
->ZF
= 0; /* NZCF = 0100 */
6902 /* We do not support re-seeding, so the two registers operate the same. */
6903 static const ARMCPRegInfo rndr_reginfo
[] = {
6904 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
6905 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
6906 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
6907 .access
= PL0_R
, .readfn
= rndr_readfn
},
6908 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
6909 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
6910 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
6911 .access
= PL0_R
, .readfn
= rndr_readfn
},
6915 #ifndef CONFIG_USER_ONLY
6916 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
6919 ARMCPU
*cpu
= env_archcpu(env
);
6920 /* CTR_EL0 System register -> DminLine, bits [19:16] */
6921 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
6922 uint64_t vaddr_in
= (uint64_t) value
;
6923 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
6925 int mem_idx
= cpu_mmu_index(env
, false);
6927 /* This won't be crossing page boundaries */
6928 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
6934 /* RCU lock is already being held */
6935 mr
= memory_region_from_host(haddr
, &offset
);
6938 memory_region_writeback(mr
, offset
, dline_size
);
6943 static const ARMCPRegInfo dcpop_reg
[] = {
6944 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
6945 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
6946 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
6947 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
6951 static const ARMCPRegInfo dcpodp_reg
[] = {
6952 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
6953 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
6954 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
6955 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
6958 #endif /*CONFIG_USER_ONLY*/
6960 static CPAccessResult
access_aa64_tid5(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6963 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID5
)) {
6964 return CP_ACCESS_TRAP_EL2
;
6967 return CP_ACCESS_OK
;
6970 static CPAccessResult
access_mte(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6973 int el
= arm_current_el(env
);
6975 if (el
< 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
6976 uint64_t hcr
= arm_hcr_el2_eff(env
);
6977 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
6978 return CP_ACCESS_TRAP_EL2
;
6982 arm_feature(env
, ARM_FEATURE_EL3
) &&
6983 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
6984 return CP_ACCESS_TRAP_EL3
;
6986 return CP_ACCESS_OK
;
6989 static uint64_t tco_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6991 return env
->pstate
& PSTATE_TCO
;
6994 static void tco_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
6996 env
->pstate
= (env
->pstate
& ~PSTATE_TCO
) | (val
& PSTATE_TCO
);
6999 static const ARMCPRegInfo mte_reginfo
[] = {
7000 { .name
= "TFSRE0_EL1", .state
= ARM_CP_STATE_AA64
,
7001 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 1,
7002 .access
= PL1_RW
, .accessfn
= access_mte
,
7003 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[0]) },
7004 { .name
= "TFSR_EL1", .state
= ARM_CP_STATE_AA64
,
7005 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 0,
7006 .access
= PL1_RW
, .accessfn
= access_mte
,
7007 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[1]) },
7008 { .name
= "TFSR_EL2", .state
= ARM_CP_STATE_AA64
,
7009 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 6, .opc2
= 0,
7010 .access
= PL2_RW
, .accessfn
= access_mte
,
7011 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[2]) },
7012 { .name
= "TFSR_EL3", .state
= ARM_CP_STATE_AA64
,
7013 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 6, .opc2
= 0,
7015 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[3]) },
7016 { .name
= "RGSR_EL1", .state
= ARM_CP_STATE_AA64
,
7017 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 5,
7018 .access
= PL1_RW
, .accessfn
= access_mte
,
7019 .fieldoffset
= offsetof(CPUARMState
, cp15
.rgsr_el1
) },
7020 { .name
= "GCR_EL1", .state
= ARM_CP_STATE_AA64
,
7021 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 6,
7022 .access
= PL1_RW
, .accessfn
= access_mte
,
7023 .fieldoffset
= offsetof(CPUARMState
, cp15
.gcr_el1
) },
7024 { .name
= "GMID_EL1", .state
= ARM_CP_STATE_AA64
,
7025 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 4,
7026 .access
= PL1_R
, .accessfn
= access_aa64_tid5
,
7027 .type
= ARM_CP_CONST
, .resetvalue
= GMID_EL1_BS
},
7028 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7029 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7030 .type
= ARM_CP_NO_RAW
,
7031 .access
= PL0_RW
, .readfn
= tco_read
, .writefn
= tco_write
},
7032 { .name
= "DC_IGVAC", .state
= ARM_CP_STATE_AA64
,
7033 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 3,
7034 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7035 .accessfn
= aa64_cacheop_poc_access
},
7036 { .name
= "DC_IGSW", .state
= ARM_CP_STATE_AA64
,
7037 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 4,
7038 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7039 { .name
= "DC_IGDVAC", .state
= ARM_CP_STATE_AA64
,
7040 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 5,
7041 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7042 .accessfn
= aa64_cacheop_poc_access
},
7043 { .name
= "DC_IGDSW", .state
= ARM_CP_STATE_AA64
,
7044 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 6,
7045 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7046 { .name
= "DC_CGSW", .state
= ARM_CP_STATE_AA64
,
7047 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 4,
7048 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7049 { .name
= "DC_CGDSW", .state
= ARM_CP_STATE_AA64
,
7050 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 6,
7051 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7052 { .name
= "DC_CIGSW", .state
= ARM_CP_STATE_AA64
,
7053 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 4,
7054 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7055 { .name
= "DC_CIGDSW", .state
= ARM_CP_STATE_AA64
,
7056 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 6,
7057 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7061 static const ARMCPRegInfo mte_tco_ro_reginfo
[] = {
7062 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7063 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7064 .type
= ARM_CP_CONST
, .access
= PL0_RW
, },
7068 static const ARMCPRegInfo mte_el0_cacheop_reginfo
[] = {
7069 { .name
= "DC_CGVAC", .state
= ARM_CP_STATE_AA64
,
7070 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 3,
7071 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7072 .accessfn
= aa64_cacheop_poc_access
},
7073 { .name
= "DC_CGDVAC", .state
= ARM_CP_STATE_AA64
,
7074 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 5,
7075 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7076 .accessfn
= aa64_cacheop_poc_access
},
7077 { .name
= "DC_CGVAP", .state
= ARM_CP_STATE_AA64
,
7078 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 3,
7079 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7080 .accessfn
= aa64_cacheop_poc_access
},
7081 { .name
= "DC_CGDVAP", .state
= ARM_CP_STATE_AA64
,
7082 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 5,
7083 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7084 .accessfn
= aa64_cacheop_poc_access
},
7085 { .name
= "DC_CGVADP", .state
= ARM_CP_STATE_AA64
,
7086 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 3,
7087 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7088 .accessfn
= aa64_cacheop_poc_access
},
7089 { .name
= "DC_CGDVADP", .state
= ARM_CP_STATE_AA64
,
7090 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 5,
7091 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7092 .accessfn
= aa64_cacheop_poc_access
},
7093 { .name
= "DC_CIGVAC", .state
= ARM_CP_STATE_AA64
,
7094 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 3,
7095 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7096 .accessfn
= aa64_cacheop_poc_access
},
7097 { .name
= "DC_CIGDVAC", .state
= ARM_CP_STATE_AA64
,
7098 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 5,
7099 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7100 .accessfn
= aa64_cacheop_poc_access
},
7101 { .name
= "DC_GVA", .state
= ARM_CP_STATE_AA64
,
7102 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 3,
7103 .access
= PL0_W
, .type
= ARM_CP_DC_GVA
,
7104 #ifndef CONFIG_USER_ONLY
7105 /* Avoid overhead of an access check that always passes in user-mode */
7106 .accessfn
= aa64_zva_access
,
7109 { .name
= "DC_GZVA", .state
= ARM_CP_STATE_AA64
,
7110 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 4,
7111 .access
= PL0_W
, .type
= ARM_CP_DC_GZVA
,
7112 #ifndef CONFIG_USER_ONLY
7113 /* Avoid overhead of an access check that always passes in user-mode */
7114 .accessfn
= aa64_zva_access
,
7122 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7125 int el
= arm_current_el(env
);
7128 uint64_t sctlr
= arm_sctlr(env
, el
);
7129 if (!(sctlr
& SCTLR_EnRCTX
)) {
7130 return CP_ACCESS_TRAP
;
7132 } else if (el
== 1) {
7133 uint64_t hcr
= arm_hcr_el2_eff(env
);
7135 return CP_ACCESS_TRAP_EL2
;
7138 return CP_ACCESS_OK
;
7141 static const ARMCPRegInfo predinv_reginfo
[] = {
7142 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
7143 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
7144 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7145 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
7146 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
7147 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7148 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
7149 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
7150 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7152 * Note the AArch32 opcodes have a different OPC1.
7154 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
7155 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
7156 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7157 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
7158 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
7159 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7160 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
7161 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
7162 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7166 static uint64_t ccsidr2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7168 /* Read the high 32 bits of the current CCSIDR */
7169 return extract64(ccsidr_read(env
, ri
), 32, 32);
7172 static const ARMCPRegInfo ccsidr2_reginfo
[] = {
7173 { .name
= "CCSIDR2", .state
= ARM_CP_STATE_BOTH
,
7174 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 2,
7176 .accessfn
= access_aa64_tid2
,
7177 .readfn
= ccsidr2_read
, .type
= ARM_CP_NO_RAW
},
7181 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7184 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
7185 return CP_ACCESS_TRAP_EL2
;
7188 return CP_ACCESS_OK
;
7191 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7194 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7195 return access_aa64_tid3(env
, ri
, isread
);
7198 return CP_ACCESS_OK
;
7201 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7204 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
7205 return CP_ACCESS_TRAP_EL2
;
7208 return CP_ACCESS_OK
;
7211 static const ARMCPRegInfo jazelle_regs
[] = {
7213 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
7214 .access
= PL1_R
, .accessfn
= access_jazelle
,
7215 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7217 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
7218 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7220 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
7221 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7225 static const ARMCPRegInfo vhe_reginfo
[] = {
7226 { .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7227 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
7229 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2]) },
7230 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
7231 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
7232 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
7233 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
7234 #ifndef CONFIG_USER_ONLY
7235 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
7236 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
7238 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
7239 .type
= ARM_CP_IO
, .access
= PL2_RW
,
7240 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
7241 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
7242 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
7243 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
7244 .resetfn
= gt_hv_timer_reset
,
7245 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
7246 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
7248 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
7250 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
7251 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
7252 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7253 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
7254 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7255 .access
= PL2_RW
, .accessfn
= e2h_access
,
7256 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
7257 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
7258 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
7259 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
7260 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7261 .access
= PL2_RW
, .accessfn
= e2h_access
,
7262 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
7263 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
7264 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7265 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
7266 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7267 .access
= PL2_RW
, .accessfn
= e2h_access
,
7268 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
7269 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7270 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
7271 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
7272 .access
= PL2_RW
, .accessfn
= e2h_access
,
7273 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
7274 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7275 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
7276 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7277 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
7278 .access
= PL2_RW
, .accessfn
= e2h_access
,
7279 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
7280 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
7281 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
7282 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7283 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
7284 .access
= PL2_RW
, .accessfn
= e2h_access
,
7285 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
7290 #ifndef CONFIG_USER_ONLY
7291 static const ARMCPRegInfo ats1e1_reginfo
[] = {
7292 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
7293 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7294 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7295 .writefn
= ats_write64
},
7296 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
7297 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7298 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7299 .writefn
= ats_write64
},
7303 static const ARMCPRegInfo ats1cp_reginfo
[] = {
7304 { .name
= "ATS1CPRP",
7305 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
7306 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7307 .writefn
= ats_write
},
7308 { .name
= "ATS1CPWP",
7309 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
7310 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
7311 .writefn
= ats_write
},
7317 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
7318 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
7319 * is non-zero, which is never for ARMv7, optionally in ARMv8
7320 * and mandatorily for ARMv8.2 and up.
7321 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
7322 * implementation is RAZ/WI we can ignore this detail, as we
7325 static const ARMCPRegInfo actlr2_hactlr2_reginfo
[] = {
7326 { .name
= "ACTLR2", .state
= ARM_CP_STATE_AA32
,
7327 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 3,
7328 .access
= PL1_RW
, .accessfn
= access_tacr
,
7329 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7330 { .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
7331 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
7332 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
7337 void register_cp_regs_for_features(ARMCPU
*cpu
)
7339 /* Register all the coprocessor registers based on feature bits */
7340 CPUARMState
*env
= &cpu
->env
;
7341 if (arm_feature(env
, ARM_FEATURE_M
)) {
7342 /* M profile has no coprocessor registers */
7346 define_arm_cp_regs(cpu
, cp_reginfo
);
7347 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
7348 /* Must go early as it is full of wildcards that may be
7349 * overridden by later definitions.
7351 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
7354 if (arm_feature(env
, ARM_FEATURE_V6
)) {
7355 /* The ID registers all have impdef reset values */
7356 ARMCPRegInfo v6_idregs
[] = {
7357 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
7358 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
7359 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7360 .accessfn
= access_aa32_tid3
,
7361 .resetvalue
= cpu
->isar
.id_pfr0
},
7362 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
7363 * the value of the GIC field until after we define these regs.
7365 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
7366 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
7367 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
7368 .accessfn
= access_aa32_tid3
,
7369 .readfn
= id_pfr1_read
,
7370 .writefn
= arm_cp_write_ignore
},
7371 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
7372 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
7373 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7374 .accessfn
= access_aa32_tid3
,
7375 .resetvalue
= cpu
->isar
.id_dfr0
},
7376 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
7377 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
7378 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7379 .accessfn
= access_aa32_tid3
,
7380 .resetvalue
= cpu
->id_afr0
},
7381 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
7382 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
7383 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7384 .accessfn
= access_aa32_tid3
,
7385 .resetvalue
= cpu
->isar
.id_mmfr0
},
7386 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
7387 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
7388 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7389 .accessfn
= access_aa32_tid3
,
7390 .resetvalue
= cpu
->isar
.id_mmfr1
},
7391 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
7392 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
7393 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7394 .accessfn
= access_aa32_tid3
,
7395 .resetvalue
= cpu
->isar
.id_mmfr2
},
7396 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
7397 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
7398 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7399 .accessfn
= access_aa32_tid3
,
7400 .resetvalue
= cpu
->isar
.id_mmfr3
},
7401 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
7402 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
7403 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7404 .accessfn
= access_aa32_tid3
,
7405 .resetvalue
= cpu
->isar
.id_isar0
},
7406 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
7407 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
7408 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7409 .accessfn
= access_aa32_tid3
,
7410 .resetvalue
= cpu
->isar
.id_isar1
},
7411 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
7412 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
7413 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7414 .accessfn
= access_aa32_tid3
,
7415 .resetvalue
= cpu
->isar
.id_isar2
},
7416 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
7417 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
7418 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7419 .accessfn
= access_aa32_tid3
,
7420 .resetvalue
= cpu
->isar
.id_isar3
},
7421 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
7422 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
7423 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7424 .accessfn
= access_aa32_tid3
,
7425 .resetvalue
= cpu
->isar
.id_isar4
},
7426 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
7427 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
7428 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7429 .accessfn
= access_aa32_tid3
,
7430 .resetvalue
= cpu
->isar
.id_isar5
},
7431 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
7432 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
7433 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7434 .accessfn
= access_aa32_tid3
,
7435 .resetvalue
= cpu
->isar
.id_mmfr4
},
7436 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
7437 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
7438 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7439 .accessfn
= access_aa32_tid3
,
7440 .resetvalue
= cpu
->isar
.id_isar6
},
7443 define_arm_cp_regs(cpu
, v6_idregs
);
7444 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
7446 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
7448 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
7449 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
7451 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
7452 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
7453 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
7455 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
7456 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
7458 if (arm_feature(env
, ARM_FEATURE_V7
)) {
7459 ARMCPRegInfo clidr
= {
7460 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
7461 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
7462 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7463 .accessfn
= access_aa64_tid2
,
7464 .resetvalue
= cpu
->clidr
7466 define_one_arm_cp_reg(cpu
, &clidr
);
7467 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
7468 define_debug_regs(cpu
);
7469 define_pmu_regs(cpu
);
7471 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
7473 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7474 /* AArch64 ID registers, which all have impdef reset values.
7475 * Note that within the ID register ranges the unused slots
7476 * must all RAZ, not UNDEF; future architecture versions may
7477 * define new registers here.
7479 ARMCPRegInfo v8_idregs
[] = {
7481 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
7482 * emulation because we don't know the right value for the
7483 * GIC field until after we define these regs.
7485 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7486 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
7488 #ifdef CONFIG_USER_ONLY
7489 .type
= ARM_CP_CONST
,
7490 .resetvalue
= cpu
->isar
.id_aa64pfr0
7492 .type
= ARM_CP_NO_RAW
,
7493 .accessfn
= access_aa64_tid3
,
7494 .readfn
= id_aa64pfr0_read
,
7495 .writefn
= arm_cp_write_ignore
7498 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7499 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
7500 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7501 .accessfn
= access_aa64_tid3
,
7502 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
7503 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7504 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
7505 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7506 .accessfn
= access_aa64_tid3
,
7508 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7509 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
7510 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7511 .accessfn
= access_aa64_tid3
,
7513 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7514 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
7515 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7516 .accessfn
= access_aa64_tid3
,
7517 /* At present, only SVEver == 0 is defined anyway. */
7519 { .name
= "ID_AA64PFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7520 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
7521 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7522 .accessfn
= access_aa64_tid3
,
7524 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7525 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
7526 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7527 .accessfn
= access_aa64_tid3
,
7529 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7530 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
7531 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7532 .accessfn
= access_aa64_tid3
,
7534 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7535 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
7536 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7537 .accessfn
= access_aa64_tid3
,
7538 .resetvalue
= cpu
->isar
.id_aa64dfr0
},
7539 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7540 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
7541 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7542 .accessfn
= access_aa64_tid3
,
7543 .resetvalue
= cpu
->isar
.id_aa64dfr1
},
7544 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7545 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
7546 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7547 .accessfn
= access_aa64_tid3
,
7549 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7550 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
7551 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7552 .accessfn
= access_aa64_tid3
,
7554 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7555 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
7556 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7557 .accessfn
= access_aa64_tid3
,
7558 .resetvalue
= cpu
->id_aa64afr0
},
7559 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7560 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
7561 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7562 .accessfn
= access_aa64_tid3
,
7563 .resetvalue
= cpu
->id_aa64afr1
},
7564 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7565 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
7566 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7567 .accessfn
= access_aa64_tid3
,
7569 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7570 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
7571 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7572 .accessfn
= access_aa64_tid3
,
7574 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
7575 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
7576 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7577 .accessfn
= access_aa64_tid3
,
7578 .resetvalue
= cpu
->isar
.id_aa64isar0
},
7579 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
7580 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
7581 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7582 .accessfn
= access_aa64_tid3
,
7583 .resetvalue
= cpu
->isar
.id_aa64isar1
},
7584 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7585 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
7586 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7587 .accessfn
= access_aa64_tid3
,
7589 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7590 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
7591 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7592 .accessfn
= access_aa64_tid3
,
7594 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7595 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
7596 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7597 .accessfn
= access_aa64_tid3
,
7599 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7600 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
7601 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7602 .accessfn
= access_aa64_tid3
,
7604 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7605 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
7606 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7607 .accessfn
= access_aa64_tid3
,
7609 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7610 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
7611 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7612 .accessfn
= access_aa64_tid3
,
7614 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7615 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
7616 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7617 .accessfn
= access_aa64_tid3
,
7618 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
7619 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7620 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
7621 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7622 .accessfn
= access_aa64_tid3
,
7623 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
7624 { .name
= "ID_AA64MMFR2_EL1", .state
= ARM_CP_STATE_AA64
,
7625 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
7626 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7627 .accessfn
= access_aa64_tid3
,
7628 .resetvalue
= cpu
->isar
.id_aa64mmfr2
},
7629 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7630 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
7631 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7632 .accessfn
= access_aa64_tid3
,
7634 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7635 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
7636 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7637 .accessfn
= access_aa64_tid3
,
7639 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7640 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
7641 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7642 .accessfn
= access_aa64_tid3
,
7644 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7645 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
7646 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7647 .accessfn
= access_aa64_tid3
,
7649 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7650 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
7651 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7652 .accessfn
= access_aa64_tid3
,
7654 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
7655 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
7656 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7657 .accessfn
= access_aa64_tid3
,
7658 .resetvalue
= cpu
->isar
.mvfr0
},
7659 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
7660 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
7661 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7662 .accessfn
= access_aa64_tid3
,
7663 .resetvalue
= cpu
->isar
.mvfr1
},
7664 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
7665 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
7666 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7667 .accessfn
= access_aa64_tid3
,
7668 .resetvalue
= cpu
->isar
.mvfr2
},
7669 { .name
= "MVFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7670 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
7671 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7672 .accessfn
= access_aa64_tid3
,
7674 { .name
= "ID_PFR2", .state
= ARM_CP_STATE_BOTH
,
7675 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
7676 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7677 .accessfn
= access_aa64_tid3
,
7678 .resetvalue
= cpu
->isar
.id_pfr2
},
7679 { .name
= "MVFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7680 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
7681 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7682 .accessfn
= access_aa64_tid3
,
7684 { .name
= "MVFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7685 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
7686 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7687 .accessfn
= access_aa64_tid3
,
7689 { .name
= "MVFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
7690 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
7691 .access
= PL1_R
, .type
= ARM_CP_CONST
,
7692 .accessfn
= access_aa64_tid3
,
7694 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
7695 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
7696 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7697 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
7698 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
7699 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
7700 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7701 .resetvalue
= cpu
->pmceid0
},
7702 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
7703 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
7704 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7705 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
7706 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
7707 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
7708 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7709 .resetvalue
= cpu
->pmceid1
},
7712 #ifdef CONFIG_USER_ONLY
7713 ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
7714 { .name
= "ID_AA64PFR0_EL1",
7715 .exported_bits
= 0x000f000f00ff0000,
7716 .fixed_bits
= 0x0000000000000011 },
7717 { .name
= "ID_AA64PFR1_EL1",
7718 .exported_bits
= 0x00000000000000f0 },
7719 { .name
= "ID_AA64PFR*_EL1_RESERVED",
7721 { .name
= "ID_AA64ZFR0_EL1" },
7722 { .name
= "ID_AA64MMFR0_EL1",
7723 .fixed_bits
= 0x00000000ff000000 },
7724 { .name
= "ID_AA64MMFR1_EL1" },
7725 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
7727 { .name
= "ID_AA64DFR0_EL1",
7728 .fixed_bits
= 0x0000000000000006 },
7729 { .name
= "ID_AA64DFR1_EL1" },
7730 { .name
= "ID_AA64DFR*_EL1_RESERVED",
7732 { .name
= "ID_AA64AFR*",
7734 { .name
= "ID_AA64ISAR0_EL1",
7735 .exported_bits
= 0x00fffffff0fffff0 },
7736 { .name
= "ID_AA64ISAR1_EL1",
7737 .exported_bits
= 0x000000f0ffffffff },
7738 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
7740 REGUSERINFO_SENTINEL
7742 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
7744 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
7745 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
7746 !arm_feature(env
, ARM_FEATURE_EL2
)) {
7747 ARMCPRegInfo rvbar
= {
7748 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
7749 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
7750 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
7752 define_one_arm_cp_reg(cpu
, &rvbar
);
7754 define_arm_cp_regs(cpu
, v8_idregs
);
7755 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
7757 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
7758 uint64_t vmpidr_def
= mpidr_read_val(env
);
7759 ARMCPRegInfo vpidr_regs
[] = {
7760 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
7761 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
7762 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
7763 .resetvalue
= cpu
->midr
, .type
= ARM_CP_ALIAS
,
7764 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
7765 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7766 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
7767 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
7768 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
7769 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
7770 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
7771 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
7772 .resetvalue
= vmpidr_def
, .type
= ARM_CP_ALIAS
,
7773 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
7774 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
7775 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
7777 .resetvalue
= vmpidr_def
,
7778 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
7781 define_arm_cp_regs(cpu
, vpidr_regs
);
7782 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
7783 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7784 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
7786 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
7787 define_arm_cp_regs(cpu
, el2_sec_cp_reginfo
);
7789 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
7790 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
7791 ARMCPRegInfo rvbar
= {
7792 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
7793 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
7794 .type
= ARM_CP_CONST
, .access
= PL2_R
, .resetvalue
= cpu
->rvbar
7796 define_one_arm_cp_reg(cpu
, &rvbar
);
7799 /* If EL2 is missing but higher ELs are enabled, we need to
7800 * register the no_el2 reginfos.
7802 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7803 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
7804 * of MIDR_EL1 and MPIDR_EL1.
7806 ARMCPRegInfo vpidr_regs
[] = {
7807 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
7808 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
7809 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
7810 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
,
7811 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
7812 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
7813 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
7814 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
7815 .type
= ARM_CP_NO_RAW
,
7816 .writefn
= arm_cp_write_ignore
, .readfn
= mpidr_read
},
7819 define_arm_cp_regs(cpu
, vpidr_regs
);
7820 define_arm_cp_regs(cpu
, el3_no_el2_cp_reginfo
);
7821 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7822 define_arm_cp_regs(cpu
, el3_no_el2_v8_cp_reginfo
);
7826 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7827 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
7828 ARMCPRegInfo el3_regs
[] = {
7829 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
7830 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
7831 .type
= ARM_CP_CONST
, .access
= PL3_R
, .resetvalue
= cpu
->rvbar
},
7832 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
7833 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
7835 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
7836 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
7837 .resetvalue
= cpu
->reset_sctlr
},
7841 define_arm_cp_regs(cpu
, el3_regs
);
7843 /* The behaviour of NSACR is sufficiently various that we don't
7844 * try to describe it in a single reginfo:
7845 * if EL3 is 64 bit, then trap to EL3 from S EL1,
7846 * reads as constant 0xc00 from NS EL1 and NS EL2
7847 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
7848 * if v7 without EL3, register doesn't exist
7849 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
7851 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7852 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
7853 ARMCPRegInfo nsacr
= {
7854 .name
= "NSACR", .type
= ARM_CP_CONST
,
7855 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
7856 .access
= PL1_RW
, .accessfn
= nsacr_access
,
7859 define_one_arm_cp_reg(cpu
, &nsacr
);
7861 ARMCPRegInfo nsacr
= {
7863 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
7864 .access
= PL3_RW
| PL1_R
,
7866 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
7868 define_one_arm_cp_reg(cpu
, &nsacr
);
7871 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7872 ARMCPRegInfo nsacr
= {
7873 .name
= "NSACR", .type
= ARM_CP_CONST
,
7874 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
7878 define_one_arm_cp_reg(cpu
, &nsacr
);
7882 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
7883 if (arm_feature(env
, ARM_FEATURE_V6
)) {
7884 /* PMSAv6 not implemented */
7885 assert(arm_feature(env
, ARM_FEATURE_V7
));
7886 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
7887 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
7889 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
7892 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
7893 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
7894 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
7895 if (cpu_isar_feature(aa32_hpd
, cpu
)) {
7896 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
7899 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
7900 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
7902 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
7903 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
7905 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
7906 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
7908 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
7909 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
7911 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
7912 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
7914 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
7915 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
7917 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
7918 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
7920 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
7921 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
7923 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
7924 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
7926 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
7927 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
7929 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
7930 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
7932 if (cpu_isar_feature(aa32_jazelle
, cpu
)) {
7933 define_arm_cp_regs(cpu
, jazelle_regs
);
7935 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
7936 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
7937 * be read-only (ie write causes UNDEF exception).
7940 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
7941 /* Pre-v8 MIDR space.
7942 * Note that the MIDR isn't a simple constant register because
7943 * of the TI925 behaviour where writes to another register can
7944 * cause the MIDR value to change.
7946 * Unimplemented registers in the c15 0 0 0 space default to
7947 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
7948 * and friends override accordingly.
7951 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
7952 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
7953 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
7954 .readfn
= midr_read
,
7955 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
7956 .type
= ARM_CP_OVERRIDE
},
7957 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
7959 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
7960 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7962 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
7963 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7965 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
7966 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7968 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
7969 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7971 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
7972 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7975 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
7976 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
7977 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
7978 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
7979 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
7980 .readfn
= midr_read
},
7981 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
7982 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
7983 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
7984 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
7985 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
7986 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
7987 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
7988 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
7989 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
7991 .accessfn
= access_aa64_tid1
,
7992 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
7995 ARMCPRegInfo id_cp_reginfo
[] = {
7996 /* These are common to v8 and pre-v8 */
7998 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
7999 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
8000 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
8001 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
8002 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
8003 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
8004 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
8005 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
8007 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
8009 .accessfn
= access_aa32_tid1
,
8010 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8013 /* TLBTR is specific to VMSA */
8014 ARMCPRegInfo id_tlbtr_reginfo
= {
8016 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
8018 .accessfn
= access_aa32_tid1
,
8019 .type
= ARM_CP_CONST
, .resetvalue
= 0,
8021 /* MPUIR is specific to PMSA V6+ */
8022 ARMCPRegInfo id_mpuir_reginfo
= {
8024 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
8025 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8026 .resetvalue
= cpu
->pmsav7_dregion
<< 8
8028 ARMCPRegInfo crn0_wi_reginfo
= {
8029 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
8030 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
8031 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
8033 #ifdef CONFIG_USER_ONLY
8034 ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
8035 { .name
= "MIDR_EL1",
8036 .exported_bits
= 0x00000000ffffffff },
8037 { .name
= "REVIDR_EL1" },
8038 REGUSERINFO_SENTINEL
8040 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
8042 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
8043 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
8045 /* Register the blanket "writes ignored" value first to cover the
8046 * whole space. Then update the specific ID registers to allow write
8047 * access, so that they ignore writes rather than causing them to
8050 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
8051 for (r
= id_pre_v8_midr_cp_reginfo
;
8052 r
->type
!= ARM_CP_SENTINEL
; r
++) {
8055 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
8058 id_mpuir_reginfo
.access
= PL1_RW
;
8059 id_tlbtr_reginfo
.access
= PL1_RW
;
8061 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8062 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
8064 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
8066 define_arm_cp_regs(cpu
, id_cp_reginfo
);
8067 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
8068 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
8069 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
8070 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
8074 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
8075 ARMCPRegInfo mpidr_cp_reginfo
[] = {
8076 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8077 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
8078 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
8081 #ifdef CONFIG_USER_ONLY
8082 ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
8083 { .name
= "MPIDR_EL1",
8084 .fixed_bits
= 0x0000000080000000 },
8085 REGUSERINFO_SENTINEL
8087 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
8089 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
8092 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
8093 ARMCPRegInfo auxcr_reginfo
[] = {
8094 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
8095 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
8096 .access
= PL1_RW
, .accessfn
= access_tacr
,
8097 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->reset_auxcr
},
8098 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
8099 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
8100 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
8102 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
8103 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
8104 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
8108 define_arm_cp_regs(cpu
, auxcr_reginfo
);
8109 if (cpu_isar_feature(aa32_ac2
, cpu
)) {
8110 define_arm_cp_regs(cpu
, actlr2_hactlr2_reginfo
);
8114 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
8116 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
8117 * There are two flavours:
8118 * (1) older 32-bit only cores have a simple 32-bit CBAR
8119 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
8120 * 32-bit register visible to AArch32 at a different encoding
8121 * to the "flavour 1" register and with the bits rearranged to
8122 * be able to squash a 64-bit address into the 32-bit view.
8123 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
8124 * in future if we support AArch32-only configs of some of the
8125 * AArch64 cores we might need to add a specific feature flag
8126 * to indicate cores with "flavour 2" CBAR.
8128 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8129 /* 32 bit view is [31:18] 0...0 [43:32]. */
8130 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
8131 | extract64(cpu
->reset_cbar
, 32, 12);
8132 ARMCPRegInfo cbar_reginfo
[] = {
8134 .type
= ARM_CP_CONST
,
8135 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
8136 .access
= PL1_R
, .resetvalue
= cbar32
},
8137 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
8138 .type
= ARM_CP_CONST
,
8139 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
8140 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
8143 /* We don't implement a r/w 64 bit CBAR currently */
8144 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
8145 define_arm_cp_regs(cpu
, cbar_reginfo
);
8147 ARMCPRegInfo cbar
= {
8149 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
8150 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
8151 .fieldoffset
= offsetof(CPUARMState
,
8152 cp15
.c15_config_base_address
)
8154 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
8155 cbar
.access
= PL1_R
;
8156 cbar
.fieldoffset
= 0;
8157 cbar
.type
= ARM_CP_CONST
;
8159 define_one_arm_cp_reg(cpu
, &cbar
);
8163 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
8164 ARMCPRegInfo vbar_cp_reginfo
[] = {
8165 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
8166 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
8167 .access
= PL1_RW
, .writefn
= vbar_write
,
8168 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
8169 offsetof(CPUARMState
, cp15
.vbar_ns
) },
8173 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
8176 /* Generic registers whose values depend on the implementation */
8178 ARMCPRegInfo sctlr
= {
8179 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
8180 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
8181 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
8182 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
8183 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
8184 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
8185 .raw_writefn
= raw_write
,
8187 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
8188 /* Normally we would always end the TB on an SCTLR write, but Linux
8189 * arch/arm/mach-pxa/sleep.S expects two instructions following
8190 * an MMU enable to execute from cache. Imitate this behaviour.
8192 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
8194 define_one_arm_cp_reg(cpu
, &sctlr
);
8197 if (cpu_isar_feature(aa64_lor
, cpu
)) {
8198 define_arm_cp_regs(cpu
, lor_reginfo
);
8200 if (cpu_isar_feature(aa64_pan
, cpu
)) {
8201 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
8203 #ifndef CONFIG_USER_ONLY
8204 if (cpu_isar_feature(aa64_ats1e1
, cpu
)) {
8205 define_arm_cp_regs(cpu
, ats1e1_reginfo
);
8207 if (cpu_isar_feature(aa32_ats1e1
, cpu
)) {
8208 define_arm_cp_regs(cpu
, ats1cp_reginfo
);
8211 if (cpu_isar_feature(aa64_uao
, cpu
)) {
8212 define_one_arm_cp_reg(cpu
, &uao_reginfo
);
8215 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
8216 define_arm_cp_regs(cpu
, vhe_reginfo
);
8219 if (cpu_isar_feature(aa64_sve
, cpu
)) {
8220 define_one_arm_cp_reg(cpu
, &zcr_el1_reginfo
);
8221 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
8222 define_one_arm_cp_reg(cpu
, &zcr_el2_reginfo
);
8224 define_one_arm_cp_reg(cpu
, &zcr_no_el2_reginfo
);
8226 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8227 define_one_arm_cp_reg(cpu
, &zcr_el3_reginfo
);
8231 #ifdef TARGET_AARCH64
8232 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
8233 define_arm_cp_regs(cpu
, pauth_reginfo
);
8235 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
8236 define_arm_cp_regs(cpu
, rndr_reginfo
);
8238 #ifndef CONFIG_USER_ONLY
8239 /* Data Cache clean instructions up to PoP */
8240 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
8241 define_one_arm_cp_reg(cpu
, dcpop_reg
);
8243 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
8244 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
8247 #endif /*CONFIG_USER_ONLY*/
8250 * If full MTE is enabled, add all of the system registers.
8251 * If only "instructions available at EL0" are enabled,
8252 * then define only a RAZ/WI version of PSTATE.TCO.
8254 if (cpu_isar_feature(aa64_mte
, cpu
)) {
8255 define_arm_cp_regs(cpu
, mte_reginfo
);
8256 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
8257 } else if (cpu_isar_feature(aa64_mte_insn_reg
, cpu
)) {
8258 define_arm_cp_regs(cpu
, mte_tco_ro_reginfo
);
8259 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
8263 if (cpu_isar_feature(any_predinv
, cpu
)) {
8264 define_arm_cp_regs(cpu
, predinv_reginfo
);
8267 if (cpu_isar_feature(any_ccidx
, cpu
)) {
8268 define_arm_cp_regs(cpu
, ccsidr2_reginfo
);
8271 #ifndef CONFIG_USER_ONLY
8273 * Register redirections and aliases must be done last,
8274 * after the registers from the other extensions have been defined.
8276 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
8277 define_arm_vh_e2h_redirects_aliases(cpu
);
8282 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
8284 CPUState
*cs
= CPU(cpu
);
8285 CPUARMState
*env
= &cpu
->env
;
8287 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8289 * The lower part of each SVE register aliases to the FPU
8290 * registers so we don't need to include both.
8292 #ifdef TARGET_AARCH64
8293 if (isar_feature_aa64_sve(&cpu
->isar
)) {
8294 gdb_register_coprocessor(cs
, arm_gdb_get_svereg
, arm_gdb_set_svereg
,
8295 arm_gen_dynamic_svereg_xml(cs
, cs
->gdb_num_regs
),
8296 "sve-registers.xml", 0);
8300 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
8301 aarch64_fpu_gdb_set_reg
,
8302 34, "aarch64-fpu.xml", 0);
8304 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
8305 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
8306 51, "arm-neon.xml", 0);
8307 } else if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
8308 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
8309 35, "arm-vfp3.xml", 0);
8310 } else if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
8311 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
8312 19, "arm-vfp.xml", 0);
8314 gdb_register_coprocessor(cs
, arm_gdb_get_sysreg
, arm_gdb_set_sysreg
,
8315 arm_gen_dynamic_sysreg_xml(cs
, cs
->gdb_num_regs
),
8316 "system-registers.xml", 0);
8320 /* Sort alphabetically by type name, except for "any". */
8321 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
8323 ObjectClass
*class_a
= (ObjectClass
*)a
;
8324 ObjectClass
*class_b
= (ObjectClass
*)b
;
8325 const char *name_a
, *name_b
;
8327 name_a
= object_class_get_name(class_a
);
8328 name_b
= object_class_get_name(class_b
);
8329 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
8331 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
8334 return strcmp(name_a
, name_b
);
8338 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
8340 ObjectClass
*oc
= data
;
8341 const char *typename
;
8344 typename
= object_class_get_name(oc
);
8345 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
8346 qemu_printf(" %s\n", name
);
8350 void arm_cpu_list(void)
8354 list
= object_class_get_list(TYPE_ARM_CPU
, false);
8355 list
= g_slist_sort(list
, arm_cpu_list_compare
);
8356 qemu_printf("Available CPUs:\n");
8357 g_slist_foreach(list
, arm_cpu_list_entry
, NULL
);
8361 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
8363 ObjectClass
*oc
= data
;
8364 CpuDefinitionInfoList
**cpu_list
= user_data
;
8365 CpuDefinitionInfo
*info
;
8366 const char *typename
;
8368 typename
= object_class_get_name(oc
);
8369 info
= g_malloc0(sizeof(*info
));
8370 info
->name
= g_strndup(typename
,
8371 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
8372 info
->q_typename
= g_strdup(typename
);
8374 QAPI_LIST_PREPEND(*cpu_list
, info
);
8377 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
8379 CpuDefinitionInfoList
*cpu_list
= NULL
;
8382 list
= object_class_get_list(TYPE_ARM_CPU
, false);
8383 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
8389 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
8390 void *opaque
, int state
, int secstate
,
8391 int crm
, int opc1
, int opc2
,
8394 /* Private utility function for define_one_arm_cp_reg_with_opaque():
8395 * add a single reginfo struct to the hash table.
8397 uint32_t *key
= g_new(uint32_t, 1);
8398 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
8399 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
8400 int ns
= (secstate
& ARM_CP_SECSTATE_NS
) ? 1 : 0;
8402 r2
->name
= g_strdup(name
);
8403 /* Reset the secure state to the specific incoming state. This is
8404 * necessary as the register may have been defined with both states.
8406 r2
->secure
= secstate
;
8408 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
8409 /* Register is banked (using both entries in array).
8410 * Overwriting fieldoffset as the array is only used to define
8411 * banked registers but later only fieldoffset is used.
8413 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
8416 if (state
== ARM_CP_STATE_AA32
) {
8417 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
8418 /* If the register is banked then we don't need to migrate or
8419 * reset the 32-bit instance in certain cases:
8421 * 1) If the register has both 32-bit and 64-bit instances then we
8422 * can count on the 64-bit instance taking care of the
8424 * 2) If ARMv8 is enabled then we can count on a 64-bit version
8425 * taking care of the secure bank. This requires that separate
8426 * 32 and 64-bit definitions are provided.
8428 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
8429 (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) && !ns
)) {
8430 r2
->type
|= ARM_CP_ALIAS
;
8432 } else if ((secstate
!= r
->secure
) && !ns
) {
8433 /* The register is not banked so we only want to allow migration of
8434 * the non-secure instance.
8436 r2
->type
|= ARM_CP_ALIAS
;
8439 if (r
->state
== ARM_CP_STATE_BOTH
) {
8440 /* We assume it is a cp15 register if the .cp field is left unset.
8446 #ifdef HOST_WORDS_BIGENDIAN
8447 if (r2
->fieldoffset
) {
8448 r2
->fieldoffset
+= sizeof(uint32_t);
8453 if (state
== ARM_CP_STATE_AA64
) {
8454 /* To allow abbreviation of ARMCPRegInfo
8455 * definitions, we treat cp == 0 as equivalent to
8456 * the value for "standard guest-visible sysreg".
8457 * STATE_BOTH definitions are also always "standard
8458 * sysreg" in their AArch64 view (the .cp value may
8459 * be non-zero for the benefit of the AArch32 view).
8461 if (r
->cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
8462 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
8464 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
8465 r2
->opc0
, opc1
, opc2
);
8467 *key
= ENCODE_CP_REG(r2
->cp
, is64
, ns
, r2
->crn
, crm
, opc1
, opc2
);
8470 r2
->opaque
= opaque
;
8472 /* reginfo passed to helpers is correct for the actual access,
8473 * and is never ARM_CP_STATE_BOTH:
8476 /* Make sure reginfo passed to helpers for wildcarded regs
8477 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
8482 /* By convention, for wildcarded registers only the first
8483 * entry is used for migration; the others are marked as
8484 * ALIAS so we don't try to transfer the register
8485 * multiple times. Special registers (ie NOP/WFI) are
8486 * never migratable and not even raw-accessible.
8488 if ((r
->type
& ARM_CP_SPECIAL
)) {
8489 r2
->type
|= ARM_CP_NO_RAW
;
8491 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
8492 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
8493 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
8494 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
8497 /* Check that raw accesses are either forbidden or handled. Note that
8498 * we can't assert this earlier because the setup of fieldoffset for
8499 * banked registers has to be done first.
8501 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
8502 assert(!raw_accessors_invalid(r2
));
8505 /* Overriding of an existing definition must be explicitly
8508 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
8509 ARMCPRegInfo
*oldreg
;
8510 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
8511 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
8512 fprintf(stderr
, "Register redefined: cp=%d %d bit "
8513 "crn=%d crm=%d opc1=%d opc2=%d, "
8514 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
8515 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
8516 oldreg
->name
, r2
->name
);
8517 g_assert_not_reached();
8520 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
8524 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
8525 const ARMCPRegInfo
*r
, void *opaque
)
8527 /* Define implementations of coprocessor registers.
8528 * We store these in a hashtable because typically
8529 * there are less than 150 registers in a space which
8530 * is 16*16*16*8*8 = 262144 in size.
8531 * Wildcarding is supported for the crm, opc1 and opc2 fields.
8532 * If a register is defined twice then the second definition is
8533 * used, so this can be used to define some generic registers and
8534 * then override them with implementation specific variations.
8535 * At least one of the original and the second definition should
8536 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
8537 * against accidental use.
8539 * The state field defines whether the register is to be
8540 * visible in the AArch32 or AArch64 execution state. If the
8541 * state is set to ARM_CP_STATE_BOTH then we synthesise a
8542 * reginfo structure for the AArch32 view, which sees the lower
8543 * 32 bits of the 64 bit register.
8545 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
8546 * be wildcarded. AArch64 registers are always considered to be 64
8547 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
8548 * the register, if any.
8550 int crm
, opc1
, opc2
, state
;
8551 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
8552 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
8553 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
8554 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
8555 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
8556 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
8557 /* 64 bit registers have only CRm and Opc1 fields */
8558 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
8559 /* op0 only exists in the AArch64 encodings */
8560 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
8561 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
8562 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
8564 * This API is only for Arm's system coprocessors (14 and 15) or
8565 * (M-profile or v7A-and-earlier only) for implementation defined
8566 * coprocessors in the range 0..7. Our decode assumes this, since
8567 * 8..13 can be used for other insns including VFP and Neon. See
8568 * valid_cp() in translate.c. Assert here that we haven't tried
8569 * to use an invalid coprocessor number.
8572 case ARM_CP_STATE_BOTH
:
8573 /* 0 has a special meaning, but otherwise the same rules as AA32. */
8578 case ARM_CP_STATE_AA32
:
8579 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
8580 !arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
8581 assert(r
->cp
>= 14 && r
->cp
<= 15);
8583 assert(r
->cp
< 8 || (r
->cp
>= 14 && r
->cp
<= 15));
8586 case ARM_CP_STATE_AA64
:
8587 assert(r
->cp
== 0 || r
->cp
== CP_REG_ARM64_SYSREG_CP
);
8590 g_assert_not_reached();
8592 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
8593 * encodes a minimum access level for the register. We roll this
8594 * runtime check into our general permission check code, so check
8595 * here that the reginfo's specified permissions are strict enough
8596 * to encompass the generic architectural permission check.
8598 if (r
->state
!= ARM_CP_STATE_AA32
) {
8602 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
8603 mask
= PL0U_R
| PL1_RW
;
8623 /* min_EL EL1, secure mode only (we don't check the latter) */
8627 /* broken reginfo with out-of-range opc1 */
8631 /* assert our permissions are not too lax (stricter is fine) */
8632 assert((r
->access
& ~mask
) == 0);
8635 /* Check that the register definition has enough info to handle
8636 * reads and writes if they are permitted.
8638 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
8639 if (r
->access
& PL3_R
) {
8640 assert((r
->fieldoffset
||
8641 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
8644 if (r
->access
& PL3_W
) {
8645 assert((r
->fieldoffset
||
8646 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
8650 /* Bad type field probably means missing sentinel at end of reg list */
8651 assert(cptype_valid(r
->type
));
8652 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
8653 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
8654 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
8655 for (state
= ARM_CP_STATE_AA32
;
8656 state
<= ARM_CP_STATE_AA64
; state
++) {
8657 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
8660 if (state
== ARM_CP_STATE_AA32
) {
8661 /* Under AArch32 CP registers can be common
8662 * (same for secure and non-secure world) or banked.
8666 switch (r
->secure
) {
8667 case ARM_CP_SECSTATE_S
:
8668 case ARM_CP_SECSTATE_NS
:
8669 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8670 r
->secure
, crm
, opc1
, opc2
,
8674 name
= g_strdup_printf("%s_S", r
->name
);
8675 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8677 crm
, opc1
, opc2
, name
);
8679 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8681 crm
, opc1
, opc2
, r
->name
);
8685 /* AArch64 registers get mapped to non-secure instance
8687 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
8689 crm
, opc1
, opc2
, r
->name
);
8697 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
8698 const ARMCPRegInfo
*regs
, void *opaque
)
8700 /* Define a whole list of registers */
8701 const ARMCPRegInfo
*r
;
8702 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
8703 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
8708 * Modify ARMCPRegInfo for access from userspace.
8710 * This is a data driven modification directed by
8711 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
8712 * user-space cannot alter any values and dynamic values pertaining to
8713 * execution state are hidden from user space view anyway.
8715 void modify_arm_cp_regs(ARMCPRegInfo
*regs
, const ARMCPRegUserSpaceInfo
*mods
)
8717 const ARMCPRegUserSpaceInfo
*m
;
8720 for (m
= mods
; m
->name
; m
++) {
8721 GPatternSpec
*pat
= NULL
;
8723 pat
= g_pattern_spec_new(m
->name
);
8725 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
8726 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
8727 r
->type
= ARM_CP_CONST
;
8731 } else if (strcmp(r
->name
, m
->name
) == 0) {
8732 r
->type
= ARM_CP_CONST
;
8734 r
->resetvalue
&= m
->exported_bits
;
8735 r
->resetvalue
|= m
->fixed_bits
;
8740 g_pattern_spec_free(pat
);
8745 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
8747 return g_hash_table_lookup(cpregs
, &encoded_cp
);
8750 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8753 /* Helper coprocessor write function for write-ignore registers */
8756 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
8758 /* Helper coprocessor write function for read-as-zero registers */
8762 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
8764 /* Helper coprocessor reset function for do-nothing-on-reset registers */
8767 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
8769 /* Return true if it is not valid for us to switch to
8770 * this CPU mode (ie all the UNPREDICTABLE cases in
8771 * the ARM ARM CPSRWriteByInstr pseudocode).
8774 /* Changes to or from Hyp via MSR and CPS are illegal. */
8775 if (write_type
== CPSRWriteByInstr
&&
8776 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
8777 mode
== ARM_CPU_MODE_HYP
)) {
8782 case ARM_CPU_MODE_USR
:
8784 case ARM_CPU_MODE_SYS
:
8785 case ARM_CPU_MODE_SVC
:
8786 case ARM_CPU_MODE_ABT
:
8787 case ARM_CPU_MODE_UND
:
8788 case ARM_CPU_MODE_IRQ
:
8789 case ARM_CPU_MODE_FIQ
:
8790 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
8791 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
8793 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
8794 * and CPS are treated as illegal mode changes.
8796 if (write_type
== CPSRWriteByInstr
&&
8797 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
8798 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
8802 case ARM_CPU_MODE_HYP
:
8803 return !arm_is_el2_enabled(env
) || arm_current_el(env
) < 2;
8804 case ARM_CPU_MODE_MON
:
8805 return arm_current_el(env
) < 3;
8811 uint32_t cpsr_read(CPUARMState
*env
)
8814 ZF
= (env
->ZF
== 0);
8815 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
8816 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
8817 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
8818 | ((env
->condexec_bits
& 0xfc) << 8)
8819 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
8822 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
8823 CPSRWriteType write_type
)
8825 uint32_t changed_daif
;
8827 if (mask
& CPSR_NZCV
) {
8828 env
->ZF
= (~val
) & CPSR_Z
;
8830 env
->CF
= (val
>> 29) & 1;
8831 env
->VF
= (val
<< 3) & 0x80000000;
8834 env
->QF
= ((val
& CPSR_Q
) != 0);
8836 env
->thumb
= ((val
& CPSR_T
) != 0);
8837 if (mask
& CPSR_IT_0_1
) {
8838 env
->condexec_bits
&= ~3;
8839 env
->condexec_bits
|= (val
>> 25) & 3;
8841 if (mask
& CPSR_IT_2_7
) {
8842 env
->condexec_bits
&= 3;
8843 env
->condexec_bits
|= (val
>> 8) & 0xfc;
8845 if (mask
& CPSR_GE
) {
8846 env
->GE
= (val
>> 16) & 0xf;
8849 /* In a V7 implementation that includes the security extensions but does
8850 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
8851 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
8852 * bits respectively.
8854 * In a V8 implementation, it is permitted for privileged software to
8855 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
8857 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
8858 arm_feature(env
, ARM_FEATURE_EL3
) &&
8859 !arm_feature(env
, ARM_FEATURE_EL2
) &&
8860 !arm_is_secure(env
)) {
8862 changed_daif
= (env
->daif
^ val
) & mask
;
8864 if (changed_daif
& CPSR_A
) {
8865 /* Check to see if we are allowed to change the masking of async
8866 * abort exceptions from a non-secure state.
8868 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
8869 qemu_log_mask(LOG_GUEST_ERROR
,
8870 "Ignoring attempt to switch CPSR_A flag from "
8871 "non-secure world with SCR.AW bit clear\n");
8876 if (changed_daif
& CPSR_F
) {
8877 /* Check to see if we are allowed to change the masking of FIQ
8878 * exceptions from a non-secure state.
8880 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
8881 qemu_log_mask(LOG_GUEST_ERROR
,
8882 "Ignoring attempt to switch CPSR_F flag from "
8883 "non-secure world with SCR.FW bit clear\n");
8887 /* Check whether non-maskable FIQ (NMFI) support is enabled.
8888 * If this bit is set software is not allowed to mask
8889 * FIQs, but is allowed to set CPSR_F to 0.
8891 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
8893 qemu_log_mask(LOG_GUEST_ERROR
,
8894 "Ignoring attempt to enable CPSR_F flag "
8895 "(non-maskable FIQ [NMFI] support enabled)\n");
8901 env
->daif
&= ~(CPSR_AIF
& mask
);
8902 env
->daif
|= val
& CPSR_AIF
& mask
;
8904 if (write_type
!= CPSRWriteRaw
&&
8905 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
8906 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
8907 /* Note that we can only get here in USR mode if this is a
8908 * gdb stub write; for this case we follow the architectural
8909 * behaviour for guest writes in USR mode of ignoring an attempt
8910 * to switch mode. (Those are caught by translate.c for writes
8911 * triggered by guest instructions.)
8914 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
8915 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
8916 * v7, and has defined behaviour in v8:
8917 * + leave CPSR.M untouched
8918 * + allow changes to the other CPSR fields
8920 * For user changes via the GDB stub, we don't set PSTATE.IL,
8921 * as this would be unnecessarily harsh for a user error.
8924 if (write_type
!= CPSRWriteByGDBStub
&&
8925 arm_feature(env
, ARM_FEATURE_V8
)) {
8929 qemu_log_mask(LOG_GUEST_ERROR
,
8930 "Illegal AArch32 mode switch attempt from %s to %s\n",
8931 aarch32_mode_name(env
->uncached_cpsr
),
8932 aarch32_mode_name(val
));
8934 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
8935 write_type
== CPSRWriteExceptionReturn
?
8936 "Exception return from AArch32" :
8937 "AArch32 mode switch from",
8938 aarch32_mode_name(env
->uncached_cpsr
),
8939 aarch32_mode_name(val
), env
->regs
[15]);
8940 switch_mode(env
, val
& CPSR_M
);
8943 mask
&= ~CACHED_CPSR_BITS
;
8944 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
8947 /* Sign/zero extend */
8948 uint32_t HELPER(sxtb16
)(uint32_t x
)
8951 res
= (uint16_t)(int8_t)x
;
8952 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
8956 uint32_t HELPER(uxtb16
)(uint32_t x
)
8959 res
= (uint16_t)(uint8_t)x
;
8960 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
8964 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
8968 if (num
== INT_MIN
&& den
== -1)
8973 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
8980 uint32_t HELPER(rbit
)(uint32_t x
)
8985 #ifdef CONFIG_USER_ONLY
8987 static void switch_mode(CPUARMState
*env
, int mode
)
8989 ARMCPU
*cpu
= env_archcpu(env
);
8991 if (mode
!= ARM_CPU_MODE_USR
) {
8992 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
8996 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
8997 uint32_t cur_el
, bool secure
)
9002 void aarch64_sync_64_to_32(CPUARMState
*env
)
9004 g_assert_not_reached();
9009 static void switch_mode(CPUARMState
*env
, int mode
)
9014 old_mode
= env
->uncached_cpsr
& CPSR_M
;
9015 if (mode
== old_mode
)
9018 if (old_mode
== ARM_CPU_MODE_FIQ
) {
9019 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
9020 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
9021 } else if (mode
== ARM_CPU_MODE_FIQ
) {
9022 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
9023 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
9026 i
= bank_number(old_mode
);
9027 env
->banked_r13
[i
] = env
->regs
[13];
9028 env
->banked_spsr
[i
] = env
->spsr
;
9030 i
= bank_number(mode
);
9031 env
->regs
[13] = env
->banked_r13
[i
];
9032 env
->spsr
= env
->banked_spsr
[i
];
9034 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
9035 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
9038 /* Physical Interrupt Target EL Lookup Table
9040 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
9042 * The below multi-dimensional table is used for looking up the target
9043 * exception level given numerous condition criteria. Specifically, the
9044 * target EL is based on SCR and HCR routing controls as well as the
9045 * currently executing EL and secure state.
9048 * target_el_table[2][2][2][2][2][4]
9049 * | | | | | +--- Current EL
9050 * | | | | +------ Non-secure(0)/Secure(1)
9051 * | | | +--------- HCR mask override
9052 * | | +------------ SCR exec state control
9053 * | +--------------- SCR mask override
9054 * +------------------ 32-bit(0)/64-bit(1) EL3
9056 * The table values are as such:
9060 * The ARM ARM target EL table includes entries indicating that an "exception
9061 * is not taken". The two cases where this is applicable are:
9062 * 1) An exception is taken from EL3 but the SCR does not have the exception
9064 * 2) An exception is taken from EL2 but the HCR does not have the exception
9066 * In these two cases, the below table contain a target of EL1. This value is
9067 * returned as it is expected that the consumer of the table data will check
9068 * for "target EL >= current EL" to ensure the exception is not taken.
9072 * BIT IRQ IMO Non-secure Secure
9073 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
9075 static const int8_t target_el_table
[2][2][2][2][2][4] = {
9076 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9077 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
9078 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9079 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
9080 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9081 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
9082 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9083 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
9084 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
9085 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
9086 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
9087 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
9088 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
9089 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
9090 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
9091 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
9095 * Determine the target EL for physical exceptions
9097 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
9098 uint32_t cur_el
, bool secure
)
9100 CPUARMState
*env
= cs
->env_ptr
;
9105 /* Is the highest EL AArch64? */
9106 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
9109 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9110 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
9112 /* Either EL2 is the highest EL (and so the EL2 register width
9113 * is given by is64); or there is no EL2 or EL3, in which case
9114 * the value of 'rw' does not affect the table lookup anyway.
9119 hcr_el2
= arm_hcr_el2_eff(env
);
9122 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
9123 hcr
= hcr_el2
& HCR_IMO
;
9126 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
9127 hcr
= hcr_el2
& HCR_FMO
;
9130 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
9131 hcr
= hcr_el2
& HCR_AMO
;
9136 * For these purposes, TGE and AMO/IMO/FMO both force the
9137 * interrupt to EL2. Fold TGE into the bit extracted above.
9139 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
9141 /* Perform a table-lookup for the target EL given the current state */
9142 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
9144 assert(target_el
> 0);
9149 void arm_log_exception(int idx
)
9151 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
9152 const char *exc
= NULL
;
9153 static const char * const excnames
[] = {
9154 [EXCP_UDEF
] = "Undefined Instruction",
9156 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
9157 [EXCP_DATA_ABORT
] = "Data Abort",
9160 [EXCP_BKPT
] = "Breakpoint",
9161 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
9162 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
9163 [EXCP_HVC
] = "Hypervisor Call",
9164 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
9165 [EXCP_SMC
] = "Secure Monitor Call",
9166 [EXCP_VIRQ
] = "Virtual IRQ",
9167 [EXCP_VFIQ
] = "Virtual FIQ",
9168 [EXCP_SEMIHOST
] = "Semihosting call",
9169 [EXCP_NOCP
] = "v7M NOCP UsageFault",
9170 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
9171 [EXCP_STKOF
] = "v8M STKOF UsageFault",
9172 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
9173 [EXCP_LSERR
] = "v8M LSERR UsageFault",
9174 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
9177 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
9178 exc
= excnames
[idx
];
9183 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s]\n", idx
, exc
);
9188 * Function used to synchronize QEMU's AArch64 register set with AArch32
9189 * register set. This is necessary when switching between AArch32 and AArch64
9192 void aarch64_sync_32_to_64(CPUARMState
*env
)
9195 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
9197 /* We can blanket copy R[0:7] to X[0:7] */
9198 for (i
= 0; i
< 8; i
++) {
9199 env
->xregs
[i
] = env
->regs
[i
];
9203 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
9204 * Otherwise, they come from the banked user regs.
9206 if (mode
== ARM_CPU_MODE_FIQ
) {
9207 for (i
= 8; i
< 13; i
++) {
9208 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
9211 for (i
= 8; i
< 13; i
++) {
9212 env
->xregs
[i
] = env
->regs
[i
];
9217 * Registers x13-x23 are the various mode SP and FP registers. Registers
9218 * r13 and r14 are only copied if we are in that mode, otherwise we copy
9219 * from the mode banked register.
9221 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
9222 env
->xregs
[13] = env
->regs
[13];
9223 env
->xregs
[14] = env
->regs
[14];
9225 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
9226 /* HYP is an exception in that it is copied from r14 */
9227 if (mode
== ARM_CPU_MODE_HYP
) {
9228 env
->xregs
[14] = env
->regs
[14];
9230 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
9234 if (mode
== ARM_CPU_MODE_HYP
) {
9235 env
->xregs
[15] = env
->regs
[13];
9237 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
9240 if (mode
== ARM_CPU_MODE_IRQ
) {
9241 env
->xregs
[16] = env
->regs
[14];
9242 env
->xregs
[17] = env
->regs
[13];
9244 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
9245 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
9248 if (mode
== ARM_CPU_MODE_SVC
) {
9249 env
->xregs
[18] = env
->regs
[14];
9250 env
->xregs
[19] = env
->regs
[13];
9252 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
9253 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
9256 if (mode
== ARM_CPU_MODE_ABT
) {
9257 env
->xregs
[20] = env
->regs
[14];
9258 env
->xregs
[21] = env
->regs
[13];
9260 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
9261 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
9264 if (mode
== ARM_CPU_MODE_UND
) {
9265 env
->xregs
[22] = env
->regs
[14];
9266 env
->xregs
[23] = env
->regs
[13];
9268 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
9269 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
9273 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9274 * mode, then we can copy from r8-r14. Otherwise, we copy from the
9275 * FIQ bank for r8-r14.
9277 if (mode
== ARM_CPU_MODE_FIQ
) {
9278 for (i
= 24; i
< 31; i
++) {
9279 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
9282 for (i
= 24; i
< 29; i
++) {
9283 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
9285 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
9286 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
9289 env
->pc
= env
->regs
[15];
9293 * Function used to synchronize QEMU's AArch32 register set with AArch64
9294 * register set. This is necessary when switching between AArch32 and AArch64
9297 void aarch64_sync_64_to_32(CPUARMState
*env
)
9300 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
9302 /* We can blanket copy X[0:7] to R[0:7] */
9303 for (i
= 0; i
< 8; i
++) {
9304 env
->regs
[i
] = env
->xregs
[i
];
9308 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
9309 * Otherwise, we copy x8-x12 into the banked user regs.
9311 if (mode
== ARM_CPU_MODE_FIQ
) {
9312 for (i
= 8; i
< 13; i
++) {
9313 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
9316 for (i
= 8; i
< 13; i
++) {
9317 env
->regs
[i
] = env
->xregs
[i
];
9322 * Registers r13 & r14 depend on the current mode.
9323 * If we are in a given mode, we copy the corresponding x registers to r13
9324 * and r14. Otherwise, we copy the x register to the banked r13 and r14
9327 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
9328 env
->regs
[13] = env
->xregs
[13];
9329 env
->regs
[14] = env
->xregs
[14];
9331 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
9334 * HYP is an exception in that it does not have its own banked r14 but
9335 * shares the USR r14
9337 if (mode
== ARM_CPU_MODE_HYP
) {
9338 env
->regs
[14] = env
->xregs
[14];
9340 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
9344 if (mode
== ARM_CPU_MODE_HYP
) {
9345 env
->regs
[13] = env
->xregs
[15];
9347 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
9350 if (mode
== ARM_CPU_MODE_IRQ
) {
9351 env
->regs
[14] = env
->xregs
[16];
9352 env
->regs
[13] = env
->xregs
[17];
9354 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
9355 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
9358 if (mode
== ARM_CPU_MODE_SVC
) {
9359 env
->regs
[14] = env
->xregs
[18];
9360 env
->regs
[13] = env
->xregs
[19];
9362 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
9363 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
9366 if (mode
== ARM_CPU_MODE_ABT
) {
9367 env
->regs
[14] = env
->xregs
[20];
9368 env
->regs
[13] = env
->xregs
[21];
9370 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
9371 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
9374 if (mode
== ARM_CPU_MODE_UND
) {
9375 env
->regs
[14] = env
->xregs
[22];
9376 env
->regs
[13] = env
->xregs
[23];
9378 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
9379 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
9382 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9383 * mode, then we can copy to r8-r14. Otherwise, we copy to the
9384 * FIQ bank for r8-r14.
9386 if (mode
== ARM_CPU_MODE_FIQ
) {
9387 for (i
= 24; i
< 31; i
++) {
9388 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
9391 for (i
= 24; i
< 29; i
++) {
9392 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
9394 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
9395 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
9398 env
->regs
[15] = env
->pc
;
9401 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
9402 uint32_t mask
, uint32_t offset
,
9407 /* Change the CPU state so as to actually take the exception. */
9408 switch_mode(env
, new_mode
);
9411 * For exceptions taken to AArch32 we must clear the SS bit in both
9412 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
9414 env
->uncached_cpsr
&= ~PSTATE_SS
;
9415 env
->spsr
= cpsr_read(env
);
9416 /* Clear IT bits. */
9417 env
->condexec_bits
= 0;
9418 /* Switch to the new mode, and to the correct instruction set. */
9419 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
9421 /* This must be after mode switching. */
9422 new_el
= arm_current_el(env
);
9424 /* Set new mode endianness */
9425 env
->uncached_cpsr
&= ~CPSR_E
;
9426 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_EE
) {
9427 env
->uncached_cpsr
|= CPSR_E
;
9429 /* J and IL must always be cleared for exception entry */
9430 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
9433 if (new_mode
== ARM_CPU_MODE_HYP
) {
9434 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
9435 env
->elr_el
[2] = env
->regs
[15];
9437 /* CPSR.PAN is normally preserved preserved unless... */
9438 if (cpu_isar_feature(aa32_pan
, env_archcpu(env
))) {
9441 if (!arm_is_secure_below_el3(env
)) {
9442 /* ... the target is EL3, from non-secure state. */
9443 env
->uncached_cpsr
&= ~CPSR_PAN
;
9446 /* ... the target is EL3, from secure state ... */
9449 /* ... the target is EL1 and SCTLR.SPAN is 0. */
9450 if (!(env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
)) {
9451 env
->uncached_cpsr
|= CPSR_PAN
;
9457 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
9458 * and we should just guard the thumb mode on V4
9460 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
9462 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
9464 env
->regs
[14] = env
->regs
[15] + offset
;
9466 env
->regs
[15] = newpc
;
9467 arm_rebuild_hflags(env
);
9470 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
9473 * Handle exception entry to Hyp mode; this is sufficiently
9474 * different to entry to other AArch32 modes that we handle it
9477 * The vector table entry used is always the 0x14 Hyp mode entry point,
9478 * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp.
9479 * The offset applied to the preferred return address is always zero
9480 * (see DDI0487C.a section G1.12.3).
9481 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
9483 uint32_t addr
, mask
;
9484 ARMCPU
*cpu
= ARM_CPU(cs
);
9485 CPUARMState
*env
= &cpu
->env
;
9487 switch (cs
->exception_index
) {
9495 /* Fall through to prefetch abort. */
9496 case EXCP_PREFETCH_ABORT
:
9497 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
9498 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
9499 (uint32_t)env
->exception
.vaddress
);
9502 case EXCP_DATA_ABORT
:
9503 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
9504 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
9505 (uint32_t)env
->exception
.vaddress
);
9521 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9524 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
9525 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
9527 * QEMU syndrome values are v8-style. v7 has the IL bit
9528 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
9529 * If this is a v7 CPU, squash the IL bit in those cases.
9531 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
9532 (cs
->exception_index
== EXCP_DATA_ABORT
&&
9533 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
9534 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
9535 env
->exception
.syndrome
&= ~ARM_EL_IL
;
9538 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
9541 if (arm_current_el(env
) != 2 && addr
< 0x14) {
9546 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
9549 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
9552 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
9556 addr
+= env
->cp15
.hvbar
;
9558 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
9561 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
9563 ARMCPU
*cpu
= ARM_CPU(cs
);
9564 CPUARMState
*env
= &cpu
->env
;
9571 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
9572 switch (syn_get_ec(env
->exception
.syndrome
)) {
9574 case EC_BREAKPOINT_SAME_EL
:
9578 case EC_WATCHPOINT_SAME_EL
:
9584 case EC_VECTORCATCH
:
9593 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
9596 if (env
->exception
.target_el
== 2) {
9597 arm_cpu_do_interrupt_aarch32_hyp(cs
);
9601 switch (cs
->exception_index
) {
9603 new_mode
= ARM_CPU_MODE_UND
;
9612 new_mode
= ARM_CPU_MODE_SVC
;
9615 /* The PC already points to the next instruction. */
9619 /* Fall through to prefetch abort. */
9620 case EXCP_PREFETCH_ABORT
:
9621 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
9622 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
9623 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
9624 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
9625 new_mode
= ARM_CPU_MODE_ABT
;
9627 mask
= CPSR_A
| CPSR_I
;
9630 case EXCP_DATA_ABORT
:
9631 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
9632 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
9633 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
9635 (uint32_t)env
->exception
.vaddress
);
9636 new_mode
= ARM_CPU_MODE_ABT
;
9638 mask
= CPSR_A
| CPSR_I
;
9642 new_mode
= ARM_CPU_MODE_IRQ
;
9644 /* Disable IRQ and imprecise data aborts. */
9645 mask
= CPSR_A
| CPSR_I
;
9647 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
9648 /* IRQ routed to monitor mode */
9649 new_mode
= ARM_CPU_MODE_MON
;
9654 new_mode
= ARM_CPU_MODE_FIQ
;
9656 /* Disable FIQ, IRQ and imprecise data aborts. */
9657 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9658 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
9659 /* FIQ routed to monitor mode */
9660 new_mode
= ARM_CPU_MODE_MON
;
9665 new_mode
= ARM_CPU_MODE_IRQ
;
9667 /* Disable IRQ and imprecise data aborts. */
9668 mask
= CPSR_A
| CPSR_I
;
9672 new_mode
= ARM_CPU_MODE_FIQ
;
9674 /* Disable FIQ, IRQ and imprecise data aborts. */
9675 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9679 new_mode
= ARM_CPU_MODE_MON
;
9681 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
9685 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9686 return; /* Never happens. Keep compiler happy. */
9689 if (new_mode
== ARM_CPU_MODE_MON
) {
9690 addr
+= env
->cp15
.mvbar
;
9691 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
9692 /* High vectors. When enabled, base address cannot be remapped. */
9695 /* ARM v7 architectures provide a vector base address register to remap
9696 * the interrupt vector table.
9697 * This register is only followed in non-monitor mode, and is banked.
9698 * Note: only bits 31:5 are valid.
9700 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
9703 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
9704 env
->cp15
.scr_el3
&= ~SCR_NS
;
9707 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
9710 static int aarch64_regnum(CPUARMState
*env
, int aarch32_reg
)
9713 * Return the register number of the AArch64 view of the AArch32
9714 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
9715 * be that of the AArch32 mode the exception came from.
9717 int mode
= env
->uncached_cpsr
& CPSR_M
;
9719 switch (aarch32_reg
) {
9723 return mode
== ARM_CPU_MODE_FIQ
? aarch32_reg
+ 16 : aarch32_reg
;
9726 case ARM_CPU_MODE_USR
:
9727 case ARM_CPU_MODE_SYS
:
9729 case ARM_CPU_MODE_HYP
:
9731 case ARM_CPU_MODE_IRQ
:
9733 case ARM_CPU_MODE_SVC
:
9735 case ARM_CPU_MODE_ABT
:
9737 case ARM_CPU_MODE_UND
:
9739 case ARM_CPU_MODE_FIQ
:
9742 g_assert_not_reached();
9746 case ARM_CPU_MODE_USR
:
9747 case ARM_CPU_MODE_SYS
:
9748 case ARM_CPU_MODE_HYP
:
9750 case ARM_CPU_MODE_IRQ
:
9752 case ARM_CPU_MODE_SVC
:
9754 case ARM_CPU_MODE_ABT
:
9756 case ARM_CPU_MODE_UND
:
9758 case ARM_CPU_MODE_FIQ
:
9761 g_assert_not_reached();
9766 g_assert_not_reached();
9770 /* Handle exception entry to a target EL which is using AArch64 */
9771 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
9773 ARMCPU
*cpu
= ARM_CPU(cs
);
9774 CPUARMState
*env
= &cpu
->env
;
9775 unsigned int new_el
= env
->exception
.target_el
;
9776 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
9777 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
9778 unsigned int old_mode
;
9779 unsigned int cur_el
= arm_current_el(env
);
9783 * Note that new_el can never be 0. If cur_el is 0, then
9784 * el0_a64 is is_a64(), else el0_a64 is ignored.
9786 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
9788 if (cur_el
< new_el
) {
9789 /* Entry vector offset depends on whether the implemented EL
9790 * immediately lower than the target level is using AArch32 or AArch64
9797 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
9800 hcr
= arm_hcr_el2_eff(env
);
9801 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
9802 is_aa64
= (hcr
& HCR_RW
) != 0;
9807 is_aa64
= is_a64(env
);
9810 g_assert_not_reached();
9818 } else if (pstate_read(env
) & PSTATE_SP
) {
9822 switch (cs
->exception_index
) {
9823 case EXCP_PREFETCH_ABORT
:
9824 case EXCP_DATA_ABORT
:
9825 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
9826 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
9827 env
->cp15
.far_el
[new_el
]);
9835 switch (syn_get_ec(env
->exception
.syndrome
)) {
9836 case EC_ADVSIMDFPACCESSTRAP
:
9838 * QEMU internal FP/SIMD syndromes from AArch32 include the
9839 * TA and coproc fields which are only exposed if the exception
9840 * is taken to AArch32 Hyp mode. Mask them out to get a valid
9841 * AArch64 format syndrome.
9843 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
9849 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
9850 * the raw register field from the insn; when taking this to
9851 * AArch64 we must convert it to the AArch64 view of the register
9852 * number. Notice that we read a 4-bit AArch32 register number and
9853 * write back a 5-bit AArch64 one.
9855 rt
= extract32(env
->exception
.syndrome
, 5, 4);
9856 rt
= aarch64_regnum(env
, rt
);
9857 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
9860 case EC_CP15RRTTRAP
:
9861 case EC_CP14RRTTRAP
:
9862 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
9863 rt
= extract32(env
->exception
.syndrome
, 5, 4);
9864 rt
= aarch64_regnum(env
, rt
);
9865 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
9867 rt
= extract32(env
->exception
.syndrome
, 10, 4);
9868 rt
= aarch64_regnum(env
, rt
);
9869 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
9873 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
9884 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
9888 old_mode
= pstate_read(env
);
9889 aarch64_save_sp(env
, arm_current_el(env
));
9890 env
->elr_el
[new_el
] = env
->pc
;
9892 old_mode
= cpsr_read(env
);
9893 env
->elr_el
[new_el
] = env
->regs
[15];
9895 aarch64_sync_32_to_64(env
);
9897 env
->condexec_bits
= 0;
9899 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = old_mode
;
9901 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
9902 env
->elr_el
[new_el
]);
9904 if (cpu_isar_feature(aa64_pan
, cpu
)) {
9905 /* The value of PSTATE.PAN is normally preserved, except when ... */
9906 new_mode
|= old_mode
& PSTATE_PAN
;
9909 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
9910 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
))
9911 != (HCR_E2H
| HCR_TGE
)) {
9916 /* ... the target is EL1 ... */
9917 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
9918 if ((env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
) == 0) {
9919 new_mode
|= PSTATE_PAN
;
9924 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9925 new_mode
|= PSTATE_TCO
;
9928 pstate_write(env
, PSTATE_DAIF
| new_mode
);
9930 aarch64_restore_sp(env
, new_el
);
9931 helper_rebuild_hflags_a64(env
, new_el
);
9935 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
9936 new_el
, env
->pc
, pstate_read(env
));
9940 * Do semihosting call and set the appropriate return value. All the
9941 * permission and validity checks have been done at translate time.
9943 * We only see semihosting exceptions in TCG only as they are not
9944 * trapped to the hypervisor in KVM.
9947 static void handle_semihosting(CPUState
*cs
)
9949 ARMCPU
*cpu
= ARM_CPU(cs
);
9950 CPUARMState
*env
= &cpu
->env
;
9953 qemu_log_mask(CPU_LOG_INT
,
9954 "...handling as semihosting call 0x%" PRIx64
"\n",
9956 env
->xregs
[0] = do_common_semihosting(cs
);
9959 qemu_log_mask(CPU_LOG_INT
,
9960 "...handling as semihosting call 0x%x\n",
9962 env
->regs
[0] = do_common_semihosting(cs
);
9963 env
->regs
[15] += env
->thumb
? 2 : 4;
9968 /* Handle a CPU exception for A and R profile CPUs.
9969 * Do any appropriate logging, handle PSCI calls, and then hand off
9970 * to the AArch64-entry or AArch32-entry function depending on the
9971 * target exception level's register width.
9973 void arm_cpu_do_interrupt(CPUState
*cs
)
9975 ARMCPU
*cpu
= ARM_CPU(cs
);
9976 CPUARMState
*env
= &cpu
->env
;
9977 unsigned int new_el
= env
->exception
.target_el
;
9979 assert(!arm_feature(env
, ARM_FEATURE_M
));
9981 arm_log_exception(cs
->exception_index
);
9982 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
9984 if (qemu_loglevel_mask(CPU_LOG_INT
)
9985 && !excp_is_internal(cs
->exception_index
)) {
9986 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
9987 syn_get_ec(env
->exception
.syndrome
),
9988 env
->exception
.syndrome
);
9991 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
9992 arm_handle_psci_call(cpu
);
9993 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
9998 * Semihosting semantics depend on the register width of the code
9999 * that caused the exception, not the target exception level, so
10000 * must be handled here.
10003 if (cs
->exception_index
== EXCP_SEMIHOST
) {
10004 handle_semihosting(cs
);
10009 /* Hooks may change global state so BQL should be held, also the
10010 * BQL needs to be held for any modification of
10011 * cs->interrupt_request.
10013 g_assert(qemu_mutex_iothread_locked());
10015 arm_call_pre_el_change_hook(cpu
);
10017 assert(!excp_is_internal(cs
->exception_index
));
10018 if (arm_el_is_aa64(env
, new_el
)) {
10019 arm_cpu_do_interrupt_aarch64(cs
);
10021 arm_cpu_do_interrupt_aarch32(cs
);
10024 arm_call_el_change_hook(cpu
);
10026 if (!kvm_enabled()) {
10027 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
10030 #endif /* !CONFIG_USER_ONLY */
10032 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
10034 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
10036 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
10037 el
= (mmu_idx
== ARMMMUIdx_E20_0
|| mmu_idx
== ARMMMUIdx_SE20_0
)
10040 return env
->cp15
.sctlr_el
[el
];
10043 /* Return the SCTLR value which controls this address translation regime */
10044 static inline uint64_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
10046 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
10049 #ifndef CONFIG_USER_ONLY
10051 /* Return true if the specified stage of address translation is disabled */
10052 static inline bool regime_translation_disabled(CPUARMState
*env
,
10057 if (arm_feature(env
, ARM_FEATURE_M
)) {
10058 switch (env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)] &
10059 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
10060 case R_V7M_MPU_CTRL_ENABLE_MASK
:
10061 /* Enabled, but not for HardFault and NMI */
10062 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
10063 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
10064 /* Enabled for all cases */
10068 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
10069 * we warned about that in armv7m_nvic.c when the guest set it.
10075 hcr_el2
= arm_hcr_el2_eff(env
);
10077 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
10078 /* HCR.DC means HCR.VM behaves as 1 */
10079 return (hcr_el2
& (HCR_DC
| HCR_VM
)) == 0;
10082 if (hcr_el2
& HCR_TGE
) {
10083 /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
10084 if (!regime_is_secure(env
, mmu_idx
) && regime_el(env
, mmu_idx
) == 1) {
10089 if ((hcr_el2
& HCR_DC
) && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
10090 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
10094 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
10097 static inline bool regime_translation_big_endian(CPUARMState
*env
,
10100 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
10103 /* Return the TTBR associated with this translation regime */
10104 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
10107 if (mmu_idx
== ARMMMUIdx_Stage2
) {
10108 return env
->cp15
.vttbr_el2
;
10110 if (mmu_idx
== ARMMMUIdx_Stage2_S
) {
10111 return env
->cp15
.vsttbr_el2
;
10114 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
10116 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
10120 #endif /* !CONFIG_USER_ONLY */
10122 /* Convert a possible stage1+2 MMU index into the appropriate
10123 * stage 1 MMU index
10125 static inline ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
10128 case ARMMMUIdx_SE10_0
:
10129 return ARMMMUIdx_Stage1_SE0
;
10130 case ARMMMUIdx_SE10_1
:
10131 return ARMMMUIdx_Stage1_SE1
;
10132 case ARMMMUIdx_SE10_1_PAN
:
10133 return ARMMMUIdx_Stage1_SE1_PAN
;
10134 case ARMMMUIdx_E10_0
:
10135 return ARMMMUIdx_Stage1_E0
;
10136 case ARMMMUIdx_E10_1
:
10137 return ARMMMUIdx_Stage1_E1
;
10138 case ARMMMUIdx_E10_1_PAN
:
10139 return ARMMMUIdx_Stage1_E1_PAN
;
10145 /* Return true if the translation regime is using LPAE format page tables */
10146 static inline bool regime_using_lpae_format(CPUARMState
*env
,
10149 int el
= regime_el(env
, mmu_idx
);
10150 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
10153 if (arm_feature(env
, ARM_FEATURE_LPAE
)
10154 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
10160 /* Returns true if the stage 1 translation regime is using LPAE format page
10161 * tables. Used when raising alignment exceptions, whose FSR changes depending
10162 * on whether the long or short descriptor format is in use. */
10163 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
10165 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
10167 return regime_using_lpae_format(env
, mmu_idx
);
10170 #ifndef CONFIG_USER_ONLY
10171 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
10174 case ARMMMUIdx_SE10_0
:
10175 case ARMMMUIdx_E20_0
:
10176 case ARMMMUIdx_SE20_0
:
10177 case ARMMMUIdx_Stage1_E0
:
10178 case ARMMMUIdx_Stage1_SE0
:
10179 case ARMMMUIdx_MUser
:
10180 case ARMMMUIdx_MSUser
:
10181 case ARMMMUIdx_MUserNegPri
:
10182 case ARMMMUIdx_MSUserNegPri
:
10186 case ARMMMUIdx_E10_0
:
10187 case ARMMMUIdx_E10_1
:
10188 case ARMMMUIdx_E10_1_PAN
:
10189 g_assert_not_reached();
10193 /* Translate section/page access permissions to page
10194 * R/W protection flags
10196 * @env: CPUARMState
10197 * @mmu_idx: MMU index indicating required translation regime
10198 * @ap: The 3-bit access permissions (AP[2:0])
10199 * @domain_prot: The 2-bit domain access permissions
10201 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
10202 int ap
, int domain_prot
)
10204 bool is_user
= regime_is_user(env
, mmu_idx
);
10206 if (domain_prot
== 3) {
10207 return PAGE_READ
| PAGE_WRITE
;
10212 if (arm_feature(env
, ARM_FEATURE_V7
)) {
10215 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
10217 return is_user
? 0 : PAGE_READ
;
10224 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
10229 return PAGE_READ
| PAGE_WRITE
;
10232 return PAGE_READ
| PAGE_WRITE
;
10233 case 4: /* Reserved. */
10236 return is_user
? 0 : PAGE_READ
;
10240 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
10245 g_assert_not_reached();
10249 /* Translate section/page access permissions to page
10250 * R/W protection flags.
10252 * @ap: The 2-bit simple AP (AP[2:1])
10253 * @is_user: TRUE if accessing from PL0
10255 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
10259 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
10261 return PAGE_READ
| PAGE_WRITE
;
10263 return is_user
? 0 : PAGE_READ
;
10267 g_assert_not_reached();
10272 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
10274 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
10277 /* Translate S2 section/page access permissions to protection flags
10279 * @env: CPUARMState
10280 * @s2ap: The 2-bit stage2 access permissions (S2AP)
10281 * @xn: XN (execute-never) bits
10282 * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0
10284 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
, bool s1_is_el0
)
10292 prot
|= PAGE_WRITE
;
10295 if (cpu_isar_feature(any_tts2uxn
, env_archcpu(env
))) {
10313 g_assert_not_reached();
10316 if (!extract32(xn
, 1, 1)) {
10317 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
10325 /* Translate section/page access permissions to protection flags
10327 * @env: CPUARMState
10328 * @mmu_idx: MMU index indicating required translation regime
10329 * @is_aa64: TRUE if AArch64
10330 * @ap: The 2-bit simple AP (AP[2:1])
10331 * @ns: NS (non-secure) bit
10332 * @xn: XN (execute-never) bit
10333 * @pxn: PXN (privileged execute-never) bit
10335 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
10336 int ap
, int ns
, int xn
, int pxn
)
10338 bool is_user
= regime_is_user(env
, mmu_idx
);
10339 int prot_rw
, user_rw
;
10343 assert(mmu_idx
!= ARMMMUIdx_Stage2
);
10344 assert(mmu_idx
!= ARMMMUIdx_Stage2_S
);
10346 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
10350 if (user_rw
&& regime_is_pan(env
, mmu_idx
)) {
10351 /* PAN forbids data accesses but doesn't affect insn fetch */
10354 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
10358 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
10362 /* TODO have_wxn should be replaced with
10363 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
10364 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
10365 * compatible processors have EL2, which is required for [U]WXN.
10367 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
10370 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
10374 if (regime_has_2_ranges(mmu_idx
) && !is_user
) {
10375 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
10377 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
10378 switch (regime_el(env
, mmu_idx
)) {
10382 xn
= xn
|| !(user_rw
& PAGE_READ
);
10386 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
10388 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
10389 (uwxn
&& (user_rw
& PAGE_WRITE
));
10399 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
10402 return prot_rw
| PAGE_EXEC
;
10405 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
10406 uint32_t *table
, uint32_t address
)
10408 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
10409 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
10411 if (address
& tcr
->mask
) {
10412 if (tcr
->raw_tcr
& TTBCR_PD1
) {
10413 /* Translation table walk disabled for TTBR1 */
10416 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
10418 if (tcr
->raw_tcr
& TTBCR_PD0
) {
10419 /* Translation table walk disabled for TTBR0 */
10422 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
10424 *table
|= (address
>> 18) & 0x3ffc;
10428 /* Translate a S1 pagetable walk through S2 if needed. */
10429 static hwaddr
S1_ptw_translate(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
10430 hwaddr addr
, bool *is_secure
,
10431 ARMMMUFaultInfo
*fi
)
10433 if (arm_mmu_idx_is_stage1_of_2(mmu_idx
) &&
10434 !regime_translation_disabled(env
, ARMMMUIdx_Stage2
)) {
10435 target_ulong s2size
;
10439 ARMMMUIdx s2_mmu_idx
= *is_secure
? ARMMMUIdx_Stage2_S
10440 : ARMMMUIdx_Stage2
;
10441 ARMCacheAttrs cacheattrs
= {};
10442 MemTxAttrs txattrs
= {};
10444 ret
= get_phys_addr_lpae(env
, addr
, MMU_DATA_LOAD
, s2_mmu_idx
, false,
10445 &s2pa
, &txattrs
, &s2prot
, &s2size
, fi
,
10448 assert(fi
->type
!= ARMFault_None
);
10452 fi
->s1ns
= !*is_secure
;
10455 if ((arm_hcr_el2_eff(env
) & HCR_PTW
) &&
10456 (cacheattrs
.attrs
& 0xf0) == 0) {
10458 * PTW set and S1 walk touched S2 Device memory:
10459 * generate Permission fault.
10461 fi
->type
= ARMFault_Permission
;
10465 fi
->s1ns
= !*is_secure
;
10469 if (arm_is_secure_below_el3(env
)) {
10470 /* Check if page table walk is to secure or non-secure PA space. */
10472 *is_secure
= !(env
->cp15
.vstcr_el2
.raw_tcr
& VSTCR_SW
);
10474 *is_secure
= !(env
->cp15
.vtcr_el2
.raw_tcr
& VTCR_NSW
);
10477 assert(!*is_secure
);
10485 /* All loads done in the course of a page table walk go through here. */
10486 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
10487 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
10489 ARMCPU
*cpu
= ARM_CPU(cs
);
10490 CPUARMState
*env
= &cpu
->env
;
10491 MemTxAttrs attrs
= {};
10492 MemTxResult result
= MEMTX_OK
;
10496 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, &is_secure
, fi
);
10497 attrs
.secure
= is_secure
;
10498 as
= arm_addressspace(cs
, attrs
);
10502 if (regime_translation_big_endian(env
, mmu_idx
)) {
10503 data
= address_space_ldl_be(as
, addr
, attrs
, &result
);
10505 data
= address_space_ldl_le(as
, addr
, attrs
, &result
);
10507 if (result
== MEMTX_OK
) {
10510 fi
->type
= ARMFault_SyncExternalOnWalk
;
10511 fi
->ea
= arm_extabort_type(result
);
10515 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
10516 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
10518 ARMCPU
*cpu
= ARM_CPU(cs
);
10519 CPUARMState
*env
= &cpu
->env
;
10520 MemTxAttrs attrs
= {};
10521 MemTxResult result
= MEMTX_OK
;
10525 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, &is_secure
, fi
);
10526 attrs
.secure
= is_secure
;
10527 as
= arm_addressspace(cs
, attrs
);
10531 if (regime_translation_big_endian(env
, mmu_idx
)) {
10532 data
= address_space_ldq_be(as
, addr
, attrs
, &result
);
10534 data
= address_space_ldq_le(as
, addr
, attrs
, &result
);
10536 if (result
== MEMTX_OK
) {
10539 fi
->type
= ARMFault_SyncExternalOnWalk
;
10540 fi
->ea
= arm_extabort_type(result
);
10544 static bool get_phys_addr_v5(CPUARMState
*env
, uint32_t address
,
10545 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10546 hwaddr
*phys_ptr
, int *prot
,
10547 target_ulong
*page_size
,
10548 ARMMMUFaultInfo
*fi
)
10550 CPUState
*cs
= env_cpu(env
);
10561 /* Pagetable walk. */
10562 /* Lookup l1 descriptor. */
10563 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
10564 /* Section translation fault if page walk is disabled by PD0 or PD1 */
10565 fi
->type
= ARMFault_Translation
;
10568 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10570 if (fi
->type
!= ARMFault_None
) {
10574 domain
= (desc
>> 5) & 0x0f;
10575 if (regime_el(env
, mmu_idx
) == 1) {
10576 dacr
= env
->cp15
.dacr_ns
;
10578 dacr
= env
->cp15
.dacr_s
;
10580 domain_prot
= (dacr
>> (domain
* 2)) & 3;
10582 /* Section translation fault. */
10583 fi
->type
= ARMFault_Translation
;
10589 if (domain_prot
== 0 || domain_prot
== 2) {
10590 fi
->type
= ARMFault_Domain
;
10595 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
10596 ap
= (desc
>> 10) & 3;
10597 *page_size
= 1024 * 1024;
10599 /* Lookup l2 entry. */
10601 /* Coarse pagetable. */
10602 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
10604 /* Fine pagetable. */
10605 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
10607 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10609 if (fi
->type
!= ARMFault_None
) {
10612 switch (desc
& 3) {
10613 case 0: /* Page translation fault. */
10614 fi
->type
= ARMFault_Translation
;
10616 case 1: /* 64k page. */
10617 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
10618 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
10619 *page_size
= 0x10000;
10621 case 2: /* 4k page. */
10622 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
10623 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
10624 *page_size
= 0x1000;
10626 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
10628 /* ARMv6/XScale extended small page format */
10629 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
10630 || arm_feature(env
, ARM_FEATURE_V6
)) {
10631 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
10632 *page_size
= 0x1000;
10634 /* UNPREDICTABLE in ARMv5; we choose to take a
10635 * page translation fault.
10637 fi
->type
= ARMFault_Translation
;
10641 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
10642 *page_size
= 0x400;
10644 ap
= (desc
>> 4) & 3;
10647 /* Never happens, but compiler isn't smart enough to tell. */
10651 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
10652 *prot
|= *prot
? PAGE_EXEC
: 0;
10653 if (!(*prot
& (1 << access_type
))) {
10654 /* Access permission fault. */
10655 fi
->type
= ARMFault_Permission
;
10658 *phys_ptr
= phys_addr
;
10661 fi
->domain
= domain
;
10666 static bool get_phys_addr_v6(CPUARMState
*env
, uint32_t address
,
10667 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
10668 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
10669 target_ulong
*page_size
, ARMMMUFaultInfo
*fi
)
10671 CPUState
*cs
= env_cpu(env
);
10672 ARMCPU
*cpu
= env_archcpu(env
);
10686 /* Pagetable walk. */
10687 /* Lookup l1 descriptor. */
10688 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
10689 /* Section translation fault if page walk is disabled by PD0 or PD1 */
10690 fi
->type
= ARMFault_Translation
;
10693 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10695 if (fi
->type
!= ARMFault_None
) {
10699 if (type
== 0 || (type
== 3 && !cpu_isar_feature(aa32_pxn
, cpu
))) {
10700 /* Section translation fault, or attempt to use the encoding
10701 * which is Reserved on implementations without PXN.
10703 fi
->type
= ARMFault_Translation
;
10706 if ((type
== 1) || !(desc
& (1 << 18))) {
10707 /* Page or Section. */
10708 domain
= (desc
>> 5) & 0x0f;
10710 if (regime_el(env
, mmu_idx
) == 1) {
10711 dacr
= env
->cp15
.dacr_ns
;
10713 dacr
= env
->cp15
.dacr_s
;
10718 domain_prot
= (dacr
>> (domain
* 2)) & 3;
10719 if (domain_prot
== 0 || domain_prot
== 2) {
10720 /* Section or Page domain fault */
10721 fi
->type
= ARMFault_Domain
;
10725 if (desc
& (1 << 18)) {
10726 /* Supersection. */
10727 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
10728 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
10729 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
10730 *page_size
= 0x1000000;
10733 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
10734 *page_size
= 0x100000;
10736 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
10737 xn
= desc
& (1 << 4);
10739 ns
= extract32(desc
, 19, 1);
10741 if (cpu_isar_feature(aa32_pxn
, cpu
)) {
10742 pxn
= (desc
>> 2) & 1;
10744 ns
= extract32(desc
, 3, 1);
10745 /* Lookup l2 entry. */
10746 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
10747 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
10749 if (fi
->type
!= ARMFault_None
) {
10752 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
10753 switch (desc
& 3) {
10754 case 0: /* Page translation fault. */
10755 fi
->type
= ARMFault_Translation
;
10757 case 1: /* 64k page. */
10758 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
10759 xn
= desc
& (1 << 15);
10760 *page_size
= 0x10000;
10762 case 2: case 3: /* 4k page. */
10763 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
10765 *page_size
= 0x1000;
10768 /* Never happens, but compiler isn't smart enough to tell. */
10772 if (domain_prot
== 3) {
10773 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
10775 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
10778 if (xn
&& access_type
== MMU_INST_FETCH
) {
10779 fi
->type
= ARMFault_Permission
;
10783 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
10784 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
10785 /* The simplified model uses AP[0] as an access control bit. */
10786 if ((ap
& 1) == 0) {
10787 /* Access flag fault. */
10788 fi
->type
= ARMFault_AccessFlag
;
10791 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
10793 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
10795 if (*prot
&& !xn
) {
10796 *prot
|= PAGE_EXEC
;
10798 if (!(*prot
& (1 << access_type
))) {
10799 /* Access permission fault. */
10800 fi
->type
= ARMFault_Permission
;
10805 /* The NS bit will (as required by the architecture) have no effect if
10806 * the CPU doesn't support TZ or this is a non-secure translation
10807 * regime, because the attribute will already be non-secure.
10809 attrs
->secure
= false;
10811 *phys_ptr
= phys_addr
;
10814 fi
->domain
= domain
;
10820 * check_s2_mmu_setup
10822 * @is_aa64: True if the translation regime is in AArch64 state
10823 * @startlevel: Suggested starting level
10824 * @inputsize: Bitsize of IPAs
10825 * @stride: Page-table stride (See the ARM ARM)
10827 * Returns true if the suggested S2 translation parameters are OK and
10830 static bool check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, int level
,
10831 int inputsize
, int stride
)
10833 const int grainsize
= stride
+ 3;
10834 int startsizecheck
;
10836 /* Negative levels are never allowed. */
10841 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
10842 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
10847 CPUARMState
*env
= &cpu
->env
;
10848 unsigned int pamax
= arm_pamax(cpu
);
10851 case 13: /* 64KB Pages. */
10852 if (level
== 0 || (level
== 1 && pamax
<= 42)) {
10856 case 11: /* 16KB Pages. */
10857 if (level
== 0 || (level
== 1 && pamax
<= 40)) {
10861 case 9: /* 4KB Pages. */
10862 if (level
== 0 && pamax
<= 42) {
10867 g_assert_not_reached();
10870 /* Inputsize checks. */
10871 if (inputsize
> pamax
&&
10872 (arm_el_is_aa64(env
, 1) || inputsize
> 40)) {
10873 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
10877 /* AArch32 only supports 4KB pages. Assert on that. */
10878 assert(stride
== 9);
10887 /* Translate from the 4-bit stage 2 representation of
10888 * memory attributes (without cache-allocation hints) to
10889 * the 8-bit representation of the stage 1 MAIR registers
10890 * (which includes allocation hints).
10892 * ref: shared/translation/attrs/S2AttrDecode()
10893 * .../S2ConvertAttrsHints()
10895 static uint8_t convert_stage2_attrs(CPUARMState
*env
, uint8_t s2attrs
)
10897 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
10898 uint8_t loattr
= extract32(s2attrs
, 0, 2);
10899 uint8_t hihint
= 0, lohint
= 0;
10901 if (hiattr
!= 0) { /* normal memory */
10902 if (arm_hcr_el2_eff(env
) & HCR_CD
) { /* cache disabled */
10903 hiattr
= loattr
= 1; /* non-cacheable */
10905 if (hiattr
!= 1) { /* Write-through or write-back */
10906 hihint
= 3; /* RW allocate */
10908 if (loattr
!= 1) { /* Write-through or write-back */
10909 lohint
= 3; /* RW allocate */
10914 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
10916 #endif /* !CONFIG_USER_ONLY */
10918 static int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
)
10920 if (regime_has_2_ranges(mmu_idx
)) {
10921 return extract64(tcr
, 37, 2);
10922 } else if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
10923 return 0; /* VTCR_EL2 */
10925 /* Replicate the single TBI bit so we always have 2 bits. */
10926 return extract32(tcr
, 20, 1) * 3;
10930 static int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
)
10932 if (regime_has_2_ranges(mmu_idx
)) {
10933 return extract64(tcr
, 51, 2);
10934 } else if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
10935 return 0; /* VTCR_EL2 */
10937 /* Replicate the single TBID bit so we always have 2 bits. */
10938 return extract32(tcr
, 29, 1) * 3;
10942 static int aa64_va_parameter_tcma(uint64_t tcr
, ARMMMUIdx mmu_idx
)
10944 if (regime_has_2_ranges(mmu_idx
)) {
10945 return extract64(tcr
, 57, 2);
10947 /* Replicate the single TCMA bit so we always have 2 bits. */
10948 return extract32(tcr
, 30, 1) * 3;
10952 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
10953 ARMMMUIdx mmu_idx
, bool data
)
10955 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
10956 bool epd
, hpd
, using16k
, using64k
;
10957 int select
, tsz
, tbi
, max_tsz
;
10959 if (!regime_has_2_ranges(mmu_idx
)) {
10961 tsz
= extract32(tcr
, 0, 6);
10962 using64k
= extract32(tcr
, 14, 1);
10963 using16k
= extract32(tcr
, 15, 1);
10964 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
10968 hpd
= extract32(tcr
, 24, 1);
10973 * Bit 55 is always between the two regions, and is canonical for
10974 * determining if address tagging is enabled.
10976 select
= extract64(va
, 55, 1);
10978 tsz
= extract32(tcr
, 0, 6);
10979 epd
= extract32(tcr
, 7, 1);
10980 using64k
= extract32(tcr
, 14, 1);
10981 using16k
= extract32(tcr
, 15, 1);
10982 hpd
= extract64(tcr
, 41, 1);
10984 int tg
= extract32(tcr
, 30, 2);
10985 using16k
= tg
== 1;
10986 using64k
= tg
== 3;
10987 tsz
= extract32(tcr
, 16, 6);
10988 epd
= extract32(tcr
, 23, 1);
10989 hpd
= extract64(tcr
, 42, 1);
10993 if (cpu_isar_feature(aa64_st
, env_archcpu(env
))) {
10994 max_tsz
= 48 - using64k
;
10999 tsz
= MIN(tsz
, max_tsz
);
11000 tsz
= MAX(tsz
, 16); /* TODO: ARMv8.2-LVA */
11002 /* Present TBI as a composite with TBID. */
11003 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
11005 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
11007 tbi
= (tbi
>> select
) & 1;
11009 return (ARMVAParameters
) {
11015 .using16k
= using16k
,
11016 .using64k
= using64k
,
11020 #ifndef CONFIG_USER_ONLY
11021 static ARMVAParameters
aa32_va_parameters(CPUARMState
*env
, uint32_t va
,
11024 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
11025 uint32_t el
= regime_el(env
, mmu_idx
);
11029 assert(mmu_idx
!= ARMMMUIdx_Stage2_S
);
11031 if (mmu_idx
== ARMMMUIdx_Stage2
) {
11033 bool sext
= extract32(tcr
, 4, 1);
11034 bool sign
= extract32(tcr
, 3, 1);
11037 * If the sign-extend bit is not the same as t0sz[3], the result
11038 * is unpredictable. Flag this as a guest error.
11040 if (sign
!= sext
) {
11041 qemu_log_mask(LOG_GUEST_ERROR
,
11042 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
11044 tsz
= sextract32(tcr
, 0, 4) + 8;
11048 } else if (el
== 2) {
11050 tsz
= extract32(tcr
, 0, 3);
11052 hpd
= extract64(tcr
, 24, 1);
11055 int t0sz
= extract32(tcr
, 0, 3);
11056 int t1sz
= extract32(tcr
, 16, 3);
11059 select
= va
> (0xffffffffu
>> t0sz
);
11061 /* Note that we will detect errors later. */
11062 select
= va
>= ~(0xffffffffu
>> t1sz
);
11066 epd
= extract32(tcr
, 7, 1);
11067 hpd
= extract64(tcr
, 41, 1);
11070 epd
= extract32(tcr
, 23, 1);
11071 hpd
= extract64(tcr
, 42, 1);
11073 /* For aarch32, hpd0 is not enabled without t2e as well. */
11074 hpd
&= extract32(tcr
, 6, 1);
11077 return (ARMVAParameters
) {
11086 * get_phys_addr_lpae: perform one stage of page table walk, LPAE format
11088 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
11089 * prot and page_size may not be filled in, and the populated fsr value provides
11090 * information on why the translation aborted, in the format of a long-format
11091 * DFSR/IFSR fault register, with the following caveats:
11092 * * the WnR bit is never set (the caller must do this).
11094 * @env: CPUARMState
11095 * @address: virtual address to get physical address for
11096 * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
11097 * @mmu_idx: MMU index indicating required translation regime
11098 * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page table
11099 * walk), must be true if this is stage 2 of a stage 1+2 walk for an
11100 * EL0 access). If @mmu_idx is anything else, @s1_is_el0 is ignored.
11101 * @phys_ptr: set to the physical address corresponding to the virtual address
11102 * @attrs: set to the memory transaction attributes to use
11103 * @prot: set to the permissions for the page containing phys_ptr
11104 * @page_size_ptr: set to the size of the page containing phys_ptr
11105 * @fi: set to fault info if the translation fails
11106 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
11108 static bool get_phys_addr_lpae(CPUARMState
*env
, uint64_t address
,
11109 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11111 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
11112 target_ulong
*page_size_ptr
,
11113 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
11115 ARMCPU
*cpu
= env_archcpu(env
);
11116 CPUState
*cs
= CPU(cpu
);
11117 /* Read an LPAE long-descriptor translation table. */
11118 ARMFaultType fault_type
= ARMFault_Translation
;
11120 ARMVAParameters param
;
11122 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
11123 uint32_t tableattrs
;
11124 target_ulong page_size
;
11127 int addrsize
, inputsize
;
11128 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
11129 int ap
, ns
, xn
, pxn
;
11130 uint32_t el
= regime_el(env
, mmu_idx
);
11131 uint64_t descaddrmask
;
11132 bool aarch64
= arm_el_is_aa64(env
, el
);
11133 bool guarded
= false;
11135 /* TODO: This code does not support shareability levels. */
11137 param
= aa64_va_parameters(env
, address
, mmu_idx
,
11138 access_type
!= MMU_INST_FETCH
);
11140 addrsize
= 64 - 8 * param
.tbi
;
11141 inputsize
= 64 - param
.tsz
;
11143 param
= aa32_va_parameters(env
, address
, mmu_idx
);
11145 addrsize
= (mmu_idx
== ARMMMUIdx_Stage2
? 40 : 32);
11146 inputsize
= addrsize
- param
.tsz
;
11150 * We determined the region when collecting the parameters, but we
11151 * have not yet validated that the address is valid for the region.
11152 * Extract the top bits and verify that they all match select.
11154 * For aa32, if inputsize == addrsize, then we have selected the
11155 * region by exclusion in aa32_va_parameters and there is no more
11156 * validation to do here.
11158 if (inputsize
< addrsize
) {
11159 target_ulong top_bits
= sextract64(address
, inputsize
,
11160 addrsize
- inputsize
);
11161 if (-top_bits
!= param
.select
) {
11162 /* The gap between the two regions is a Translation fault */
11163 fault_type
= ARMFault_Translation
;
11168 if (param
.using64k
) {
11170 } else if (param
.using16k
) {
11176 /* Note that QEMU ignores shareability and cacheability attributes,
11177 * so we don't need to do anything with the SH, ORGN, IRGN fields
11178 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
11179 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
11180 * implement any ASID-like capability so we can ignore it (instead
11181 * we will always flush the TLB any time the ASID is changed).
11183 ttbr
= regime_ttbr(env
, mmu_idx
, param
.select
);
11185 /* Here we should have set up all the parameters for the translation:
11186 * inputsize, ttbr, epd, stride, tbi
11190 /* Translation table walk disabled => Translation fault on TLB miss
11191 * Note: This is always 0 on 64-bit EL2 and EL3.
11196 if (mmu_idx
!= ARMMMUIdx_Stage2
&& mmu_idx
!= ARMMMUIdx_Stage2_S
) {
11197 /* The starting level depends on the virtual address size (which can
11198 * be up to 48 bits) and the translation granule size. It indicates
11199 * the number of strides (stride bits at a time) needed to
11200 * consume the bits of the input address. In the pseudocode this is:
11201 * level = 4 - RoundUp((inputsize - grainsize) / stride)
11202 * where their 'inputsize' is our 'inputsize', 'grainsize' is
11203 * our 'stride + 3' and 'stride' is our 'stride'.
11204 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
11205 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
11206 * = 4 - (inputsize - 4) / stride;
11208 level
= 4 - (inputsize
- 4) / stride
;
11210 /* For stage 2 translations the starting level is specified by the
11211 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
11213 uint32_t sl0
= extract32(tcr
->raw_tcr
, 6, 2);
11214 uint32_t startlevel
;
11217 if (!aarch64
|| stride
== 9) {
11218 /* AArch32 or 4KB pages */
11219 startlevel
= 2 - sl0
;
11221 if (cpu_isar_feature(aa64_st
, cpu
)) {
11225 /* 16KB or 64KB pages */
11226 startlevel
= 3 - sl0
;
11229 /* Check that the starting level is valid. */
11230 ok
= check_s2_mmu_setup(cpu
, aarch64
, startlevel
,
11231 inputsize
, stride
);
11233 fault_type
= ARMFault_Translation
;
11236 level
= startlevel
;
11239 indexmask_grainsize
= (1ULL << (stride
+ 3)) - 1;
11240 indexmask
= (1ULL << (inputsize
- (stride
* (4 - level
)))) - 1;
11242 /* Now we can extract the actual base address from the TTBR */
11243 descaddr
= extract64(ttbr
, 0, 48);
11245 * We rely on this masking to clear the RES0 bits at the bottom of the TTBR
11246 * and also to mask out CnP (bit 0) which could validly be non-zero.
11248 descaddr
&= ~indexmask
;
11250 /* The address field in the descriptor goes up to bit 39 for ARMv7
11251 * but up to bit 47 for ARMv8, but we use the descaddrmask
11252 * up to bit 39 for AArch32, because we don't need other bits in that case
11253 * to construct next descriptor address (anyway they should be all zeroes).
11255 descaddrmask
= ((1ull << (aarch64
? 48 : 40)) - 1) &
11256 ~indexmask_grainsize
;
11258 /* Secure accesses start with the page table in secure memory and
11259 * can be downgraded to non-secure at any step. Non-secure accesses
11260 * remain non-secure. We implement this by just ORing in the NSTable/NS
11261 * bits at each step.
11263 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
11265 uint64_t descriptor
;
11268 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
11270 nstable
= extract32(tableattrs
, 4, 1);
11271 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
, mmu_idx
, fi
);
11272 if (fi
->type
!= ARMFault_None
) {
11276 if (!(descriptor
& 1) ||
11277 (!(descriptor
& 2) && (level
== 3))) {
11278 /* Invalid, or the Reserved level 3 encoding */
11281 descaddr
= descriptor
& descaddrmask
;
11283 if ((descriptor
& 2) && (level
< 3)) {
11284 /* Table entry. The top five bits are attributes which may
11285 * propagate down through lower levels of the table (and
11286 * which are all arranged so that 0 means "no effect", so
11287 * we can gather them up by ORing in the bits at each level).
11289 tableattrs
|= extract64(descriptor
, 59, 5);
11291 indexmask
= indexmask_grainsize
;
11294 /* Block entry at level 1 or 2, or page entry at level 3.
11295 * These are basically the same thing, although the number
11296 * of bits we pull in from the vaddr varies.
11298 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
11299 descaddr
|= (address
& (page_size
- 1));
11300 /* Extract attributes from the descriptor */
11301 attrs
= extract64(descriptor
, 2, 10)
11302 | (extract64(descriptor
, 52, 12) << 10);
11304 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
11305 /* Stage 2 table descriptors do not include any attribute fields */
11308 /* Merge in attributes from table descriptors */
11309 attrs
|= nstable
<< 3; /* NS */
11310 guarded
= extract64(descriptor
, 50, 1); /* GP */
11312 /* HPD disables all the table attributes except NSTable. */
11315 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
11316 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
11317 * means "force PL1 access only", which means forcing AP[1] to 0.
11319 attrs
&= ~(extract32(tableattrs
, 2, 1) << 4); /* !APT[0] => AP[1] */
11320 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APT[1] => AP[2] */
11323 /* Here descaddr is the final physical address, and attributes
11324 * are all in attrs.
11326 fault_type
= ARMFault_AccessFlag
;
11327 if ((attrs
& (1 << 8)) == 0) {
11332 ap
= extract32(attrs
, 4, 2);
11334 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
11335 ns
= mmu_idx
== ARMMMUIdx_Stage2
;
11336 xn
= extract32(attrs
, 11, 2);
11337 *prot
= get_S2prot(env
, ap
, xn
, s1_is_el0
);
11339 ns
= extract32(attrs
, 3, 1);
11340 xn
= extract32(attrs
, 12, 1);
11341 pxn
= extract32(attrs
, 11, 1);
11342 *prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
11345 fault_type
= ARMFault_Permission
;
11346 if (!(*prot
& (1 << access_type
))) {
11351 /* The NS bit will (as required by the architecture) have no effect if
11352 * the CPU doesn't support TZ or this is a non-secure translation
11353 * regime, because the attribute will already be non-secure.
11355 txattrs
->secure
= false;
11357 /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
11358 if (aarch64
&& guarded
&& cpu_isar_feature(aa64_bti
, cpu
)) {
11359 arm_tlb_bti_gp(txattrs
) = true;
11362 if (mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
) {
11363 cacheattrs
->attrs
= convert_stage2_attrs(env
, extract32(attrs
, 0, 4));
11365 /* Index into MAIR registers for cache attributes */
11366 uint8_t attrindx
= extract32(attrs
, 0, 3);
11367 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
11368 assert(attrindx
<= 7);
11369 cacheattrs
->attrs
= extract64(mair
, attrindx
* 8, 8);
11371 cacheattrs
->shareability
= extract32(attrs
, 6, 2);
11373 *phys_ptr
= descaddr
;
11374 *page_size_ptr
= page_size
;
11378 fi
->type
= fault_type
;
11380 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
11381 fi
->stage2
= fi
->s1ptw
|| (mmu_idx
== ARMMMUIdx_Stage2
||
11382 mmu_idx
== ARMMMUIdx_Stage2_S
);
11383 fi
->s1ns
= mmu_idx
== ARMMMUIdx_Stage2
;
11387 static inline void get_phys_addr_pmsav7_default(CPUARMState
*env
,
11389 int32_t address
, int *prot
)
11391 if (!arm_feature(env
, ARM_FEATURE_M
)) {
11392 *prot
= PAGE_READ
| PAGE_WRITE
;
11394 case 0xF0000000 ... 0xFFFFFFFF:
11395 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
11396 /* hivecs execing is ok */
11397 *prot
|= PAGE_EXEC
;
11400 case 0x00000000 ... 0x7FFFFFFF:
11401 *prot
|= PAGE_EXEC
;
11405 /* Default system address map for M profile cores.
11406 * The architecture specifies which regions are execute-never;
11407 * at the MPU level no other checks are defined.
11410 case 0x00000000 ... 0x1fffffff: /* ROM */
11411 case 0x20000000 ... 0x3fffffff: /* SRAM */
11412 case 0x60000000 ... 0x7fffffff: /* RAM */
11413 case 0x80000000 ... 0x9fffffff: /* RAM */
11414 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
11416 case 0x40000000 ... 0x5fffffff: /* Peripheral */
11417 case 0xa0000000 ... 0xbfffffff: /* Device */
11418 case 0xc0000000 ... 0xdfffffff: /* Device */
11419 case 0xe0000000 ... 0xffffffff: /* System */
11420 *prot
= PAGE_READ
| PAGE_WRITE
;
11423 g_assert_not_reached();
11428 static bool pmsav7_use_background_region(ARMCPU
*cpu
,
11429 ARMMMUIdx mmu_idx
, bool is_user
)
11431 /* Return true if we should use the default memory map as a
11432 * "background" region if there are no hits against any MPU regions.
11434 CPUARMState
*env
= &cpu
->env
;
11440 if (arm_feature(env
, ARM_FEATURE_M
)) {
11441 return env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)]
11442 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
11444 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
11448 static inline bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
11450 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
11451 return arm_feature(env
, ARM_FEATURE_M
) &&
11452 extract32(address
, 20, 12) == 0xe00;
11455 static inline bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
11457 /* True if address is in the M profile system region
11458 * 0xe0000000 - 0xffffffff
11460 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
11463 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
11464 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11465 hwaddr
*phys_ptr
, int *prot
,
11466 target_ulong
*page_size
,
11467 ARMMMUFaultInfo
*fi
)
11469 ARMCPU
*cpu
= env_archcpu(env
);
11471 bool is_user
= regime_is_user(env
, mmu_idx
);
11473 *phys_ptr
= address
;
11474 *page_size
= TARGET_PAGE_SIZE
;
11477 if (regime_translation_disabled(env
, mmu_idx
) ||
11478 m_is_ppb_region(env
, address
)) {
11479 /* MPU disabled or M profile PPB access: use default memory map.
11480 * The other case which uses the default memory map in the
11481 * v7M ARM ARM pseudocode is exception vector reads from the vector
11482 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
11483 * which always does a direct read using address_space_ldl(), rather
11484 * than going via this function, so we don't need to check that here.
11486 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
11487 } else { /* MPU enabled */
11488 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
11489 /* region search */
11490 uint32_t base
= env
->pmsav7
.drbar
[n
];
11491 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
11493 bool srdis
= false;
11495 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
11500 qemu_log_mask(LOG_GUEST_ERROR
,
11501 "DRSR[%d]: Rsize field cannot be 0\n", n
);
11505 rmask
= (1ull << rsize
) - 1;
11507 if (base
& rmask
) {
11508 qemu_log_mask(LOG_GUEST_ERROR
,
11509 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
11510 "to DRSR region size, mask = 0x%" PRIx32
"\n",
11515 if (address
< base
|| address
> base
+ rmask
) {
11517 * Address not in this region. We must check whether the
11518 * region covers addresses in the same page as our address.
11519 * In that case we must not report a size that covers the
11520 * whole page for a subsequent hit against a different MPU
11521 * region or the background region, because it would result in
11522 * incorrect TLB hits for subsequent accesses to addresses that
11523 * are in this MPU region.
11525 if (ranges_overlap(base
, rmask
,
11526 address
& TARGET_PAGE_MASK
,
11527 TARGET_PAGE_SIZE
)) {
11533 /* Region matched */
11535 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
11537 uint32_t srdis_mask
;
11539 rsize
-= 3; /* sub region size (power of 2) */
11540 snd
= ((address
- base
) >> rsize
) & 0x7;
11541 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
11543 srdis_mask
= srdis
? 0x3 : 0x0;
11544 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
11545 /* This will check in groups of 2, 4 and then 8, whether
11546 * the subregion bits are consistent. rsize is incremented
11547 * back up to give the region size, considering consistent
11548 * adjacent subregions as one region. Stop testing if rsize
11549 * is already big enough for an entire QEMU page.
11551 int snd_rounded
= snd
& ~(i
- 1);
11552 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
11553 snd_rounded
+ 8, i
);
11554 if (srdis_mask
^ srdis_multi
) {
11557 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
11564 if (rsize
< TARGET_PAGE_BITS
) {
11565 *page_size
= 1 << rsize
;
11570 if (n
== -1) { /* no hits */
11571 if (!pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
11572 /* background fault */
11573 fi
->type
= ARMFault_Background
;
11576 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
11577 } else { /* a MPU hit! */
11578 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
11579 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
11581 if (m_is_system_region(env
, address
)) {
11582 /* System space is always execute never */
11586 if (is_user
) { /* User mode AP bit decoding */
11591 break; /* no access */
11593 *prot
|= PAGE_WRITE
;
11597 *prot
|= PAGE_READ
| PAGE_EXEC
;
11600 /* for v7M, same as 6; for R profile a reserved value */
11601 if (arm_feature(env
, ARM_FEATURE_M
)) {
11602 *prot
|= PAGE_READ
| PAGE_EXEC
;
11607 qemu_log_mask(LOG_GUEST_ERROR
,
11608 "DRACR[%d]: Bad value for AP bits: 0x%"
11609 PRIx32
"\n", n
, ap
);
11611 } else { /* Priv. mode AP bits decoding */
11614 break; /* no access */
11618 *prot
|= PAGE_WRITE
;
11622 *prot
|= PAGE_READ
| PAGE_EXEC
;
11625 /* for v7M, same as 6; for R profile a reserved value */
11626 if (arm_feature(env
, ARM_FEATURE_M
)) {
11627 *prot
|= PAGE_READ
| PAGE_EXEC
;
11632 qemu_log_mask(LOG_GUEST_ERROR
,
11633 "DRACR[%d]: Bad value for AP bits: 0x%"
11634 PRIx32
"\n", n
, ap
);
11638 /* execute never */
11640 *prot
&= ~PAGE_EXEC
;
11645 fi
->type
= ARMFault_Permission
;
11647 return !(*prot
& (1 << access_type
));
11650 static bool v8m_is_sau_exempt(CPUARMState
*env
,
11651 uint32_t address
, MMUAccessType access_type
)
11653 /* The architecture specifies that certain address ranges are
11654 * exempt from v8M SAU/IDAU checks.
11657 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
11658 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
11659 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
11660 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
11661 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
11662 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
11665 void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
11666 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11667 V8M_SAttributes
*sattrs
)
11669 /* Look up the security attributes for this address. Compare the
11670 * pseudocode SecurityCheck() function.
11671 * We assume the caller has zero-initialized *sattrs.
11673 ARMCPU
*cpu
= env_archcpu(env
);
11675 bool idau_exempt
= false, idau_ns
= true, idau_nsc
= true;
11676 int idau_region
= IREGION_NOTVALID
;
11677 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
11678 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
11681 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_GET_CLASS(cpu
->idau
);
11682 IDAUInterface
*ii
= IDAU_INTERFACE(cpu
->idau
);
11684 iic
->check(ii
, address
, &idau_region
, &idau_exempt
, &idau_ns
,
11688 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
11689 /* 0xf0000000..0xffffffff is always S for insn fetches */
11693 if (idau_exempt
|| v8m_is_sau_exempt(env
, address
, access_type
)) {
11694 sattrs
->ns
= !regime_is_secure(env
, mmu_idx
);
11698 if (idau_region
!= IREGION_NOTVALID
) {
11699 sattrs
->irvalid
= true;
11700 sattrs
->iregion
= idau_region
;
11703 switch (env
->sau
.ctrl
& 3) {
11704 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
11706 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
11709 default: /* SAU.ENABLE == 1 */
11710 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
11711 if (env
->sau
.rlar
[r
] & 1) {
11712 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
11713 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
11715 if (base
<= address
&& limit
>= address
) {
11716 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
11717 sattrs
->subpage
= true;
11719 if (sattrs
->srvalid
) {
11720 /* If we hit in more than one region then we must report
11721 * as Secure, not NS-Callable, with no valid region
11724 sattrs
->ns
= false;
11725 sattrs
->nsc
= false;
11726 sattrs
->sregion
= 0;
11727 sattrs
->srvalid
= false;
11730 if (env
->sau
.rlar
[r
] & 2) {
11731 sattrs
->nsc
= true;
11735 sattrs
->srvalid
= true;
11736 sattrs
->sregion
= r
;
11740 * Address not in this region. We must check whether the
11741 * region covers addresses in the same page as our address.
11742 * In that case we must not report a size that covers the
11743 * whole page for a subsequent hit against a different MPU
11744 * region or the background region, because it would result
11745 * in incorrect TLB hits for subsequent accesses to
11746 * addresses that are in this MPU region.
11748 if (limit
>= base
&&
11749 ranges_overlap(base
, limit
- base
+ 1,
11751 TARGET_PAGE_SIZE
)) {
11752 sattrs
->subpage
= true;
11761 * The IDAU will override the SAU lookup results if it specifies
11762 * higher security than the SAU does.
11765 if (sattrs
->ns
|| (!idau_nsc
&& sattrs
->nsc
)) {
11766 sattrs
->ns
= false;
11767 sattrs
->nsc
= idau_nsc
;
11772 bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
11773 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11774 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
11775 int *prot
, bool *is_subpage
,
11776 ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
11778 /* Perform a PMSAv8 MPU lookup (without also doing the SAU check
11779 * that a full phys-to-virt translation does).
11780 * mregion is (if not NULL) set to the region number which matched,
11781 * or -1 if no region number is returned (MPU off, address did not
11782 * hit a region, address hit in multiple regions).
11783 * We set is_subpage to true if the region hit doesn't cover the
11784 * entire TARGET_PAGE the address is within.
11786 ARMCPU
*cpu
= env_archcpu(env
);
11787 bool is_user
= regime_is_user(env
, mmu_idx
);
11788 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
11790 int matchregion
= -1;
11792 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
11793 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
11795 *is_subpage
= false;
11796 *phys_ptr
= address
;
11802 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
11803 * was an exception vector read from the vector table (which is always
11804 * done using the default system address map), because those accesses
11805 * are done in arm_v7m_load_vector(), which always does a direct
11806 * read using address_space_ldl(), rather than going via this function.
11808 if (regime_translation_disabled(env
, mmu_idx
)) { /* MPU disabled */
11810 } else if (m_is_ppb_region(env
, address
)) {
11813 if (pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
11817 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
11818 /* region search */
11819 /* Note that the base address is bits [31:5] from the register
11820 * with bits [4:0] all zeroes, but the limit address is bits
11821 * [31:5] from the register with bits [4:0] all ones.
11823 uint32_t base
= env
->pmsav8
.rbar
[secure
][n
] & ~0x1f;
11824 uint32_t limit
= env
->pmsav8
.rlar
[secure
][n
] | 0x1f;
11826 if (!(env
->pmsav8
.rlar
[secure
][n
] & 0x1)) {
11827 /* Region disabled */
11831 if (address
< base
|| address
> limit
) {
11833 * Address not in this region. We must check whether the
11834 * region covers addresses in the same page as our address.
11835 * In that case we must not report a size that covers the
11836 * whole page for a subsequent hit against a different MPU
11837 * region or the background region, because it would result in
11838 * incorrect TLB hits for subsequent accesses to addresses that
11839 * are in this MPU region.
11841 if (limit
>= base
&&
11842 ranges_overlap(base
, limit
- base
+ 1,
11844 TARGET_PAGE_SIZE
)) {
11845 *is_subpage
= true;
11850 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
11851 *is_subpage
= true;
11854 if (matchregion
!= -1) {
11855 /* Multiple regions match -- always a failure (unlike
11856 * PMSAv7 where highest-numbered-region wins)
11858 fi
->type
= ARMFault_Permission
;
11869 /* background fault */
11870 fi
->type
= ARMFault_Background
;
11874 if (matchregion
== -1) {
11875 /* hit using the background region */
11876 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
11878 uint32_t ap
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 1, 2);
11879 uint32_t xn
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 0, 1);
11882 if (arm_feature(env
, ARM_FEATURE_V8_1M
)) {
11883 pxn
= extract32(env
->pmsav8
.rlar
[secure
][matchregion
], 4, 1);
11886 if (m_is_system_region(env
, address
)) {
11887 /* System space is always execute never */
11891 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
11892 if (*prot
&& !xn
&& !(pxn
&& !is_user
)) {
11893 *prot
|= PAGE_EXEC
;
11895 /* We don't need to look the attribute up in the MAIR0/MAIR1
11896 * registers because that only tells us about cacheability.
11899 *mregion
= matchregion
;
11903 fi
->type
= ARMFault_Permission
;
11905 return !(*prot
& (1 << access_type
));
11909 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
11910 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11911 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
11912 int *prot
, target_ulong
*page_size
,
11913 ARMMMUFaultInfo
*fi
)
11915 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
11916 V8M_SAttributes sattrs
= {};
11918 bool mpu_is_subpage
;
11920 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
11921 v8m_security_lookup(env
, address
, access_type
, mmu_idx
, &sattrs
);
11922 if (access_type
== MMU_INST_FETCH
) {
11923 /* Instruction fetches always use the MMU bank and the
11924 * transaction attribute determined by the fetch address,
11925 * regardless of CPU state. This is painful for QEMU
11926 * to handle, because it would mean we need to encode
11927 * into the mmu_idx not just the (user, negpri) information
11928 * for the current security state but also that for the
11929 * other security state, which would balloon the number
11930 * of mmu_idx values needed alarmingly.
11931 * Fortunately we can avoid this because it's not actually
11932 * possible to arbitrarily execute code from memory with
11933 * the wrong security attribute: it will always generate
11934 * an exception of some kind or another, apart from the
11935 * special case of an NS CPU executing an SG instruction
11936 * in S&NSC memory. So we always just fail the translation
11937 * here and sort things out in the exception handler
11938 * (including possibly emulating an SG instruction).
11940 if (sattrs
.ns
!= !secure
) {
11942 fi
->type
= ARMFault_QEMU_NSCExec
;
11944 fi
->type
= ARMFault_QEMU_SFault
;
11946 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
11947 *phys_ptr
= address
;
11952 /* For data accesses we always use the MMU bank indicated
11953 * by the current CPU state, but the security attributes
11954 * might downgrade a secure access to nonsecure.
11957 txattrs
->secure
= false;
11958 } else if (!secure
) {
11959 /* NS access to S memory must fault.
11960 * Architecturally we should first check whether the
11961 * MPU information for this address indicates that we
11962 * are doing an unaligned access to Device memory, which
11963 * should generate a UsageFault instead. QEMU does not
11964 * currently check for that kind of unaligned access though.
11965 * If we added it we would need to do so as a special case
11966 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
11968 fi
->type
= ARMFault_QEMU_SFault
;
11969 *page_size
= sattrs
.subpage
? 1 : TARGET_PAGE_SIZE
;
11970 *phys_ptr
= address
;
11977 ret
= pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, phys_ptr
,
11978 txattrs
, prot
, &mpu_is_subpage
, fi
, NULL
);
11979 *page_size
= sattrs
.subpage
|| mpu_is_subpage
? 1 : TARGET_PAGE_SIZE
;
11983 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
11984 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
11985 hwaddr
*phys_ptr
, int *prot
,
11986 ARMMMUFaultInfo
*fi
)
11991 bool is_user
= regime_is_user(env
, mmu_idx
);
11993 if (regime_translation_disabled(env
, mmu_idx
)) {
11994 /* MPU disabled. */
11995 *phys_ptr
= address
;
11996 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
12000 *phys_ptr
= address
;
12001 for (n
= 7; n
>= 0; n
--) {
12002 base
= env
->cp15
.c6_region
[n
];
12003 if ((base
& 1) == 0) {
12006 mask
= 1 << ((base
>> 1) & 0x1f);
12007 /* Keep this shift separate from the above to avoid an
12008 (undefined) << 32. */
12009 mask
= (mask
<< 1) - 1;
12010 if (((base
^ address
) & ~mask
) == 0) {
12015 fi
->type
= ARMFault_Background
;
12019 if (access_type
== MMU_INST_FETCH
) {
12020 mask
= env
->cp15
.pmsav5_insn_ap
;
12022 mask
= env
->cp15
.pmsav5_data_ap
;
12024 mask
= (mask
>> (n
* 4)) & 0xf;
12027 fi
->type
= ARMFault_Permission
;
12032 fi
->type
= ARMFault_Permission
;
12036 *prot
= PAGE_READ
| PAGE_WRITE
;
12041 *prot
|= PAGE_WRITE
;
12045 *prot
= PAGE_READ
| PAGE_WRITE
;
12049 fi
->type
= ARMFault_Permission
;
12059 /* Bad permission. */
12060 fi
->type
= ARMFault_Permission
;
12064 *prot
|= PAGE_EXEC
;
12068 /* Combine either inner or outer cacheability attributes for normal
12069 * memory, according to table D4-42 and pseudocode procedure
12070 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
12072 * NB: only stage 1 includes allocation hints (RW bits), leading to
12075 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
12077 if (s1
== 4 || s2
== 4) {
12078 /* non-cacheable has precedence */
12080 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
12081 /* stage 1 write-through takes precedence */
12083 } else if (extract32(s2
, 2, 2) == 2) {
12084 /* stage 2 write-through takes precedence, but the allocation hint
12085 * is still taken from stage 1
12087 return (2 << 2) | extract32(s1
, 0, 2);
12088 } else { /* write-back */
12093 /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
12094 * and CombineS1S2Desc()
12096 * @s1: Attributes from stage 1 walk
12097 * @s2: Attributes from stage 2 walk
12099 static ARMCacheAttrs
combine_cacheattrs(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
12101 uint8_t s1lo
, s2lo
, s1hi
, s2hi
;
12103 bool tagged
= false;
12105 if (s1
.attrs
== 0xf0) {
12110 s1lo
= extract32(s1
.attrs
, 0, 4);
12111 s2lo
= extract32(s2
.attrs
, 0, 4);
12112 s1hi
= extract32(s1
.attrs
, 4, 4);
12113 s2hi
= extract32(s2
.attrs
, 4, 4);
12115 /* Combine shareability attributes (table D4-43) */
12116 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
12117 /* if either are outer-shareable, the result is outer-shareable */
12118 ret
.shareability
= 2;
12119 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
12120 /* if either are inner-shareable, the result is inner-shareable */
12121 ret
.shareability
= 3;
12123 /* both non-shareable */
12124 ret
.shareability
= 0;
12127 /* Combine memory type and cacheability attributes */
12128 if (s1hi
== 0 || s2hi
== 0) {
12129 /* Device has precedence over normal */
12130 if (s1lo
== 0 || s2lo
== 0) {
12131 /* nGnRnE has precedence over anything */
12133 } else if (s1lo
== 4 || s2lo
== 4) {
12134 /* non-Reordering has precedence over Reordering */
12135 ret
.attrs
= 4; /* nGnRE */
12136 } else if (s1lo
== 8 || s2lo
== 8) {
12137 /* non-Gathering has precedence over Gathering */
12138 ret
.attrs
= 8; /* nGRE */
12140 ret
.attrs
= 0xc; /* GRE */
12143 /* Any location for which the resultant memory type is any
12144 * type of Device memory is always treated as Outer Shareable.
12146 ret
.shareability
= 2;
12147 } else { /* Normal memory */
12148 /* Outer/inner cacheability combine independently */
12149 ret
.attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
12150 | combine_cacheattr_nibble(s1lo
, s2lo
);
12152 if (ret
.attrs
== 0x44) {
12153 /* Any location for which the resultant memory type is Normal
12154 * Inner Non-cacheable, Outer Non-cacheable is always treated
12155 * as Outer Shareable.
12157 ret
.shareability
= 2;
12161 /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */
12162 if (tagged
&& ret
.attrs
== 0xff) {
12170 /* get_phys_addr - get the physical address for this virtual address
12172 * Find the physical address corresponding to the given virtual address,
12173 * by doing a translation table walk on MMU based systems or using the
12174 * MPU state on MPU based systems.
12176 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
12177 * prot and page_size may not be filled in, and the populated fsr value provides
12178 * information on why the translation aborted, in the format of a
12179 * DFSR/IFSR fault register, with the following caveats:
12180 * * we honour the short vs long DFSR format differences.
12181 * * the WnR bit is never set (the caller must do this).
12182 * * for PSMAv5 based systems we don't bother to return a full FSR format
12185 * @env: CPUARMState
12186 * @address: virtual address to get physical address for
12187 * @access_type: 0 for read, 1 for write, 2 for execute
12188 * @mmu_idx: MMU index indicating required translation regime
12189 * @phys_ptr: set to the physical address corresponding to the virtual address
12190 * @attrs: set to the memory transaction attributes to use
12191 * @prot: set to the permissions for the page containing phys_ptr
12192 * @page_size: set to the size of the page containing phys_ptr
12193 * @fi: set to fault info if the translation fails
12194 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
12196 bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
12197 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
12198 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
12199 target_ulong
*page_size
,
12200 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
12202 ARMMMUIdx s1_mmu_idx
= stage_1_mmu_idx(mmu_idx
);
12204 if (mmu_idx
!= s1_mmu_idx
) {
12205 /* Call ourselves recursively to do the stage 1 and then stage 2
12206 * translations if mmu_idx is a two-stage regime.
12208 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
12212 ARMCacheAttrs cacheattrs2
= {};
12213 ARMMMUIdx s2_mmu_idx
;
12216 ret
= get_phys_addr(env
, address
, access_type
, s1_mmu_idx
, &ipa
,
12217 attrs
, prot
, page_size
, fi
, cacheattrs
);
12219 /* If S1 fails or S2 is disabled, return early. */
12220 if (ret
|| regime_translation_disabled(env
, ARMMMUIdx_Stage2
)) {
12225 s2_mmu_idx
= attrs
->secure
? ARMMMUIdx_Stage2_S
: ARMMMUIdx_Stage2
;
12226 is_el0
= mmu_idx
== ARMMMUIdx_E10_0
|| mmu_idx
== ARMMMUIdx_SE10_0
;
12228 /* S1 is done. Now do S2 translation. */
12229 ret
= get_phys_addr_lpae(env
, ipa
, access_type
, s2_mmu_idx
, is_el0
,
12230 phys_ptr
, attrs
, &s2_prot
,
12231 page_size
, fi
, &cacheattrs2
);
12233 /* Combine the S1 and S2 perms. */
12236 /* If S2 fails, return early. */
12241 /* Combine the S1 and S2 cache attributes. */
12242 if (arm_hcr_el2_eff(env
) & HCR_DC
) {
12244 * HCR.DC forces the first stage attributes to
12245 * Normal Non-Shareable,
12246 * Inner Write-Back Read-Allocate Write-Allocate,
12247 * Outer Write-Back Read-Allocate Write-Allocate.
12248 * Do not overwrite Tagged within attrs.
12250 if (cacheattrs
->attrs
!= 0xf0) {
12251 cacheattrs
->attrs
= 0xff;
12253 cacheattrs
->shareability
= 0;
12255 *cacheattrs
= combine_cacheattrs(*cacheattrs
, cacheattrs2
);
12257 /* Check if IPA translates to secure or non-secure PA space. */
12258 if (arm_is_secure_below_el3(env
)) {
12259 if (attrs
->secure
) {
12261 !(env
->cp15
.vstcr_el2
.raw_tcr
& (VSTCR_SA
| VSTCR_SW
));
12264 !((env
->cp15
.vtcr_el2
.raw_tcr
& (VTCR_NSA
| VTCR_NSW
))
12265 || (env
->cp15
.vstcr_el2
.raw_tcr
& VSTCR_SA
));
12271 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
12273 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
12277 /* The page table entries may downgrade secure to non-secure, but
12278 * cannot upgrade an non-secure translation regime's attributes
12281 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
12282 attrs
->user
= regime_is_user(env
, mmu_idx
);
12284 /* Fast Context Switch Extension. This doesn't exist at all in v8.
12285 * In v7 and earlier it affects all stage 1 translations.
12287 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_Stage2
12288 && !arm_feature(env
, ARM_FEATURE_V8
)) {
12289 if (regime_el(env
, mmu_idx
) == 3) {
12290 address
+= env
->cp15
.fcseidr_s
;
12292 address
+= env
->cp15
.fcseidr_ns
;
12296 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
12298 *page_size
= TARGET_PAGE_SIZE
;
12300 if (arm_feature(env
, ARM_FEATURE_V8
)) {
12302 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
12303 phys_ptr
, attrs
, prot
, page_size
, fi
);
12304 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
12306 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
12307 phys_ptr
, prot
, page_size
, fi
);
12310 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
12311 phys_ptr
, prot
, fi
);
12313 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
12314 " mmu_idx %u -> %s (prot %c%c%c)\n",
12315 access_type
== MMU_DATA_LOAD
? "reading" :
12316 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
12317 (uint32_t)address
, mmu_idx
,
12318 ret
? "Miss" : "Hit",
12319 *prot
& PAGE_READ
? 'r' : '-',
12320 *prot
& PAGE_WRITE
? 'w' : '-',
12321 *prot
& PAGE_EXEC
? 'x' : '-');
12326 /* Definitely a real MMU, not an MPU */
12328 if (regime_translation_disabled(env
, mmu_idx
)) {
12333 * MMU disabled. S1 addresses within aa64 translation regimes are
12334 * still checked for bounds -- see AArch64.TranslateAddressS1Off.
12336 if (mmu_idx
!= ARMMMUIdx_Stage2
&& mmu_idx
!= ARMMMUIdx_Stage2_S
) {
12337 int r_el
= regime_el(env
, mmu_idx
);
12338 if (arm_el_is_aa64(env
, r_el
)) {
12339 int pamax
= arm_pamax(env_archcpu(env
));
12340 uint64_t tcr
= env
->cp15
.tcr_el
[r_el
].raw_tcr
;
12343 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
12344 if (access_type
== MMU_INST_FETCH
) {
12345 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
12347 tbi
= (tbi
>> extract64(address
, 55, 1)) & 1;
12348 addrtop
= (tbi
? 55 : 63);
12350 if (extract64(address
, pamax
, addrtop
- pamax
+ 1) != 0) {
12351 fi
->type
= ARMFault_AddressSize
;
12353 fi
->stage2
= false;
12358 * When TBI is disabled, we've just validated that all of the
12359 * bits above PAMax are zero, so logically we only need to
12360 * clear the top byte for TBI. But it's clearer to follow
12361 * the pseudocode set of addrdesc.paddress.
12363 address
= extract64(address
, 0, 52);
12366 *phys_ptr
= address
;
12367 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
12368 *page_size
= TARGET_PAGE_SIZE
;
12370 /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
12371 hcr
= arm_hcr_el2_eff(env
);
12372 cacheattrs
->shareability
= 0;
12373 if (hcr
& HCR_DC
) {
12374 if (hcr
& HCR_DCT
) {
12375 memattr
= 0xf0; /* Tagged, Normal, WB, RWA */
12377 memattr
= 0xff; /* Normal, WB, RWA */
12379 } else if (access_type
== MMU_INST_FETCH
) {
12380 if (regime_sctlr(env
, mmu_idx
) & SCTLR_I
) {
12381 memattr
= 0xee; /* Normal, WT, RA, NT */
12383 memattr
= 0x44; /* Normal, NC, No */
12385 cacheattrs
->shareability
= 2; /* outer sharable */
12387 memattr
= 0x00; /* Device, nGnRnE */
12389 cacheattrs
->attrs
= memattr
;
12393 if (regime_using_lpae_format(env
, mmu_idx
)) {
12394 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
, false,
12395 phys_ptr
, attrs
, prot
, page_size
,
12397 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
12398 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
,
12399 phys_ptr
, attrs
, prot
, page_size
, fi
);
12401 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
,
12402 phys_ptr
, prot
, page_size
, fi
);
12406 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
12409 ARMCPU
*cpu
= ARM_CPU(cs
);
12410 CPUARMState
*env
= &cpu
->env
;
12412 target_ulong page_size
;
12415 ARMMMUFaultInfo fi
= {};
12416 ARMMMUIdx mmu_idx
= arm_mmu_idx(env
);
12417 ARMCacheAttrs cacheattrs
= {};
12419 *attrs
= (MemTxAttrs
) {};
12421 ret
= get_phys_addr(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &phys_addr
,
12422 attrs
, &prot
, &page_size
, &fi
, &cacheattrs
);
12432 /* Note that signed overflow is undefined in C. The following routines are
12433 careful to use unsigned types where modulo arithmetic is required.
12434 Failure to do so _will_ break on newer gcc. */
12436 /* Signed saturating arithmetic. */
12438 /* Perform 16-bit signed saturating addition. */
12439 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
12444 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
12453 /* Perform 8-bit signed saturating addition. */
12454 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
12459 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
12468 /* Perform 16-bit signed saturating subtraction. */
12469 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
12474 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
12483 /* Perform 8-bit signed saturating subtraction. */
12484 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
12489 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
12498 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
12499 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
12500 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
12501 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
12504 #include "op_addsub.h"
12506 /* Unsigned saturating arithmetic. */
12507 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
12516 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
12524 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
12533 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
12541 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
12542 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
12543 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
12544 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
12547 #include "op_addsub.h"
12549 /* Signed modulo arithmetic. */
12550 #define SARITH16(a, b, n, op) do { \
12552 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
12553 RESULT(sum, n, 16); \
12555 ge |= 3 << (n * 2); \
12558 #define SARITH8(a, b, n, op) do { \
12560 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
12561 RESULT(sum, n, 8); \
12567 #define ADD16(a, b, n) SARITH16(a, b, n, +)
12568 #define SUB16(a, b, n) SARITH16(a, b, n, -)
12569 #define ADD8(a, b, n) SARITH8(a, b, n, +)
12570 #define SUB8(a, b, n) SARITH8(a, b, n, -)
12574 #include "op_addsub.h"
12576 /* Unsigned modulo arithmetic. */
12577 #define ADD16(a, b, n) do { \
12579 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
12580 RESULT(sum, n, 16); \
12581 if ((sum >> 16) == 1) \
12582 ge |= 3 << (n * 2); \
12585 #define ADD8(a, b, n) do { \
12587 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
12588 RESULT(sum, n, 8); \
12589 if ((sum >> 8) == 1) \
12593 #define SUB16(a, b, n) do { \
12595 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
12596 RESULT(sum, n, 16); \
12597 if ((sum >> 16) == 0) \
12598 ge |= 3 << (n * 2); \
12601 #define SUB8(a, b, n) do { \
12603 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
12604 RESULT(sum, n, 8); \
12605 if ((sum >> 8) == 0) \
12612 #include "op_addsub.h"
12614 /* Halved signed arithmetic. */
12615 #define ADD16(a, b, n) \
12616 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
12617 #define SUB16(a, b, n) \
12618 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
12619 #define ADD8(a, b, n) \
12620 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
12621 #define SUB8(a, b, n) \
12622 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
12625 #include "op_addsub.h"
12627 /* Halved unsigned arithmetic. */
12628 #define ADD16(a, b, n) \
12629 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
12630 #define SUB16(a, b, n) \
12631 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
12632 #define ADD8(a, b, n) \
12633 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
12634 #define SUB8(a, b, n) \
12635 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
12638 #include "op_addsub.h"
12640 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
12648 /* Unsigned sum of absolute byte differences. */
12649 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
12652 sum
= do_usad(a
, b
);
12653 sum
+= do_usad(a
>> 8, b
>> 8);
12654 sum
+= do_usad(a
>> 16, b
>> 16);
12655 sum
+= do_usad(a
>> 24, b
>> 24);
12659 /* For ARMv6 SEL instruction. */
12660 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
12672 mask
|= 0xff000000;
12673 return (a
& mask
) | (b
& ~mask
);
12677 * The upper bytes of val (above the number specified by 'bytes') must have
12678 * been zeroed out by the caller.
12680 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
12684 stl_le_p(buf
, val
);
12686 /* zlib crc32 converts the accumulator and output to one's complement. */
12687 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
12690 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
12694 stl_le_p(buf
, val
);
12696 /* Linux crc32c converts the output to one's complement. */
12697 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
12700 /* Return the exception level to which FP-disabled exceptions should
12701 * be taken, or 0 if FP is enabled.
12703 int fp_exception_el(CPUARMState
*env
, int cur_el
)
12705 #ifndef CONFIG_USER_ONLY
12706 /* CPACR and the CPTR registers don't exist before v6, so FP is
12707 * always accessible
12709 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
12713 if (arm_feature(env
, ARM_FEATURE_M
)) {
12714 /* CPACR can cause a NOCP UsageFault taken to current security state */
12715 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
12719 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
12720 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
12721 /* FP insns cause a NOCP UsageFault taken to Secure */
12729 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
12730 * 0, 2 : trap EL0 and EL1/PL1 accesses
12731 * 1 : trap only EL0 accesses
12732 * 3 : trap no accesses
12733 * This register is ignored if E2H+TGE are both set.
12735 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
12736 int fpen
= extract32(env
->cp15
.cpacr_el1
, 20, 2);
12741 if (cur_el
== 0 || cur_el
== 1) {
12742 /* Trap to PL1, which might be EL1 or EL3 */
12743 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
12748 if (cur_el
== 3 && !is_a64(env
)) {
12749 /* Secure PL1 running at EL3 */
12764 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
12765 * to control non-secure access to the FPU. It doesn't have any
12766 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
12768 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
12769 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
12770 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
12771 /* FP insns act as UNDEF */
12772 return cur_el
== 2 ? 2 : 1;
12776 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
12777 * check because zero bits in the registers mean "don't trap".
12780 /* CPTR_EL2 : present in v7VE or v8 */
12781 if (cur_el
<= 2 && extract32(env
->cp15
.cptr_el
[2], 10, 1)
12782 && arm_is_el2_enabled(env
)) {
12783 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
12787 /* CPTR_EL3 : present in v8 */
12788 if (extract32(env
->cp15
.cptr_el
[3], 10, 1)) {
12789 /* Trap all FP ops to EL3 */
12796 /* Return the exception level we're running at if this is our mmu_idx */
12797 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
12799 if (mmu_idx
& ARM_MMU_IDX_M
) {
12800 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
12804 case ARMMMUIdx_E10_0
:
12805 case ARMMMUIdx_E20_0
:
12806 case ARMMMUIdx_SE10_0
:
12807 case ARMMMUIdx_SE20_0
:
12809 case ARMMMUIdx_E10_1
:
12810 case ARMMMUIdx_E10_1_PAN
:
12811 case ARMMMUIdx_SE10_1
:
12812 case ARMMMUIdx_SE10_1_PAN
:
12815 case ARMMMUIdx_E20_2
:
12816 case ARMMMUIdx_E20_2_PAN
:
12817 case ARMMMUIdx_SE2
:
12818 case ARMMMUIdx_SE20_2
:
12819 case ARMMMUIdx_SE20_2_PAN
:
12821 case ARMMMUIdx_SE3
:
12824 g_assert_not_reached();
12829 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
12831 g_assert_not_reached();
12835 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
12840 if (arm_feature(env
, ARM_FEATURE_M
)) {
12841 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
12844 /* See ARM pseudo-function ELIsInHost. */
12847 hcr
= arm_hcr_el2_eff(env
);
12848 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
12849 idx
= ARMMMUIdx_E20_0
;
12851 idx
= ARMMMUIdx_E10_0
;
12855 if (env
->pstate
& PSTATE_PAN
) {
12856 idx
= ARMMMUIdx_E10_1_PAN
;
12858 idx
= ARMMMUIdx_E10_1
;
12862 /* Note that TGE does not apply at EL2. */
12863 if (arm_hcr_el2_eff(env
) & HCR_E2H
) {
12864 if (env
->pstate
& PSTATE_PAN
) {
12865 idx
= ARMMMUIdx_E20_2_PAN
;
12867 idx
= ARMMMUIdx_E20_2
;
12870 idx
= ARMMMUIdx_E2
;
12874 return ARMMMUIdx_SE3
;
12876 g_assert_not_reached();
12879 if (arm_is_secure_below_el3(env
)) {
12880 idx
&= ~ARM_MMU_IDX_A_NS
;
12886 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
12888 return arm_mmu_idx_el(env
, arm_current_el(env
));
12891 #ifndef CONFIG_USER_ONLY
12892 ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
)
12894 return stage_1_mmu_idx(arm_mmu_idx(env
));
12898 static uint32_t rebuild_hflags_common(CPUARMState
*env
, int fp_el
,
12899 ARMMMUIdx mmu_idx
, uint32_t flags
)
12901 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, FPEXC_EL
, fp_el
);
12902 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, MMUIDX
,
12903 arm_to_core_mmu_idx(mmu_idx
));
12905 if (arm_singlestep_active(env
)) {
12906 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, SS_ACTIVE
, 1);
12911 static uint32_t rebuild_hflags_common_32(CPUARMState
*env
, int fp_el
,
12912 ARMMMUIdx mmu_idx
, uint32_t flags
)
12914 bool sctlr_b
= arm_sctlr_b(env
);
12917 flags
= FIELD_DP32(flags
, TBFLAG_A32
, SCTLR_B
, 1);
12919 if (arm_cpu_data_is_big_endian_a32(env
, sctlr_b
)) {
12920 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, BE_DATA
, 1);
12922 flags
= FIELD_DP32(flags
, TBFLAG_A32
, NS
, !access_secure_reg(env
));
12924 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
12927 static uint32_t rebuild_hflags_m32(CPUARMState
*env
, int fp_el
,
12930 uint32_t flags
= 0;
12932 if (arm_v7m_is_handler_mode(env
)) {
12933 flags
= FIELD_DP32(flags
, TBFLAG_M32
, HANDLER
, 1);
12937 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
12938 * is suppressing them because the requested execution priority
12941 if (arm_feature(env
, ARM_FEATURE_V8
) &&
12942 !((mmu_idx
& ARM_MMU_IDX_M_NEGPRI
) &&
12943 (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_STKOFHFNMIGN_MASK
))) {
12944 flags
= FIELD_DP32(flags
, TBFLAG_M32
, STACKCHECK
, 1);
12947 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
12950 static uint32_t rebuild_hflags_aprofile(CPUARMState
*env
)
12954 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
,
12955 arm_debug_target_el(env
));
12959 static uint32_t rebuild_hflags_a32(CPUARMState
*env
, int fp_el
,
12962 uint32_t flags
= rebuild_hflags_aprofile(env
);
12964 if (arm_el_is_aa64(env
, 1)) {
12965 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VFPEN
, 1);
12968 if (arm_current_el(env
) < 2 && env
->cp15
.hstr_el2
&&
12969 (arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
12970 flags
= FIELD_DP32(flags
, TBFLAG_A32
, HSTR_ACTIVE
, 1);
12973 return rebuild_hflags_common_32(env
, fp_el
, mmu_idx
, flags
);
12976 static uint32_t rebuild_hflags_a64(CPUARMState
*env
, int el
, int fp_el
,
12979 uint32_t flags
= rebuild_hflags_aprofile(env
);
12980 ARMMMUIdx stage1
= stage_1_mmu_idx(mmu_idx
);
12981 uint64_t tcr
= regime_tcr(env
, mmu_idx
)->raw_tcr
;
12985 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, AARCH64_STATE
, 1);
12987 /* Get control bits for tagged addresses. */
12988 tbid
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
12989 tbii
= tbid
& ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
12991 flags
= FIELD_DP32(flags
, TBFLAG_A64
, TBII
, tbii
);
12992 flags
= FIELD_DP32(flags
, TBFLAG_A64
, TBID
, tbid
);
12994 if (cpu_isar_feature(aa64_sve
, env_archcpu(env
))) {
12995 int sve_el
= sve_exception_el(env
, el
);
12999 * If SVE is disabled, but FP is enabled,
13000 * then the effective len is 0.
13002 if (sve_el
!= 0 && fp_el
== 0) {
13005 zcr_len
= sve_zcr_len_for_el(env
, el
);
13007 flags
= FIELD_DP32(flags
, TBFLAG_A64
, SVEEXC_EL
, sve_el
);
13008 flags
= FIELD_DP32(flags
, TBFLAG_A64
, ZCR_LEN
, zcr_len
);
13011 sctlr
= regime_sctlr(env
, stage1
);
13013 if (arm_cpu_data_is_big_endian_a64(el
, sctlr
)) {
13014 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, BE_DATA
, 1);
13017 if (cpu_isar_feature(aa64_pauth
, env_archcpu(env
))) {
13019 * In order to save space in flags, we record only whether
13020 * pauth is "inactive", meaning all insns are implemented as
13021 * a nop, or "active" when some action must be performed.
13022 * The decision of which action to take is left to a helper.
13024 if (sctlr
& (SCTLR_EnIA
| SCTLR_EnIB
| SCTLR_EnDA
| SCTLR_EnDB
)) {
13025 flags
= FIELD_DP32(flags
, TBFLAG_A64
, PAUTH_ACTIVE
, 1);
13029 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
13030 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
13031 if (sctlr
& (el
== 0 ? SCTLR_BT0
: SCTLR_BT1
)) {
13032 flags
= FIELD_DP32(flags
, TBFLAG_A64
, BT
, 1);
13036 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
13037 if (!(env
->pstate
& PSTATE_UAO
)) {
13039 case ARMMMUIdx_E10_1
:
13040 case ARMMMUIdx_E10_1_PAN
:
13041 case ARMMMUIdx_SE10_1
:
13042 case ARMMMUIdx_SE10_1_PAN
:
13043 /* TODO: ARMv8.3-NV */
13044 flags
= FIELD_DP32(flags
, TBFLAG_A64
, UNPRIV
, 1);
13046 case ARMMMUIdx_E20_2
:
13047 case ARMMMUIdx_E20_2_PAN
:
13048 case ARMMMUIdx_SE20_2
:
13049 case ARMMMUIdx_SE20_2_PAN
:
13051 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
13052 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
13054 if (env
->cp15
.hcr_el2
& HCR_TGE
) {
13055 flags
= FIELD_DP32(flags
, TBFLAG_A64
, UNPRIV
, 1);
13063 if (cpu_isar_feature(aa64_mte
, env_archcpu(env
))) {
13065 * Set MTE_ACTIVE if any access may be Checked, and leave clear
13066 * if all accesses must be Unchecked:
13067 * 1) If no TBI, then there are no tags in the address to check,
13068 * 2) If Tag Check Override, then all accesses are Unchecked,
13069 * 3) If Tag Check Fail == 0, then Checked access have no effect,
13070 * 4) If no Allocation Tag Access, then all accesses are Unchecked.
13072 if (allocation_tag_access_enabled(env
, el
, sctlr
)) {
13073 flags
= FIELD_DP32(flags
, TBFLAG_A64
, ATA
, 1);
13075 && !(env
->pstate
& PSTATE_TCO
)
13076 && (sctlr
& (el
== 0 ? SCTLR_TCF0
: SCTLR_TCF
))) {
13077 flags
= FIELD_DP32(flags
, TBFLAG_A64
, MTE_ACTIVE
, 1);
13080 /* And again for unprivileged accesses, if required. */
13081 if (FIELD_EX32(flags
, TBFLAG_A64
, UNPRIV
)
13083 && !(env
->pstate
& PSTATE_TCO
)
13084 && (sctlr
& SCTLR_TCF
)
13085 && allocation_tag_access_enabled(env
, 0, sctlr
)) {
13086 flags
= FIELD_DP32(flags
, TBFLAG_A64
, MTE0_ACTIVE
, 1);
13088 /* Cache TCMA as well as TBI. */
13089 flags
= FIELD_DP32(flags
, TBFLAG_A64
, TCMA
,
13090 aa64_va_parameter_tcma(tcr
, mmu_idx
));
13093 return rebuild_hflags_common(env
, fp_el
, mmu_idx
, flags
);
13096 static uint32_t rebuild_hflags_internal(CPUARMState
*env
)
13098 int el
= arm_current_el(env
);
13099 int fp_el
= fp_exception_el(env
, el
);
13100 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
13103 return rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
13104 } else if (arm_feature(env
, ARM_FEATURE_M
)) {
13105 return rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
13107 return rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
13111 void arm_rebuild_hflags(CPUARMState
*env
)
13113 env
->hflags
= rebuild_hflags_internal(env
);
13117 * If we have triggered a EL state change we can't rely on the
13118 * translator having passed it to us, we need to recompute.
13120 void HELPER(rebuild_hflags_m32_newel
)(CPUARMState
*env
)
13122 int el
= arm_current_el(env
);
13123 int fp_el
= fp_exception_el(env
, el
);
13124 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
13125 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
13128 void HELPER(rebuild_hflags_m32
)(CPUARMState
*env
, int el
)
13130 int fp_el
= fp_exception_el(env
, el
);
13131 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
13133 env
->hflags
= rebuild_hflags_m32(env
, fp_el
, mmu_idx
);
13137 * If we have triggered a EL state change we can't rely on the
13138 * translator having passed it to us, we need to recompute.
13140 void HELPER(rebuild_hflags_a32_newel
)(CPUARMState
*env
)
13142 int el
= arm_current_el(env
);
13143 int fp_el
= fp_exception_el(env
, el
);
13144 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
13145 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
13148 void HELPER(rebuild_hflags_a32
)(CPUARMState
*env
, int el
)
13150 int fp_el
= fp_exception_el(env
, el
);
13151 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
13153 env
->hflags
= rebuild_hflags_a32(env
, fp_el
, mmu_idx
);
13156 void HELPER(rebuild_hflags_a64
)(CPUARMState
*env
, int el
)
13158 int fp_el
= fp_exception_el(env
, el
);
13159 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, el
);
13161 env
->hflags
= rebuild_hflags_a64(env
, el
, fp_el
, mmu_idx
);
13164 static inline void assert_hflags_rebuild_correctly(CPUARMState
*env
)
13166 #ifdef CONFIG_DEBUG_TCG
13167 uint32_t env_flags_current
= env
->hflags
;
13168 uint32_t env_flags_rebuilt
= rebuild_hflags_internal(env
);
13170 if (unlikely(env_flags_current
!= env_flags_rebuilt
)) {
13171 fprintf(stderr
, "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n",
13172 env_flags_current
, env_flags_rebuilt
);
13178 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
13179 target_ulong
*cs_base
, uint32_t *pflags
)
13181 uint32_t flags
= env
->hflags
;
13182 uint32_t pstate_for_ss
;
13185 assert_hflags_rebuild_correctly(env
);
13187 if (FIELD_EX32(flags
, TBFLAG_ANY
, AARCH64_STATE
)) {
13189 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
13190 flags
= FIELD_DP32(flags
, TBFLAG_A64
, BTYPE
, env
->btype
);
13192 pstate_for_ss
= env
->pstate
;
13194 *pc
= env
->regs
[15];
13196 if (arm_feature(env
, ARM_FEATURE_M
)) {
13197 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
13198 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
13199 != env
->v7m
.secure
) {
13200 flags
= FIELD_DP32(flags
, TBFLAG_M32
, FPCCR_S_WRONG
, 1);
13203 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
13204 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
13205 (env
->v7m
.secure
&&
13206 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
13208 * ASPEN is set, but FPCA/SFPA indicate that there is no
13209 * active FP context; we must create a new FP context before
13210 * executing any FP insn.
13212 flags
= FIELD_DP32(flags
, TBFLAG_M32
, NEW_FP_CTXT_NEEDED
, 1);
13215 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
13216 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
13217 flags
= FIELD_DP32(flags
, TBFLAG_M32
, LSPACT
, 1);
13221 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
13222 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
13224 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
13225 flags
= FIELD_DP32(flags
, TBFLAG_A32
,
13226 XSCALE_CPAR
, env
->cp15
.c15_cpar
);
13228 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VECLEN
,
13230 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VECSTRIDE
,
13231 env
->vfp
.vec_stride
);
13233 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
13234 flags
= FIELD_DP32(flags
, TBFLAG_A32
, VFPEN
, 1);
13238 flags
= FIELD_DP32(flags
, TBFLAG_AM32
, THUMB
, env
->thumb
);
13239 flags
= FIELD_DP32(flags
, TBFLAG_AM32
, CONDEXEC
, env
->condexec_bits
);
13240 pstate_for_ss
= env
->uncached_cpsr
;
13244 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
13245 * states defined in the ARM ARM for software singlestep:
13246 * SS_ACTIVE PSTATE.SS State
13247 * 0 x Inactive (the TB flag for SS is always 0)
13248 * 1 0 Active-pending
13249 * 1 1 Active-not-pending
13250 * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB.
13252 if (FIELD_EX32(flags
, TBFLAG_ANY
, SS_ACTIVE
) &&
13253 (pstate_for_ss
& PSTATE_SS
)) {
13254 flags
= FIELD_DP32(flags
, TBFLAG_ANY
, PSTATE_SS
, 1);
13260 #ifdef TARGET_AARCH64
13262 * The manual says that when SVE is enabled and VQ is widened the
13263 * implementation is allowed to zero the previously inaccessible
13264 * portion of the registers. The corollary to that is that when
13265 * SVE is enabled and VQ is narrowed we are also allowed to zero
13266 * the now inaccessible portion of the registers.
13268 * The intent of this is that no predicate bit beyond VQ is ever set.
13269 * Which means that some operations on predicate registers themselves
13270 * may operate on full uint64_t or even unrolled across the maximum
13271 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
13272 * may well be cheaper than conditionals to restrict the operation
13273 * to the relevant portion of a uint16_t[16].
13275 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
13280 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
13281 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
13283 /* Zap the high bits of the zregs. */
13284 for (i
= 0; i
< 32; i
++) {
13285 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
13288 /* Zap the high bits of the pregs and ffr. */
13291 pmask
= ~(-1ULL << (16 * (vq
& 3)));
13293 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
13294 for (i
= 0; i
< 17; ++i
) {
13295 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
13302 * Notice a change in SVE vector size when changing EL.
13304 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
13305 int new_el
, bool el0_a64
)
13307 ARMCPU
*cpu
= env_archcpu(env
);
13308 int old_len
, new_len
;
13309 bool old_a64
, new_a64
;
13311 /* Nothing to do if no SVE. */
13312 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
13316 /* Nothing to do if FP is disabled in either EL. */
13317 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
13322 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
13323 * at ELx, or not available because the EL is in AArch32 state, then
13324 * for all purposes other than a direct read, the ZCR_ELx.LEN field
13325 * has an effective value of 0".
13327 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
13328 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
13329 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
13330 * we already have the correct register contents when encountering the
13331 * vq0->vq0 transition between EL0->EL1.
13333 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
13334 old_len
= (old_a64
&& !sve_exception_el(env
, old_el
)
13335 ? sve_zcr_len_for_el(env
, old_el
) : 0);
13336 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
13337 new_len
= (new_a64
&& !sve_exception_el(env
, new_el
)
13338 ? sve_zcr_len_for_el(env
, new_el
) : 0);
13340 /* When changing vector length, clear inaccessible state. */
13341 if (new_len
< old_len
) {
13342 aarch64_sve_narrow_vq(env
, new_len
+ 1);