hw/char/mchp_pfsoc_mmuart.c

   1 /*
   2  * Microchip PolarFire SoC MMUART emulation
   3  *
   4  * Copyright (c) 2020 Wind River Systems, Inc.
   5  *
   6  * Author:
   7  *   Bin Meng <bin.meng@windriver.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 or
  12  * (at your option) version 3 of the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along
  20  * with this program; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "qemu/log.h"
  25 #include "chardev/char.h"
  26 #include "hw/char/mchp_pfsoc_mmuart.h"
  27
  28 static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
  29 {
  30     MchpPfSoCMMUartState *s = opaque;
  31
  32     if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
  33         qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
  34                       __func__, addr);
  35         return 0;
  36     }
  37
  38     return s->reg[addr / sizeof(uint32_t)];
  39 }
  40
  41 static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
  42                                     uint64_t value, unsigned size)
  43 {
  44     MchpPfSoCMMUartState *s = opaque;
  45     uint32_t val32 = (uint32_t)value;
  46
  47     if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
  48         qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
  49                       " v=0x%x\n", __func__, addr, val32);
  50         return;
  51     }
  52
  53     s->reg[addr / sizeof(uint32_t)] = val32;
  54 }
  55
  56 static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
  57     .read = mchp_pfsoc_mmuart_read,
  58     .write = mchp_pfsoc_mmuart_write,
  59     .endianness = DEVICE_LITTLE_ENDIAN,
  60     .impl = {
  61         .min_access_size = 4,
  62         .max_access_size = 4,
  63     },
  64 };
  65
  66 MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
  67     hwaddr base, qemu_irq irq, Chardev *chr)
  68 {
  69     MchpPfSoCMMUartState *s;
  70
  71     s = g_new0(MchpPfSoCMMUartState, 1);
  72
  73     memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
  74                           "mchp.pfsoc.mmuart", 0x1000);
  75
  76     s->base = base;
  77     s->irq = irq;
  78
  79     s->serial = serial_mm_init(sysmem, base, 2, irq, 399193, chr,
  80                                DEVICE_LITTLE_ENDIAN);
  81
  82     memory_region_add_subregion(sysmem, base + 0x20, &s->iomem);
  83
  84     return s;
  85 }