4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
7 * Copyright 2016 IBM Corp.
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "hw/misc/unimp.h"
16 #include "hw/arm/aspeed_soc.h"
17 #include "hw/char/serial.h"
18 #include "qemu/module.h"
19 #include "qemu/error-report.h"
20 #include "hw/i2c/aspeed_i2c.h"
22 #include "sysemu/sysemu.h"
24 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
26 static const hwaddr aspeed_soc_ast2400_memmap
[] = {
27 [ASPEED_DEV_IOMEM
] = 0x1E600000,
28 [ASPEED_DEV_FMC
] = 0x1E620000,
29 [ASPEED_DEV_SPI1
] = 0x1E630000,
30 [ASPEED_DEV_EHCI1
] = 0x1E6A1000,
31 [ASPEED_DEV_VIC
] = 0x1E6C0000,
32 [ASPEED_DEV_SDMC
] = 0x1E6E0000,
33 [ASPEED_DEV_SCU
] = 0x1E6E2000,
34 [ASPEED_DEV_XDMA
] = 0x1E6E7000,
35 [ASPEED_DEV_VIDEO
] = 0x1E700000,
36 [ASPEED_DEV_ADC
] = 0x1E6E9000,
37 [ASPEED_DEV_SRAM
] = 0x1E720000,
38 [ASPEED_DEV_SDHCI
] = 0x1E740000,
39 [ASPEED_DEV_GPIO
] = 0x1E780000,
40 [ASPEED_DEV_RTC
] = 0x1E781000,
41 [ASPEED_DEV_TIMER1
] = 0x1E782000,
42 [ASPEED_DEV_WDT
] = 0x1E785000,
43 [ASPEED_DEV_PWM
] = 0x1E786000,
44 [ASPEED_DEV_LPC
] = 0x1E789000,
45 [ASPEED_DEV_IBT
] = 0x1E789140,
46 [ASPEED_DEV_I2C
] = 0x1E78A000,
47 [ASPEED_DEV_ETH1
] = 0x1E660000,
48 [ASPEED_DEV_ETH2
] = 0x1E680000,
49 [ASPEED_DEV_UART1
] = 0x1E783000,
50 [ASPEED_DEV_UART5
] = 0x1E784000,
51 [ASPEED_DEV_VUART
] = 0x1E787000,
52 [ASPEED_DEV_SDRAM
] = 0x40000000,
55 static const hwaddr aspeed_soc_ast2500_memmap
[] = {
56 [ASPEED_DEV_IOMEM
] = 0x1E600000,
57 [ASPEED_DEV_FMC
] = 0x1E620000,
58 [ASPEED_DEV_SPI1
] = 0x1E630000,
59 [ASPEED_DEV_SPI2
] = 0x1E631000,
60 [ASPEED_DEV_EHCI1
] = 0x1E6A1000,
61 [ASPEED_DEV_EHCI2
] = 0x1E6A3000,
62 [ASPEED_DEV_VIC
] = 0x1E6C0000,
63 [ASPEED_DEV_SDMC
] = 0x1E6E0000,
64 [ASPEED_DEV_SCU
] = 0x1E6E2000,
65 [ASPEED_DEV_XDMA
] = 0x1E6E7000,
66 [ASPEED_DEV_ADC
] = 0x1E6E9000,
67 [ASPEED_DEV_VIDEO
] = 0x1E700000,
68 [ASPEED_DEV_SRAM
] = 0x1E720000,
69 [ASPEED_DEV_SDHCI
] = 0x1E740000,
70 [ASPEED_DEV_GPIO
] = 0x1E780000,
71 [ASPEED_DEV_RTC
] = 0x1E781000,
72 [ASPEED_DEV_TIMER1
] = 0x1E782000,
73 [ASPEED_DEV_WDT
] = 0x1E785000,
74 [ASPEED_DEV_PWM
] = 0x1E786000,
75 [ASPEED_DEV_LPC
] = 0x1E789000,
76 [ASPEED_DEV_IBT
] = 0x1E789140,
77 [ASPEED_DEV_I2C
] = 0x1E78A000,
78 [ASPEED_DEV_ETH1
] = 0x1E660000,
79 [ASPEED_DEV_ETH2
] = 0x1E680000,
80 [ASPEED_DEV_UART1
] = 0x1E783000,
81 [ASPEED_DEV_UART5
] = 0x1E784000,
82 [ASPEED_DEV_VUART
] = 0x1E787000,
83 [ASPEED_DEV_SDRAM
] = 0x80000000,
86 static const int aspeed_soc_ast2400_irqmap
[] = {
87 [ASPEED_DEV_UART1
] = 9,
88 [ASPEED_DEV_UART2
] = 32,
89 [ASPEED_DEV_UART3
] = 33,
90 [ASPEED_DEV_UART4
] = 34,
91 [ASPEED_DEV_UART5
] = 10,
92 [ASPEED_DEV_VUART
] = 8,
93 [ASPEED_DEV_FMC
] = 19,
94 [ASPEED_DEV_EHCI1
] = 5,
95 [ASPEED_DEV_EHCI2
] = 13,
96 [ASPEED_DEV_SDMC
] = 0,
97 [ASPEED_DEV_SCU
] = 21,
98 [ASPEED_DEV_ADC
] = 31,
99 [ASPEED_DEV_GPIO
] = 20,
100 [ASPEED_DEV_RTC
] = 22,
101 [ASPEED_DEV_TIMER1
] = 16,
102 [ASPEED_DEV_TIMER2
] = 17,
103 [ASPEED_DEV_TIMER3
] = 18,
104 [ASPEED_DEV_TIMER4
] = 35,
105 [ASPEED_DEV_TIMER5
] = 36,
106 [ASPEED_DEV_TIMER6
] = 37,
107 [ASPEED_DEV_TIMER7
] = 38,
108 [ASPEED_DEV_TIMER8
] = 39,
109 [ASPEED_DEV_WDT
] = 27,
110 [ASPEED_DEV_PWM
] = 28,
111 [ASPEED_DEV_LPC
] = 8,
112 [ASPEED_DEV_I2C
] = 12,
113 [ASPEED_DEV_ETH1
] = 2,
114 [ASPEED_DEV_ETH2
] = 3,
115 [ASPEED_DEV_XDMA
] = 6,
116 [ASPEED_DEV_SDHCI
] = 26,
119 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
121 static qemu_irq
aspeed_soc_get_irq(AspeedSoCState
*s
, int ctrl
)
123 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
125 return qdev_get_gpio_in(DEVICE(&s
->vic
), sc
->irqmap
[ctrl
]);
128 static void aspeed_soc_init(Object
*obj
)
130 AspeedSoCState
*s
= ASPEED_SOC(obj
);
131 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
136 if (sscanf(sc
->name
, "%7s", socname
) != 1) {
137 g_assert_not_reached();
140 for (i
= 0; i
< sc
->num_cpus
; i
++) {
141 object_initialize_child(obj
, "cpu[*]", &s
->cpu
[i
], sc
->cpu_type
);
144 snprintf(typename
, sizeof(typename
), "aspeed.scu-%s", socname
);
145 object_initialize_child(obj
, "scu", &s
->scu
, typename
);
146 qdev_prop_set_uint32(DEVICE(&s
->scu
), "silicon-rev",
148 object_property_add_alias(obj
, "hw-strap1", OBJECT(&s
->scu
),
150 object_property_add_alias(obj
, "hw-strap2", OBJECT(&s
->scu
),
152 object_property_add_alias(obj
, "hw-prot-key", OBJECT(&s
->scu
),
155 object_initialize_child(obj
, "vic", &s
->vic
, TYPE_ASPEED_VIC
);
157 object_initialize_child(obj
, "rtc", &s
->rtc
, TYPE_ASPEED_RTC
);
159 snprintf(typename
, sizeof(typename
), "aspeed.timer-%s", socname
);
160 object_initialize_child(obj
, "timerctrl", &s
->timerctrl
, typename
);
162 snprintf(typename
, sizeof(typename
), "aspeed.i2c-%s", socname
);
163 object_initialize_child(obj
, "i2c", &s
->i2c
, typename
);
165 snprintf(typename
, sizeof(typename
), "aspeed.fmc-%s", socname
);
166 object_initialize_child(obj
, "fmc", &s
->fmc
, typename
);
167 object_property_add_alias(obj
, "num-cs", OBJECT(&s
->fmc
), "num-cs");
169 for (i
= 0; i
< sc
->spis_num
; i
++) {
170 snprintf(typename
, sizeof(typename
), "aspeed.spi%d-%s", i
+ 1, socname
);
171 object_initialize_child(obj
, "spi[*]", &s
->spi
[i
], typename
);
174 for (i
= 0; i
< sc
->ehcis_num
; i
++) {
175 object_initialize_child(obj
, "ehci[*]", &s
->ehci
[i
],
179 snprintf(typename
, sizeof(typename
), "aspeed.sdmc-%s", socname
);
180 object_initialize_child(obj
, "sdmc", &s
->sdmc
, typename
);
181 object_property_add_alias(obj
, "ram-size", OBJECT(&s
->sdmc
),
183 object_property_add_alias(obj
, "max-ram-size", OBJECT(&s
->sdmc
),
186 for (i
= 0; i
< sc
->wdts_num
; i
++) {
187 snprintf(typename
, sizeof(typename
), "aspeed.wdt-%s", socname
);
188 object_initialize_child(obj
, "wdt[*]", &s
->wdt
[i
], typename
);
191 for (i
= 0; i
< sc
->macs_num
; i
++) {
192 object_initialize_child(obj
, "ftgmac100[*]", &s
->ftgmac100
[i
],
196 object_initialize_child(obj
, "xdma", &s
->xdma
, TYPE_ASPEED_XDMA
);
198 snprintf(typename
, sizeof(typename
), "aspeed.gpio-%s", socname
);
199 object_initialize_child(obj
, "gpio", &s
->gpio
, typename
);
201 object_initialize_child(obj
, "sdc", &s
->sdhci
, TYPE_ASPEED_SDHCI
);
203 object_property_set_int(OBJECT(&s
->sdhci
), "num-slots", 2, &error_abort
);
205 /* Init sd card slot class here so that they're under the correct parent */
206 for (i
= 0; i
< ASPEED_SDHCI_NUM_SLOTS
; ++i
) {
207 object_initialize_child(obj
, "sdhci[*]", &s
->sdhci
.slots
[i
],
211 object_initialize_child(obj
, "lpc", &s
->lpc
, TYPE_ASPEED_LPC
);
214 static void aspeed_soc_realize(DeviceState
*dev
, Error
**errp
)
217 AspeedSoCState
*s
= ASPEED_SOC(dev
);
218 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
222 create_unimplemented_device("aspeed_soc.io", sc
->memmap
[ASPEED_DEV_IOMEM
],
223 ASPEED_SOC_IOMEM_SIZE
);
225 /* Video engine stub */
226 create_unimplemented_device("aspeed.video", sc
->memmap
[ASPEED_DEV_VIDEO
],
230 for (i
= 0; i
< sc
->num_cpus
; i
++) {
231 if (!qdev_realize(DEVICE(&s
->cpu
[i
]), NULL
, errp
)) {
237 memory_region_init_ram(&s
->sram
, OBJECT(dev
), "aspeed.sram",
238 sc
->sram_size
, &err
);
240 error_propagate(errp
, err
);
243 memory_region_add_subregion(get_system_memory(),
244 sc
->memmap
[ASPEED_DEV_SRAM
], &s
->sram
);
247 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->scu
), errp
)) {
250 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->scu
), 0, sc
->memmap
[ASPEED_DEV_SCU
]);
253 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->vic
), errp
)) {
256 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->vic
), 0, sc
->memmap
[ASPEED_DEV_VIC
]);
257 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->vic
), 0,
258 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_IRQ
));
259 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->vic
), 1,
260 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_FIQ
));
263 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->rtc
), errp
)) {
266 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->rtc
), 0, sc
->memmap
[ASPEED_DEV_RTC
]);
267 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->rtc
), 0,
268 aspeed_soc_get_irq(s
, ASPEED_DEV_RTC
));
271 object_property_set_link(OBJECT(&s
->timerctrl
), "scu", OBJECT(&s
->scu
),
273 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->timerctrl
), errp
)) {
276 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->timerctrl
), 0,
277 sc
->memmap
[ASPEED_DEV_TIMER1
]);
278 for (i
= 0; i
< ASPEED_TIMER_NR_TIMERS
; i
++) {
279 qemu_irq irq
= aspeed_soc_get_irq(s
, ASPEED_DEV_TIMER1
+ i
);
280 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timerctrl
), i
, irq
);
283 /* UART - attach an 8250 to the IO space as our UART5 */
284 serial_mm_init(get_system_memory(), sc
->memmap
[ASPEED_DEV_UART5
], 2,
285 aspeed_soc_get_irq(s
, ASPEED_DEV_UART5
), 38400,
286 serial_hd(0), DEVICE_LITTLE_ENDIAN
);
289 object_property_set_link(OBJECT(&s
->i2c
), "dram", OBJECT(s
->dram_mr
),
291 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->i2c
), errp
)) {
294 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->i2c
), 0, sc
->memmap
[ASPEED_DEV_I2C
]);
295 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c
), 0,
296 aspeed_soc_get_irq(s
, ASPEED_DEV_I2C
));
298 /* FMC, The number of CS is set at the board level */
299 object_property_set_link(OBJECT(&s
->fmc
), "dram", OBJECT(s
->dram_mr
),
301 if (!object_property_set_int(OBJECT(&s
->fmc
), "sdram-base",
302 sc
->memmap
[ASPEED_DEV_SDRAM
], errp
)) {
305 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->fmc
), errp
)) {
308 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->fmc
), 0, sc
->memmap
[ASPEED_DEV_FMC
]);
309 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->fmc
), 1,
310 s
->fmc
.ctrl
->flash_window_base
);
311 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->fmc
), 0,
312 aspeed_soc_get_irq(s
, ASPEED_DEV_FMC
));
315 for (i
= 0; i
< sc
->spis_num
; i
++) {
316 object_property_set_int(OBJECT(&s
->spi
[i
]), "num-cs", 1, &error_abort
);
317 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->spi
[i
]), errp
)) {
320 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
321 sc
->memmap
[ASPEED_DEV_SPI1
+ i
]);
322 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 1,
323 s
->spi
[i
].ctrl
->flash_window_base
);
327 for (i
= 0; i
< sc
->ehcis_num
; i
++) {
328 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->ehci
[i
]), errp
)) {
331 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ehci
[i
]), 0,
332 sc
->memmap
[ASPEED_DEV_EHCI1
+ i
]);
333 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->ehci
[i
]), 0,
334 aspeed_soc_get_irq(s
, ASPEED_DEV_EHCI1
+ i
));
337 /* SDMC - SDRAM Memory Controller */
338 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->sdmc
), errp
)) {
341 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sdmc
), 0, sc
->memmap
[ASPEED_DEV_SDMC
]);
344 for (i
= 0; i
< sc
->wdts_num
; i
++) {
345 AspeedWDTClass
*awc
= ASPEED_WDT_GET_CLASS(&s
->wdt
[i
]);
347 object_property_set_link(OBJECT(&s
->wdt
[i
]), "scu", OBJECT(&s
->scu
),
349 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->wdt
[i
]), errp
)) {
352 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->wdt
[i
]), 0,
353 sc
->memmap
[ASPEED_DEV_WDT
] + i
* awc
->offset
);
357 for (i
= 0; i
< sc
->macs_num
; i
++) {
358 object_property_set_bool(OBJECT(&s
->ftgmac100
[i
]), "aspeed", true,
360 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), errp
)) {
363 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), 0,
364 sc
->memmap
[ASPEED_DEV_ETH1
+ i
]);
365 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), 0,
366 aspeed_soc_get_irq(s
, ASPEED_DEV_ETH1
+ i
));
370 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->xdma
), errp
)) {
373 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->xdma
), 0,
374 sc
->memmap
[ASPEED_DEV_XDMA
]);
375 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->xdma
), 0,
376 aspeed_soc_get_irq(s
, ASPEED_DEV_XDMA
));
379 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->gpio
), errp
)) {
382 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpio
), 0, sc
->memmap
[ASPEED_DEV_GPIO
]);
383 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio
), 0,
384 aspeed_soc_get_irq(s
, ASPEED_DEV_GPIO
));
387 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->sdhci
), errp
)) {
390 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sdhci
), 0,
391 sc
->memmap
[ASPEED_DEV_SDHCI
]);
392 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->sdhci
), 0,
393 aspeed_soc_get_irq(s
, ASPEED_DEV_SDHCI
));
396 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->lpc
), errp
)) {
399 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->lpc
), 0, sc
->memmap
[ASPEED_DEV_LPC
]);
401 /* Connect the LPC IRQ to the VIC */
402 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 0,
403 aspeed_soc_get_irq(s
, ASPEED_DEV_LPC
));
406 * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the
407 * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by
408 * contrast, on the AST2600, the subdevice IRQs are connected straight to
411 * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output
412 * to the VIC is at offset 0.
414 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 1 + aspeed_lpc_kcs_1
,
415 qdev_get_gpio_in(DEVICE(&s
->lpc
), aspeed_lpc_kcs_1
));
417 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 1 + aspeed_lpc_kcs_2
,
418 qdev_get_gpio_in(DEVICE(&s
->lpc
), aspeed_lpc_kcs_2
));
420 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 1 + aspeed_lpc_kcs_3
,
421 qdev_get_gpio_in(DEVICE(&s
->lpc
), aspeed_lpc_kcs_3
));
423 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 1 + aspeed_lpc_kcs_4
,
424 qdev_get_gpio_in(DEVICE(&s
->lpc
), aspeed_lpc_kcs_4
));
426 static Property aspeed_soc_properties
[] = {
427 DEFINE_PROP_LINK("dram", AspeedSoCState
, dram_mr
, TYPE_MEMORY_REGION
,
429 DEFINE_PROP_END_OF_LIST(),
432 static void aspeed_soc_class_init(ObjectClass
*oc
, void *data
)
434 DeviceClass
*dc
= DEVICE_CLASS(oc
);
436 dc
->realize
= aspeed_soc_realize
;
437 /* Reason: Uses serial_hds and nd_table in realize() directly */
438 dc
->user_creatable
= false;
439 device_class_set_props(dc
, aspeed_soc_properties
);
442 static const TypeInfo aspeed_soc_type_info
= {
443 .name
= TYPE_ASPEED_SOC
,
444 .parent
= TYPE_DEVICE
,
445 .instance_size
= sizeof(AspeedSoCState
),
446 .class_size
= sizeof(AspeedSoCClass
),
447 .class_init
= aspeed_soc_class_init
,
451 static void aspeed_soc_ast2400_class_init(ObjectClass
*oc
, void *data
)
453 AspeedSoCClass
*sc
= ASPEED_SOC_CLASS(oc
);
455 sc
->name
= "ast2400-a1";
456 sc
->cpu_type
= ARM_CPU_TYPE_NAME("arm926");
457 sc
->silicon_rev
= AST2400_A1_SILICON_REV
;
458 sc
->sram_size
= 0x8000;
463 sc
->irqmap
= aspeed_soc_ast2400_irqmap
;
464 sc
->memmap
= aspeed_soc_ast2400_memmap
;
468 static const TypeInfo aspeed_soc_ast2400_type_info
= {
469 .name
= "ast2400-a1",
470 .parent
= TYPE_ASPEED_SOC
,
471 .instance_init
= aspeed_soc_init
,
472 .instance_size
= sizeof(AspeedSoCState
),
473 .class_init
= aspeed_soc_ast2400_class_init
,
476 static void aspeed_soc_ast2500_class_init(ObjectClass
*oc
, void *data
)
478 AspeedSoCClass
*sc
= ASPEED_SOC_CLASS(oc
);
480 sc
->name
= "ast2500-a1";
481 sc
->cpu_type
= ARM_CPU_TYPE_NAME("arm1176");
482 sc
->silicon_rev
= AST2500_A1_SILICON_REV
;
483 sc
->sram_size
= 0x9000;
488 sc
->irqmap
= aspeed_soc_ast2500_irqmap
;
489 sc
->memmap
= aspeed_soc_ast2500_memmap
;
493 static const TypeInfo aspeed_soc_ast2500_type_info
= {
494 .name
= "ast2500-a1",
495 .parent
= TYPE_ASPEED_SOC
,
496 .instance_init
= aspeed_soc_init
,
497 .instance_size
= sizeof(AspeedSoCState
),
498 .class_init
= aspeed_soc_ast2500_class_init
,
500 static void aspeed_soc_register_types(void)
502 type_register_static(&aspeed_soc_type_info
);
503 type_register_static(&aspeed_soc_ast2400_type_info
);
504 type_register_static(&aspeed_soc_ast2500_type_info
);
507 type_init(aspeed_soc_register_types
)