include/hw/arm/fsl-imx25.h

   1 /*
   2  * Freescale i.MX25 SoC emulation
   3  *
   4  * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14  * for more details.
  15  */
  16
  17 #ifndef FSL_IMX25_H
  18 #define FSL_IMX25_H
  19
  20 #include "hw/arm/arm.h"
  21 #include "hw/intc/imx_avic.h"
  22 #include "hw/misc/imx_ccm.h"
  23 #include "hw/char/imx_serial.h"
  24 #include "hw/timer/imx_gpt.h"
  25 #include "hw/timer/imx_epit.h"
  26 #include "hw/net/imx_fec.h"
  27 #include "hw/i2c/imx_i2c.h"
  28 #include "exec/memory.h"
  29
  30 #define TYPE_FSL_IMX25 "fsl,imx25"
  31 #define FSL_IMX25(obj) OBJECT_CHECK(FslIMX25State, (obj), TYPE_FSL_IMX25)
  32
  33 #define FSL_IMX25_NUM_UARTS 5
  34 #define FSL_IMX25_NUM_GPTS 4
  35 #define FSL_IMX25_NUM_EPITS 2
  36 #define FSL_IMX25_NUM_I2CS 3
  37
  38 typedef struct FslIMX25State {
  39     /*< private >*/
  40     DeviceState parent_obj;
  41
  42     /*< public >*/
  43     ARMCPU         cpu;
  44     IMXAVICState   avic;
  45     IMXCCMState    ccm;
  46     IMXSerialState uart[FSL_IMX25_NUM_UARTS];
  47     IMXGPTState    gpt[FSL_IMX25_NUM_GPTS];
  48     IMXEPITState   epit[FSL_IMX25_NUM_EPITS];
  49     IMXFECState    fec;
  50     IMXI2CState    i2c[FSL_IMX25_NUM_I2CS];
  51     MemoryRegion   rom[2];
  52     MemoryRegion   iram;
  53     MemoryRegion   iram_alias;
  54 } FslIMX25State;
  55
  56 /**
  57  * i.MX25 memory map
  58  ****************************************************************
  59  * 0x0000_0000 0x0000_3FFF 16 Kbytes    ROM (36 Kbytes)
  60  * 0x0000_4000 0x0040_3FFF 4 Mbytes     Reserved
  61  * 0x0040_4000 0x0040_8FFF 20 Kbytes    ROM (36 Kbytes)
  62  * 0x0040_9000 0x0FFF_FFFF 252 Mbytes (minus 36 Kbytes) Reserved
  63  * 0x1000_0000 0x1FFF_FFFF 256 Mbytes   Reserved
  64  * 0x2000_0000 0x2FFF_FFFF 256 Mbytes   Reserved
  65  * 0x3000_0000 0x3FFF_FFFF 256 Mbytes   Reserved
  66  * 0x4000_0000 0x43EF_FFFF 63 Mbytes    Reserved
  67  * 0x43F0_0000 0x43F0_3FFF 16 Kbytes    AIPS A control registers
  68  * 0x43F0_4000 0x43F0_7FFF 16 Kbytes    ARM926 platform MAX
  69  * 0x43F0_8000 0x43F0_BFFF 16 Kbytes    ARM926 platform CLKCTL
  70  * 0x43F0_C000 0x43F0_FFFF 16 Kbytes    ARM926 platform ETB registers
  71  * 0x43F1_0000 0x43F1_3FFF 16 Kbytes    ARM926 platform ETB memory
  72  * 0x43F1_4000 0x43F1_7FFF 16 Kbytes    ARM926 platform AAPE registers
  73  * 0x43F1_8000 0x43F7_FFFF 416 Kbytes   Reserved
  74  * 0x43F8_0000 0x43F8_3FFF 16 Kbytes    I2C-1
  75  * 0x43F8_4000 0x43F8_7FFF 16 Kbytes    I2C-3
  76  * 0x43F8_8000 0x43F8_BFFF 16 Kbytes    CAN-1
  77  * 0x43F8_C000 0x43F8_FFFF 16 Kbytes    CAN-2
  78  * 0x43F9_0000 0x43F9_3FFF 16 Kbytes    UART-1
  79  * 0x43F9_4000 0x43F9_7FFF 16 Kbytes    UART-2
  80  * 0x43F9_8000 0x43F9_BFFF 16 Kbytes    I2C-2
  81  * 0x43F9_C000 0x43F9_FFFF 16 Kbytes    1-Wire
  82  * 0x43FA_0000 0x43FA_3FFF 16 Kbytes    ATA (CPU side)
  83  * 0x43FA_4000 0x43FA_7FFF 16 Kbytes    CSPI-1
  84  * 0x43FA_8000 0x43FA_BFFF 16 Kbytes    KPP
  85  * 0x43FA_C000 0x43FA_FFFF 16 Kbytes    IOMUXC
  86  * 0x43FB_0000 0x43FB_3FFF 16 Kbytes    AUDMUX
  87  * 0x43FB_4000 0x43FB_7FFF 16 Kbytes    Reserved
  88  * 0x43FB_8000 0x43FB_BFFF 16 Kbytes    ECT (IP BUS A)
  89  * 0x43FB_C000 0x43FB_FFFF 16 Kbytes    ECT (IP BUS B)
  90  * 0x43FC_0000 0x43FF_FFFF 256 Kbytes   Reserved AIPS A off-platform slots
  91  * 0x4400_0000 0x4FFF_FFFF 192 Mbytes   Reserved
  92  * 0x5000_0000 0x5000_3FFF 16 Kbytes    SPBA base address
  93  * 0x5000_4000 0x5000_7FFF 16 Kbytes    CSPI-3
  94  * 0x5000_8000 0x5000_BFFF 16 Kbytes    UART-4
  95  * 0x5000_C000 0x5000_FFFF 16 Kbytes    UART-3
  96  * 0x5001_0000 0x5001_3FFF 16 Kbytes    CSPI-2
  97  * 0x5001_4000 0x5001_7FFF 16 Kbytes    SSI-2
  98  * 0x5001_C000 0x5001_FFFF 16 Kbytes    Reserved
  99  * 0x5002_0000 0x5002_3FFF 16 Kbytes    ATA
 100  * 0x5002_4000 0x5002_7FFF 16 Kbytes    SIM-1
 101  * 0x5002_8000 0x5002_BFFF 16 Kbytes    SIM-2
 102  * 0x5002_C000 0x5002_FFFF 16 Kbytes    UART-5
 103  * 0x5003_0000 0x5003_3FFF 16 Kbytes    TSC
 104  * 0x5003_4000 0x5003_7FFF 16 Kbytes    SSI-1
 105  * 0x5003_8000 0x5003_BFFF 16 Kbytes    FEC
 106  * 0x5003_C000 0x5003_FFFF 16 Kbytes    SPBA registers
 107  * 0x5004_0000 0x51FF_FFFF 32 Mbytes (minus 256 Kbytes)
 108  * 0x5200_0000 0x53EF_FFFF 31 Mbytes    Reserved
 109  * 0x53F0_0000 0x53F0_3FFF 16 Kbytes    AIPS B control registers
 110  * 0x53F0_4000 0x53F7_FFFF 496 Kbytes   Reserved
 111  * 0x53F8_0000 0x53F8_3FFF 16 Kbytes    CCM
 112  * 0x53F8_4000 0x53F8_7FFF 16 Kbytes    GPT-4
 113  * 0x53F8_8000 0x53F8_BFFF 16 Kbytes    GPT-3
 114  * 0x53F8_C000 0x53F8_FFFF 16 Kbytes    GPT-2
 115  * 0x53F9_0000 0x53F9_3FFF 16 Kbytes    GPT-1
 116  * 0x53F9_4000 0x53F9_7FFF 16 Kbytes    EPIT-1
 117  * 0x53F9_8000 0x53F9_BFFF 16 Kbytes    EPIT-2
 118  * 0x53F9_C000 0x53F9_FFFF 16 Kbytes    GPIO-4
 119  * 0x53FA_0000 0x53FA_3FFF 16 Kbytes    PWM-2
 120  * 0x53FA_4000 0x53FA_7FFF 16 Kbytes    GPIO-3
 121  * 0x53FA_8000 0x53FA_BFFF 16 Kbytes    PWM-3
 122  * 0x53FA_C000 0x53FA_FFFF 16 Kbytes    SCC
 123  * 0x53FB_0000 0x53FB_3FFF 16 Kbytes    RNGB
 124  * 0x53FB_4000 0x53FB_7FFF 16 Kbytes    eSDHC-1
 125  * 0x53FB_8000 0x53FB_BFFF 16 Kbytes    eSDHC-2
 126  * 0x53FB_C000 0x53FB_FFFF 16 Kbytes    LCDC
 127  * 0x53FC_0000 0x53FC_3FFF 16 Kbytes    SLCDC
 128  * 0x53FC_4000 0x53FC_7FFF 16 Kbytes    Reserved
 129  * 0x53FC_8000 0x53FC_BFFF 16 Kbytes    PWM-4
 130  * 0x53FC_C000 0x53FC_FFFF 16 Kbytes    GPIO-1
 131  * 0x53FD_0000 0x53FD_3FFF 16 Kbytes    GPIO-2
 132  * 0x53FD_4000 0x53FD_7FFF 16 Kbytes    SDMA
 133  * 0x53FD_8000 0x53FD_BFFF 16 Kbytes    Reserved
 134  * 0x53FD_C000 0x53FD_FFFF 16 Kbytes    WDOG
 135  * 0x53FE_0000 0x53FE_3FFF 16 Kbytes    PWM-1
 136  * 0x53FE_4000 0x53FE_7FFF 16 Kbytes    Reserved
 137  * 0x53FE_8000 0x53FE_BFFF 16 Kbytes    Reserved
 138  * 0x53FE_C000 0x53FE_FFFF 16 Kbytes    RTICv3
 139  * 0x53FF_0000 0x53FF_3FFF 16 Kbytes    IIM
 140  * 0x53FF_4000 0x53FF_7FFF 16 Kbytes    USB
 141  * 0x53FF_8000 0x53FF_BFFF 16 Kbytes    CSI
 142  * 0x53FF_C000 0x53FF_FFFF 16 Kbytes    DryIce
 143  * 0x5400_0000 0x5FFF_FFFF 192 Mbytes   Reserved (aliased AIPS B slots)
 144  * 0x6000_0000 0x67FF_FFFF 128 Mbytes   ARM926 platform ROMPATCH
 145  * 0x6800_0000 0x6FFF_FFFF 128 Mbytes   ARM926 platform ASIC
 146  * 0x7000_0000 0x77FF_FFFF 128 Mbytes   Reserved
 147  * 0x7800_0000 0x7801_FFFF 128 Kbytes   RAM
 148  * 0x7802_0000 0x7FFF_FFFF 128 Mbytes (minus 128 Kbytes)
 149  * 0x8000_0000 0x8FFF_FFFF 256 Mbytes   SDRAM bank 0
 150  * 0x9000_0000 0x9FFF_FFFF 256 Mbytes   SDRAM bank 1
 151  * 0xA000_0000 0xA7FF_FFFF 128 Mbytes   WEIM CS0 (flash 128) 1
 152  * 0xA800_0000 0xAFFF_FFFF 128 Mbytes   WEIM CS1 (flash 64) 1
 153  * 0xB000_0000 0xB1FF_FFFF 32 Mbytes    WEIM CS2 (SRAM)
 154  * 0xB200_0000 0xB3FF_FFFF 32 Mbytes    WEIM CS3 (SRAM)
 155  * 0xB400_0000 0xB5FF_FFFF 32 Mbytes    WEIM CS4
 156  * 0xB600_0000 0xB7FF_FFFF 32 Mbytes    Reserved
 157  * 0xB800_0000 0xB800_0FFF 4 Kbytes     Reserved
 158  * 0xB800_1000 0xB800_1FFF 4 Kbytes     SDRAM control registers
 159  * 0xB800_2000 0xB800_2FFF 4 Kbytes     WEIM control registers
 160  * 0xB800_3000 0xB800_3FFF 4 Kbytes     M3IF control registers
 161  * 0xB800_4000 0xB800_4FFF 4 Kbytes     EMI control registers
 162  * 0xB800_5000 0xBAFF_FFFF 32 Mbytes (minus 20 Kbytes)
 163  * 0xBB00_0000 0xBB00_0FFF 4 Kbytes     NAND flash main area buffer
 164  * 0xBB00_1000 0xBB00_11FF 512 B        NAND flash spare area buffer
 165  * 0xBB00_1200 0xBB00_1DFF 3 Kbytes     Reserved
 166  * 0xBB00_1E00 0xBB00_1FFF 512 B        NAND flash control regisers
 167  * 0xBB01_2000 0xBFFF_FFFF 96 Mbytes (minus 8 Kbytes) Reserved
 168  * 0xC000_0000 0xFFFF_FFFF 1024 Mbytes  Reserved
 169  */
 170
 171 #define FSL_IMX25_ROM0_ADDR     0x00000000
 172 #define FSL_IMX25_ROM0_SIZE     0x4000
 173 #define FSL_IMX25_ROM1_ADDR     0x00404000
 174 #define FSL_IMX25_ROM1_SIZE     0x4000
 175 #define FSL_IMX25_I2C1_ADDR     0x43F80000
 176 #define FSL_IMX25_I2C1_SIZE     0x4000
 177 #define FSL_IMX25_I2C3_ADDR     0x43F84000
 178 #define FSL_IMX25_I2C3_SIZE     0x4000
 179 #define FSL_IMX25_UART1_ADDR    0x43F90000
 180 #define FSL_IMX25_UART1_SIZE    0x4000
 181 #define FSL_IMX25_UART2_ADDR    0x43F94000
 182 #define FSL_IMX25_UART2_SIZE    0x4000
 183 #define FSL_IMX25_I2C2_ADDR     0x43F98000
 184 #define FSL_IMX25_I2C2_SIZE     0x4000
 185 #define FSL_IMX25_UART4_ADDR    0x50008000
 186 #define FSL_IMX25_UART4_SIZE    0x4000
 187 #define FSL_IMX25_UART3_ADDR    0x5000C000
 188 #define FSL_IMX25_UART3_SIZE    0x4000
 189 #define FSL_IMX25_UART5_ADDR    0x5002C000
 190 #define FSL_IMX25_UART5_SIZE    0x4000
 191 #define FSL_IMX25_FEC_ADDR      0x50038000
 192 #define FSL_IMX25_FEC_SIZE      0x4000
 193 #define FSL_IMX25_CCM_ADDR      0x53F80000
 194 #define FSL_IMX25_CCM_SIZE      0x4000
 195 #define FSL_IMX25_GPT4_ADDR     0x53F84000
 196 #define FSL_IMX25_GPT4_SIZE     0x4000
 197 #define FSL_IMX25_GPT3_ADDR     0x53F88000
 198 #define FSL_IMX25_GPT3_SIZE     0x4000
 199 #define FSL_IMX25_GPT2_ADDR     0x53F8C000
 200 #define FSL_IMX25_GPT2_SIZE     0x4000
 201 #define FSL_IMX25_GPT1_ADDR     0x53F90000
 202 #define FSL_IMX25_GPT1_SIZE     0x4000
 203 #define FSL_IMX25_EPIT1_ADDR    0x53F94000
 204 #define FSL_IMX25_EPIT1_SIZE    0x4000
 205 #define FSL_IMX25_EPIT2_ADDR    0x53F98000
 206 #define FSL_IMX25_EPIT2_SIZE    0x4000
 207 #define FSL_IMX25_AVIC_ADDR     0x68000000
 208 #define FSL_IMX25_AVIC_SIZE     0x4000
 209 #define FSL_IMX25_IRAM_ADDR     0x78000000
 210 #define FSL_IMX25_IRAM_SIZE     0x20000
 211 #define FSL_IMX25_IRAM_ALIAS_ADDR     0x78020000
 212 #define FSL_IMX25_IRAM_ALIAS_SIZE     0x7FE0000
 213 #define FSL_IMX25_SDRAM0_ADDR   0x80000000
 214 #define FSL_IMX25_SDRAM0_SIZE   0x10000000
 215 #define FSL_IMX25_SDRAM1_ADDR   0x90000000
 216 #define FSL_IMX25_SDRAM1_SIZE   0x10000000
 217
 218 #define FSL_IMX25_UART1_IRQ     45
 219 #define FSL_IMX25_UART2_IRQ     32
 220 #define FSL_IMX25_UART3_IRQ     18
 221 #define FSL_IMX25_UART4_IRQ     5
 222 #define FSL_IMX25_UART5_IRQ     40
 223 #define FSL_IMX25_GPT1_IRQ      54
 224 #define FSL_IMX25_GPT2_IRQ      53
 225 #define FSL_IMX25_GPT3_IRQ      29
 226 #define FSL_IMX25_GPT4_IRQ      1
 227 #define FSL_IMX25_EPIT1_IRQ     28
 228 #define FSL_IMX25_EPIT2_IRQ     27
 229 #define FSL_IMX25_FEC_IRQ       57
 230 #define FSL_IMX25_I2C1_IRQ      3
 231 #define FSL_IMX25_I2C2_IRQ      4
 232 #define FSL_IMX25_I2C3_IRQ      10
 233
 234 #endif /* FSL_IMX25_H */