gitlab-CI: Test 32-bit builds with the fedora-i386-cross container
[qemu/ar7.git] / target / arm / helper.c
blob2d0d4cd1e102d52305c929011710a34ad618bf68
1 /*
2 * ARM generic helpers.
4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
9 #include "qemu/osdep.h"
10 #include "qemu/units.h"
11 #include "target/arm/idau.h"
12 #include "trace.h"
13 #include "cpu.h"
14 #include "internals.h"
15 #include "exec/gdbstub.h"
16 #include "exec/helper-proto.h"
17 #include "qemu/host-utils.h"
18 #include "qemu/main-loop.h"
19 #include "qemu/bitops.h"
20 #include "qemu/crc32c.h"
21 #include "qemu/qemu-print.h"
22 #include "exec/exec-all.h"
23 #include <zlib.h> /* For crc32 */
24 #include "hw/irq.h"
25 #include "hw/semihosting/semihost.h"
26 #include "sysemu/cpus.h"
27 #include "sysemu/cpu-timers.h"
28 #include "sysemu/kvm.h"
29 #include "sysemu/tcg.h"
30 #include "qemu/range.h"
31 #include "qapi/qapi-commands-machine-target.h"
32 #include "qapi/error.h"
33 #include "qemu/guest-random.h"
34 #ifdef CONFIG_TCG
35 #include "arm_ldst.h"
36 #include "exec/cpu_ldst.h"
37 #endif
39 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
41 #ifndef CONFIG_USER_ONLY
43 static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
44 MMUAccessType access_type, ARMMMUIdx mmu_idx,
45 bool s1_is_el0,
46 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
47 target_ulong *page_size_ptr,
48 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
49 __attribute__((nonnull));
50 #endif
52 static void switch_mode(CPUARMState *env, int mode);
53 static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx);
55 static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
57 ARMCPU *cpu = env_archcpu(env);
58 int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
60 /* VFP data registers are always little-endian. */
61 if (reg < nregs) {
62 return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg));
64 if (arm_feature(env, ARM_FEATURE_NEON)) {
65 /* Aliases for Q regs. */
66 nregs += 16;
67 if (reg < nregs) {
68 uint64_t *q = aa32_vfp_qreg(env, reg - 32);
69 return gdb_get_reg128(buf, q[0], q[1]);
72 switch (reg - nregs) {
73 case 0: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); break;
74 case 1: return gdb_get_reg32(buf, vfp_get_fpscr(env)); break;
75 case 2: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); break;
77 return 0;
80 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
82 ARMCPU *cpu = env_archcpu(env);
83 int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
85 if (reg < nregs) {
86 *aa32_vfp_dreg(env, reg) = ldq_le_p(buf);
87 return 8;
89 if (arm_feature(env, ARM_FEATURE_NEON)) {
90 nregs += 16;
91 if (reg < nregs) {
92 uint64_t *q = aa32_vfp_qreg(env, reg - 32);
93 q[0] = ldq_le_p(buf);
94 q[1] = ldq_le_p(buf + 8);
95 return 16;
98 switch (reg - nregs) {
99 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
100 case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
101 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
103 return 0;
106 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
108 switch (reg) {
109 case 0 ... 31:
111 /* 128 bit FP register - quads are in LE order */
112 uint64_t *q = aa64_vfp_qreg(env, reg);
113 return gdb_get_reg128(buf, q[1], q[0]);
115 case 32:
116 /* FPSR */
117 return gdb_get_reg32(buf, vfp_get_fpsr(env));
118 case 33:
119 /* FPCR */
120 return gdb_get_reg32(buf,vfp_get_fpcr(env));
121 default:
122 return 0;
126 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
128 switch (reg) {
129 case 0 ... 31:
130 /* 128 bit FP register */
132 uint64_t *q = aa64_vfp_qreg(env, reg);
133 q[0] = ldq_le_p(buf);
134 q[1] = ldq_le_p(buf + 8);
135 return 16;
137 case 32:
138 /* FPSR */
139 vfp_set_fpsr(env, ldl_p(buf));
140 return 4;
141 case 33:
142 /* FPCR */
143 vfp_set_fpcr(env, ldl_p(buf));
144 return 4;
145 default:
146 return 0;
150 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
152 assert(ri->fieldoffset);
153 if (cpreg_field_is_64bit(ri)) {
154 return CPREG_FIELD64(env, ri);
155 } else {
156 return CPREG_FIELD32(env, ri);
160 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
161 uint64_t value)
163 assert(ri->fieldoffset);
164 if (cpreg_field_is_64bit(ri)) {
165 CPREG_FIELD64(env, ri) = value;
166 } else {
167 CPREG_FIELD32(env, ri) = value;
171 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
173 return (char *)env + ri->fieldoffset;
176 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
178 /* Raw read of a coprocessor register (as needed for migration, etc). */
179 if (ri->type & ARM_CP_CONST) {
180 return ri->resetvalue;
181 } else if (ri->raw_readfn) {
182 return ri->raw_readfn(env, ri);
183 } else if (ri->readfn) {
184 return ri->readfn(env, ri);
185 } else {
186 return raw_read(env, ri);
190 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
191 uint64_t v)
193 /* Raw write of a coprocessor register (as needed for migration, etc).
194 * Note that constant registers are treated as write-ignored; the
195 * caller should check for success by whether a readback gives the
196 * value written.
198 if (ri->type & ARM_CP_CONST) {
199 return;
200 } else if (ri->raw_writefn) {
201 ri->raw_writefn(env, ri, v);
202 } else if (ri->writefn) {
203 ri->writefn(env, ri, v);
204 } else {
205 raw_write(env, ri, v);
210 * arm_get/set_gdb_*: get/set a gdb register
211 * @env: the CPU state
212 * @buf: a buffer to copy to/from
213 * @reg: register number (offset from start of group)
215 * We return the number of bytes copied
218 static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
220 ARMCPU *cpu = env_archcpu(env);
221 const ARMCPRegInfo *ri;
222 uint32_t key;
224 key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg];
225 ri = get_arm_cp_reginfo(cpu->cp_regs, key);
226 if (ri) {
227 if (cpreg_field_is_64bit(ri)) {
228 return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri));
229 } else {
230 return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri));
233 return 0;
236 static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
238 return 0;
241 #ifdef TARGET_AARCH64
242 static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
244 ARMCPU *cpu = env_archcpu(env);
246 switch (reg) {
247 /* The first 32 registers are the zregs */
248 case 0 ... 31:
250 int vq, len = 0;
251 for (vq = 0; vq < cpu->sve_max_vq; vq++) {
252 len += gdb_get_reg128(buf,
253 env->vfp.zregs[reg].d[vq * 2 + 1],
254 env->vfp.zregs[reg].d[vq * 2]);
256 return len;
258 case 32:
259 return gdb_get_reg32(buf, vfp_get_fpsr(env));
260 case 33:
261 return gdb_get_reg32(buf, vfp_get_fpcr(env));
262 /* then 16 predicates and the ffr */
263 case 34 ... 50:
265 int preg = reg - 34;
266 int vq, len = 0;
267 for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
268 len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]);
270 return len;
272 case 51:
275 * We report in Vector Granules (VG) which is 64bit in a Z reg
276 * while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
278 int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1;
279 return gdb_get_reg32(buf, vq * 2);
281 default:
282 /* gdbstub asked for something out our range */
283 qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);
284 break;
287 return 0;
290 static int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
292 ARMCPU *cpu = env_archcpu(env);
294 /* The first 32 registers are the zregs */
295 switch (reg) {
296 /* The first 32 registers are the zregs */
297 case 0 ... 31:
299 int vq, len = 0;
300 uint64_t *p = (uint64_t *) buf;
301 for (vq = 0; vq < cpu->sve_max_vq; vq++) {
302 env->vfp.zregs[reg].d[vq * 2 + 1] = *p++;
303 env->vfp.zregs[reg].d[vq * 2] = *p++;
304 len += 16;
306 return len;
308 case 32:
309 vfp_set_fpsr(env, *(uint32_t *)buf);
310 return 4;
311 case 33:
312 vfp_set_fpcr(env, *(uint32_t *)buf);
313 return 4;
314 case 34 ... 50:
316 int preg = reg - 34;
317 int vq, len = 0;
318 uint64_t *p = (uint64_t *) buf;
319 for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
320 env->vfp.pregs[preg].p[vq / 4] = *p++;
321 len += 8;
323 return len;
325 case 51:
326 /* cannot set vg via gdbstub */
327 return 0;
328 default:
329 /* gdbstub asked for something out our range */
330 break;
333 return 0;
335 #endif /* TARGET_AARCH64 */
337 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
339 /* Return true if the regdef would cause an assertion if you called
340 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
341 * program bug for it not to have the NO_RAW flag).
342 * NB that returning false here doesn't necessarily mean that calling
343 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
344 * read/write access functions which are safe for raw use" from "has
345 * read/write access functions which have side effects but has forgotten
346 * to provide raw access functions".
347 * The tests here line up with the conditions in read/write_raw_cp_reg()
348 * and assertions in raw_read()/raw_write().
350 if ((ri->type & ARM_CP_CONST) ||
351 ri->fieldoffset ||
352 ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
353 return false;
355 return true;
358 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
360 /* Write the coprocessor state from cpu->env to the (index,value) list. */
361 int i;
362 bool ok = true;
364 for (i = 0; i < cpu->cpreg_array_len; i++) {
365 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
366 const ARMCPRegInfo *ri;
367 uint64_t newval;
369 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
370 if (!ri) {
371 ok = false;
372 continue;
374 if (ri->type & ARM_CP_NO_RAW) {
375 continue;
378 newval = read_raw_cp_reg(&cpu->env, ri);
379 if (kvm_sync) {
381 * Only sync if the previous list->cpustate sync succeeded.
382 * Rather than tracking the success/failure state for every
383 * item in the list, we just recheck "does the raw write we must
384 * have made in write_list_to_cpustate() read back OK" here.
386 uint64_t oldval = cpu->cpreg_values[i];
388 if (oldval == newval) {
389 continue;
392 write_raw_cp_reg(&cpu->env, ri, oldval);
393 if (read_raw_cp_reg(&cpu->env, ri) != oldval) {
394 continue;
397 write_raw_cp_reg(&cpu->env, ri, newval);
399 cpu->cpreg_values[i] = newval;
401 return ok;
404 bool write_list_to_cpustate(ARMCPU *cpu)
406 int i;
407 bool ok = true;
409 for (i = 0; i < cpu->cpreg_array_len; i++) {
410 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
411 uint64_t v = cpu->cpreg_values[i];
412 const ARMCPRegInfo *ri;
414 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
415 if (!ri) {
416 ok = false;
417 continue;
419 if (ri->type & ARM_CP_NO_RAW) {
420 continue;
422 /* Write value and confirm it reads back as written
423 * (to catch read-only registers and partially read-only
424 * registers where the incoming migration value doesn't match)
426 write_raw_cp_reg(&cpu->env, ri, v);
427 if (read_raw_cp_reg(&cpu->env, ri) != v) {
428 ok = false;
431 return ok;
434 static void add_cpreg_to_list(gpointer key, gpointer opaque)
436 ARMCPU *cpu = opaque;
437 uint64_t regidx;
438 const ARMCPRegInfo *ri;
440 regidx = *(uint32_t *)key;
441 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
443 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
444 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
445 /* The value array need not be initialized at this point */
446 cpu->cpreg_array_len++;
450 static void count_cpreg(gpointer key, gpointer opaque)
452 ARMCPU *cpu = opaque;
453 uint64_t regidx;
454 const ARMCPRegInfo *ri;
456 regidx = *(uint32_t *)key;
457 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
459 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
460 cpu->cpreg_array_len++;
464 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
466 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
467 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
469 if (aidx > bidx) {
470 return 1;
472 if (aidx < bidx) {
473 return -1;
475 return 0;
478 void init_cpreg_list(ARMCPU *cpu)
480 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
481 * Note that we require cpreg_tuples[] to be sorted by key ID.
483 GList *keys;
484 int arraylen;
486 keys = g_hash_table_get_keys(cpu->cp_regs);
487 keys = g_list_sort(keys, cpreg_key_compare);
489 cpu->cpreg_array_len = 0;
491 g_list_foreach(keys, count_cpreg, cpu);
493 arraylen = cpu->cpreg_array_len;
494 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
495 cpu->cpreg_values = g_new(uint64_t, arraylen);
496 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
497 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
498 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
499 cpu->cpreg_array_len = 0;
501 g_list_foreach(keys, add_cpreg_to_list, cpu);
503 assert(cpu->cpreg_array_len == arraylen);
505 g_list_free(keys);
509 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
511 static CPAccessResult access_el3_aa32ns(CPUARMState *env,
512 const ARMCPRegInfo *ri,
513 bool isread)
515 if (!is_a64(env) && arm_current_el(env) == 3 &&
516 arm_is_secure_below_el3(env)) {
517 return CP_ACCESS_TRAP_UNCATEGORIZED;
519 return CP_ACCESS_OK;
522 /* Some secure-only AArch32 registers trap to EL3 if used from
523 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
524 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
525 * We assume that the .access field is set to PL1_RW.
527 static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
528 const ARMCPRegInfo *ri,
529 bool isread)
531 if (arm_current_el(env) == 3) {
532 return CP_ACCESS_OK;
534 if (arm_is_secure_below_el3(env)) {
535 return CP_ACCESS_TRAP_EL3;
537 /* This will be EL1 NS and EL2 NS, which just UNDEF */
538 return CP_ACCESS_TRAP_UNCATEGORIZED;
541 /* Check for traps to "powerdown debug" registers, which are controlled
542 * by MDCR.TDOSA
544 static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri,
545 bool isread)
547 int el = arm_current_el(env);
548 bool mdcr_el2_tdosa = (env->cp15.mdcr_el2 & MDCR_TDOSA) ||
549 (env->cp15.mdcr_el2 & MDCR_TDE) ||
550 (arm_hcr_el2_eff(env) & HCR_TGE);
552 if (el < 2 && mdcr_el2_tdosa && !arm_is_secure_below_el3(env)) {
553 return CP_ACCESS_TRAP_EL2;
555 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) {
556 return CP_ACCESS_TRAP_EL3;
558 return CP_ACCESS_OK;
561 /* Check for traps to "debug ROM" registers, which are controlled
562 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
564 static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri,
565 bool isread)
567 int el = arm_current_el(env);
568 bool mdcr_el2_tdra = (env->cp15.mdcr_el2 & MDCR_TDRA) ||
569 (env->cp15.mdcr_el2 & MDCR_TDE) ||
570 (arm_hcr_el2_eff(env) & HCR_TGE);
572 if (el < 2 && mdcr_el2_tdra && !arm_is_secure_below_el3(env)) {
573 return CP_ACCESS_TRAP_EL2;
575 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
576 return CP_ACCESS_TRAP_EL3;
578 return CP_ACCESS_OK;
581 /* Check for traps to general debug registers, which are controlled
582 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
584 static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
585 bool isread)
587 int el = arm_current_el(env);
588 bool mdcr_el2_tda = (env->cp15.mdcr_el2 & MDCR_TDA) ||
589 (env->cp15.mdcr_el2 & MDCR_TDE) ||
590 (arm_hcr_el2_eff(env) & HCR_TGE);
592 if (el < 2 && mdcr_el2_tda && !arm_is_secure_below_el3(env)) {
593 return CP_ACCESS_TRAP_EL2;
595 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
596 return CP_ACCESS_TRAP_EL3;
598 return CP_ACCESS_OK;
601 /* Check for traps to performance monitor registers, which are controlled
602 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
604 static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
605 bool isread)
607 int el = arm_current_el(env);
609 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
610 && !arm_is_secure_below_el3(env)) {
611 return CP_ACCESS_TRAP_EL2;
613 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
614 return CP_ACCESS_TRAP_EL3;
616 return CP_ACCESS_OK;
619 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
620 static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
621 bool isread)
623 if (arm_current_el(env) == 1) {
624 uint64_t trap = isread ? HCR_TRVM : HCR_TVM;
625 if (arm_hcr_el2_eff(env) & trap) {
626 return CP_ACCESS_TRAP_EL2;
629 return CP_ACCESS_OK;
632 /* Check for traps from EL1 due to HCR_EL2.TSW. */
633 static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri,
634 bool isread)
636 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TSW)) {
637 return CP_ACCESS_TRAP_EL2;
639 return CP_ACCESS_OK;
642 /* Check for traps from EL1 due to HCR_EL2.TACR. */
643 static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri,
644 bool isread)
646 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TACR)) {
647 return CP_ACCESS_TRAP_EL2;
649 return CP_ACCESS_OK;
652 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
653 static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri,
654 bool isread)
656 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TTLB)) {
657 return CP_ACCESS_TRAP_EL2;
659 return CP_ACCESS_OK;
662 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
664 ARMCPU *cpu = env_archcpu(env);
666 raw_write(env, ri, value);
667 tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */
670 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
672 ARMCPU *cpu = env_archcpu(env);
674 if (raw_read(env, ri) != value) {
675 /* Unlike real hardware the qemu TLB uses virtual addresses,
676 * not modified virtual addresses, so this causes a TLB flush.
678 tlb_flush(CPU(cpu));
679 raw_write(env, ri, value);
683 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
684 uint64_t value)
686 ARMCPU *cpu = env_archcpu(env);
688 if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA)
689 && !extended_addresses_enabled(env)) {
690 /* For VMSA (when not using the LPAE long descriptor page table
691 * format) this register includes the ASID, so do a TLB flush.
692 * For PMSA it is purely a process ID and no action is needed.
694 tlb_flush(CPU(cpu));
696 raw_write(env, ri, value);
699 /* IS variants of TLB operations must affect all cores */
700 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
701 uint64_t value)
703 CPUState *cs = env_cpu(env);
705 tlb_flush_all_cpus_synced(cs);
708 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
709 uint64_t value)
711 CPUState *cs = env_cpu(env);
713 tlb_flush_all_cpus_synced(cs);
716 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
717 uint64_t value)
719 CPUState *cs = env_cpu(env);
721 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
724 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
725 uint64_t value)
727 CPUState *cs = env_cpu(env);
729 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
733 * Non-IS variants of TLB operations are upgraded to
734 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
735 * force broadcast of these operations.
737 static bool tlb_force_broadcast(CPUARMState *env)
739 return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB);
742 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
743 uint64_t value)
745 /* Invalidate all (TLBIALL) */
746 CPUState *cs = env_cpu(env);
748 if (tlb_force_broadcast(env)) {
749 tlb_flush_all_cpus_synced(cs);
750 } else {
751 tlb_flush(cs);
755 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
756 uint64_t value)
758 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
759 CPUState *cs = env_cpu(env);
761 value &= TARGET_PAGE_MASK;
762 if (tlb_force_broadcast(env)) {
763 tlb_flush_page_all_cpus_synced(cs, value);
764 } else {
765 tlb_flush_page(cs, value);
769 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
770 uint64_t value)
772 /* Invalidate by ASID (TLBIASID) */
773 CPUState *cs = env_cpu(env);
775 if (tlb_force_broadcast(env)) {
776 tlb_flush_all_cpus_synced(cs);
777 } else {
778 tlb_flush(cs);
782 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
783 uint64_t value)
785 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
786 CPUState *cs = env_cpu(env);
788 value &= TARGET_PAGE_MASK;
789 if (tlb_force_broadcast(env)) {
790 tlb_flush_page_all_cpus_synced(cs, value);
791 } else {
792 tlb_flush_page(cs, value);
796 static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
797 uint64_t value)
799 CPUState *cs = env_cpu(env);
801 tlb_flush_by_mmuidx(cs,
802 ARMMMUIdxBit_E10_1 |
803 ARMMMUIdxBit_E10_1_PAN |
804 ARMMMUIdxBit_E10_0);
807 static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
808 uint64_t value)
810 CPUState *cs = env_cpu(env);
812 tlb_flush_by_mmuidx_all_cpus_synced(cs,
813 ARMMMUIdxBit_E10_1 |
814 ARMMMUIdxBit_E10_1_PAN |
815 ARMMMUIdxBit_E10_0);
819 static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
820 uint64_t value)
822 CPUState *cs = env_cpu(env);
824 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2);
827 static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
828 uint64_t value)
830 CPUState *cs = env_cpu(env);
832 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
835 static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
836 uint64_t value)
838 CPUState *cs = env_cpu(env);
839 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
841 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);
844 static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
845 uint64_t value)
847 CPUState *cs = env_cpu(env);
848 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
850 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
851 ARMMMUIdxBit_E2);
854 static const ARMCPRegInfo cp_reginfo[] = {
855 /* Define the secure and non-secure FCSE identifier CP registers
856 * separately because there is no secure bank in V8 (no _EL3). This allows
857 * the secure register to be properly reset and migrated. There is also no
858 * v8 EL1 version of the register so the non-secure instance stands alone.
860 { .name = "FCSEIDR",
861 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
862 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
863 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
864 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
865 { .name = "FCSEIDR_S",
866 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
867 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
868 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
869 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
870 /* Define the secure and non-secure context identifier CP registers
871 * separately because there is no secure bank in V8 (no _EL3). This allows
872 * the secure register to be properly reset and migrated. In the
873 * non-secure case, the 32-bit register will have reset and migration
874 * disabled during registration as it is handled by the 64-bit instance.
876 { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
877 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
878 .access = PL1_RW, .accessfn = access_tvm_trvm,
879 .secure = ARM_CP_SECSTATE_NS,
880 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
881 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
882 { .name = "CONTEXTIDR_S", .state = ARM_CP_STATE_AA32,
883 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
884 .access = PL1_RW, .accessfn = access_tvm_trvm,
885 .secure = ARM_CP_SECSTATE_S,
886 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
887 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
888 REGINFO_SENTINEL
891 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
892 /* NB: Some of these registers exist in v8 but with more precise
893 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
895 /* MMU Domain access control / MPU write buffer control */
896 { .name = "DACR",
897 .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
898 .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,
899 .writefn = dacr_write, .raw_writefn = raw_write,
900 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
901 offsetoflow32(CPUARMState, cp15.dacr_ns) } },
902 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
903 * For v6 and v5, these mappings are overly broad.
905 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
906 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
907 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
908 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
909 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
910 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
911 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
912 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
913 /* Cache maintenance ops; some of this space may be overridden later. */
914 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
915 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
916 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
917 REGINFO_SENTINEL
920 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
921 /* Not all pre-v6 cores implemented this WFI, so this is slightly
922 * over-broad.
924 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
925 .access = PL1_W, .type = ARM_CP_WFI },
926 REGINFO_SENTINEL
929 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
930 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
931 * is UNPREDICTABLE; we choose to NOP as most implementations do).
933 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
934 .access = PL1_W, .type = ARM_CP_WFI },
935 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
936 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
937 * OMAPCP will override this space.
939 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
940 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
941 .resetvalue = 0 },
942 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
943 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
944 .resetvalue = 0 },
945 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
946 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
947 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
948 .resetvalue = 0 },
949 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
950 * implementing it as RAZ means the "debug architecture version" bits
951 * will read as a reserved value, which should cause Linux to not try
952 * to use the debug hardware.
954 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
955 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
956 /* MMU TLB control. Note that the wildcarding means we cover not just
957 * the unified TLB ops but also the dside/iside/inner-shareable variants.
959 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
960 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
961 .type = ARM_CP_NO_RAW },
962 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
963 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
964 .type = ARM_CP_NO_RAW },
965 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
966 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
967 .type = ARM_CP_NO_RAW },
968 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
969 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
970 .type = ARM_CP_NO_RAW },
971 { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2,
972 .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
973 { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
974 .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
975 REGINFO_SENTINEL
978 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
979 uint64_t value)
981 uint32_t mask = 0;
983 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
984 if (!arm_feature(env, ARM_FEATURE_V8)) {
985 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
986 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
987 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
989 if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
990 /* VFP coprocessor: cp10 & cp11 [23:20] */
991 mask |= (1 << 31) | (1 << 30) | (0xf << 20);
993 if (!arm_feature(env, ARM_FEATURE_NEON)) {
994 /* ASEDIS [31] bit is RAO/WI */
995 value |= (1 << 31);
998 /* VFPv3 and upwards with NEON implement 32 double precision
999 * registers (D0-D31).
1001 if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) {
1002 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
1003 value |= (1 << 30);
1006 value &= mask;
1010 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
1011 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
1013 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
1014 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
1015 value &= ~(0xf << 20);
1016 value |= env->cp15.cpacr_el1 & (0xf << 20);
1019 env->cp15.cpacr_el1 = value;
1022 static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1025 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
1026 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
1028 uint64_t value = env->cp15.cpacr_el1;
1030 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
1031 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
1032 value &= ~(0xf << 20);
1034 return value;
1038 static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1040 /* Call cpacr_write() so that we reset with the correct RAO bits set
1041 * for our CPU features.
1043 cpacr_write(env, ri, 0);
1046 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
1047 bool isread)
1049 if (arm_feature(env, ARM_FEATURE_V8)) {
1050 /* Check if CPACR accesses are to be trapped to EL2 */
1051 if (arm_current_el(env) == 1 &&
1052 (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
1053 return CP_ACCESS_TRAP_EL2;
1054 /* Check if CPACR accesses are to be trapped to EL3 */
1055 } else if (arm_current_el(env) < 3 &&
1056 (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
1057 return CP_ACCESS_TRAP_EL3;
1061 return CP_ACCESS_OK;
1064 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri,
1065 bool isread)
1067 /* Check if CPTR accesses are set to trap to EL3 */
1068 if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
1069 return CP_ACCESS_TRAP_EL3;
1072 return CP_ACCESS_OK;
1075 static const ARMCPRegInfo v6_cp_reginfo[] = {
1076 /* prefetch by MVA in v6, NOP in v7 */
1077 { .name = "MVA_prefetch",
1078 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
1079 .access = PL1_W, .type = ARM_CP_NOP },
1080 /* We need to break the TB after ISB to execute self-modifying code
1081 * correctly and also to take any pending interrupts immediately.
1082 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
1084 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
1085 .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
1086 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
1087 .access = PL0_W, .type = ARM_CP_NOP },
1088 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
1089 .access = PL0_W, .type = ARM_CP_NOP },
1090 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
1091 .access = PL1_RW, .accessfn = access_tvm_trvm,
1092 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
1093 offsetof(CPUARMState, cp15.ifar_ns) },
1094 .resetvalue = 0, },
1095 /* Watchpoint Fault Address Register : should actually only be present
1096 * for 1136, 1176, 11MPCore.
1098 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
1099 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
1100 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
1101 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
1102 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
1103 .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read },
1104 REGINFO_SENTINEL
1107 /* Definitions for the PMU registers */
1108 #define PMCRN_MASK 0xf800
1109 #define PMCRN_SHIFT 11
1110 #define PMCRLC 0x40
1111 #define PMCRDP 0x20
1112 #define PMCRX 0x10
1113 #define PMCRD 0x8
1114 #define PMCRC 0x4
1115 #define PMCRP 0x2
1116 #define PMCRE 0x1
1118 * Mask of PMCR bits writeable by guest (not including WO bits like C, P,
1119 * which can be written as 1 to trigger behaviour but which stay RAZ).
1121 #define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
1123 #define PMXEVTYPER_P 0x80000000
1124 #define PMXEVTYPER_U 0x40000000
1125 #define PMXEVTYPER_NSK 0x20000000
1126 #define PMXEVTYPER_NSU 0x10000000
1127 #define PMXEVTYPER_NSH 0x08000000
1128 #define PMXEVTYPER_M 0x04000000
1129 #define PMXEVTYPER_MT 0x02000000
1130 #define PMXEVTYPER_EVTCOUNT 0x0000ffff
1131 #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
1132 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
1133 PMXEVTYPER_M | PMXEVTYPER_MT | \
1134 PMXEVTYPER_EVTCOUNT)
1136 #define PMCCFILTR 0xf8000000
1137 #define PMCCFILTR_M PMXEVTYPER_M
1138 #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
1140 static inline uint32_t pmu_num_counters(CPUARMState *env)
1142 return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
1145 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
1146 static inline uint64_t pmu_counter_mask(CPUARMState *env)
1148 return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
1151 typedef struct pm_event {
1152 uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */
1153 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
1154 bool (*supported)(CPUARMState *);
1156 * Retrieve the current count of the underlying event. The programmed
1157 * counters hold a difference from the return value from this function
1159 uint64_t (*get_count)(CPUARMState *);
1161 * Return how many nanoseconds it will take (at a minimum) for count events
1162 * to occur. A negative value indicates the counter will never overflow, or
1163 * that the counter has otherwise arranged for the overflow bit to be set
1164 * and the PMU interrupt to be raised on overflow.
1166 int64_t (*ns_per_count)(uint64_t);
1167 } pm_event;
1169 static bool event_always_supported(CPUARMState *env)
1171 return true;
1174 static uint64_t swinc_get_count(CPUARMState *env)
1177 * SW_INCR events are written directly to the pmevcntr's by writes to
1178 * PMSWINC, so there is no underlying count maintained by the PMU itself
1180 return 0;
1183 static int64_t swinc_ns_per(uint64_t ignored)
1185 return -1;
1189 * Return the underlying cycle count for the PMU cycle counters. If we're in
1190 * usermode, simply return 0.
1192 static uint64_t cycles_get_count(CPUARMState *env)
1194 #ifndef CONFIG_USER_ONLY
1195 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
1196 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
1197 #else
1198 return cpu_get_host_ticks();
1199 #endif
1202 #ifndef CONFIG_USER_ONLY
1203 static int64_t cycles_ns_per(uint64_t cycles)
1205 return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles;
1208 static bool instructions_supported(CPUARMState *env)
1210 return icount_enabled() == 1; /* Precise instruction counting */
1213 static uint64_t instructions_get_count(CPUARMState *env)
1215 return (uint64_t)icount_get_raw();
1218 static int64_t instructions_ns_per(uint64_t icount)
1220 return icount_to_ns((int64_t)icount);
1222 #endif
1224 static bool pmu_8_1_events_supported(CPUARMState *env)
1226 /* For events which are supported in any v8.1 PMU */
1227 return cpu_isar_feature(any_pmu_8_1, env_archcpu(env));
1230 static bool pmu_8_4_events_supported(CPUARMState *env)
1232 /* For events which are supported in any v8.1 PMU */
1233 return cpu_isar_feature(any_pmu_8_4, env_archcpu(env));
1236 static uint64_t zero_event_get_count(CPUARMState *env)
1238 /* For events which on QEMU never fire, so their count is always zero */
1239 return 0;
1242 static int64_t zero_event_ns_per(uint64_t cycles)
1244 /* An event which never fires can never overflow */
1245 return -1;
1248 static const pm_event pm_events[] = {
1249 { .number = 0x000, /* SW_INCR */
1250 .supported = event_always_supported,
1251 .get_count = swinc_get_count,
1252 .ns_per_count = swinc_ns_per,
1254 #ifndef CONFIG_USER_ONLY
1255 { .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */
1256 .supported = instructions_supported,
1257 .get_count = instructions_get_count,
1258 .ns_per_count = instructions_ns_per,
1260 { .number = 0x011, /* CPU_CYCLES, Cycle */
1261 .supported = event_always_supported,
1262 .get_count = cycles_get_count,
1263 .ns_per_count = cycles_ns_per,
1265 #endif
1266 { .number = 0x023, /* STALL_FRONTEND */
1267 .supported = pmu_8_1_events_supported,
1268 .get_count = zero_event_get_count,
1269 .ns_per_count = zero_event_ns_per,
1271 { .number = 0x024, /* STALL_BACKEND */
1272 .supported = pmu_8_1_events_supported,
1273 .get_count = zero_event_get_count,
1274 .ns_per_count = zero_event_ns_per,
1276 { .number = 0x03c, /* STALL */
1277 .supported = pmu_8_4_events_supported,
1278 .get_count = zero_event_get_count,
1279 .ns_per_count = zero_event_ns_per,
1284 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1285 * events (i.e. the statistical profiling extension), this implementation
1286 * should first be updated to something sparse instead of the current
1287 * supported_event_map[] array.
1289 #define MAX_EVENT_ID 0x3c
1290 #define UNSUPPORTED_EVENT UINT16_MAX
1291 static uint16_t supported_event_map[MAX_EVENT_ID + 1];
1294 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1295 * of ARM event numbers to indices in our pm_events array.
1297 * Note: Events in the 0x40XX range are not currently supported.
1299 void pmu_init(ARMCPU *cpu)
1301 unsigned int i;
1304 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1305 * events to them
1307 for (i = 0; i < ARRAY_SIZE(supported_event_map); i++) {
1308 supported_event_map[i] = UNSUPPORTED_EVENT;
1310 cpu->pmceid0 = 0;
1311 cpu->pmceid1 = 0;
1313 for (i = 0; i < ARRAY_SIZE(pm_events); i++) {
1314 const pm_event *cnt = &pm_events[i];
1315 assert(cnt->number <= MAX_EVENT_ID);
1316 /* We do not currently support events in the 0x40xx range */
1317 assert(cnt->number <= 0x3f);
1319 if (cnt->supported(&cpu->env)) {
1320 supported_event_map[cnt->number] = i;
1321 uint64_t event_mask = 1ULL << (cnt->number & 0x1f);
1322 if (cnt->number & 0x20) {
1323 cpu->pmceid1 |= event_mask;
1324 } else {
1325 cpu->pmceid0 |= event_mask;
1332 * Check at runtime whether a PMU event is supported for the current machine
1334 static bool event_supported(uint16_t number)
1336 if (number > MAX_EVENT_ID) {
1337 return false;
1339 return supported_event_map[number] != UNSUPPORTED_EVENT;
1342 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
1343 bool isread)
1345 /* Performance monitor registers user accessibility is controlled
1346 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1347 * trapping to EL2 or EL3 for other accesses.
1349 int el = arm_current_el(env);
1351 if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) {
1352 return CP_ACCESS_TRAP;
1354 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
1355 && !arm_is_secure_below_el3(env)) {
1356 return CP_ACCESS_TRAP_EL2;
1358 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
1359 return CP_ACCESS_TRAP_EL3;
1362 return CP_ACCESS_OK;
1365 static CPAccessResult pmreg_access_xevcntr(CPUARMState *env,
1366 const ARMCPRegInfo *ri,
1367 bool isread)
1369 /* ER: event counter read trap control */
1370 if (arm_feature(env, ARM_FEATURE_V8)
1371 && arm_current_el(env) == 0
1372 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0
1373 && isread) {
1374 return CP_ACCESS_OK;
1377 return pmreg_access(env, ri, isread);
1380 static CPAccessResult pmreg_access_swinc(CPUARMState *env,
1381 const ARMCPRegInfo *ri,
1382 bool isread)
1384 /* SW: software increment write trap control */
1385 if (arm_feature(env, ARM_FEATURE_V8)
1386 && arm_current_el(env) == 0
1387 && (env->cp15.c9_pmuserenr & (1 << 1)) != 0
1388 && !isread) {
1389 return CP_ACCESS_OK;
1392 return pmreg_access(env, ri, isread);
1395 static CPAccessResult pmreg_access_selr(CPUARMState *env,
1396 const ARMCPRegInfo *ri,
1397 bool isread)
1399 /* ER: event counter read trap control */
1400 if (arm_feature(env, ARM_FEATURE_V8)
1401 && arm_current_el(env) == 0
1402 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) {
1403 return CP_ACCESS_OK;
1406 return pmreg_access(env, ri, isread);
1409 static CPAccessResult pmreg_access_ccntr(CPUARMState *env,
1410 const ARMCPRegInfo *ri,
1411 bool isread)
1413 /* CR: cycle counter read trap control */
1414 if (arm_feature(env, ARM_FEATURE_V8)
1415 && arm_current_el(env) == 0
1416 && (env->cp15.c9_pmuserenr & (1 << 2)) != 0
1417 && isread) {
1418 return CP_ACCESS_OK;
1421 return pmreg_access(env, ri, isread);
1424 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using
1425 * the current EL, security state, and register configuration.
1427 static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
1429 uint64_t filter;
1430 bool e, p, u, nsk, nsu, nsh, m;
1431 bool enabled, prohibited, filtered;
1432 bool secure = arm_is_secure(env);
1433 int el = arm_current_el(env);
1434 uint8_t hpmn = env->cp15.mdcr_el2 & MDCR_HPMN;
1436 if (!arm_feature(env, ARM_FEATURE_PMU)) {
1437 return false;
1440 if (!arm_feature(env, ARM_FEATURE_EL2) ||
1441 (counter < hpmn || counter == 31)) {
1442 e = env->cp15.c9_pmcr & PMCRE;
1443 } else {
1444 e = env->cp15.mdcr_el2 & MDCR_HPME;
1446 enabled = e && (env->cp15.c9_pmcnten & (1 << counter));
1448 if (!secure) {
1449 if (el == 2 && (counter < hpmn || counter == 31)) {
1450 prohibited = env->cp15.mdcr_el2 & MDCR_HPMD;
1451 } else {
1452 prohibited = false;
1454 } else {
1455 prohibited = arm_feature(env, ARM_FEATURE_EL3) &&
1456 !(env->cp15.mdcr_el3 & MDCR_SPME);
1459 if (prohibited && counter == 31) {
1460 prohibited = env->cp15.c9_pmcr & PMCRDP;
1463 if (counter == 31) {
1464 filter = env->cp15.pmccfiltr_el0;
1465 } else {
1466 filter = env->cp15.c14_pmevtyper[counter];
1469 p = filter & PMXEVTYPER_P;
1470 u = filter & PMXEVTYPER_U;
1471 nsk = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK);
1472 nsu = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU);
1473 nsh = arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH);
1474 m = arm_el_is_aa64(env, 1) &&
1475 arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M);
1477 if (el == 0) {
1478 filtered = secure ? u : u != nsu;
1479 } else if (el == 1) {
1480 filtered = secure ? p : p != nsk;
1481 } else if (el == 2) {
1482 filtered = !nsh;
1483 } else { /* EL3 */
1484 filtered = m != p;
1487 if (counter != 31) {
1489 * If not checking PMCCNTR, ensure the counter is setup to an event we
1490 * support
1492 uint16_t event = filter & PMXEVTYPER_EVTCOUNT;
1493 if (!event_supported(event)) {
1494 return false;
1498 return enabled && !prohibited && !filtered;
1501 static void pmu_update_irq(CPUARMState *env)
1503 ARMCPU *cpu = env_archcpu(env);
1504 qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) &&
1505 (env->cp15.c9_pminten & env->cp15.c9_pmovsr));
1509 * Ensure c15_ccnt is the guest-visible count so that operations such as
1510 * enabling/disabling the counter or filtering, modifying the count itself,
1511 * etc. can be done logically. This is essentially a no-op if the counter is
1512 * not enabled at the time of the call.
1514 static void pmccntr_op_start(CPUARMState *env)
1516 uint64_t cycles = cycles_get_count(env);
1518 if (pmu_counter_enabled(env, 31)) {
1519 uint64_t eff_cycles = cycles;
1520 if (env->cp15.c9_pmcr & PMCRD) {
1521 /* Increment once every 64 processor clock cycles */
1522 eff_cycles /= 64;
1525 uint64_t new_pmccntr = eff_cycles - env->cp15.c15_ccnt_delta;
1527 uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \
1528 1ull << 63 : 1ull << 31;
1529 if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) {
1530 env->cp15.c9_pmovsr |= (1 << 31);
1531 pmu_update_irq(env);
1534 env->cp15.c15_ccnt = new_pmccntr;
1536 env->cp15.c15_ccnt_delta = cycles;
1540 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1541 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1542 * pmccntr_op_start.
1544 static void pmccntr_op_finish(CPUARMState *env)
1546 if (pmu_counter_enabled(env, 31)) {
1547 #ifndef CONFIG_USER_ONLY
1548 /* Calculate when the counter will next overflow */
1549 uint64_t remaining_cycles = -env->cp15.c15_ccnt;
1550 if (!(env->cp15.c9_pmcr & PMCRLC)) {
1551 remaining_cycles = (uint32_t)remaining_cycles;
1553 int64_t overflow_in = cycles_ns_per(remaining_cycles);
1555 if (overflow_in > 0) {
1556 int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1557 overflow_in;
1558 ARMCPU *cpu = env_archcpu(env);
1559 timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at);
1561 #endif
1563 uint64_t prev_cycles = env->cp15.c15_ccnt_delta;
1564 if (env->cp15.c9_pmcr & PMCRD) {
1565 /* Increment once every 64 processor clock cycles */
1566 prev_cycles /= 64;
1568 env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt;
1572 static void pmevcntr_op_start(CPUARMState *env, uint8_t counter)
1575 uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT;
1576 uint64_t count = 0;
1577 if (event_supported(event)) {
1578 uint16_t event_idx = supported_event_map[event];
1579 count = pm_events[event_idx].get_count(env);
1582 if (pmu_counter_enabled(env, counter)) {
1583 uint32_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter];
1585 if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & INT32_MIN) {
1586 env->cp15.c9_pmovsr |= (1 << counter);
1587 pmu_update_irq(env);
1589 env->cp15.c14_pmevcntr[counter] = new_pmevcntr;
1591 env->cp15.c14_pmevcntr_delta[counter] = count;
1594 static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter)
1596 if (pmu_counter_enabled(env, counter)) {
1597 #ifndef CONFIG_USER_ONLY
1598 uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT;
1599 uint16_t event_idx = supported_event_map[event];
1600 uint64_t delta = UINT32_MAX -
1601 (uint32_t)env->cp15.c14_pmevcntr[counter] + 1;
1602 int64_t overflow_in = pm_events[event_idx].ns_per_count(delta);
1604 if (overflow_in > 0) {
1605 int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1606 overflow_in;
1607 ARMCPU *cpu = env_archcpu(env);
1608 timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at);
1610 #endif
1612 env->cp15.c14_pmevcntr_delta[counter] -=
1613 env->cp15.c14_pmevcntr[counter];
1617 void pmu_op_start(CPUARMState *env)
1619 unsigned int i;
1620 pmccntr_op_start(env);
1621 for (i = 0; i < pmu_num_counters(env); i++) {
1622 pmevcntr_op_start(env, i);
1626 void pmu_op_finish(CPUARMState *env)
1628 unsigned int i;
1629 pmccntr_op_finish(env);
1630 for (i = 0; i < pmu_num_counters(env); i++) {
1631 pmevcntr_op_finish(env, i);
1635 void pmu_pre_el_change(ARMCPU *cpu, void *ignored)
1637 pmu_op_start(&cpu->env);
1640 void pmu_post_el_change(ARMCPU *cpu, void *ignored)
1642 pmu_op_finish(&cpu->env);
1645 void arm_pmu_timer_cb(void *opaque)
1647 ARMCPU *cpu = opaque;
1650 * Update all the counter values based on the current underlying counts,
1651 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1652 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1653 * counter may expire.
1655 pmu_op_start(&cpu->env);
1656 pmu_op_finish(&cpu->env);
1659 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1660 uint64_t value)
1662 pmu_op_start(env);
1664 if (value & PMCRC) {
1665 /* The counter has been reset */
1666 env->cp15.c15_ccnt = 0;
1669 if (value & PMCRP) {
1670 unsigned int i;
1671 for (i = 0; i < pmu_num_counters(env); i++) {
1672 env->cp15.c14_pmevcntr[i] = 0;
1676 env->cp15.c9_pmcr &= ~PMCR_WRITEABLE_MASK;
1677 env->cp15.c9_pmcr |= (value & PMCR_WRITEABLE_MASK);
1679 pmu_op_finish(env);
1682 static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri,
1683 uint64_t value)
1685 unsigned int i;
1686 for (i = 0; i < pmu_num_counters(env); i++) {
1687 /* Increment a counter's count iff: */
1688 if ((value & (1 << i)) && /* counter's bit is set */
1689 /* counter is enabled and not filtered */
1690 pmu_counter_enabled(env, i) &&
1691 /* counter is SW_INCR */
1692 (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) {
1693 pmevcntr_op_start(env, i);
1696 * Detect if this write causes an overflow since we can't predict
1697 * PMSWINC overflows like we can for other events
1699 uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1;
1701 if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) {
1702 env->cp15.c9_pmovsr |= (1 << i);
1703 pmu_update_irq(env);
1706 env->cp15.c14_pmevcntr[i] = new_pmswinc;
1708 pmevcntr_op_finish(env, i);
1713 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1715 uint64_t ret;
1716 pmccntr_op_start(env);
1717 ret = env->cp15.c15_ccnt;
1718 pmccntr_op_finish(env);
1719 return ret;
1722 static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1723 uint64_t value)
1725 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1726 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1727 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1728 * accessed.
1730 env->cp15.c9_pmselr = value & 0x1f;
1733 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1734 uint64_t value)
1736 pmccntr_op_start(env);
1737 env->cp15.c15_ccnt = value;
1738 pmccntr_op_finish(env);
1741 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
1742 uint64_t value)
1744 uint64_t cur_val = pmccntr_read(env, NULL);
1746 pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
1749 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1750 uint64_t value)
1752 pmccntr_op_start(env);
1753 env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0;
1754 pmccntr_op_finish(env);
1757 static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri,
1758 uint64_t value)
1760 pmccntr_op_start(env);
1761 /* M is not accessible from AArch32 */
1762 env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) |
1763 (value & PMCCFILTR);
1764 pmccntr_op_finish(env);
1767 static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri)
1769 /* M is not visible in AArch32 */
1770 return env->cp15.pmccfiltr_el0 & PMCCFILTR;
1773 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
1774 uint64_t value)
1776 value &= pmu_counter_mask(env);
1777 env->cp15.c9_pmcnten |= value;
1780 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1781 uint64_t value)
1783 value &= pmu_counter_mask(env);
1784 env->cp15.c9_pmcnten &= ~value;
1787 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1788 uint64_t value)
1790 value &= pmu_counter_mask(env);
1791 env->cp15.c9_pmovsr &= ~value;
1792 pmu_update_irq(env);
1795 static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri,
1796 uint64_t value)
1798 value &= pmu_counter_mask(env);
1799 env->cp15.c9_pmovsr |= value;
1800 pmu_update_irq(env);
1803 static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
1804 uint64_t value, const uint8_t counter)
1806 if (counter == 31) {
1807 pmccfiltr_write(env, ri, value);
1808 } else if (counter < pmu_num_counters(env)) {
1809 pmevcntr_op_start(env, counter);
1812 * If this counter's event type is changing, store the current
1813 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1814 * pmevcntr_op_finish has the correct baseline when it converts back to
1815 * a delta.
1817 uint16_t old_event = env->cp15.c14_pmevtyper[counter] &
1818 PMXEVTYPER_EVTCOUNT;
1819 uint16_t new_event = value & PMXEVTYPER_EVTCOUNT;
1820 if (old_event != new_event) {
1821 uint64_t count = 0;
1822 if (event_supported(new_event)) {
1823 uint16_t event_idx = supported_event_map[new_event];
1824 count = pm_events[event_idx].get_count(env);
1826 env->cp15.c14_pmevcntr_delta[counter] = count;
1829 env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK;
1830 pmevcntr_op_finish(env, counter);
1832 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1833 * PMSELR value is equal to or greater than the number of implemented
1834 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1838 static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri,
1839 const uint8_t counter)
1841 if (counter == 31) {
1842 return env->cp15.pmccfiltr_el0;
1843 } else if (counter < pmu_num_counters(env)) {
1844 return env->cp15.c14_pmevtyper[counter];
1845 } else {
1847 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1848 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1850 return 0;
1854 static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri,
1855 uint64_t value)
1857 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1858 pmevtyper_write(env, ri, value, counter);
1861 static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri,
1862 uint64_t value)
1864 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1865 env->cp15.c14_pmevtyper[counter] = value;
1868 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1869 * pmu_op_finish calls when loading saved state for a migration. Because
1870 * we're potentially updating the type of event here, the value written to
1871 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1872 * different counter type. Therefore, we need to set this value to the
1873 * current count for the counter type we're writing so that pmu_op_finish
1874 * has the correct count for its calculation.
1876 uint16_t event = value & PMXEVTYPER_EVTCOUNT;
1877 if (event_supported(event)) {
1878 uint16_t event_idx = supported_event_map[event];
1879 env->cp15.c14_pmevcntr_delta[counter] =
1880 pm_events[event_idx].get_count(env);
1884 static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
1886 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1887 return pmevtyper_read(env, ri, counter);
1890 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
1891 uint64_t value)
1893 pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31);
1896 static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri)
1898 return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31);
1901 static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1902 uint64_t value, uint8_t counter)
1904 if (counter < pmu_num_counters(env)) {
1905 pmevcntr_op_start(env, counter);
1906 env->cp15.c14_pmevcntr[counter] = value;
1907 pmevcntr_op_finish(env, counter);
1910 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1911 * are CONSTRAINED UNPREDICTABLE.
1915 static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1916 uint8_t counter)
1918 if (counter < pmu_num_counters(env)) {
1919 uint64_t ret;
1920 pmevcntr_op_start(env, counter);
1921 ret = env->cp15.c14_pmevcntr[counter];
1922 pmevcntr_op_finish(env, counter);
1923 return ret;
1924 } else {
1925 /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1926 * are CONSTRAINED UNPREDICTABLE. */
1927 return 0;
1931 static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri,
1932 uint64_t value)
1934 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1935 pmevcntr_write(env, ri, value, counter);
1938 static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
1940 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1941 return pmevcntr_read(env, ri, counter);
1944 static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri,
1945 uint64_t value)
1947 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1948 assert(counter < pmu_num_counters(env));
1949 env->cp15.c14_pmevcntr[counter] = value;
1950 pmevcntr_write(env, ri, value, counter);
1953 static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri)
1955 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1956 assert(counter < pmu_num_counters(env));
1957 return env->cp15.c14_pmevcntr[counter];
1960 static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1961 uint64_t value)
1963 pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31);
1966 static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1968 return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31);
1971 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1972 uint64_t value)
1974 if (arm_feature(env, ARM_FEATURE_V8)) {
1975 env->cp15.c9_pmuserenr = value & 0xf;
1976 } else {
1977 env->cp15.c9_pmuserenr = value & 1;
1981 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
1982 uint64_t value)
1984 /* We have no event counters so only the C bit can be changed */
1985 value &= pmu_counter_mask(env);
1986 env->cp15.c9_pminten |= value;
1987 pmu_update_irq(env);
1990 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1991 uint64_t value)
1993 value &= pmu_counter_mask(env);
1994 env->cp15.c9_pminten &= ~value;
1995 pmu_update_irq(env);
1998 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1999 uint64_t value)
2001 /* Note that even though the AArch64 view of this register has bits
2002 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
2003 * architectural requirements for bits which are RES0 only in some
2004 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
2005 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
2007 raw_write(env, ri, value & ~0x1FULL);
2010 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
2012 /* Begin with base v8.0 state. */
2013 uint32_t valid_mask = 0x3fff;
2014 ARMCPU *cpu = env_archcpu(env);
2016 if (ri->state == ARM_CP_STATE_AA64) {
2017 value |= SCR_FW | SCR_AW; /* these two bits are RES1. */
2018 valid_mask &= ~SCR_NET;
2020 if (cpu_isar_feature(aa64_lor, cpu)) {
2021 valid_mask |= SCR_TLOR;
2023 if (cpu_isar_feature(aa64_pauth, cpu)) {
2024 valid_mask |= SCR_API | SCR_APK;
2026 if (cpu_isar_feature(aa64_mte, cpu)) {
2027 valid_mask |= SCR_ATA;
2029 } else {
2030 valid_mask &= ~(SCR_RW | SCR_ST);
2033 if (!arm_feature(env, ARM_FEATURE_EL2)) {
2034 valid_mask &= ~SCR_HCE;
2036 /* On ARMv7, SMD (or SCD as it is called in v7) is only
2037 * supported if EL2 exists. The bit is UNK/SBZP when
2038 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
2039 * when EL2 is unavailable.
2040 * On ARMv8, this bit is always available.
2042 if (arm_feature(env, ARM_FEATURE_V7) &&
2043 !arm_feature(env, ARM_FEATURE_V8)) {
2044 valid_mask &= ~SCR_SMD;
2048 /* Clear all-context RES0 bits. */
2049 value &= valid_mask;
2050 raw_write(env, ri, value);
2053 static CPAccessResult access_aa64_tid2(CPUARMState *env,
2054 const ARMCPRegInfo *ri,
2055 bool isread)
2057 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID2)) {
2058 return CP_ACCESS_TRAP_EL2;
2061 return CP_ACCESS_OK;
2064 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2066 ARMCPU *cpu = env_archcpu(env);
2068 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
2069 * bank
2071 uint32_t index = A32_BANKED_REG_GET(env, csselr,
2072 ri->secure & ARM_CP_SECSTATE_S);
2074 return cpu->ccsidr[index];
2077 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2078 uint64_t value)
2080 raw_write(env, ri, value & 0xf);
2083 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2085 CPUState *cs = env_cpu(env);
2086 uint64_t hcr_el2 = arm_hcr_el2_eff(env);
2087 uint64_t ret = 0;
2088 bool allow_virt = (arm_current_el(env) == 1 &&
2089 (!arm_is_secure_below_el3(env) ||
2090 (env->cp15.scr_el3 & SCR_EEL2)));
2092 if (allow_virt && (hcr_el2 & HCR_IMO)) {
2093 if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
2094 ret |= CPSR_I;
2096 } else {
2097 if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
2098 ret |= CPSR_I;
2102 if (allow_virt && (hcr_el2 & HCR_FMO)) {
2103 if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
2104 ret |= CPSR_F;
2106 } else {
2107 if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
2108 ret |= CPSR_F;
2112 /* External aborts are not possible in QEMU so A bit is always clear */
2113 return ret;
2116 static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInfo *ri,
2117 bool isread)
2119 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID1)) {
2120 return CP_ACCESS_TRAP_EL2;
2123 return CP_ACCESS_OK;
2126 static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInfo *ri,
2127 bool isread)
2129 if (arm_feature(env, ARM_FEATURE_V8)) {
2130 return access_aa64_tid1(env, ri, isread);
2133 return CP_ACCESS_OK;
2136 static const ARMCPRegInfo v7_cp_reginfo[] = {
2137 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
2138 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
2139 .access = PL1_W, .type = ARM_CP_NOP },
2140 /* Performance monitors are implementation defined in v7,
2141 * but with an ARM recommended set of registers, which we
2142 * follow.
2144 * Performance registers fall into three categories:
2145 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2146 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2147 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2148 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2149 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2151 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
2152 .access = PL0_RW, .type = ARM_CP_ALIAS,
2153 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
2154 .writefn = pmcntenset_write,
2155 .accessfn = pmreg_access,
2156 .raw_writefn = raw_write },
2157 { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
2158 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
2159 .access = PL0_RW, .accessfn = pmreg_access,
2160 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
2161 .writefn = pmcntenset_write, .raw_writefn = raw_write },
2162 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
2163 .access = PL0_RW,
2164 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
2165 .accessfn = pmreg_access,
2166 .writefn = pmcntenclr_write,
2167 .type = ARM_CP_ALIAS },
2168 { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
2169 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
2170 .access = PL0_RW, .accessfn = pmreg_access,
2171 .type = ARM_CP_ALIAS,
2172 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
2173 .writefn = pmcntenclr_write },
2174 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
2175 .access = PL0_RW, .type = ARM_CP_IO,
2176 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
2177 .accessfn = pmreg_access,
2178 .writefn = pmovsr_write,
2179 .raw_writefn = raw_write },
2180 { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
2181 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
2182 .access = PL0_RW, .accessfn = pmreg_access,
2183 .type = ARM_CP_ALIAS | ARM_CP_IO,
2184 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
2185 .writefn = pmovsr_write,
2186 .raw_writefn = raw_write },
2187 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
2188 .access = PL0_W, .accessfn = pmreg_access_swinc,
2189 .type = ARM_CP_NO_RAW | ARM_CP_IO,
2190 .writefn = pmswinc_write },
2191 { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64,
2192 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4,
2193 .access = PL0_W, .accessfn = pmreg_access_swinc,
2194 .type = ARM_CP_NO_RAW | ARM_CP_IO,
2195 .writefn = pmswinc_write },
2196 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
2197 .access = PL0_RW, .type = ARM_CP_ALIAS,
2198 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
2199 .accessfn = pmreg_access_selr, .writefn = pmselr_write,
2200 .raw_writefn = raw_write},
2201 { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
2202 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
2203 .access = PL0_RW, .accessfn = pmreg_access_selr,
2204 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
2205 .writefn = pmselr_write, .raw_writefn = raw_write, },
2206 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
2207 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO,
2208 .readfn = pmccntr_read, .writefn = pmccntr_write32,
2209 .accessfn = pmreg_access_ccntr },
2210 { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
2211 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
2212 .access = PL0_RW, .accessfn = pmreg_access_ccntr,
2213 .type = ARM_CP_IO,
2214 .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt),
2215 .readfn = pmccntr_read, .writefn = pmccntr_write,
2216 .raw_readfn = raw_read, .raw_writefn = raw_write, },
2217 { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7,
2218 .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32,
2219 .access = PL0_RW, .accessfn = pmreg_access,
2220 .type = ARM_CP_ALIAS | ARM_CP_IO,
2221 .resetvalue = 0, },
2222 { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
2223 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
2224 .writefn = pmccfiltr_write, .raw_writefn = raw_write,
2225 .access = PL0_RW, .accessfn = pmreg_access,
2226 .type = ARM_CP_IO,
2227 .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
2228 .resetvalue = 0, },
2229 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
2230 .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2231 .accessfn = pmreg_access,
2232 .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
2233 { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64,
2234 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1,
2235 .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2236 .accessfn = pmreg_access,
2237 .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
2238 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
2239 .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2240 .accessfn = pmreg_access_xevcntr,
2241 .writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
2242 { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64,
2243 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2,
2244 .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2245 .accessfn = pmreg_access_xevcntr,
2246 .writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
2247 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
2248 .access = PL0_R | PL1_RW, .accessfn = access_tpm,
2249 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr),
2250 .resetvalue = 0,
2251 .writefn = pmuserenr_write, .raw_writefn = raw_write },
2252 { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
2253 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0,
2254 .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
2255 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
2256 .resetvalue = 0,
2257 .writefn = pmuserenr_write, .raw_writefn = raw_write },
2258 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
2259 .access = PL1_RW, .accessfn = access_tpm,
2260 .type = ARM_CP_ALIAS | ARM_CP_IO,
2261 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten),
2262 .resetvalue = 0,
2263 .writefn = pmintenset_write, .raw_writefn = raw_write },
2264 { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64,
2265 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1,
2266 .access = PL1_RW, .accessfn = access_tpm,
2267 .type = ARM_CP_IO,
2268 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
2269 .writefn = pmintenset_write, .raw_writefn = raw_write,
2270 .resetvalue = 0x0 },
2271 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
2272 .access = PL1_RW, .accessfn = access_tpm,
2273 .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
2274 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
2275 .writefn = pmintenclr_write, },
2276 { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
2277 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
2278 .access = PL1_RW, .accessfn = access_tpm,
2279 .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
2280 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
2281 .writefn = pmintenclr_write },
2282 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
2283 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
2284 .access = PL1_R,
2285 .accessfn = access_aa64_tid2,
2286 .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
2287 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
2288 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
2289 .access = PL1_RW,
2290 .accessfn = access_aa64_tid2,
2291 .writefn = csselr_write, .resetvalue = 0,
2292 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
2293 offsetof(CPUARMState, cp15.csselr_ns) } },
2294 /* Auxiliary ID register: this actually has an IMPDEF value but for now
2295 * just RAZ for all cores:
2297 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
2298 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
2299 .access = PL1_R, .type = ARM_CP_CONST,
2300 .accessfn = access_aa64_tid1,
2301 .resetvalue = 0 },
2302 /* Auxiliary fault status registers: these also are IMPDEF, and we
2303 * choose to RAZ/WI for all cores.
2305 { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
2306 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
2307 .access = PL1_RW, .accessfn = access_tvm_trvm,
2308 .type = ARM_CP_CONST, .resetvalue = 0 },
2309 { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
2310 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
2311 .access = PL1_RW, .accessfn = access_tvm_trvm,
2312 .type = ARM_CP_CONST, .resetvalue = 0 },
2313 /* MAIR can just read-as-written because we don't implement caches
2314 * and so don't need to care about memory attributes.
2316 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
2317 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
2318 .access = PL1_RW, .accessfn = access_tvm_trvm,
2319 .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
2320 .resetvalue = 0 },
2321 { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
2322 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
2323 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
2324 .resetvalue = 0 },
2325 /* For non-long-descriptor page tables these are PRRR and NMRR;
2326 * regardless they still act as reads-as-written for QEMU.
2328 /* MAIR0/1 are defined separately from their 64-bit counterpart which
2329 * allows them to assign the correct fieldoffset based on the endianness
2330 * handled in the field definitions.
2332 { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
2333 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
2334 .access = PL1_RW, .accessfn = access_tvm_trvm,
2335 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
2336 offsetof(CPUARMState, cp15.mair0_ns) },
2337 .resetfn = arm_cp_reset_ignore },
2338 { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
2339 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1,
2340 .access = PL1_RW, .accessfn = access_tvm_trvm,
2341 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
2342 offsetof(CPUARMState, cp15.mair1_ns) },
2343 .resetfn = arm_cp_reset_ignore },
2344 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
2345 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
2346 .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
2347 /* 32 bit ITLB invalidates */
2348 { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
2349 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2350 .writefn = tlbiall_write },
2351 { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
2352 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2353 .writefn = tlbimva_write },
2354 { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
2355 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2356 .writefn = tlbiasid_write },
2357 /* 32 bit DTLB invalidates */
2358 { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
2359 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2360 .writefn = tlbiall_write },
2361 { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
2362 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2363 .writefn = tlbimva_write },
2364 { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
2365 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2366 .writefn = tlbiasid_write },
2367 /* 32 bit TLB invalidates */
2368 { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2369 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2370 .writefn = tlbiall_write },
2371 { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2372 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2373 .writefn = tlbimva_write },
2374 { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2375 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2376 .writefn = tlbiasid_write },
2377 { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2378 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2379 .writefn = tlbimvaa_write },
2380 REGINFO_SENTINEL
2383 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
2384 /* 32 bit TLB invalidates, Inner Shareable */
2385 { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2386 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2387 .writefn = tlbiall_is_write },
2388 { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2389 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2390 .writefn = tlbimva_is_write },
2391 { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2392 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2393 .writefn = tlbiasid_is_write },
2394 { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2395 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2396 .writefn = tlbimvaa_is_write },
2397 REGINFO_SENTINEL
2400 static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
2401 /* PMOVSSET is not implemented in v7 before v7ve */
2402 { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3,
2403 .access = PL0_RW, .accessfn = pmreg_access,
2404 .type = ARM_CP_ALIAS | ARM_CP_IO,
2405 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
2406 .writefn = pmovsset_write,
2407 .raw_writefn = raw_write },
2408 { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64,
2409 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3,
2410 .access = PL0_RW, .accessfn = pmreg_access,
2411 .type = ARM_CP_ALIAS | ARM_CP_IO,
2412 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
2413 .writefn = pmovsset_write,
2414 .raw_writefn = raw_write },
2415 REGINFO_SENTINEL
2418 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2419 uint64_t value)
2421 value &= 1;
2422 env->teecr = value;
2425 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri,
2426 bool isread)
2428 if (arm_current_el(env) == 0 && (env->teecr & 1)) {
2429 return CP_ACCESS_TRAP;
2431 return CP_ACCESS_OK;
2434 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
2435 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
2436 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
2437 .resetvalue = 0,
2438 .writefn = teecr_write },
2439 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
2440 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
2441 .accessfn = teehbr_access, .resetvalue = 0 },
2442 REGINFO_SENTINEL
2445 static const ARMCPRegInfo v6k_cp_reginfo[] = {
2446 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
2447 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
2448 .access = PL0_RW,
2449 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
2450 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
2451 .access = PL0_RW,
2452 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
2453 offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
2454 .resetfn = arm_cp_reset_ignore },
2455 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
2456 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
2457 .access = PL0_R|PL1_W,
2458 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
2459 .resetvalue = 0},
2460 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
2461 .access = PL0_R|PL1_W,
2462 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
2463 offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
2464 .resetfn = arm_cp_reset_ignore },
2465 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
2466 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
2467 .access = PL1_RW,
2468 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
2469 { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
2470 .access = PL1_RW,
2471 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
2472 offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
2473 .resetvalue = 0 },
2474 REGINFO_SENTINEL
2477 #ifndef CONFIG_USER_ONLY
2479 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
2480 bool isread)
2482 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2483 * Writable only at the highest implemented exception level.
2485 int el = arm_current_el(env);
2486 uint64_t hcr;
2487 uint32_t cntkctl;
2489 switch (el) {
2490 case 0:
2491 hcr = arm_hcr_el2_eff(env);
2492 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
2493 cntkctl = env->cp15.cnthctl_el2;
2494 } else {
2495 cntkctl = env->cp15.c14_cntkctl;
2497 if (!extract32(cntkctl, 0, 2)) {
2498 return CP_ACCESS_TRAP;
2500 break;
2501 case 1:
2502 if (!isread && ri->state == ARM_CP_STATE_AA32 &&
2503 arm_is_secure_below_el3(env)) {
2504 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2505 return CP_ACCESS_TRAP_UNCATEGORIZED;
2507 break;
2508 case 2:
2509 case 3:
2510 break;
2513 if (!isread && el < arm_highest_el(env)) {
2514 return CP_ACCESS_TRAP_UNCATEGORIZED;
2517 return CP_ACCESS_OK;
2520 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
2521 bool isread)
2523 unsigned int cur_el = arm_current_el(env);
2524 bool secure = arm_is_secure(env);
2525 uint64_t hcr = arm_hcr_el2_eff(env);
2527 switch (cur_el) {
2528 case 0:
2529 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2530 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
2531 return (extract32(env->cp15.cnthctl_el2, timeridx, 1)
2532 ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2);
2535 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2536 if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
2537 return CP_ACCESS_TRAP;
2540 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
2541 if (hcr & HCR_E2H) {
2542 if (timeridx == GTIMER_PHYS &&
2543 !extract32(env->cp15.cnthctl_el2, 10, 1)) {
2544 return CP_ACCESS_TRAP_EL2;
2546 } else {
2547 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2548 if (arm_feature(env, ARM_FEATURE_EL2) &&
2549 timeridx == GTIMER_PHYS && !secure &&
2550 !extract32(env->cp15.cnthctl_el2, 1, 1)) {
2551 return CP_ACCESS_TRAP_EL2;
2554 break;
2556 case 1:
2557 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2558 if (arm_feature(env, ARM_FEATURE_EL2) &&
2559 timeridx == GTIMER_PHYS && !secure &&
2560 (hcr & HCR_E2H
2561 ? !extract32(env->cp15.cnthctl_el2, 10, 1)
2562 : !extract32(env->cp15.cnthctl_el2, 0, 1))) {
2563 return CP_ACCESS_TRAP_EL2;
2565 break;
2567 return CP_ACCESS_OK;
2570 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
2571 bool isread)
2573 unsigned int cur_el = arm_current_el(env);
2574 bool secure = arm_is_secure(env);
2575 uint64_t hcr = arm_hcr_el2_eff(env);
2577 switch (cur_el) {
2578 case 0:
2579 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
2580 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2581 return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1)
2582 ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2);
2586 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2587 * EL0 if EL0[PV]TEN is zero.
2589 if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
2590 return CP_ACCESS_TRAP;
2592 /* fall through */
2594 case 1:
2595 if (arm_feature(env, ARM_FEATURE_EL2) &&
2596 timeridx == GTIMER_PHYS && !secure) {
2597 if (hcr & HCR_E2H) {
2598 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2599 if (!extract32(env->cp15.cnthctl_el2, 11, 1)) {
2600 return CP_ACCESS_TRAP_EL2;
2602 } else {
2603 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2604 if (!extract32(env->cp15.cnthctl_el2, 1, 1)) {
2605 return CP_ACCESS_TRAP_EL2;
2609 break;
2611 return CP_ACCESS_OK;
2614 static CPAccessResult gt_pct_access(CPUARMState *env,
2615 const ARMCPRegInfo *ri,
2616 bool isread)
2618 return gt_counter_access(env, GTIMER_PHYS, isread);
2621 static CPAccessResult gt_vct_access(CPUARMState *env,
2622 const ARMCPRegInfo *ri,
2623 bool isread)
2625 return gt_counter_access(env, GTIMER_VIRT, isread);
2628 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
2629 bool isread)
2631 return gt_timer_access(env, GTIMER_PHYS, isread);
2634 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
2635 bool isread)
2637 return gt_timer_access(env, GTIMER_VIRT, isread);
2640 static CPAccessResult gt_stimer_access(CPUARMState *env,
2641 const ARMCPRegInfo *ri,
2642 bool isread)
2644 /* The AArch64 register view of the secure physical timer is
2645 * always accessible from EL3, and configurably accessible from
2646 * Secure EL1.
2648 switch (arm_current_el(env)) {
2649 case 1:
2650 if (!arm_is_secure(env)) {
2651 return CP_ACCESS_TRAP;
2653 if (!(env->cp15.scr_el3 & SCR_ST)) {
2654 return CP_ACCESS_TRAP_EL3;
2656 return CP_ACCESS_OK;
2657 case 0:
2658 case 2:
2659 return CP_ACCESS_TRAP;
2660 case 3:
2661 return CP_ACCESS_OK;
2662 default:
2663 g_assert_not_reached();
2667 static uint64_t gt_get_countervalue(CPUARMState *env)
2669 ARMCPU *cpu = env_archcpu(env);
2671 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu);
2674 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
2676 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
2678 if (gt->ctl & 1) {
2679 /* Timer enabled: calculate and set current ISTATUS, irq, and
2680 * reset timer to when ISTATUS next has to change
2682 uint64_t offset = timeridx == GTIMER_VIRT ?
2683 cpu->env.cp15.cntvoff_el2 : 0;
2684 uint64_t count = gt_get_countervalue(&cpu->env);
2685 /* Note that this must be unsigned 64 bit arithmetic: */
2686 int istatus = count - offset >= gt->cval;
2687 uint64_t nexttick;
2688 int irqstate;
2690 gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
2692 irqstate = (istatus && !(gt->ctl & 2));
2693 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);
2695 if (istatus) {
2696 /* Next transition is when count rolls back over to zero */
2697 nexttick = UINT64_MAX;
2698 } else {
2699 /* Next transition is when we hit cval */
2700 nexttick = gt->cval + offset;
2702 /* Note that the desired next expiry time might be beyond the
2703 * signed-64-bit range of a QEMUTimer -- in this case we just
2704 * set the timer for as far in the future as possible. When the
2705 * timer expires we will reset the timer for any remaining period.
2707 if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) {
2708 timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX);
2709 } else {
2710 timer_mod(cpu->gt_timer[timeridx], nexttick);
2712 trace_arm_gt_recalc(timeridx, irqstate, nexttick);
2713 } else {
2714 /* Timer disabled: ISTATUS and timer output always clear */
2715 gt->ctl &= ~4;
2716 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
2717 timer_del(cpu->gt_timer[timeridx]);
2718 trace_arm_gt_recalc_disabled(timeridx);
2722 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
2723 int timeridx)
2725 ARMCPU *cpu = env_archcpu(env);
2727 timer_del(cpu->gt_timer[timeridx]);
2730 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
2732 return gt_get_countervalue(env);
2735 static uint64_t gt_virt_cnt_offset(CPUARMState *env)
2737 uint64_t hcr;
2739 switch (arm_current_el(env)) {
2740 case 2:
2741 hcr = arm_hcr_el2_eff(env);
2742 if (hcr & HCR_E2H) {
2743 return 0;
2745 break;
2746 case 0:
2747 hcr = arm_hcr_el2_eff(env);
2748 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
2749 return 0;
2751 break;
2754 return env->cp15.cntvoff_el2;
2757 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
2759 return gt_get_countervalue(env) - gt_virt_cnt_offset(env);
2762 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2763 int timeridx,
2764 uint64_t value)
2766 trace_arm_gt_cval_write(timeridx, value);
2767 env->cp15.c14_timer[timeridx].cval = value;
2768 gt_recalc_timer(env_archcpu(env), timeridx);
2771 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
2772 int timeridx)
2774 uint64_t offset = 0;
2776 switch (timeridx) {
2777 case GTIMER_VIRT:
2778 case GTIMER_HYPVIRT:
2779 offset = gt_virt_cnt_offset(env);
2780 break;
2783 return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
2784 (gt_get_countervalue(env) - offset));
2787 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2788 int timeridx,
2789 uint64_t value)
2791 uint64_t offset = 0;
2793 switch (timeridx) {
2794 case GTIMER_VIRT:
2795 case GTIMER_HYPVIRT:
2796 offset = gt_virt_cnt_offset(env);
2797 break;
2800 trace_arm_gt_tval_write(timeridx, value);
2801 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
2802 sextract64(value, 0, 32);
2803 gt_recalc_timer(env_archcpu(env), timeridx);
2806 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2807 int timeridx,
2808 uint64_t value)
2810 ARMCPU *cpu = env_archcpu(env);
2811 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
2813 trace_arm_gt_ctl_write(timeridx, value);
2814 env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
2815 if ((oldval ^ value) & 1) {
2816 /* Enable toggled */
2817 gt_recalc_timer(cpu, timeridx);
2818 } else if ((oldval ^ value) & 2) {
2819 /* IMASK toggled: don't need to recalculate,
2820 * just set the interrupt line based on ISTATUS
2822 int irqstate = (oldval & 4) && !(value & 2);
2824 trace_arm_gt_imask_toggle(timeridx, irqstate);
2825 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);
2829 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2831 gt_timer_reset(env, ri, GTIMER_PHYS);
2834 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2835 uint64_t value)
2837 gt_cval_write(env, ri, GTIMER_PHYS, value);
2840 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
2842 return gt_tval_read(env, ri, GTIMER_PHYS);
2845 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2846 uint64_t value)
2848 gt_tval_write(env, ri, GTIMER_PHYS, value);
2851 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2852 uint64_t value)
2854 gt_ctl_write(env, ri, GTIMER_PHYS, value);
2857 static int gt_phys_redir_timeridx(CPUARMState *env)
2859 switch (arm_mmu_idx(env)) {
2860 case ARMMMUIdx_E20_0:
2861 case ARMMMUIdx_E20_2:
2862 case ARMMMUIdx_E20_2_PAN:
2863 return GTIMER_HYP;
2864 default:
2865 return GTIMER_PHYS;
2869 static int gt_virt_redir_timeridx(CPUARMState *env)
2871 switch (arm_mmu_idx(env)) {
2872 case ARMMMUIdx_E20_0:
2873 case ARMMMUIdx_E20_2:
2874 case ARMMMUIdx_E20_2_PAN:
2875 return GTIMER_HYPVIRT;
2876 default:
2877 return GTIMER_VIRT;
2881 static uint64_t gt_phys_redir_cval_read(CPUARMState *env,
2882 const ARMCPRegInfo *ri)
2884 int timeridx = gt_phys_redir_timeridx(env);
2885 return env->cp15.c14_timer[timeridx].cval;
2888 static void gt_phys_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2889 uint64_t value)
2891 int timeridx = gt_phys_redir_timeridx(env);
2892 gt_cval_write(env, ri, timeridx, value);
2895 static uint64_t gt_phys_redir_tval_read(CPUARMState *env,
2896 const ARMCPRegInfo *ri)
2898 int timeridx = gt_phys_redir_timeridx(env);
2899 return gt_tval_read(env, ri, timeridx);
2902 static void gt_phys_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2903 uint64_t value)
2905 int timeridx = gt_phys_redir_timeridx(env);
2906 gt_tval_write(env, ri, timeridx, value);
2909 static uint64_t gt_phys_redir_ctl_read(CPUARMState *env,
2910 const ARMCPRegInfo *ri)
2912 int timeridx = gt_phys_redir_timeridx(env);
2913 return env->cp15.c14_timer[timeridx].ctl;
2916 static void gt_phys_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2917 uint64_t value)
2919 int timeridx = gt_phys_redir_timeridx(env);
2920 gt_ctl_write(env, ri, timeridx, value);
2923 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2925 gt_timer_reset(env, ri, GTIMER_VIRT);
2928 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2929 uint64_t value)
2931 gt_cval_write(env, ri, GTIMER_VIRT, value);
2934 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
2936 return gt_tval_read(env, ri, GTIMER_VIRT);
2939 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2940 uint64_t value)
2942 gt_tval_write(env, ri, GTIMER_VIRT, value);
2945 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2946 uint64_t value)
2948 gt_ctl_write(env, ri, GTIMER_VIRT, value);
2951 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
2952 uint64_t value)
2954 ARMCPU *cpu = env_archcpu(env);
2956 trace_arm_gt_cntvoff_write(value);
2957 raw_write(env, ri, value);
2958 gt_recalc_timer(cpu, GTIMER_VIRT);
2961 static uint64_t gt_virt_redir_cval_read(CPUARMState *env,
2962 const ARMCPRegInfo *ri)
2964 int timeridx = gt_virt_redir_timeridx(env);
2965 return env->cp15.c14_timer[timeridx].cval;
2968 static void gt_virt_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2969 uint64_t value)
2971 int timeridx = gt_virt_redir_timeridx(env);
2972 gt_cval_write(env, ri, timeridx, value);
2975 static uint64_t gt_virt_redir_tval_read(CPUARMState *env,
2976 const ARMCPRegInfo *ri)
2978 int timeridx = gt_virt_redir_timeridx(env);
2979 return gt_tval_read(env, ri, timeridx);
2982 static void gt_virt_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2983 uint64_t value)
2985 int timeridx = gt_virt_redir_timeridx(env);
2986 gt_tval_write(env, ri, timeridx, value);
2989 static uint64_t gt_virt_redir_ctl_read(CPUARMState *env,
2990 const ARMCPRegInfo *ri)
2992 int timeridx = gt_virt_redir_timeridx(env);
2993 return env->cp15.c14_timer[timeridx].ctl;
2996 static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2997 uint64_t value)
2999 int timeridx = gt_virt_redir_timeridx(env);
3000 gt_ctl_write(env, ri, timeridx, value);
3003 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
3005 gt_timer_reset(env, ri, GTIMER_HYP);
3008 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
3009 uint64_t value)
3011 gt_cval_write(env, ri, GTIMER_HYP, value);
3014 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
3016 return gt_tval_read(env, ri, GTIMER_HYP);
3019 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
3020 uint64_t value)
3022 gt_tval_write(env, ri, GTIMER_HYP, value);
3025 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
3026 uint64_t value)
3028 gt_ctl_write(env, ri, GTIMER_HYP, value);
3031 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
3033 gt_timer_reset(env, ri, GTIMER_SEC);
3036 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
3037 uint64_t value)
3039 gt_cval_write(env, ri, GTIMER_SEC, value);
3042 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
3044 return gt_tval_read(env, ri, GTIMER_SEC);
3047 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
3048 uint64_t value)
3050 gt_tval_write(env, ri, GTIMER_SEC, value);
3053 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
3054 uint64_t value)
3056 gt_ctl_write(env, ri, GTIMER_SEC, value);
3059 static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
3061 gt_timer_reset(env, ri, GTIMER_HYPVIRT);
3064 static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
3065 uint64_t value)
3067 gt_cval_write(env, ri, GTIMER_HYPVIRT, value);
3070 static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
3072 return gt_tval_read(env, ri, GTIMER_HYPVIRT);
3075 static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
3076 uint64_t value)
3078 gt_tval_write(env, ri, GTIMER_HYPVIRT, value);
3081 static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
3082 uint64_t value)
3084 gt_ctl_write(env, ri, GTIMER_HYPVIRT, value);
3087 void arm_gt_ptimer_cb(void *opaque)
3089 ARMCPU *cpu = opaque;
3091 gt_recalc_timer(cpu, GTIMER_PHYS);
3094 void arm_gt_vtimer_cb(void *opaque)
3096 ARMCPU *cpu = opaque;
3098 gt_recalc_timer(cpu, GTIMER_VIRT);
3101 void arm_gt_htimer_cb(void *opaque)
3103 ARMCPU *cpu = opaque;
3105 gt_recalc_timer(cpu, GTIMER_HYP);
3108 void arm_gt_stimer_cb(void *opaque)
3110 ARMCPU *cpu = opaque;
3112 gt_recalc_timer(cpu, GTIMER_SEC);
3115 void arm_gt_hvtimer_cb(void *opaque)
3117 ARMCPU *cpu = opaque;
3119 gt_recalc_timer(cpu, GTIMER_HYPVIRT);
3122 static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
3124 ARMCPU *cpu = env_archcpu(env);
3126 cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz;
3129 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
3130 /* Note that CNTFRQ is purely reads-as-written for the benefit
3131 * of software; writing it doesn't actually change the timer frequency.
3132 * Our reset value matches the fixed frequency we implement the timer at.
3134 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
3135 .type = ARM_CP_ALIAS,
3136 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
3137 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
3139 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
3140 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
3141 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
3142 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
3143 .resetfn = arm_gt_cntfrq_reset,
3145 /* overall control: mostly access permissions */
3146 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
3147 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
3148 .access = PL1_RW,
3149 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
3150 .resetvalue = 0,
3152 /* per-timer control */
3153 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
3154 .secure = ARM_CP_SECSTATE_NS,
3155 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW,
3156 .accessfn = gt_ptimer_access,
3157 .fieldoffset = offsetoflow32(CPUARMState,
3158 cp15.c14_timer[GTIMER_PHYS].ctl),
3159 .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read,
3160 .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write,
3162 { .name = "CNTP_CTL_S",
3163 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
3164 .secure = ARM_CP_SECSTATE_S,
3165 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW,
3166 .accessfn = gt_ptimer_access,
3167 .fieldoffset = offsetoflow32(CPUARMState,
3168 cp15.c14_timer[GTIMER_SEC].ctl),
3169 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
3171 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
3172 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
3173 .type = ARM_CP_IO, .access = PL0_RW,
3174 .accessfn = gt_ptimer_access,
3175 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
3176 .resetvalue = 0,
3177 .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read,
3178 .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write,
3180 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
3181 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW,
3182 .accessfn = gt_vtimer_access,
3183 .fieldoffset = offsetoflow32(CPUARMState,
3184 cp15.c14_timer[GTIMER_VIRT].ctl),
3185 .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read,
3186 .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write,
3188 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
3189 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
3190 .type = ARM_CP_IO, .access = PL0_RW,
3191 .accessfn = gt_vtimer_access,
3192 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
3193 .resetvalue = 0,
3194 .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read,
3195 .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write,
3197 /* TimerValue views: a 32 bit downcounting view of the underlying state */
3198 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
3199 .secure = ARM_CP_SECSTATE_NS,
3200 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
3201 .accessfn = gt_ptimer_access,
3202 .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write,
3204 { .name = "CNTP_TVAL_S",
3205 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
3206 .secure = ARM_CP_SECSTATE_S,
3207 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
3208 .accessfn = gt_ptimer_access,
3209 .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
3211 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
3212 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
3213 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
3214 .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset,
3215 .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write,
3217 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
3218 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
3219 .accessfn = gt_vtimer_access,
3220 .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write,
3222 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
3223 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
3224 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
3225 .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset,
3226 .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write,
3228 /* The counter itself */
3229 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
3230 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
3231 .accessfn = gt_pct_access,
3232 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
3234 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
3235 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
3236 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
3237 .accessfn = gt_pct_access, .readfn = gt_cnt_read,
3239 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
3240 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
3241 .accessfn = gt_vct_access,
3242 .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
3244 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
3245 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
3246 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
3247 .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
3249 /* Comparison value, indicating when the timer goes off */
3250 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
3251 .secure = ARM_CP_SECSTATE_NS,
3252 .access = PL0_RW,
3253 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
3254 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
3255 .accessfn = gt_ptimer_access,
3256 .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read,
3257 .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write,
3259 { .name = "CNTP_CVAL_S", .cp = 15, .crm = 14, .opc1 = 2,
3260 .secure = ARM_CP_SECSTATE_S,
3261 .access = PL0_RW,
3262 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
3263 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
3264 .accessfn = gt_ptimer_access,
3265 .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
3267 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
3268 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
3269 .access = PL0_RW,
3270 .type = ARM_CP_IO,
3271 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
3272 .resetvalue = 0, .accessfn = gt_ptimer_access,
3273 .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read,
3274 .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write,
3276 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
3277 .access = PL0_RW,
3278 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
3279 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
3280 .accessfn = gt_vtimer_access,
3281 .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read,
3282 .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write,
3284 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
3285 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
3286 .access = PL0_RW,
3287 .type = ARM_CP_IO,
3288 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
3289 .resetvalue = 0, .accessfn = gt_vtimer_access,
3290 .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read,
3291 .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write,
3293 /* Secure timer -- this is actually restricted to only EL3
3294 * and configurably Secure-EL1 via the accessfn.
3296 { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
3297 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0,
3298 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW,
3299 .accessfn = gt_stimer_access,
3300 .readfn = gt_sec_tval_read,
3301 .writefn = gt_sec_tval_write,
3302 .resetfn = gt_sec_timer_reset,
3304 { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64,
3305 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1,
3306 .type = ARM_CP_IO, .access = PL1_RW,
3307 .accessfn = gt_stimer_access,
3308 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl),
3309 .resetvalue = 0,
3310 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
3312 { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
3313 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
3314 .type = ARM_CP_IO, .access = PL1_RW,
3315 .accessfn = gt_stimer_access,
3316 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
3317 .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
3319 REGINFO_SENTINEL
3322 static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
3323 bool isread)
3325 if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
3326 return CP_ACCESS_TRAP;
3328 return CP_ACCESS_OK;
3331 #else
3333 /* In user-mode most of the generic timer registers are inaccessible
3334 * however modern kernels (4.12+) allow access to cntvct_el0
3337 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
3339 ARMCPU *cpu = env_archcpu(env);
3341 /* Currently we have no support for QEMUTimer in linux-user so we
3342 * can't call gt_get_countervalue(env), instead we directly
3343 * call the lower level functions.
3345 return cpu_get_clock() / gt_cntfrq_period_ns(cpu);
3348 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
3349 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
3350 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
3351 .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */,
3352 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
3353 .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE,
3355 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
3356 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
3357 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
3358 .readfn = gt_virt_cnt_read,
3360 REGINFO_SENTINEL
3363 #endif
3365 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3367 if (arm_feature(env, ARM_FEATURE_LPAE)) {
3368 raw_write(env, ri, value);
3369 } else if (arm_feature(env, ARM_FEATURE_V7)) {
3370 raw_write(env, ri, value & 0xfffff6ff);
3371 } else {
3372 raw_write(env, ri, value & 0xfffff1ff);
3376 #ifndef CONFIG_USER_ONLY
3377 /* get_phys_addr() isn't present for user-mode-only targets */
3379 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
3380 bool isread)
3382 if (ri->opc2 & 4) {
3383 /* The ATS12NSO* operations must trap to EL3 if executed in
3384 * Secure EL1 (which can only happen if EL3 is AArch64).
3385 * They are simply UNDEF if executed from NS EL1.
3386 * They function normally from EL2 or EL3.
3388 if (arm_current_el(env) == 1) {
3389 if (arm_is_secure_below_el3(env)) {
3390 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
3392 return CP_ACCESS_TRAP_UNCATEGORIZED;
3395 return CP_ACCESS_OK;
3398 #ifdef CONFIG_TCG
3399 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
3400 MMUAccessType access_type, ARMMMUIdx mmu_idx)
3402 hwaddr phys_addr;
3403 target_ulong page_size;
3404 int prot;
3405 bool ret;
3406 uint64_t par64;
3407 bool format64 = false;
3408 MemTxAttrs attrs = {};
3409 ARMMMUFaultInfo fi = {};
3410 ARMCacheAttrs cacheattrs = {};
3412 ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs,
3413 &prot, &page_size, &fi, &cacheattrs);
3415 if (ret) {
3417 * Some kinds of translation fault must cause exceptions rather
3418 * than being reported in the PAR.
3420 int current_el = arm_current_el(env);
3421 int target_el;
3422 uint32_t syn, fsr, fsc;
3423 bool take_exc = false;
3425 if (fi.s1ptw && current_el == 1 && !arm_is_secure(env)
3426 && arm_mmu_idx_is_stage1_of_2(mmu_idx)) {
3428 * Synchronous stage 2 fault on an access made as part of the
3429 * translation table walk for AT S1E0* or AT S1E1* insn
3430 * executed from NS EL1. If this is a synchronous external abort
3431 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3432 * to EL3. Otherwise the fault is taken as an exception to EL2,
3433 * and HPFAR_EL2 holds the faulting IPA.
3435 if (fi.type == ARMFault_SyncExternalOnWalk &&
3436 (env->cp15.scr_el3 & SCR_EA)) {
3437 target_el = 3;
3438 } else {
3439 env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4;
3440 target_el = 2;
3442 take_exc = true;
3443 } else if (fi.type == ARMFault_SyncExternalOnWalk) {
3445 * Synchronous external aborts during a translation table walk
3446 * are taken as Data Abort exceptions.
3448 if (fi.stage2) {
3449 if (current_el == 3) {
3450 target_el = 3;
3451 } else {
3452 target_el = 2;
3454 } else {
3455 target_el = exception_target_el(env);
3457 take_exc = true;
3460 if (take_exc) {
3461 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3462 if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
3463 arm_s1_regime_using_lpae_format(env, mmu_idx)) {
3464 fsr = arm_fi_to_lfsc(&fi);
3465 fsc = extract32(fsr, 0, 6);
3466 } else {
3467 fsr = arm_fi_to_sfsc(&fi);
3468 fsc = 0x3f;
3471 * Report exception with ESR indicating a fault due to a
3472 * translation table walk for a cache maintenance instruction.
3474 syn = syn_data_abort_no_iss(current_el == target_el, 0,
3475 fi.ea, 1, fi.s1ptw, 1, fsc);
3476 env->exception.vaddress = value;
3477 env->exception.fsr = fsr;
3478 raise_exception(env, EXCP_DATA_ABORT, syn, target_el);
3482 if (is_a64(env)) {
3483 format64 = true;
3484 } else if (arm_feature(env, ARM_FEATURE_LPAE)) {
3486 * ATS1Cxx:
3487 * * TTBCR.EAE determines whether the result is returned using the
3488 * 32-bit or the 64-bit PAR format
3489 * * Instructions executed in Hyp mode always use the 64bit format
3491 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3492 * * The Non-secure TTBCR.EAE bit is set to 1
3493 * * The implementation includes EL2, and the value of HCR.VM is 1
3495 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3497 * ATS1Hx always uses the 64bit format.
3499 format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);
3501 if (arm_feature(env, ARM_FEATURE_EL2)) {
3502 if (mmu_idx == ARMMMUIdx_E10_0 ||
3503 mmu_idx == ARMMMUIdx_E10_1 ||
3504 mmu_idx == ARMMMUIdx_E10_1_PAN) {
3505 format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC);
3506 } else {
3507 format64 |= arm_current_el(env) == 2;
3512 if (format64) {
3513 /* Create a 64-bit PAR */
3514 par64 = (1 << 11); /* LPAE bit always set */
3515 if (!ret) {
3516 par64 |= phys_addr & ~0xfffULL;
3517 if (!attrs.secure) {
3518 par64 |= (1 << 9); /* NS */
3520 par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */
3521 par64 |= cacheattrs.shareability << 7; /* SH */
3522 } else {
3523 uint32_t fsr = arm_fi_to_lfsc(&fi);
3525 par64 |= 1; /* F */
3526 par64 |= (fsr & 0x3f) << 1; /* FS */
3527 if (fi.stage2) {
3528 par64 |= (1 << 9); /* S */
3530 if (fi.s1ptw) {
3531 par64 |= (1 << 8); /* PTW */
3534 } else {
3535 /* fsr is a DFSR/IFSR value for the short descriptor
3536 * translation table format (with WnR always clear).
3537 * Convert it to a 32-bit PAR.
3539 if (!ret) {
3540 /* We do not set any attribute bits in the PAR */
3541 if (page_size == (1 << 24)
3542 && arm_feature(env, ARM_FEATURE_V7)) {
3543 par64 = (phys_addr & 0xff000000) | (1 << 1);
3544 } else {
3545 par64 = phys_addr & 0xfffff000;
3547 if (!attrs.secure) {
3548 par64 |= (1 << 9); /* NS */
3550 } else {
3551 uint32_t fsr = arm_fi_to_sfsc(&fi);
3553 par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
3554 ((fsr & 0xf) << 1) | 1;
3557 return par64;
3559 #endif /* CONFIG_TCG */
3561 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3563 #ifdef CONFIG_TCG
3564 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
3565 uint64_t par64;
3566 ARMMMUIdx mmu_idx;
3567 int el = arm_current_el(env);
3568 bool secure = arm_is_secure_below_el3(env);
3570 switch (ri->opc2 & 6) {
3571 case 0:
3572 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3573 switch (el) {
3574 case 3:
3575 mmu_idx = ARMMMUIdx_SE3;
3576 break;
3577 case 2:
3578 g_assert(!secure); /* TODO: ARMv8.4-SecEL2 */
3579 /* fall through */
3580 case 1:
3581 if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) {
3582 mmu_idx = (secure ? ARMMMUIdx_SE10_1_PAN
3583 : ARMMMUIdx_Stage1_E1_PAN);
3584 } else {
3585 mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1;
3587 break;
3588 default:
3589 g_assert_not_reached();
3591 break;
3592 case 2:
3593 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3594 switch (el) {
3595 case 3:
3596 mmu_idx = ARMMMUIdx_SE10_0;
3597 break;
3598 case 2:
3599 mmu_idx = ARMMMUIdx_Stage1_E0;
3600 break;
3601 case 1:
3602 mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0;
3603 break;
3604 default:
3605 g_assert_not_reached();
3607 break;
3608 case 4:
3609 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3610 mmu_idx = ARMMMUIdx_E10_1;
3611 break;
3612 case 6:
3613 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3614 mmu_idx = ARMMMUIdx_E10_0;
3615 break;
3616 default:
3617 g_assert_not_reached();
3620 par64 = do_ats_write(env, value, access_type, mmu_idx);
3622 A32_BANKED_CURRENT_REG_SET(env, par, par64);
3623 #else
3624 /* Handled by hardware accelerator. */
3625 g_assert_not_reached();
3626 #endif /* CONFIG_TCG */
3629 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
3630 uint64_t value)
3632 #ifdef CONFIG_TCG
3633 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
3634 uint64_t par64;
3636 par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2);
3638 A32_BANKED_CURRENT_REG_SET(env, par, par64);
3639 #else
3640 /* Handled by hardware accelerator. */
3641 g_assert_not_reached();
3642 #endif /* CONFIG_TCG */
3645 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
3646 bool isread)
3648 if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
3649 return CP_ACCESS_TRAP;
3651 return CP_ACCESS_OK;
3654 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
3655 uint64_t value)
3657 #ifdef CONFIG_TCG
3658 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
3659 ARMMMUIdx mmu_idx;
3660 int secure = arm_is_secure_below_el3(env);
3662 switch (ri->opc2 & 6) {
3663 case 0:
3664 switch (ri->opc1) {
3665 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3666 if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) {
3667 mmu_idx = (secure ? ARMMMUIdx_SE10_1_PAN
3668 : ARMMMUIdx_Stage1_E1_PAN);
3669 } else {
3670 mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1;
3672 break;
3673 case 4: /* AT S1E2R, AT S1E2W */
3674 mmu_idx = ARMMMUIdx_E2;
3675 break;
3676 case 6: /* AT S1E3R, AT S1E3W */
3677 mmu_idx = ARMMMUIdx_SE3;
3678 break;
3679 default:
3680 g_assert_not_reached();
3682 break;
3683 case 2: /* AT S1E0R, AT S1E0W */
3684 mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0;
3685 break;
3686 case 4: /* AT S12E1R, AT S12E1W */
3687 mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1;
3688 break;
3689 case 6: /* AT S12E0R, AT S12E0W */
3690 mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0;
3691 break;
3692 default:
3693 g_assert_not_reached();
3696 env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
3697 #else
3698 /* Handled by hardware accelerator. */
3699 g_assert_not_reached();
3700 #endif /* CONFIG_TCG */
3702 #endif
3704 static const ARMCPRegInfo vapa_cp_reginfo[] = {
3705 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
3706 .access = PL1_RW, .resetvalue = 0,
3707 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
3708 offsetoflow32(CPUARMState, cp15.par_ns) },
3709 .writefn = par_write },
3710 #ifndef CONFIG_USER_ONLY
3711 /* This underdecoding is safe because the reginfo is NO_RAW. */
3712 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
3713 .access = PL1_W, .accessfn = ats_access,
3714 .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
3715 #endif
3716 REGINFO_SENTINEL
3719 /* Return basic MPU access permission bits. */
3720 static uint32_t simple_mpu_ap_bits(uint32_t val)
3722 uint32_t ret;
3723 uint32_t mask;
3724 int i;
3725 ret = 0;
3726 mask = 3;
3727 for (i = 0; i < 16; i += 2) {
3728 ret |= (val >> i) & mask;
3729 mask <<= 2;
3731 return ret;
3734 /* Pad basic MPU access permission bits to extended format. */
3735 static uint32_t extended_mpu_ap_bits(uint32_t val)
3737 uint32_t ret;
3738 uint32_t mask;
3739 int i;
3740 ret = 0;
3741 mask = 3;
3742 for (i = 0; i < 16; i += 2) {
3743 ret |= (val & mask) << i;
3744 mask <<= 2;
3746 return ret;
3749 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
3750 uint64_t value)
3752 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
3755 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
3757 return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
3760 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
3761 uint64_t value)
3763 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
3766 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
3768 return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
3771 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
3773 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
3775 if (!u32p) {
3776 return 0;
3779 u32p += env->pmsav7.rnr[M_REG_NS];
3780 return *u32p;
3783 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
3784 uint64_t value)
3786 ARMCPU *cpu = env_archcpu(env);
3787 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
3789 if (!u32p) {
3790 return;
3793 u32p += env->pmsav7.rnr[M_REG_NS];
3794 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
3795 *u32p = value;
3798 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3799 uint64_t value)
3801 ARMCPU *cpu = env_archcpu(env);
3802 uint32_t nrgs = cpu->pmsav7_dregion;
3804 if (value >= nrgs) {
3805 qemu_log_mask(LOG_GUEST_ERROR,
3806 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3807 " > %" PRIu32 "\n", (uint32_t)value, nrgs);
3808 return;
3811 raw_write(env, ri, value);
3814 static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
3815 /* Reset for all these registers is handled in arm_cpu_reset(),
3816 * because the PMSAv7 is also used by M-profile CPUs, which do
3817 * not register cpregs but still need the state to be reset.
3819 { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,
3820 .access = PL1_RW, .type = ARM_CP_NO_RAW,
3821 .fieldoffset = offsetof(CPUARMState, pmsav7.drbar),
3822 .readfn = pmsav7_read, .writefn = pmsav7_write,
3823 .resetfn = arm_cp_reset_ignore },
3824 { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,
3825 .access = PL1_RW, .type = ARM_CP_NO_RAW,
3826 .fieldoffset = offsetof(CPUARMState, pmsav7.drsr),
3827 .readfn = pmsav7_read, .writefn = pmsav7_write,
3828 .resetfn = arm_cp_reset_ignore },
3829 { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,
3830 .access = PL1_RW, .type = ARM_CP_NO_RAW,
3831 .fieldoffset = offsetof(CPUARMState, pmsav7.dracr),
3832 .readfn = pmsav7_read, .writefn = pmsav7_write,
3833 .resetfn = arm_cp_reset_ignore },
3834 { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
3835 .access = PL1_RW,
3836 .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]),
3837 .writefn = pmsav7_rgnr_write,
3838 .resetfn = arm_cp_reset_ignore },
3839 REGINFO_SENTINEL
3842 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
3843 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
3844 .access = PL1_RW, .type = ARM_CP_ALIAS,
3845 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
3846 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
3847 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
3848 .access = PL1_RW, .type = ARM_CP_ALIAS,
3849 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
3850 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
3851 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
3852 .access = PL1_RW,
3853 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
3854 .resetvalue = 0, },
3855 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
3856 .access = PL1_RW,
3857 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
3858 .resetvalue = 0, },
3859 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
3860 .access = PL1_RW,
3861 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
3862 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
3863 .access = PL1_RW,
3864 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
3865 /* Protection region base and size registers */
3866 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
3867 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3868 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
3869 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
3870 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3871 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
3872 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
3873 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3874 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
3875 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
3876 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3877 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
3878 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
3879 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3880 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
3881 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
3882 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3883 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
3884 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
3885 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3886 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
3887 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
3888 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3889 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
3890 REGINFO_SENTINEL
3893 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
3894 uint64_t value)
3896 TCR *tcr = raw_ptr(env, ri);
3897 int maskshift = extract32(value, 0, 3);
3899 if (!arm_feature(env, ARM_FEATURE_V8)) {
3900 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
3901 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
3902 * using Long-desciptor translation table format */
3903 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
3904 } else if (arm_feature(env, ARM_FEATURE_EL3)) {
3905 /* In an implementation that includes the Security Extensions
3906 * TTBCR has additional fields PD0 [4] and PD1 [5] for
3907 * Short-descriptor translation table format.
3909 value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
3910 } else {
3911 value &= TTBCR_N;
3915 /* Update the masks corresponding to the TCR bank being written
3916 * Note that we always calculate mask and base_mask, but
3917 * they are only used for short-descriptor tables (ie if EAE is 0);
3918 * for long-descriptor tables the TCR fields are used differently
3919 * and the mask and base_mask values are meaningless.
3921 tcr->raw_tcr = value;
3922 tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
3923 tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
3926 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3927 uint64_t value)
3929 ARMCPU *cpu = env_archcpu(env);
3930 TCR *tcr = raw_ptr(env, ri);
3932 if (arm_feature(env, ARM_FEATURE_LPAE)) {
3933 /* With LPAE the TTBCR could result in a change of ASID
3934 * via the TTBCR.A1 bit, so do a TLB flush.
3936 tlb_flush(CPU(cpu));
3938 /* Preserve the high half of TCR_EL1, set via TTBCR2. */
3939 value = deposit64(tcr->raw_tcr, 0, 32, value);
3940 vmsa_ttbcr_raw_write(env, ri, value);
3943 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
3945 TCR *tcr = raw_ptr(env, ri);
3947 /* Reset both the TCR as well as the masks corresponding to the bank of
3948 * the TCR being reset.
3950 tcr->raw_tcr = 0;
3951 tcr->mask = 0;
3952 tcr->base_mask = 0xffffc000u;
3955 static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri,
3956 uint64_t value)
3958 ARMCPU *cpu = env_archcpu(env);
3959 TCR *tcr = raw_ptr(env, ri);
3961 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
3962 tlb_flush(CPU(cpu));
3963 tcr->raw_tcr = value;
3966 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3967 uint64_t value)
3969 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
3970 if (cpreg_field_is_64bit(ri) &&
3971 extract64(raw_read(env, ri) ^ value, 48, 16) != 0) {
3972 ARMCPU *cpu = env_archcpu(env);
3973 tlb_flush(CPU(cpu));
3975 raw_write(env, ri, value);
3978 static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
3979 uint64_t value)
3982 * If we are running with E2&0 regime, then an ASID is active.
3983 * Flush if that might be changing. Note we're not checking
3984 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
3985 * holds the active ASID, only checking the field that might.
3987 if (extract64(raw_read(env, ri) ^ value, 48, 16) &&
3988 (arm_hcr_el2_eff(env) & HCR_E2H)) {
3989 tlb_flush_by_mmuidx(env_cpu(env),
3990 ARMMMUIdxBit_E20_2 |
3991 ARMMMUIdxBit_E20_2_PAN |
3992 ARMMMUIdxBit_E20_0);
3994 raw_write(env, ri, value);
3997 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3998 uint64_t value)
4000 ARMCPU *cpu = env_archcpu(env);
4001 CPUState *cs = CPU(cpu);
4004 * A change in VMID to the stage2 page table (Stage2) invalidates
4005 * the combined stage 1&2 tlbs (EL10_1 and EL10_0).
4007 if (raw_read(env, ri) != value) {
4008 tlb_flush_by_mmuidx(cs,
4009 ARMMMUIdxBit_E10_1 |
4010 ARMMMUIdxBit_E10_1_PAN |
4011 ARMMMUIdxBit_E10_0);
4012 raw_write(env, ri, value);
4016 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
4017 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
4018 .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS,
4019 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
4020 offsetoflow32(CPUARMState, cp15.dfsr_ns) }, },
4021 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
4022 .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,
4023 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
4024 offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
4025 { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
4026 .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,
4027 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
4028 offsetof(CPUARMState, cp15.dfar_ns) } },
4029 { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
4030 .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
4031 .access = PL1_RW, .accessfn = access_tvm_trvm,
4032 .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
4033 .resetvalue = 0, },
4034 REGINFO_SENTINEL
4037 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
4038 { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
4039 .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
4040 .access = PL1_RW, .accessfn = access_tvm_trvm,
4041 .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
4042 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
4043 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
4044 .access = PL1_RW, .accessfn = access_tvm_trvm,
4045 .writefn = vmsa_ttbr_write, .resetvalue = 0,
4046 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
4047 offsetof(CPUARMState, cp15.ttbr0_ns) } },
4048 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
4049 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
4050 .access = PL1_RW, .accessfn = access_tvm_trvm,
4051 .writefn = vmsa_ttbr_write, .resetvalue = 0,
4052 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
4053 offsetof(CPUARMState, cp15.ttbr1_ns) } },
4054 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
4055 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
4056 .access = PL1_RW, .accessfn = access_tvm_trvm,
4057 .writefn = vmsa_tcr_el12_write,
4058 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
4059 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
4060 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
4061 .access = PL1_RW, .accessfn = access_tvm_trvm,
4062 .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
4063 .raw_writefn = vmsa_ttbcr_raw_write,
4064 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
4065 offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
4066 REGINFO_SENTINEL
4069 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
4070 * qemu tlbs nor adjusting cached masks.
4072 static const ARMCPRegInfo ttbcr2_reginfo = {
4073 .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3,
4074 .access = PL1_RW, .accessfn = access_tvm_trvm,
4075 .type = ARM_CP_ALIAS,
4076 .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]),
4077 offsetofhigh32(CPUARMState, cp15.tcr_el[1]) },
4080 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
4081 uint64_t value)
4083 env->cp15.c15_ticonfig = value & 0xe7;
4084 /* The OS_TYPE bit in this register changes the reported CPUID! */
4085 env->cp15.c0_cpuid = (value & (1 << 5)) ?
4086 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
4089 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
4090 uint64_t value)
4092 env->cp15.c15_threadid = value & 0xffff;
4095 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
4096 uint64_t value)
4098 /* Wait-for-interrupt (deprecated) */
4099 cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT);
4102 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
4103 uint64_t value)
4105 /* On OMAP there are registers indicating the max/min index of dcache lines
4106 * containing a dirty line; cache flush operations have to reset these.
4108 env->cp15.c15_i_max = 0x000;
4109 env->cp15.c15_i_min = 0xff0;
4112 static const ARMCPRegInfo omap_cp_reginfo[] = {
4113 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
4114 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
4115 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
4116 .resetvalue = 0, },
4117 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
4118 .access = PL1_RW, .type = ARM_CP_NOP },
4119 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
4120 .access = PL1_RW,
4121 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
4122 .writefn = omap_ticonfig_write },
4123 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
4124 .access = PL1_RW,
4125 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
4126 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
4127 .access = PL1_RW, .resetvalue = 0xff0,
4128 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
4129 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
4130 .access = PL1_RW,
4131 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
4132 .writefn = omap_threadid_write },
4133 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
4134 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
4135 .type = ARM_CP_NO_RAW,
4136 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
4137 /* TODO: Peripheral port remap register:
4138 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
4139 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
4140 * when MMU is off.
4142 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
4143 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
4144 .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
4145 .writefn = omap_cachemaint_write },
4146 { .name = "C9", .cp = 15, .crn = 9,
4147 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
4148 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
4149 REGINFO_SENTINEL
4152 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
4153 uint64_t value)
4155 env->cp15.c15_cpar = value & 0x3fff;
4158 static const ARMCPRegInfo xscale_cp_reginfo[] = {
4159 { .name = "XSCALE_CPAR",
4160 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
4161 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
4162 .writefn = xscale_cpar_write, },
4163 { .name = "XSCALE_AUXCR",
4164 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
4165 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
4166 .resetvalue = 0, },
4167 /* XScale specific cache-lockdown: since we have no cache we NOP these
4168 * and hope the guest does not really rely on cache behaviour.
4170 { .name = "XSCALE_LOCK_ICACHE_LINE",
4171 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
4172 .access = PL1_W, .type = ARM_CP_NOP },
4173 { .name = "XSCALE_UNLOCK_ICACHE",
4174 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
4175 .access = PL1_W, .type = ARM_CP_NOP },
4176 { .name = "XSCALE_DCACHE_LOCK",
4177 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
4178 .access = PL1_RW, .type = ARM_CP_NOP },
4179 { .name = "XSCALE_UNLOCK_DCACHE",
4180 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
4181 .access = PL1_W, .type = ARM_CP_NOP },
4182 REGINFO_SENTINEL
4185 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
4186 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
4187 * implementation of this implementation-defined space.
4188 * Ideally this should eventually disappear in favour of actually
4189 * implementing the correct behaviour for all cores.
4191 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
4192 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
4193 .access = PL1_RW,
4194 .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
4195 .resetvalue = 0 },
4196 REGINFO_SENTINEL
4199 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
4200 /* Cache status: RAZ because we have no cache so it's always clean */
4201 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
4202 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
4203 .resetvalue = 0 },
4204 REGINFO_SENTINEL
4207 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
4208 /* We never have a a block transfer operation in progress */
4209 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
4210 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
4211 .resetvalue = 0 },
4212 /* The cache ops themselves: these all NOP for QEMU */
4213 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
4214 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4215 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
4216 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4217 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
4218 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4219 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
4220 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4221 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
4222 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4223 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
4224 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4225 REGINFO_SENTINEL
4228 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
4229 /* The cache test-and-clean instructions always return (1 << 30)
4230 * to indicate that there are no dirty cache lines.
4232 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
4233 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
4234 .resetvalue = (1 << 30) },
4235 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
4236 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
4237 .resetvalue = (1 << 30) },
4238 REGINFO_SENTINEL
4241 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
4242 /* Ignore ReadBuffer accesses */
4243 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
4244 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
4245 .access = PL1_RW, .resetvalue = 0,
4246 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
4247 REGINFO_SENTINEL
4250 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
4252 ARMCPU *cpu = env_archcpu(env);
4253 unsigned int cur_el = arm_current_el(env);
4254 bool secure = arm_is_secure(env);
4256 if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
4257 return env->cp15.vpidr_el2;
4259 return raw_read(env, ri);
4262 static uint64_t mpidr_read_val(CPUARMState *env)
4264 ARMCPU *cpu = env_archcpu(env);
4265 uint64_t mpidr = cpu->mp_affinity;
4267 if (arm_feature(env, ARM_FEATURE_V7MP)) {
4268 mpidr |= (1U << 31);
4269 /* Cores which are uniprocessor (non-coherent)
4270 * but still implement the MP extensions set
4271 * bit 30. (For instance, Cortex-R5).
4273 if (cpu->mp_is_up) {
4274 mpidr |= (1u << 30);
4277 return mpidr;
4280 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
4282 unsigned int cur_el = arm_current_el(env);
4283 bool secure = arm_is_secure(env);
4285 if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
4286 return env->cp15.vmpidr_el2;
4288 return mpidr_read_val(env);
4291 static const ARMCPRegInfo lpae_cp_reginfo[] = {
4292 /* NOP AMAIR0/1 */
4293 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
4294 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
4295 .access = PL1_RW, .accessfn = access_tvm_trvm,
4296 .type = ARM_CP_CONST, .resetvalue = 0 },
4297 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4298 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
4299 .access = PL1_RW, .accessfn = access_tvm_trvm,
4300 .type = ARM_CP_CONST, .resetvalue = 0 },
4301 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
4302 .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
4303 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
4304 offsetof(CPUARMState, cp15.par_ns)} },
4305 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
4306 .access = PL1_RW, .accessfn = access_tvm_trvm,
4307 .type = ARM_CP_64BIT | ARM_CP_ALIAS,
4308 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
4309 offsetof(CPUARMState, cp15.ttbr0_ns) },
4310 .writefn = vmsa_ttbr_write, },
4311 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
4312 .access = PL1_RW, .accessfn = access_tvm_trvm,
4313 .type = ARM_CP_64BIT | ARM_CP_ALIAS,
4314 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
4315 offsetof(CPUARMState, cp15.ttbr1_ns) },
4316 .writefn = vmsa_ttbr_write, },
4317 REGINFO_SENTINEL
4320 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
4322 return vfp_get_fpcr(env);
4325 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4326 uint64_t value)
4328 vfp_set_fpcr(env, value);
4331 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
4333 return vfp_get_fpsr(env);
4336 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4337 uint64_t value)
4339 vfp_set_fpsr(env, value);
4342 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri,
4343 bool isread)
4345 if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) {
4346 return CP_ACCESS_TRAP;
4348 return CP_ACCESS_OK;
4351 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
4352 uint64_t value)
4354 env->daif = value & PSTATE_DAIF;
4357 static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri)
4359 return env->pstate & PSTATE_PAN;
4362 static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri,
4363 uint64_t value)
4365 env->pstate = (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN);
4368 static const ARMCPRegInfo pan_reginfo = {
4369 .name = "PAN", .state = ARM_CP_STATE_AA64,
4370 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 3,
4371 .type = ARM_CP_NO_RAW, .access = PL1_RW,
4372 .readfn = aa64_pan_read, .writefn = aa64_pan_write
4375 static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri)
4377 return env->pstate & PSTATE_UAO;
4380 static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri,
4381 uint64_t value)
4383 env->pstate = (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO);
4386 static const ARMCPRegInfo uao_reginfo = {
4387 .name = "UAO", .state = ARM_CP_STATE_AA64,
4388 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4,
4389 .type = ARM_CP_NO_RAW, .access = PL1_RW,
4390 .readfn = aa64_uao_read, .writefn = aa64_uao_write
4393 static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
4394 const ARMCPRegInfo *ri,
4395 bool isread)
4397 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4398 switch (arm_current_el(env)) {
4399 case 0:
4400 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4401 if (!(arm_sctlr(env, 0) & SCTLR_UCI)) {
4402 return CP_ACCESS_TRAP;
4404 /* fall through */
4405 case 1:
4406 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4407 if (arm_hcr_el2_eff(env) & HCR_TPCP) {
4408 return CP_ACCESS_TRAP_EL2;
4410 break;
4412 return CP_ACCESS_OK;
4415 static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
4416 const ARMCPRegInfo *ri,
4417 bool isread)
4419 /* Cache invalidate/clean to Point of Unification... */
4420 switch (arm_current_el(env)) {
4421 case 0:
4422 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4423 if (!(arm_sctlr(env, 0) & SCTLR_UCI)) {
4424 return CP_ACCESS_TRAP;
4426 /* fall through */
4427 case 1:
4428 /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */
4429 if (arm_hcr_el2_eff(env) & HCR_TPU) {
4430 return CP_ACCESS_TRAP_EL2;
4432 break;
4434 return CP_ACCESS_OK;
4437 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4438 * Page D4-1736 (DDI0487A.b)
4441 static int vae1_tlbmask(CPUARMState *env)
4443 /* Since we exclude secure first, we may read HCR_EL2 directly. */
4444 if (arm_is_secure_below_el3(env)) {
4445 return ARMMMUIdxBit_SE10_1 |
4446 ARMMMUIdxBit_SE10_1_PAN |
4447 ARMMMUIdxBit_SE10_0;
4448 } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE))
4449 == (HCR_E2H | HCR_TGE)) {
4450 return ARMMMUIdxBit_E20_2 |
4451 ARMMMUIdxBit_E20_2_PAN |
4452 ARMMMUIdxBit_E20_0;
4453 } else {
4454 return ARMMMUIdxBit_E10_1 |
4455 ARMMMUIdxBit_E10_1_PAN |
4456 ARMMMUIdxBit_E10_0;
4460 /* Return 56 if TBI is enabled, 64 otherwise. */
4461 static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx,
4462 uint64_t addr)
4464 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
4465 int tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
4466 int select = extract64(addr, 55, 1);
4468 return (tbi >> select) & 1 ? 56 : 64;
4471 static int vae1_tlbbits(CPUARMState *env, uint64_t addr)
4473 ARMMMUIdx mmu_idx;
4475 /* Only the regime of the mmu_idx below is significant. */
4476 if (arm_is_secure_below_el3(env)) {
4477 mmu_idx = ARMMMUIdx_SE10_0;
4478 } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE))
4479 == (HCR_E2H | HCR_TGE)) {
4480 mmu_idx = ARMMMUIdx_E20_0;
4481 } else {
4482 mmu_idx = ARMMMUIdx_E10_0;
4484 return tlbbits_for_regime(env, mmu_idx, addr);
4487 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4488 uint64_t value)
4490 CPUState *cs = env_cpu(env);
4491 int mask = vae1_tlbmask(env);
4493 tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
4496 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
4497 uint64_t value)
4499 CPUState *cs = env_cpu(env);
4500 int mask = vae1_tlbmask(env);
4502 if (tlb_force_broadcast(env)) {
4503 tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
4504 } else {
4505 tlb_flush_by_mmuidx(cs, mask);
4509 static int alle1_tlbmask(CPUARMState *env)
4512 * Note that the 'ALL' scope must invalidate both stage 1 and
4513 * stage 2 translations, whereas most other scopes only invalidate
4514 * stage 1 translations.
4516 if (arm_is_secure_below_el3(env)) {
4517 return ARMMMUIdxBit_SE10_1 |
4518 ARMMMUIdxBit_SE10_1_PAN |
4519 ARMMMUIdxBit_SE10_0;
4520 } else {
4521 return ARMMMUIdxBit_E10_1 |
4522 ARMMMUIdxBit_E10_1_PAN |
4523 ARMMMUIdxBit_E10_0;
4527 static int e2_tlbmask(CPUARMState *env)
4529 /* TODO: ARMv8.4-SecEL2 */
4530 return ARMMMUIdxBit_E20_0 |
4531 ARMMMUIdxBit_E20_2 |
4532 ARMMMUIdxBit_E20_2_PAN |
4533 ARMMMUIdxBit_E2;
4536 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
4537 uint64_t value)
4539 CPUState *cs = env_cpu(env);
4540 int mask = alle1_tlbmask(env);
4542 tlb_flush_by_mmuidx(cs, mask);
4545 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
4546 uint64_t value)
4548 CPUState *cs = env_cpu(env);
4549 int mask = e2_tlbmask(env);
4551 tlb_flush_by_mmuidx(cs, mask);
4554 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
4555 uint64_t value)
4557 ARMCPU *cpu = env_archcpu(env);
4558 CPUState *cs = CPU(cpu);
4560 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3);
4563 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4564 uint64_t value)
4566 CPUState *cs = env_cpu(env);
4567 int mask = alle1_tlbmask(env);
4569 tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
4572 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4573 uint64_t value)
4575 CPUState *cs = env_cpu(env);
4576 int mask = e2_tlbmask(env);
4578 tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
4581 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4582 uint64_t value)
4584 CPUState *cs = env_cpu(env);
4586 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3);
4589 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
4590 uint64_t value)
4592 /* Invalidate by VA, EL2
4593 * Currently handles both VAE2 and VALE2, since we don't support
4594 * flush-last-level-only.
4596 CPUState *cs = env_cpu(env);
4597 int mask = e2_tlbmask(env);
4598 uint64_t pageaddr = sextract64(value << 12, 0, 56);
4600 tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
4603 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
4604 uint64_t value)
4606 /* Invalidate by VA, EL3
4607 * Currently handles both VAE3 and VALE3, since we don't support
4608 * flush-last-level-only.
4610 ARMCPU *cpu = env_archcpu(env);
4611 CPUState *cs = CPU(cpu);
4612 uint64_t pageaddr = sextract64(value << 12, 0, 56);
4614 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3);
4617 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4618 uint64_t value)
4620 CPUState *cs = env_cpu(env);
4621 int mask = vae1_tlbmask(env);
4622 uint64_t pageaddr = sextract64(value << 12, 0, 56);
4623 int bits = vae1_tlbbits(env, pageaddr);
4625 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);
4628 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
4629 uint64_t value)
4631 /* Invalidate by VA, EL1&0 (AArch64 version).
4632 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4633 * since we don't support flush-for-specific-ASID-only or
4634 * flush-last-level-only.
4636 CPUState *cs = env_cpu(env);
4637 int mask = vae1_tlbmask(env);
4638 uint64_t pageaddr = sextract64(value << 12, 0, 56);
4639 int bits = vae1_tlbbits(env, pageaddr);
4641 if (tlb_force_broadcast(env)) {
4642 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);
4643 } else {
4644 tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits);
4648 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4649 uint64_t value)
4651 CPUState *cs = env_cpu(env);
4652 uint64_t pageaddr = sextract64(value << 12, 0, 56);
4653 int bits = tlbbits_for_regime(env, ARMMMUIdx_E2, pageaddr);
4655 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
4656 ARMMMUIdxBit_E2, bits);
4659 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4660 uint64_t value)
4662 CPUState *cs = env_cpu(env);
4663 uint64_t pageaddr = sextract64(value << 12, 0, 56);
4664 int bits = tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr);
4666 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
4667 ARMMMUIdxBit_SE3, bits);
4670 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
4671 bool isread)
4673 int cur_el = arm_current_el(env);
4675 if (cur_el < 2) {
4676 uint64_t hcr = arm_hcr_el2_eff(env);
4678 if (cur_el == 0) {
4679 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
4680 if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) {
4681 return CP_ACCESS_TRAP_EL2;
4683 } else {
4684 if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
4685 return CP_ACCESS_TRAP;
4687 if (hcr & HCR_TDZ) {
4688 return CP_ACCESS_TRAP_EL2;
4691 } else if (hcr & HCR_TDZ) {
4692 return CP_ACCESS_TRAP_EL2;
4695 return CP_ACCESS_OK;
4698 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
4700 ARMCPU *cpu = env_archcpu(env);
4701 int dzp_bit = 1 << 4;
4703 /* DZP indicates whether DC ZVA access is allowed */
4704 if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) {
4705 dzp_bit = 0;
4707 return cpu->dcz_blocksize | dzp_bit;
4710 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
4711 bool isread)
4713 if (!(env->pstate & PSTATE_SP)) {
4714 /* Access to SP_EL0 is undefined if it's being used as
4715 * the stack pointer.
4717 return CP_ACCESS_TRAP_UNCATEGORIZED;
4719 return CP_ACCESS_OK;
4722 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
4724 return env->pstate & PSTATE_SP;
4727 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
4729 update_spsel(env, val);
4732 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4733 uint64_t value)
4735 ARMCPU *cpu = env_archcpu(env);
4737 if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) {
4738 /* M bit is RAZ/WI for PMSA with no MPU implemented */
4739 value &= ~SCTLR_M;
4742 /* ??? Lots of these bits are not implemented. */
4744 if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) {
4745 if (ri->opc1 == 6) { /* SCTLR_EL3 */
4746 value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA);
4747 } else {
4748 value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF |
4749 SCTLR_ATA0 | SCTLR_ATA);
4753 if (raw_read(env, ri) == value) {
4754 /* Skip the TLB flush if nothing actually changed; Linux likes
4755 * to do a lot of pointless SCTLR writes.
4757 return;
4760 raw_write(env, ri, value);
4762 /* This may enable/disable the MMU, so do a TLB flush. */
4763 tlb_flush(CPU(cpu));
4765 if (ri->type & ARM_CP_SUPPRESS_TB_END) {
4767 * Normally we would always end the TB on an SCTLR write; see the
4768 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
4769 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
4770 * of hflags from the translator, so do it here.
4772 arm_rebuild_hflags(env);
4776 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri,
4777 bool isread)
4779 if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) {
4780 return CP_ACCESS_TRAP_FP_EL2;
4782 if (env->cp15.cptr_el[3] & CPTR_TFP) {
4783 return CP_ACCESS_TRAP_FP_EL3;
4785 return CP_ACCESS_OK;
4788 static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4789 uint64_t value)
4791 env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
4794 static const ARMCPRegInfo v8_cp_reginfo[] = {
4795 /* Minimal set of EL0-visible registers. This will need to be expanded
4796 * significantly for system emulation of AArch64 CPUs.
4798 { .name = "NZCV", .state = ARM_CP_STATE_AA64,
4799 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
4800 .access = PL0_RW, .type = ARM_CP_NZCV },
4801 { .name = "DAIF", .state = ARM_CP_STATE_AA64,
4802 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
4803 .type = ARM_CP_NO_RAW,
4804 .access = PL0_RW, .accessfn = aa64_daif_access,
4805 .fieldoffset = offsetof(CPUARMState, daif),
4806 .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
4807 { .name = "FPCR", .state = ARM_CP_STATE_AA64,
4808 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
4809 .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END,
4810 .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
4811 { .name = "FPSR", .state = ARM_CP_STATE_AA64,
4812 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
4813 .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END,
4814 .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
4815 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
4816 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
4817 .access = PL0_R, .type = ARM_CP_NO_RAW,
4818 .readfn = aa64_dczid_read },
4819 { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
4820 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
4821 .access = PL0_W, .type = ARM_CP_DC_ZVA,
4822 #ifndef CONFIG_USER_ONLY
4823 /* Avoid overhead of an access check that always passes in user-mode */
4824 .accessfn = aa64_zva_access,
4825 #endif
4827 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
4828 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
4829 .access = PL1_R, .type = ARM_CP_CURRENTEL },
4830 /* Cache ops: all NOPs since we don't emulate caches */
4831 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
4832 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
4833 .access = PL1_W, .type = ARM_CP_NOP,
4834 .accessfn = aa64_cacheop_pou_access },
4835 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
4836 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
4837 .access = PL1_W, .type = ARM_CP_NOP,
4838 .accessfn = aa64_cacheop_pou_access },
4839 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
4840 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
4841 .access = PL0_W, .type = ARM_CP_NOP,
4842 .accessfn = aa64_cacheop_pou_access },
4843 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
4844 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
4845 .access = PL1_W, .accessfn = aa64_cacheop_poc_access,
4846 .type = ARM_CP_NOP },
4847 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
4848 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
4849 .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
4850 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
4851 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
4852 .access = PL0_W, .type = ARM_CP_NOP,
4853 .accessfn = aa64_cacheop_poc_access },
4854 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
4855 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
4856 .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
4857 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
4858 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
4859 .access = PL0_W, .type = ARM_CP_NOP,
4860 .accessfn = aa64_cacheop_pou_access },
4861 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
4862 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
4863 .access = PL0_W, .type = ARM_CP_NOP,
4864 .accessfn = aa64_cacheop_poc_access },
4865 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
4866 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
4867 .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
4868 /* TLBI operations */
4869 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
4870 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
4871 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4872 .writefn = tlbi_aa64_vmalle1is_write },
4873 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
4874 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
4875 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4876 .writefn = tlbi_aa64_vae1is_write },
4877 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
4878 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
4879 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4880 .writefn = tlbi_aa64_vmalle1is_write },
4881 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
4882 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
4883 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4884 .writefn = tlbi_aa64_vae1is_write },
4885 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
4886 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
4887 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4888 .writefn = tlbi_aa64_vae1is_write },
4889 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
4890 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
4891 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4892 .writefn = tlbi_aa64_vae1is_write },
4893 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
4894 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
4895 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4896 .writefn = tlbi_aa64_vmalle1_write },
4897 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
4898 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
4899 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4900 .writefn = tlbi_aa64_vae1_write },
4901 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
4902 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
4903 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4904 .writefn = tlbi_aa64_vmalle1_write },
4905 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
4906 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
4907 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4908 .writefn = tlbi_aa64_vae1_write },
4909 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
4910 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
4911 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4912 .writefn = tlbi_aa64_vae1_write },
4913 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
4914 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
4915 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
4916 .writefn = tlbi_aa64_vae1_write },
4917 { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
4918 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
4919 .access = PL2_W, .type = ARM_CP_NOP },
4920 { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
4921 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
4922 .access = PL2_W, .type = ARM_CP_NOP },
4923 { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
4924 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
4925 .access = PL2_W, .type = ARM_CP_NO_RAW,
4926 .writefn = tlbi_aa64_alle1is_write },
4927 { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
4928 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
4929 .access = PL2_W, .type = ARM_CP_NO_RAW,
4930 .writefn = tlbi_aa64_alle1is_write },
4931 { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
4932 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
4933 .access = PL2_W, .type = ARM_CP_NOP },
4934 { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
4935 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
4936 .access = PL2_W, .type = ARM_CP_NOP },
4937 { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
4938 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
4939 .access = PL2_W, .type = ARM_CP_NO_RAW,
4940 .writefn = tlbi_aa64_alle1_write },
4941 { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
4942 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
4943 .access = PL2_W, .type = ARM_CP_NO_RAW,
4944 .writefn = tlbi_aa64_alle1is_write },
4945 #ifndef CONFIG_USER_ONLY
4946 /* 64 bit address translation operations */
4947 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
4948 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
4949 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4950 .writefn = ats_write64 },
4951 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
4952 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
4953 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4954 .writefn = ats_write64 },
4955 { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
4956 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
4957 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4958 .writefn = ats_write64 },
4959 { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
4960 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
4961 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4962 .writefn = ats_write64 },
4963 { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
4964 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
4965 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4966 .writefn = ats_write64 },
4967 { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
4968 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5,
4969 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4970 .writefn = ats_write64 },
4971 { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
4972 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6,
4973 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4974 .writefn = ats_write64 },
4975 { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
4976 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7,
4977 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4978 .writefn = ats_write64 },
4979 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
4980 { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
4981 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
4982 .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4983 .writefn = ats_write64 },
4984 { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
4985 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
4986 .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4987 .writefn = ats_write64 },
4988 { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
4989 .type = ARM_CP_ALIAS,
4990 .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
4991 .access = PL1_RW, .resetvalue = 0,
4992 .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
4993 .writefn = par_write },
4994 #endif
4995 /* TLB invalidate last level of translation table walk */
4996 { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
4997 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
4998 .writefn = tlbimva_is_write },
4999 { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
5000 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
5001 .writefn = tlbimvaa_is_write },
5002 { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
5003 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
5004 .writefn = tlbimva_write },
5005 { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
5006 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
5007 .writefn = tlbimvaa_write },
5008 { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
5009 .type = ARM_CP_NO_RAW, .access = PL2_W,
5010 .writefn = tlbimva_hyp_write },
5011 { .name = "TLBIMVALHIS",
5012 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
5013 .type = ARM_CP_NO_RAW, .access = PL2_W,
5014 .writefn = tlbimva_hyp_is_write },
5015 { .name = "TLBIIPAS2",
5016 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
5017 .type = ARM_CP_NOP, .access = PL2_W },
5018 { .name = "TLBIIPAS2IS",
5019 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
5020 .type = ARM_CP_NOP, .access = PL2_W },
5021 { .name = "TLBIIPAS2L",
5022 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
5023 .type = ARM_CP_NOP, .access = PL2_W },
5024 { .name = "TLBIIPAS2LIS",
5025 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
5026 .type = ARM_CP_NOP, .access = PL2_W },
5027 /* 32 bit cache operations */
5028 { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
5029 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
5030 { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
5031 .type = ARM_CP_NOP, .access = PL1_W },
5032 { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
5033 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
5034 { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
5035 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
5036 { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
5037 .type = ARM_CP_NOP, .access = PL1_W },
5038 { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
5039 .type = ARM_CP_NOP, .access = PL1_W },
5040 { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
5041 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access },
5042 { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
5043 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
5044 { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
5045 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access },
5046 { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
5047 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
5048 { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
5049 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
5050 { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
5051 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access },
5052 { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
5053 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
5054 /* MMU Domain access control / MPU write buffer control */
5055 { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
5056 .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,
5057 .writefn = dacr_write, .raw_writefn = raw_write,
5058 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
5059 offsetoflow32(CPUARMState, cp15.dacr_ns) } },
5060 { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
5061 .type = ARM_CP_ALIAS,
5062 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
5063 .access = PL1_RW,
5064 .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
5065 { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
5066 .type = ARM_CP_ALIAS,
5067 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
5068 .access = PL1_RW,
5069 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
5070 /* We rely on the access checks not allowing the guest to write to the
5071 * state field when SPSel indicates that it's being used as the stack
5072 * pointer.
5074 { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
5075 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
5076 .access = PL1_RW, .accessfn = sp_el0_access,
5077 .type = ARM_CP_ALIAS,
5078 .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
5079 { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
5080 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
5081 .access = PL2_RW, .type = ARM_CP_ALIAS,
5082 .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
5083 { .name = "SPSel", .state = ARM_CP_STATE_AA64,
5084 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
5085 .type = ARM_CP_NO_RAW,
5086 .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
5087 { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
5088 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
5089 .type = ARM_CP_ALIAS,
5090 .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]),
5091 .access = PL2_RW, .accessfn = fpexc32_access },
5092 { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
5093 .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
5094 .access = PL2_RW, .resetvalue = 0,
5095 .writefn = dacr_write, .raw_writefn = raw_write,
5096 .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
5097 { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
5098 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
5099 .access = PL2_RW, .resetvalue = 0,
5100 .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
5101 { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
5102 .type = ARM_CP_ALIAS,
5103 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
5104 .access = PL2_RW,
5105 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) },
5106 { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64,
5107 .type = ARM_CP_ALIAS,
5108 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
5109 .access = PL2_RW,
5110 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) },
5111 { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64,
5112 .type = ARM_CP_ALIAS,
5113 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
5114 .access = PL2_RW,
5115 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) },
5116 { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64,
5117 .type = ARM_CP_ALIAS,
5118 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
5119 .access = PL2_RW,
5120 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
5121 { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
5122 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
5123 .resetvalue = 0,
5124 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
5125 { .name = "SDCR", .type = ARM_CP_ALIAS,
5126 .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
5127 .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
5128 .writefn = sdcr_write,
5129 .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
5130 REGINFO_SENTINEL
5133 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
5134 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
5135 { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
5136 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
5137 .access = PL2_RW,
5138 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
5139 { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
5140 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
5141 .access = PL2_RW,
5142 .type = ARM_CP_CONST, .resetvalue = 0 },
5143 { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
5144 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
5145 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5146 { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
5147 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
5148 .access = PL2_RW,
5149 .type = ARM_CP_CONST, .resetvalue = 0 },
5150 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
5151 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
5152 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5153 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
5154 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
5155 .access = PL2_RW, .type = ARM_CP_CONST,
5156 .resetvalue = 0 },
5157 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
5158 .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
5159 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5160 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
5161 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
5162 .access = PL2_RW, .type = ARM_CP_CONST,
5163 .resetvalue = 0 },
5164 { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
5165 .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
5166 .access = PL2_RW, .type = ARM_CP_CONST,
5167 .resetvalue = 0 },
5168 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
5169 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
5170 .access = PL2_RW, .type = ARM_CP_CONST,
5171 .resetvalue = 0 },
5172 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
5173 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
5174 .access = PL2_RW, .type = ARM_CP_CONST,
5175 .resetvalue = 0 },
5176 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
5177 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
5178 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5179 { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
5180 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
5181 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5182 .type = ARM_CP_CONST, .resetvalue = 0 },
5183 { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
5184 .cp = 15, .opc1 = 6, .crm = 2,
5185 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5186 .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
5187 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
5188 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
5189 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5190 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
5191 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
5192 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5193 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
5194 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
5195 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5196 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
5197 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
5198 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5199 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
5200 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
5201 .resetvalue = 0 },
5202 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
5203 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
5204 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5205 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
5206 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
5207 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5208 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
5209 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
5210 .resetvalue = 0 },
5211 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
5212 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
5213 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5214 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
5215 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
5216 .resetvalue = 0 },
5217 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
5218 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
5219 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5220 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
5221 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
5222 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5223 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
5224 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
5225 .access = PL2_RW, .accessfn = access_tda,
5226 .type = ARM_CP_CONST, .resetvalue = 0 },
5227 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
5228 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
5229 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5230 .type = ARM_CP_CONST, .resetvalue = 0 },
5231 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
5232 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
5233 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5234 { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
5235 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
5236 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5237 { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
5238 .type = ARM_CP_CONST,
5239 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
5240 .access = PL2_RW, .resetvalue = 0 },
5241 REGINFO_SENTINEL
5244 /* Ditto, but for registers which exist in ARMv8 but not v7 */
5245 static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
5246 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
5247 .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
5248 .access = PL2_RW,
5249 .type = ARM_CP_CONST, .resetvalue = 0 },
5250 REGINFO_SENTINEL
5253 static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
5255 ARMCPU *cpu = env_archcpu(env);
5257 if (arm_feature(env, ARM_FEATURE_V8)) {
5258 valid_mask |= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5259 } else {
5260 valid_mask |= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5263 if (arm_feature(env, ARM_FEATURE_EL3)) {
5264 valid_mask &= ~HCR_HCD;
5265 } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
5266 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5267 * However, if we're using the SMC PSCI conduit then QEMU is
5268 * effectively acting like EL3 firmware and so the guest at
5269 * EL2 should retain the ability to prevent EL1 from being
5270 * able to make SMC calls into the ersatz firmware, so in
5271 * that case HCR.TSC should be read/write.
5273 valid_mask &= ~HCR_TSC;
5276 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
5277 if (cpu_isar_feature(aa64_vh, cpu)) {
5278 valid_mask |= HCR_E2H;
5280 if (cpu_isar_feature(aa64_lor, cpu)) {
5281 valid_mask |= HCR_TLOR;
5283 if (cpu_isar_feature(aa64_pauth, cpu)) {
5284 valid_mask |= HCR_API | HCR_APK;
5286 if (cpu_isar_feature(aa64_mte, cpu)) {
5287 valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5;
5291 /* Clear RES0 bits. */
5292 value &= valid_mask;
5295 * These bits change the MMU setup:
5296 * HCR_VM enables stage 2 translation
5297 * HCR_PTW forbids certain page-table setups
5298 * HCR_DC disables stage1 and enables stage2 translation
5299 * HCR_DCT enables tagging on (disabled) stage1 translation
5301 if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT)) {
5302 tlb_flush(CPU(cpu));
5304 env->cp15.hcr_el2 = value;
5307 * Updates to VI and VF require us to update the status of
5308 * virtual interrupts, which are the logical OR of these bits
5309 * and the state of the input lines from the GIC. (This requires
5310 * that we have the iothread lock, which is done by marking the
5311 * reginfo structs as ARM_CP_IO.)
5312 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5313 * possible for it to be taken immediately, because VIRQ and
5314 * VFIQ are masked unless running at EL0 or EL1, and HCR
5315 * can only be written at EL2.
5317 g_assert(qemu_mutex_iothread_locked());
5318 arm_cpu_update_virq(cpu);
5319 arm_cpu_update_vfiq(cpu);
5322 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
5324 do_hcr_write(env, value, 0);
5327 static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri,
5328 uint64_t value)
5330 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5331 value = deposit64(env->cp15.hcr_el2, 32, 32, value);
5332 do_hcr_write(env, value, MAKE_64BIT_MASK(0, 32));
5335 static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri,
5336 uint64_t value)
5338 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5339 value = deposit64(env->cp15.hcr_el2, 0, 32, value);
5340 do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32));
5344 * Return the effective value of HCR_EL2.
5345 * Bits that are not included here:
5346 * RW (read from SCR_EL3.RW as needed)
5348 uint64_t arm_hcr_el2_eff(CPUARMState *env)
5350 uint64_t ret = env->cp15.hcr_el2;
5352 if (arm_is_secure_below_el3(env)) {
5354 * "This register has no effect if EL2 is not enabled in the
5355 * current Security state". This is ARMv8.4-SecEL2 speak for
5356 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5358 * Prior to that, the language was "In an implementation that
5359 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5360 * as if this field is 0 for all purposes other than a direct
5361 * read or write access of HCR_EL2". With lots of enumeration
5362 * on a per-field basis. In current QEMU, this is condition
5363 * is arm_is_secure_below_el3.
5365 * Since the v8.4 language applies to the entire register, and
5366 * appears to be backward compatible, use that.
5368 return 0;
5372 * For a cpu that supports both aarch64 and aarch32, we can set bits
5373 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5374 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5376 if (!arm_el_is_aa64(env, 2)) {
5377 uint64_t aa32_valid;
5380 * These bits are up-to-date as of ARMv8.6.
5381 * For HCR, it's easiest to list just the 2 bits that are invalid.
5382 * For HCR2, list those that are valid.
5384 aa32_valid = MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ);
5385 aa32_valid |= (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNCE |
5386 HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS);
5387 ret &= aa32_valid;
5390 if (ret & HCR_TGE) {
5391 /* These bits are up-to-date as of ARMv8.6. */
5392 if (ret & HCR_E2H) {
5393 ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO |
5394 HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE |
5395 HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU |
5396 HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE |
5397 HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT |
5398 HCR_TTLBIS | HCR_TTLBOS | HCR_TID5);
5399 } else {
5400 ret |= HCR_FMO | HCR_IMO | HCR_AMO;
5402 ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE |
5403 HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR |
5404 HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM |
5405 HCR_TLOR);
5408 return ret;
5411 static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
5412 uint64_t value)
5415 * For A-profile AArch32 EL3, if NSACR.CP10
5416 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5418 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
5419 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
5420 value &= ~(0x3 << 10);
5421 value |= env->cp15.cptr_el[2] & (0x3 << 10);
5423 env->cp15.cptr_el[2] = value;
5426 static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri)
5429 * For A-profile AArch32 EL3, if NSACR.CP10
5430 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5432 uint64_t value = env->cp15.cptr_el[2];
5434 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
5435 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
5436 value |= 0x3 << 10;
5438 return value;
5441 static const ARMCPRegInfo el2_cp_reginfo[] = {
5442 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
5443 .type = ARM_CP_IO,
5444 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
5445 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
5446 .writefn = hcr_write },
5447 { .name = "HCR", .state = ARM_CP_STATE_AA32,
5448 .type = ARM_CP_ALIAS | ARM_CP_IO,
5449 .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
5450 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
5451 .writefn = hcr_writelow },
5452 { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
5453 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
5454 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5455 { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
5456 .type = ARM_CP_ALIAS,
5457 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
5458 .access = PL2_RW,
5459 .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
5460 { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
5461 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
5462 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
5463 { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
5464 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
5465 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
5466 { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
5467 .type = ARM_CP_ALIAS,
5468 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
5469 .access = PL2_RW,
5470 .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) },
5471 { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
5472 .type = ARM_CP_ALIAS,
5473 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
5474 .access = PL2_RW,
5475 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) },
5476 { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
5477 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
5478 .access = PL2_RW, .writefn = vbar_write,
5479 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
5480 .resetvalue = 0 },
5481 { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
5482 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
5483 .access = PL3_RW, .type = ARM_CP_ALIAS,
5484 .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
5485 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
5486 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
5487 .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
5488 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]),
5489 .readfn = cptr_el2_read, .writefn = cptr_el2_write },
5490 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
5491 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
5492 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
5493 .resetvalue = 0 },
5494 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
5495 .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
5496 .access = PL2_RW, .type = ARM_CP_ALIAS,
5497 .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
5498 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
5499 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
5500 .access = PL2_RW, .type = ARM_CP_CONST,
5501 .resetvalue = 0 },
5502 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
5503 { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
5504 .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
5505 .access = PL2_RW, .type = ARM_CP_CONST,
5506 .resetvalue = 0 },
5507 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
5508 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
5509 .access = PL2_RW, .type = ARM_CP_CONST,
5510 .resetvalue = 0 },
5511 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
5512 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
5513 .access = PL2_RW, .type = ARM_CP_CONST,
5514 .resetvalue = 0 },
5515 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
5516 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
5517 .access = PL2_RW, .writefn = vmsa_tcr_el12_write,
5518 /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */
5519 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
5520 { .name = "VTCR", .state = ARM_CP_STATE_AA32,
5521 .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
5522 .type = ARM_CP_ALIAS,
5523 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5524 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
5525 { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
5526 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
5527 .access = PL2_RW,
5528 /* no .writefn needed as this can't cause an ASID change;
5529 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
5531 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
5532 { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
5533 .cp = 15, .opc1 = 6, .crm = 2,
5534 .type = ARM_CP_64BIT | ARM_CP_ALIAS,
5535 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5536 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
5537 .writefn = vttbr_write },
5538 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
5539 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
5540 .access = PL2_RW, .writefn = vttbr_write,
5541 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
5542 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
5543 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
5544 .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
5545 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) },
5546 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
5547 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
5548 .access = PL2_RW, .resetvalue = 0,
5549 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
5550 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
5551 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
5552 .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write,
5553 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
5554 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
5555 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
5556 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
5557 { .name = "TLBIALLNSNH",
5558 .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
5559 .type = ARM_CP_NO_RAW, .access = PL2_W,
5560 .writefn = tlbiall_nsnh_write },
5561 { .name = "TLBIALLNSNHIS",
5562 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
5563 .type = ARM_CP_NO_RAW, .access = PL2_W,
5564 .writefn = tlbiall_nsnh_is_write },
5565 { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
5566 .type = ARM_CP_NO_RAW, .access = PL2_W,
5567 .writefn = tlbiall_hyp_write },
5568 { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
5569 .type = ARM_CP_NO_RAW, .access = PL2_W,
5570 .writefn = tlbiall_hyp_is_write },
5571 { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
5572 .type = ARM_CP_NO_RAW, .access = PL2_W,
5573 .writefn = tlbimva_hyp_write },
5574 { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
5575 .type = ARM_CP_NO_RAW, .access = PL2_W,
5576 .writefn = tlbimva_hyp_is_write },
5577 { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
5578 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
5579 .type = ARM_CP_NO_RAW, .access = PL2_W,
5580 .writefn = tlbi_aa64_alle2_write },
5581 { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
5582 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
5583 .type = ARM_CP_NO_RAW, .access = PL2_W,
5584 .writefn = tlbi_aa64_vae2_write },
5585 { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
5586 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
5587 .access = PL2_W, .type = ARM_CP_NO_RAW,
5588 .writefn = tlbi_aa64_vae2_write },
5589 { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
5590 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
5591 .access = PL2_W, .type = ARM_CP_NO_RAW,
5592 .writefn = tlbi_aa64_alle2is_write },
5593 { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
5594 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
5595 .type = ARM_CP_NO_RAW, .access = PL2_W,
5596 .writefn = tlbi_aa64_vae2is_write },
5597 { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
5598 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
5599 .access = PL2_W, .type = ARM_CP_NO_RAW,
5600 .writefn = tlbi_aa64_vae2is_write },
5601 #ifndef CONFIG_USER_ONLY
5602 /* Unlike the other EL2-related AT operations, these must
5603 * UNDEF from EL3 if EL2 is not implemented, which is why we
5604 * define them here rather than with the rest of the AT ops.
5606 { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
5607 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
5608 .access = PL2_W, .accessfn = at_s1e2_access,
5609 .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
5610 { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
5611 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
5612 .access = PL2_W, .accessfn = at_s1e2_access,
5613 .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
5614 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
5615 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
5616 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
5617 * to behave as if SCR.NS was 1.
5619 { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
5620 .access = PL2_W,
5621 .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
5622 { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
5623 .access = PL2_W,
5624 .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
5625 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
5626 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
5627 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
5628 * reset values as IMPDEF. We choose to reset to 3 to comply with
5629 * both ARMv7 and ARMv8.
5631 .access = PL2_RW, .resetvalue = 3,
5632 .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
5633 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
5634 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
5635 .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
5636 .writefn = gt_cntvoff_write,
5637 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
5638 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
5639 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
5640 .writefn = gt_cntvoff_write,
5641 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
5642 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
5643 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
5644 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
5645 .type = ARM_CP_IO, .access = PL2_RW,
5646 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
5647 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
5648 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
5649 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO,
5650 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
5651 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
5652 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
5653 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
5654 .resetfn = gt_hyp_timer_reset,
5655 .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write },
5656 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
5657 .type = ARM_CP_IO,
5658 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
5659 .access = PL2_RW,
5660 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl),
5661 .resetvalue = 0,
5662 .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
5663 #endif
5664 /* The only field of MDCR_EL2 that has a defined architectural reset value
5665 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
5666 * don't implement any PMU event counters, so using zero as a reset
5667 * value for MDCR_EL2 is okay
5669 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
5670 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
5671 .access = PL2_RW, .resetvalue = 0,
5672 .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
5673 { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
5674 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
5675 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5676 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
5677 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
5678 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
5679 .access = PL2_RW,
5680 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
5681 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
5682 .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
5683 .access = PL2_RW,
5684 .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) },
5685 REGINFO_SENTINEL
5688 static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
5689 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
5690 .type = ARM_CP_ALIAS | ARM_CP_IO,
5691 .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
5692 .access = PL2_RW,
5693 .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2),
5694 .writefn = hcr_writehigh },
5695 REGINFO_SENTINEL
5698 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
5699 bool isread)
5701 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
5702 * At Secure EL1 it traps to EL3.
5704 if (arm_current_el(env) == 3) {
5705 return CP_ACCESS_OK;
5707 if (arm_is_secure_below_el3(env)) {
5708 return CP_ACCESS_TRAP_EL3;
5710 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
5711 if (isread) {
5712 return CP_ACCESS_OK;
5714 return CP_ACCESS_TRAP_UNCATEGORIZED;
5717 static const ARMCPRegInfo el3_cp_reginfo[] = {
5718 { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
5719 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
5720 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
5721 .resetvalue = 0, .writefn = scr_write },
5722 { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL,
5723 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
5724 .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
5725 .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
5726 .writefn = scr_write },
5727 { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
5728 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
5729 .access = PL3_RW, .resetvalue = 0,
5730 .fieldoffset = offsetof(CPUARMState, cp15.sder) },
5731 { .name = "SDER",
5732 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
5733 .access = PL3_RW, .resetvalue = 0,
5734 .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
5735 { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
5736 .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
5737 .writefn = vbar_write, .resetvalue = 0,
5738 .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
5739 { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
5740 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
5741 .access = PL3_RW, .resetvalue = 0,
5742 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
5743 { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
5744 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
5745 .access = PL3_RW,
5746 /* no .writefn needed as this can't cause an ASID change;
5747 * we must provide a .raw_writefn and .resetfn because we handle
5748 * reset and migration for the AArch32 TTBCR(S), which might be
5749 * using mask and base_mask.
5751 .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write,
5752 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
5753 { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
5754 .type = ARM_CP_ALIAS,
5755 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
5756 .access = PL3_RW,
5757 .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
5758 { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
5759 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
5760 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
5761 { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
5762 .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
5763 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
5764 { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
5765 .type = ARM_CP_ALIAS,
5766 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
5767 .access = PL3_RW,
5768 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) },
5769 { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
5770 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
5771 .access = PL3_RW, .writefn = vbar_write,
5772 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
5773 .resetvalue = 0 },
5774 { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
5775 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
5776 .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
5777 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
5778 { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
5779 .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
5780 .access = PL3_RW, .resetvalue = 0,
5781 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
5782 { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
5783 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
5784 .access = PL3_RW, .type = ARM_CP_CONST,
5785 .resetvalue = 0 },
5786 { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
5787 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
5788 .access = PL3_RW, .type = ARM_CP_CONST,
5789 .resetvalue = 0 },
5790 { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
5791 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
5792 .access = PL3_RW, .type = ARM_CP_CONST,
5793 .resetvalue = 0 },
5794 { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
5795 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
5796 .access = PL3_W, .type = ARM_CP_NO_RAW,
5797 .writefn = tlbi_aa64_alle3is_write },
5798 { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
5799 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
5800 .access = PL3_W, .type = ARM_CP_NO_RAW,
5801 .writefn = tlbi_aa64_vae3is_write },
5802 { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
5803 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
5804 .access = PL3_W, .type = ARM_CP_NO_RAW,
5805 .writefn = tlbi_aa64_vae3is_write },
5806 { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
5807 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
5808 .access = PL3_W, .type = ARM_CP_NO_RAW,
5809 .writefn = tlbi_aa64_alle3_write },
5810 { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
5811 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
5812 .access = PL3_W, .type = ARM_CP_NO_RAW,
5813 .writefn = tlbi_aa64_vae3_write },
5814 { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
5815 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
5816 .access = PL3_W, .type = ARM_CP_NO_RAW,
5817 .writefn = tlbi_aa64_vae3_write },
5818 REGINFO_SENTINEL
5821 #ifndef CONFIG_USER_ONLY
5822 /* Test if system register redirection is to occur in the current state. */
5823 static bool redirect_for_e2h(CPUARMState *env)
5825 return arm_current_el(env) == 2 && (arm_hcr_el2_eff(env) & HCR_E2H);
5828 static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri)
5830 CPReadFn *readfn;
5832 if (redirect_for_e2h(env)) {
5833 /* Switch to the saved EL2 version of the register. */
5834 ri = ri->opaque;
5835 readfn = ri->readfn;
5836 } else {
5837 readfn = ri->orig_readfn;
5839 if (readfn == NULL) {
5840 readfn = raw_read;
5842 return readfn(env, ri);
5845 static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri,
5846 uint64_t value)
5848 CPWriteFn *writefn;
5850 if (redirect_for_e2h(env)) {
5851 /* Switch to the saved EL2 version of the register. */
5852 ri = ri->opaque;
5853 writefn = ri->writefn;
5854 } else {
5855 writefn = ri->orig_writefn;
5857 if (writefn == NULL) {
5858 writefn = raw_write;
5860 writefn(env, ri, value);
5863 static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
5865 struct E2HAlias {
5866 uint32_t src_key, dst_key, new_key;
5867 const char *src_name, *dst_name, *new_name;
5868 bool (*feature)(const ARMISARegisters *id);
5871 #define K(op0, op1, crn, crm, op2) \
5872 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
5874 static const struct E2HAlias aliases[] = {
5875 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
5876 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
5877 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
5878 "CPACR", "CPTR_EL2", "CPACR_EL12" },
5879 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
5880 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
5881 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
5882 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
5883 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
5884 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
5885 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
5886 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
5887 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
5888 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
5889 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
5890 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
5891 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
5892 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
5893 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
5894 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
5895 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
5896 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
5897 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
5898 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
5899 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
5900 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
5901 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
5902 "VBAR", "VBAR_EL2", "VBAR_EL12" },
5903 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
5904 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
5905 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
5906 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
5909 * Note that redirection of ZCR is mentioned in the description
5910 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
5911 * not in the summary table.
5913 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
5914 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve },
5916 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
5917 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },
5919 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
5920 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
5922 #undef K
5924 size_t i;
5926 for (i = 0; i < ARRAY_SIZE(aliases); i++) {
5927 const struct E2HAlias *a = &aliases[i];
5928 ARMCPRegInfo *src_reg, *dst_reg;
5930 if (a->feature && !a->feature(&cpu->isar)) {
5931 continue;
5934 src_reg = g_hash_table_lookup(cpu->cp_regs, &a->src_key);
5935 dst_reg = g_hash_table_lookup(cpu->cp_regs, &a->dst_key);
5936 g_assert(src_reg != NULL);
5937 g_assert(dst_reg != NULL);
5939 /* Cross-compare names to detect typos in the keys. */
5940 g_assert(strcmp(src_reg->name, a->src_name) == 0);
5941 g_assert(strcmp(dst_reg->name, a->dst_name) == 0);
5943 /* None of the core system registers use opaque; we will. */
5944 g_assert(src_reg->opaque == NULL);
5946 /* Create alias before redirection so we dup the right data. */
5947 if (a->new_key) {
5948 ARMCPRegInfo *new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
5949 uint32_t *new_key = g_memdup(&a->new_key, sizeof(uint32_t));
5950 bool ok;
5952 new_reg->name = a->new_name;
5953 new_reg->type |= ARM_CP_ALIAS;
5954 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
5955 new_reg->access &= PL2_RW | PL3_RW;
5957 ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
5958 g_assert(ok);
5961 src_reg->opaque = dst_reg;
5962 src_reg->orig_readfn = src_reg->readfn ?: raw_read;
5963 src_reg->orig_writefn = src_reg->writefn ?: raw_write;
5964 if (!src_reg->raw_readfn) {
5965 src_reg->raw_readfn = raw_read;
5967 if (!src_reg->raw_writefn) {
5968 src_reg->raw_writefn = raw_write;
5970 src_reg->readfn = el2_e2h_read;
5971 src_reg->writefn = el2_e2h_write;
5974 #endif
5976 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
5977 bool isread)
5979 int cur_el = arm_current_el(env);
5981 if (cur_el < 2) {
5982 uint64_t hcr = arm_hcr_el2_eff(env);
5984 if (cur_el == 0) {
5985 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
5986 if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) {
5987 return CP_ACCESS_TRAP_EL2;
5989 } else {
5990 if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
5991 return CP_ACCESS_TRAP;
5993 if (hcr & HCR_TID2) {
5994 return CP_ACCESS_TRAP_EL2;
5997 } else if (hcr & HCR_TID2) {
5998 return CP_ACCESS_TRAP_EL2;
6002 if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) {
6003 return CP_ACCESS_TRAP_EL2;
6006 return CP_ACCESS_OK;
6009 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
6010 uint64_t value)
6012 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
6013 * read via a bit in OSLSR_EL1.
6015 int oslock;
6017 if (ri->state == ARM_CP_STATE_AA32) {
6018 oslock = (value == 0xC5ACCE55);
6019 } else {
6020 oslock = value & 1;
6023 env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
6026 static const ARMCPRegInfo debug_cp_reginfo[] = {
6027 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
6028 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
6029 * unlike DBGDRAR it is never accessible from EL0.
6030 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
6031 * accessor.
6033 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
6034 .access = PL0_R, .accessfn = access_tdra,
6035 .type = ARM_CP_CONST, .resetvalue = 0 },
6036 { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
6037 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
6038 .access = PL1_R, .accessfn = access_tdra,
6039 .type = ARM_CP_CONST, .resetvalue = 0 },
6040 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
6041 .access = PL0_R, .accessfn = access_tdra,
6042 .type = ARM_CP_CONST, .resetvalue = 0 },
6043 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
6044 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
6045 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
6046 .access = PL1_RW, .accessfn = access_tda,
6047 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
6048 .resetvalue = 0 },
6049 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
6050 * We don't implement the configurable EL0 access.
6052 { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
6053 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
6054 .type = ARM_CP_ALIAS,
6055 .access = PL1_R, .accessfn = access_tda,
6056 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
6057 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
6058 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
6059 .access = PL1_W, .type = ARM_CP_NO_RAW,
6060 .accessfn = access_tdosa,
6061 .writefn = oslar_write },
6062 { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
6063 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
6064 .access = PL1_R, .resetvalue = 10,
6065 .accessfn = access_tdosa,
6066 .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
6067 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
6068 { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
6069 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
6070 .access = PL1_RW, .accessfn = access_tdosa,
6071 .type = ARM_CP_NOP },
6072 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
6073 * implement vector catch debug events yet.
6075 { .name = "DBGVCR",
6076 .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
6077 .access = PL1_RW, .accessfn = access_tda,
6078 .type = ARM_CP_NOP },
6079 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
6080 * to save and restore a 32-bit guest's DBGVCR)
6082 { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
6083 .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
6084 .access = PL2_RW, .accessfn = access_tda,
6085 .type = ARM_CP_NOP },
6086 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
6087 * Channel but Linux may try to access this register. The 32-bit
6088 * alias is DBGDCCINT.
6090 { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
6091 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
6092 .access = PL1_RW, .accessfn = access_tda,
6093 .type = ARM_CP_NOP },
6094 REGINFO_SENTINEL
6097 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
6098 /* 64 bit access versions of the (dummy) debug registers */
6099 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
6100 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
6101 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
6102 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
6103 REGINFO_SENTINEL
6106 /* Return the exception level to which exceptions should be taken
6107 * via SVEAccessTrap. If an exception should be routed through
6108 * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
6109 * take care of raising that exception.
6110 * C.f. the ARM pseudocode function CheckSVEEnabled.
6112 int sve_exception_el(CPUARMState *env, int el)
6114 #ifndef CONFIG_USER_ONLY
6115 uint64_t hcr_el2 = arm_hcr_el2_eff(env);
6117 if (el <= 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
6118 bool disabled = false;
6120 /* The CPACR.ZEN controls traps to EL1:
6121 * 0, 2 : trap EL0 and EL1 accesses
6122 * 1 : trap only EL0 accesses
6123 * 3 : trap no accesses
6125 if (!extract32(env->cp15.cpacr_el1, 16, 1)) {
6126 disabled = true;
6127 } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) {
6128 disabled = el == 0;
6130 if (disabled) {
6131 /* route_to_el2 */
6132 return hcr_el2 & HCR_TGE ? 2 : 1;
6135 /* Check CPACR.FPEN. */
6136 if (!extract32(env->cp15.cpacr_el1, 20, 1)) {
6137 disabled = true;
6138 } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) {
6139 disabled = el == 0;
6141 if (disabled) {
6142 return 0;
6146 /* CPTR_EL2. Since TZ and TFP are positive,
6147 * they will be zero when EL2 is not present.
6149 if (el <= 2 && !arm_is_secure_below_el3(env)) {
6150 if (env->cp15.cptr_el[2] & CPTR_TZ) {
6151 return 2;
6153 if (env->cp15.cptr_el[2] & CPTR_TFP) {
6154 return 0;
6158 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6159 if (arm_feature(env, ARM_FEATURE_EL3)
6160 && !(env->cp15.cptr_el[3] & CPTR_EZ)) {
6161 return 3;
6163 #endif
6164 return 0;
6167 static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
6169 uint32_t end_len;
6171 end_len = start_len &= 0xf;
6172 if (!test_bit(start_len, cpu->sve_vq_map)) {
6173 end_len = find_last_bit(cpu->sve_vq_map, start_len);
6174 assert(end_len < start_len);
6176 return end_len;
6180 * Given that SVE is enabled, return the vector length for EL.
6182 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
6184 ARMCPU *cpu = env_archcpu(env);
6185 uint32_t zcr_len = cpu->sve_max_vq - 1;
6187 if (el <= 1) {
6188 zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]);
6190 if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) {
6191 zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]);
6193 if (arm_feature(env, ARM_FEATURE_EL3)) {
6194 zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
6197 return sve_zcr_get_valid_len(cpu, zcr_len);
6200 static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
6201 uint64_t value)
6203 int cur_el = arm_current_el(env);
6204 int old_len = sve_zcr_len_for_el(env, cur_el);
6205 int new_len;
6207 /* Bits other than [3:0] are RAZ/WI. */
6208 QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16);
6209 raw_write(env, ri, value & 0xf);
6212 * Because we arrived here, we know both FP and SVE are enabled;
6213 * otherwise we would have trapped access to the ZCR_ELn register.
6215 new_len = sve_zcr_len_for_el(env, cur_el);
6216 if (new_len < old_len) {
6217 aarch64_sve_narrow_vq(env, new_len + 1);
6221 static const ARMCPRegInfo zcr_el1_reginfo = {
6222 .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
6223 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
6224 .access = PL1_RW, .type = ARM_CP_SVE,
6225 .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
6226 .writefn = zcr_write, .raw_writefn = raw_write
6229 static const ARMCPRegInfo zcr_el2_reginfo = {
6230 .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
6231 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
6232 .access = PL2_RW, .type = ARM_CP_SVE,
6233 .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
6234 .writefn = zcr_write, .raw_writefn = raw_write
6237 static const ARMCPRegInfo zcr_no_el2_reginfo = {
6238 .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
6239 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
6240 .access = PL2_RW, .type = ARM_CP_SVE,
6241 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
6244 static const ARMCPRegInfo zcr_el3_reginfo = {
6245 .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
6246 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
6247 .access = PL3_RW, .type = ARM_CP_SVE,
6248 .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
6249 .writefn = zcr_write, .raw_writefn = raw_write
6252 void hw_watchpoint_update(ARMCPU *cpu, int n)
6254 CPUARMState *env = &cpu->env;
6255 vaddr len = 0;
6256 vaddr wvr = env->cp15.dbgwvr[n];
6257 uint64_t wcr = env->cp15.dbgwcr[n];
6258 int mask;
6259 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
6261 if (env->cpu_watchpoint[n]) {
6262 cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
6263 env->cpu_watchpoint[n] = NULL;
6266 if (!extract64(wcr, 0, 1)) {
6267 /* E bit clear : watchpoint disabled */
6268 return;
6271 switch (extract64(wcr, 3, 2)) {
6272 case 0:
6273 /* LSC 00 is reserved and must behave as if the wp is disabled */
6274 return;
6275 case 1:
6276 flags |= BP_MEM_READ;
6277 break;
6278 case 2:
6279 flags |= BP_MEM_WRITE;
6280 break;
6281 case 3:
6282 flags |= BP_MEM_ACCESS;
6283 break;
6286 /* Attempts to use both MASK and BAS fields simultaneously are
6287 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
6288 * thus generating a watchpoint for every byte in the masked region.
6290 mask = extract64(wcr, 24, 4);
6291 if (mask == 1 || mask == 2) {
6292 /* Reserved values of MASK; we must act as if the mask value was
6293 * some non-reserved value, or as if the watchpoint were disabled.
6294 * We choose the latter.
6296 return;
6297 } else if (mask) {
6298 /* Watchpoint covers an aligned area up to 2GB in size */
6299 len = 1ULL << mask;
6300 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
6301 * whether the watchpoint fires when the unmasked bits match; we opt
6302 * to generate the exceptions.
6304 wvr &= ~(len - 1);
6305 } else {
6306 /* Watchpoint covers bytes defined by the byte address select bits */
6307 int bas = extract64(wcr, 5, 8);
6308 int basstart;
6310 if (extract64(wvr, 2, 1)) {
6311 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
6312 * ignored, and BAS[3:0] define which bytes to watch.
6314 bas &= 0xf;
6317 if (bas == 0) {
6318 /* This must act as if the watchpoint is disabled */
6319 return;
6322 /* The BAS bits are supposed to be programmed to indicate a contiguous
6323 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
6324 * we fire for each byte in the word/doubleword addressed by the WVR.
6325 * We choose to ignore any non-zero bits after the first range of 1s.
6327 basstart = ctz32(bas);
6328 len = cto32(bas >> basstart);
6329 wvr += basstart;
6332 cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
6333 &env->cpu_watchpoint[n]);
6336 void hw_watchpoint_update_all(ARMCPU *cpu)
6338 int i;
6339 CPUARMState *env = &cpu->env;
6341 /* Completely clear out existing QEMU watchpoints and our array, to
6342 * avoid possible stale entries following migration load.
6344 cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
6345 memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
6347 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
6348 hw_watchpoint_update(cpu, i);
6352 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
6353 uint64_t value)
6355 ARMCPU *cpu = env_archcpu(env);
6356 int i = ri->crm;
6358 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
6359 * register reads and behaves as if values written are sign extended.
6360 * Bits [1:0] are RES0.
6362 value = sextract64(value, 0, 49) & ~3ULL;
6364 raw_write(env, ri, value);
6365 hw_watchpoint_update(cpu, i);
6368 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
6369 uint64_t value)
6371 ARMCPU *cpu = env_archcpu(env);
6372 int i = ri->crm;
6374 raw_write(env, ri, value);
6375 hw_watchpoint_update(cpu, i);
6378 void hw_breakpoint_update(ARMCPU *cpu, int n)
6380 CPUARMState *env = &cpu->env;
6381 uint64_t bvr = env->cp15.dbgbvr[n];
6382 uint64_t bcr = env->cp15.dbgbcr[n];
6383 vaddr addr;
6384 int bt;
6385 int flags = BP_CPU;
6387 if (env->cpu_breakpoint[n]) {
6388 cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
6389 env->cpu_breakpoint[n] = NULL;
6392 if (!extract64(bcr, 0, 1)) {
6393 /* E bit clear : watchpoint disabled */
6394 return;
6397 bt = extract64(bcr, 20, 4);
6399 switch (bt) {
6400 case 4: /* unlinked address mismatch (reserved if AArch64) */
6401 case 5: /* linked address mismatch (reserved if AArch64) */
6402 qemu_log_mask(LOG_UNIMP,
6403 "arm: address mismatch breakpoint types not implemented\n");
6404 return;
6405 case 0: /* unlinked address match */
6406 case 1: /* linked address match */
6408 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
6409 * we behave as if the register was sign extended. Bits [1:0] are
6410 * RES0. The BAS field is used to allow setting breakpoints on 16
6411 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
6412 * a bp will fire if the addresses covered by the bp and the addresses
6413 * covered by the insn overlap but the insn doesn't start at the
6414 * start of the bp address range. We choose to require the insn and
6415 * the bp to have the same address. The constraints on writing to
6416 * BAS enforced in dbgbcr_write mean we have only four cases:
6417 * 0b0000 => no breakpoint
6418 * 0b0011 => breakpoint on addr
6419 * 0b1100 => breakpoint on addr + 2
6420 * 0b1111 => breakpoint on addr
6421 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
6423 int bas = extract64(bcr, 5, 4);
6424 addr = sextract64(bvr, 0, 49) & ~3ULL;
6425 if (bas == 0) {
6426 return;
6428 if (bas == 0xc) {
6429 addr += 2;
6431 break;
6433 case 2: /* unlinked context ID match */
6434 case 8: /* unlinked VMID match (reserved if no EL2) */
6435 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
6436 qemu_log_mask(LOG_UNIMP,
6437 "arm: unlinked context breakpoint types not implemented\n");
6438 return;
6439 case 9: /* linked VMID match (reserved if no EL2) */
6440 case 11: /* linked context ID and VMID match (reserved if no EL2) */
6441 case 3: /* linked context ID match */
6442 default:
6443 /* We must generate no events for Linked context matches (unless
6444 * they are linked to by some other bp/wp, which is handled in
6445 * updates for the linking bp/wp). We choose to also generate no events
6446 * for reserved values.
6448 return;
6451 cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
6454 void hw_breakpoint_update_all(ARMCPU *cpu)
6456 int i;
6457 CPUARMState *env = &cpu->env;
6459 /* Completely clear out existing QEMU breakpoints and our array, to
6460 * avoid possible stale entries following migration load.
6462 cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
6463 memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
6465 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
6466 hw_breakpoint_update(cpu, i);
6470 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
6471 uint64_t value)
6473 ARMCPU *cpu = env_archcpu(env);
6474 int i = ri->crm;
6476 raw_write(env, ri, value);
6477 hw_breakpoint_update(cpu, i);
6480 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
6481 uint64_t value)
6483 ARMCPU *cpu = env_archcpu(env);
6484 int i = ri->crm;
6486 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
6487 * copy of BAS[0].
6489 value = deposit64(value, 6, 1, extract64(value, 5, 1));
6490 value = deposit64(value, 8, 1, extract64(value, 7, 1));
6492 raw_write(env, ri, value);
6493 hw_breakpoint_update(cpu, i);
6496 static void define_debug_regs(ARMCPU *cpu)
6498 /* Define v7 and v8 architectural debug registers.
6499 * These are just dummy implementations for now.
6501 int i;
6502 int wrps, brps, ctx_cmps;
6503 ARMCPRegInfo dbgdidr = {
6504 .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
6505 .access = PL0_R, .accessfn = access_tda,
6506 .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
6509 /* Note that all these register fields hold "number of Xs minus 1". */
6510 brps = arm_num_brps(cpu);
6511 wrps = arm_num_wrps(cpu);
6512 ctx_cmps = arm_num_ctx_cmps(cpu);
6514 assert(ctx_cmps <= brps);
6516 define_one_arm_cp_reg(cpu, &dbgdidr);
6517 define_arm_cp_regs(cpu, debug_cp_reginfo);
6519 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
6520 define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
6523 for (i = 0; i < brps; i++) {
6524 ARMCPRegInfo dbgregs[] = {
6525 { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
6526 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
6527 .access = PL1_RW, .accessfn = access_tda,
6528 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
6529 .writefn = dbgbvr_write, .raw_writefn = raw_write
6531 { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
6532 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
6533 .access = PL1_RW, .accessfn = access_tda,
6534 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
6535 .writefn = dbgbcr_write, .raw_writefn = raw_write
6537 REGINFO_SENTINEL
6539 define_arm_cp_regs(cpu, dbgregs);
6542 for (i = 0; i < wrps; i++) {
6543 ARMCPRegInfo dbgregs[] = {
6544 { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
6545 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
6546 .access = PL1_RW, .accessfn = access_tda,
6547 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
6548 .writefn = dbgwvr_write, .raw_writefn = raw_write
6550 { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
6551 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
6552 .access = PL1_RW, .accessfn = access_tda,
6553 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
6554 .writefn = dbgwcr_write, .raw_writefn = raw_write
6556 REGINFO_SENTINEL
6558 define_arm_cp_regs(cpu, dbgregs);
6562 static void define_pmu_regs(ARMCPU *cpu)
6565 * v7 performance monitor control register: same implementor
6566 * field as main ID register, and we implement four counters in
6567 * addition to the cycle count register.
6569 unsigned int i, pmcrn = 4;
6570 ARMCPRegInfo pmcr = {
6571 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
6572 .access = PL0_RW,
6573 .type = ARM_CP_IO | ARM_CP_ALIAS,
6574 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
6575 .accessfn = pmreg_access, .writefn = pmcr_write,
6576 .raw_writefn = raw_write,
6578 ARMCPRegInfo pmcr64 = {
6579 .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
6580 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
6581 .access = PL0_RW, .accessfn = pmreg_access,
6582 .type = ARM_CP_IO,
6583 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
6584 .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) |
6585 PMCRLC,
6586 .writefn = pmcr_write, .raw_writefn = raw_write,
6588 define_one_arm_cp_reg(cpu, &pmcr);
6589 define_one_arm_cp_reg(cpu, &pmcr64);
6590 for (i = 0; i < pmcrn; i++) {
6591 char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i);
6592 char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i);
6593 char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i);
6594 char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i);
6595 ARMCPRegInfo pmev_regs[] = {
6596 { .name = pmevcntr_name, .cp = 15, .crn = 14,
6597 .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
6598 .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
6599 .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
6600 .accessfn = pmreg_access },
6601 { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
6602 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
6603 .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
6604 .type = ARM_CP_IO,
6605 .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
6606 .raw_readfn = pmevcntr_rawread,
6607 .raw_writefn = pmevcntr_rawwrite },
6608 { .name = pmevtyper_name, .cp = 15, .crn = 14,
6609 .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
6610 .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
6611 .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
6612 .accessfn = pmreg_access },
6613 { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,
6614 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)),
6615 .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
6616 .type = ARM_CP_IO,
6617 .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
6618 .raw_writefn = pmevtyper_rawwrite },
6619 REGINFO_SENTINEL
6621 define_arm_cp_regs(cpu, pmev_regs);
6622 g_free(pmevcntr_name);
6623 g_free(pmevcntr_el0_name);
6624 g_free(pmevtyper_name);
6625 g_free(pmevtyper_el0_name);
6627 if (cpu_isar_feature(aa32_pmu_8_1, cpu)) {
6628 ARMCPRegInfo v81_pmu_regs[] = {
6629 { .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
6630 .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
6631 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
6632 .resetvalue = extract64(cpu->pmceid0, 32, 32) },
6633 { .name = "PMCEID3", .state = ARM_CP_STATE_AA32,
6634 .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
6635 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
6636 .resetvalue = extract64(cpu->pmceid1, 32, 32) },
6637 REGINFO_SENTINEL
6639 define_arm_cp_regs(cpu, v81_pmu_regs);
6641 if (cpu_isar_feature(any_pmu_8_4, cpu)) {
6642 static const ARMCPRegInfo v84_pmmir = {
6643 .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH,
6644 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6,
6645 .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
6646 .resetvalue = 0
6648 define_one_arm_cp_reg(cpu, &v84_pmmir);
6652 /* We don't know until after realize whether there's a GICv3
6653 * attached, and that is what registers the gicv3 sysregs.
6654 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
6655 * at runtime.
6657 static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
6659 ARMCPU *cpu = env_archcpu(env);
6660 uint64_t pfr1 = cpu->isar.id_pfr1;
6662 if (env->gicv3state) {
6663 pfr1 |= 1 << 28;
6665 return pfr1;
6668 #ifndef CONFIG_USER_ONLY
6669 static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
6671 ARMCPU *cpu = env_archcpu(env);
6672 uint64_t pfr0 = cpu->isar.id_aa64pfr0;
6674 if (env->gicv3state) {
6675 pfr0 |= 1 << 24;
6677 return pfr0;
6679 #endif
6681 /* Shared logic between LORID and the rest of the LOR* registers.
6682 * Secure state exclusion has already been dealt with.
6684 static CPAccessResult access_lor_ns(CPUARMState *env,
6685 const ARMCPRegInfo *ri, bool isread)
6687 int el = arm_current_el(env);
6689 if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) {
6690 return CP_ACCESS_TRAP_EL2;
6692 if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) {
6693 return CP_ACCESS_TRAP_EL3;
6695 return CP_ACCESS_OK;
6698 static CPAccessResult access_lor_other(CPUARMState *env,
6699 const ARMCPRegInfo *ri, bool isread)
6701 if (arm_is_secure_below_el3(env)) {
6702 /* Access denied in secure mode. */
6703 return CP_ACCESS_TRAP;
6705 return access_lor_ns(env, ri, isread);
6709 * A trivial implementation of ARMv8.1-LOR leaves all of these
6710 * registers fixed at 0, which indicates that there are zero
6711 * supported Limited Ordering regions.
6713 static const ARMCPRegInfo lor_reginfo[] = {
6714 { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64,
6715 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0,
6716 .access = PL1_RW, .accessfn = access_lor_other,
6717 .type = ARM_CP_CONST, .resetvalue = 0 },
6718 { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64,
6719 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1,
6720 .access = PL1_RW, .accessfn = access_lor_other,
6721 .type = ARM_CP_CONST, .resetvalue = 0 },
6722 { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64,
6723 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2,
6724 .access = PL1_RW, .accessfn = access_lor_other,
6725 .type = ARM_CP_CONST, .resetvalue = 0 },
6726 { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64,
6727 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3,
6728 .access = PL1_RW, .accessfn = access_lor_other,
6729 .type = ARM_CP_CONST, .resetvalue = 0 },
6730 { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
6731 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
6732 .access = PL1_R, .accessfn = access_lor_ns,
6733 .type = ARM_CP_CONST, .resetvalue = 0 },
6734 REGINFO_SENTINEL
6737 #ifdef TARGET_AARCH64
6738 static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri,
6739 bool isread)
6741 int el = arm_current_el(env);
6743 if (el < 2 &&
6744 arm_feature(env, ARM_FEATURE_EL2) &&
6745 !(arm_hcr_el2_eff(env) & HCR_APK)) {
6746 return CP_ACCESS_TRAP_EL2;
6748 if (el < 3 &&
6749 arm_feature(env, ARM_FEATURE_EL3) &&
6750 !(env->cp15.scr_el3 & SCR_APK)) {
6751 return CP_ACCESS_TRAP_EL3;
6753 return CP_ACCESS_OK;
6756 static const ARMCPRegInfo pauth_reginfo[] = {
6757 { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
6758 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0,
6759 .access = PL1_RW, .accessfn = access_pauth,
6760 .fieldoffset = offsetof(CPUARMState, keys.apda.lo) },
6761 { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
6762 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1,
6763 .access = PL1_RW, .accessfn = access_pauth,
6764 .fieldoffset = offsetof(CPUARMState, keys.apda.hi) },
6765 { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
6766 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2,
6767 .access = PL1_RW, .accessfn = access_pauth,
6768 .fieldoffset = offsetof(CPUARMState, keys.apdb.lo) },
6769 { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
6770 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3,
6771 .access = PL1_RW, .accessfn = access_pauth,
6772 .fieldoffset = offsetof(CPUARMState, keys.apdb.hi) },
6773 { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
6774 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0,
6775 .access = PL1_RW, .accessfn = access_pauth,
6776 .fieldoffset = offsetof(CPUARMState, keys.apga.lo) },
6777 { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
6778 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1,
6779 .access = PL1_RW, .accessfn = access_pauth,
6780 .fieldoffset = offsetof(CPUARMState, keys.apga.hi) },
6781 { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
6782 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0,
6783 .access = PL1_RW, .accessfn = access_pauth,
6784 .fieldoffset = offsetof(CPUARMState, keys.apia.lo) },
6785 { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
6786 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1,
6787 .access = PL1_RW, .accessfn = access_pauth,
6788 .fieldoffset = offsetof(CPUARMState, keys.apia.hi) },
6789 { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
6790 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2,
6791 .access = PL1_RW, .accessfn = access_pauth,
6792 .fieldoffset = offsetof(CPUARMState, keys.apib.lo) },
6793 { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
6794 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3,
6795 .access = PL1_RW, .accessfn = access_pauth,
6796 .fieldoffset = offsetof(CPUARMState, keys.apib.hi) },
6797 REGINFO_SENTINEL
6800 static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
6802 Error *err = NULL;
6803 uint64_t ret;
6805 /* Success sets NZCV = 0000. */
6806 env->NF = env->CF = env->VF = 0, env->ZF = 1;
6808 if (qemu_guest_getrandom(&ret, sizeof(ret), &err) < 0) {
6810 * ??? Failed, for unknown reasons in the crypto subsystem.
6811 * The best we can do is log the reason and return the
6812 * timed-out indication to the guest. There is no reason
6813 * we know to expect this failure to be transitory, so the
6814 * guest may well hang retrying the operation.
6816 qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
6817 ri->name, error_get_pretty(err));
6818 error_free(err);
6820 env->ZF = 0; /* NZCF = 0100 */
6821 return 0;
6823 return ret;
6826 /* We do not support re-seeding, so the two registers operate the same. */
6827 static const ARMCPRegInfo rndr_reginfo[] = {
6828 { .name = "RNDR", .state = ARM_CP_STATE_AA64,
6829 .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO,
6830 .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 0,
6831 .access = PL0_R, .readfn = rndr_readfn },
6832 { .name = "RNDRRS", .state = ARM_CP_STATE_AA64,
6833 .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO,
6834 .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1,
6835 .access = PL0_R, .readfn = rndr_readfn },
6836 REGINFO_SENTINEL
6839 #ifndef CONFIG_USER_ONLY
6840 static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque,
6841 uint64_t value)
6843 ARMCPU *cpu = env_archcpu(env);
6844 /* CTR_EL0 System register -> DminLine, bits [19:16] */
6845 uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF);
6846 uint64_t vaddr_in = (uint64_t) value;
6847 uint64_t vaddr = vaddr_in & ~(dline_size - 1);
6848 void *haddr;
6849 int mem_idx = cpu_mmu_index(env, false);
6851 /* This won't be crossing page boundaries */
6852 haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC());
6853 if (haddr) {
6855 ram_addr_t offset;
6856 MemoryRegion *mr;
6858 /* RCU lock is already being held */
6859 mr = memory_region_from_host(haddr, &offset);
6861 if (mr) {
6862 memory_region_writeback(mr, offset, dline_size);
6867 static const ARMCPRegInfo dcpop_reg[] = {
6868 { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64,
6869 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1,
6870 .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
6871 .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
6872 REGINFO_SENTINEL
6875 static const ARMCPRegInfo dcpodp_reg[] = {
6876 { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64,
6877 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1,
6878 .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
6879 .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
6880 REGINFO_SENTINEL
6882 #endif /*CONFIG_USER_ONLY*/
6884 static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInfo *ri,
6885 bool isread)
6887 if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID5)) {
6888 return CP_ACCESS_TRAP_EL2;
6891 return CP_ACCESS_OK;
6894 static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri,
6895 bool isread)
6897 int el = arm_current_el(env);
6899 if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
6900 uint64_t hcr = arm_hcr_el2_eff(env);
6901 if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) {
6902 return CP_ACCESS_TRAP_EL2;
6905 if (el < 3 &&
6906 arm_feature(env, ARM_FEATURE_EL3) &&
6907 !(env->cp15.scr_el3 & SCR_ATA)) {
6908 return CP_ACCESS_TRAP_EL3;
6910 return CP_ACCESS_OK;
6913 static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri)
6915 return env->pstate & PSTATE_TCO;
6918 static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
6920 env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO);
6923 static const ARMCPRegInfo mte_reginfo[] = {
6924 { .name = "TFSRE0_EL1", .state = ARM_CP_STATE_AA64,
6925 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 1,
6926 .access = PL1_RW, .accessfn = access_mte,
6927 .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[0]) },
6928 { .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64,
6929 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 0,
6930 .access = PL1_RW, .accessfn = access_mte,
6931 .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) },
6932 { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64,
6933 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 6, .opc2 = 0,
6934 .access = PL2_RW, .accessfn = access_mte,
6935 .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) },
6936 { .name = "TFSR_EL3", .state = ARM_CP_STATE_AA64,
6937 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 6, .opc2 = 0,
6938 .access = PL3_RW,
6939 .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[3]) },
6940 { .name = "RGSR_EL1", .state = ARM_CP_STATE_AA64,
6941 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 5,
6942 .access = PL1_RW, .accessfn = access_mte,
6943 .fieldoffset = offsetof(CPUARMState, cp15.rgsr_el1) },
6944 { .name = "GCR_EL1", .state = ARM_CP_STATE_AA64,
6945 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6,
6946 .access = PL1_RW, .accessfn = access_mte,
6947 .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) },
6948 { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
6949 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
6950 .access = PL1_R, .accessfn = access_aa64_tid5,
6951 .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
6952 { .name = "TCO", .state = ARM_CP_STATE_AA64,
6953 .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
6954 .type = ARM_CP_NO_RAW,
6955 .access = PL0_RW, .readfn = tco_read, .writefn = tco_write },
6956 { .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64,
6957 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3,
6958 .type = ARM_CP_NOP, .access = PL1_W,
6959 .accessfn = aa64_cacheop_poc_access },
6960 { .name = "DC_IGSW", .state = ARM_CP_STATE_AA64,
6961 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4,
6962 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
6963 { .name = "DC_IGDVAC", .state = ARM_CP_STATE_AA64,
6964 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5,
6965 .type = ARM_CP_NOP, .access = PL1_W,
6966 .accessfn = aa64_cacheop_poc_access },
6967 { .name = "DC_IGDSW", .state = ARM_CP_STATE_AA64,
6968 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6,
6969 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
6970 { .name = "DC_CGSW", .state = ARM_CP_STATE_AA64,
6971 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4,
6972 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
6973 { .name = "DC_CGDSW", .state = ARM_CP_STATE_AA64,
6974 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6,
6975 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
6976 { .name = "DC_CIGSW", .state = ARM_CP_STATE_AA64,
6977 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4,
6978 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
6979 { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64,
6980 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
6981 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
6982 REGINFO_SENTINEL
6985 static const ARMCPRegInfo mte_tco_ro_reginfo[] = {
6986 { .name = "TCO", .state = ARM_CP_STATE_AA64,
6987 .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
6988 .type = ARM_CP_CONST, .access = PL0_RW, },
6989 REGINFO_SENTINEL
6992 static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
6993 { .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64,
6994 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3,
6995 .type = ARM_CP_NOP, .access = PL0_W,
6996 .accessfn = aa64_cacheop_poc_access },
6997 { .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64,
6998 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5,
6999 .type = ARM_CP_NOP, .access = PL0_W,
7000 .accessfn = aa64_cacheop_poc_access },
7001 { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64,
7002 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
7003 .type = ARM_CP_NOP, .access = PL0_W,
7004 .accessfn = aa64_cacheop_poc_access },
7005 { .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64,
7006 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5,
7007 .type = ARM_CP_NOP, .access = PL0_W,
7008 .accessfn = aa64_cacheop_poc_access },
7009 { .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64,
7010 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3,
7011 .type = ARM_CP_NOP, .access = PL0_W,
7012 .accessfn = aa64_cacheop_poc_access },
7013 { .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64,
7014 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5,
7015 .type = ARM_CP_NOP, .access = PL0_W,
7016 .accessfn = aa64_cacheop_poc_access },
7017 { .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64,
7018 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3,
7019 .type = ARM_CP_NOP, .access = PL0_W,
7020 .accessfn = aa64_cacheop_poc_access },
7021 { .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64,
7022 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5,
7023 .type = ARM_CP_NOP, .access = PL0_W,
7024 .accessfn = aa64_cacheop_poc_access },
7025 { .name = "DC_GVA", .state = ARM_CP_STATE_AA64,
7026 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3,
7027 .access = PL0_W, .type = ARM_CP_DC_GVA,
7028 #ifndef CONFIG_USER_ONLY
7029 /* Avoid overhead of an access check that always passes in user-mode */
7030 .accessfn = aa64_zva_access,
7031 #endif
7033 { .name = "DC_GZVA", .state = ARM_CP_STATE_AA64,
7034 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 4,
7035 .access = PL0_W, .type = ARM_CP_DC_GZVA,
7036 #ifndef CONFIG_USER_ONLY
7037 /* Avoid overhead of an access check that always passes in user-mode */
7038 .accessfn = aa64_zva_access,
7039 #endif
7041 REGINFO_SENTINEL
7044 #endif
7046 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
7047 bool isread)
7049 int el = arm_current_el(env);
7051 if (el == 0) {
7052 uint64_t sctlr = arm_sctlr(env, el);
7053 if (!(sctlr & SCTLR_EnRCTX)) {
7054 return CP_ACCESS_TRAP;
7056 } else if (el == 1) {
7057 uint64_t hcr = arm_hcr_el2_eff(env);
7058 if (hcr & HCR_NV) {
7059 return CP_ACCESS_TRAP_EL2;
7062 return CP_ACCESS_OK;
7065 static const ARMCPRegInfo predinv_reginfo[] = {
7066 { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64,
7067 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4,
7068 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
7069 { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64,
7070 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5,
7071 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
7072 { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64,
7073 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7,
7074 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
7076 * Note the AArch32 opcodes have a different OPC1.
7078 { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32,
7079 .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4,
7080 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
7081 { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32,
7082 .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5,
7083 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
7084 { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,
7085 .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
7086 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
7087 REGINFO_SENTINEL
7090 static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri)
7092 /* Read the high 32 bits of the current CCSIDR */
7093 return extract64(ccsidr_read(env, ri), 32, 32);
7096 static const ARMCPRegInfo ccsidr2_reginfo[] = {
7097 { .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH,
7098 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2,
7099 .access = PL1_R,
7100 .accessfn = access_aa64_tid2,
7101 .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW },
7102 REGINFO_SENTINEL
7105 static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
7106 bool isread)
7108 if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) {
7109 return CP_ACCESS_TRAP_EL2;
7112 return CP_ACCESS_OK;
7115 static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
7116 bool isread)
7118 if (arm_feature(env, ARM_FEATURE_V8)) {
7119 return access_aa64_tid3(env, ri, isread);
7122 return CP_ACCESS_OK;
7125 static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri,
7126 bool isread)
7128 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID0)) {
7129 return CP_ACCESS_TRAP_EL2;
7132 return CP_ACCESS_OK;
7135 static const ARMCPRegInfo jazelle_regs[] = {
7136 { .name = "JIDR",
7137 .cp = 14, .crn = 0, .crm = 0, .opc1 = 7, .opc2 = 0,
7138 .access = PL1_R, .accessfn = access_jazelle,
7139 .type = ARM_CP_CONST, .resetvalue = 0 },
7140 { .name = "JOSCR",
7141 .cp = 14, .crn = 1, .crm = 0, .opc1 = 7, .opc2 = 0,
7142 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
7143 { .name = "JMCR",
7144 .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0,
7145 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
7146 REGINFO_SENTINEL
7149 static const ARMCPRegInfo vhe_reginfo[] = {
7150 { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
7151 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
7152 .access = PL2_RW,
7153 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
7154 { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
7155 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
7156 .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
7157 .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) },
7158 #ifndef CONFIG_USER_ONLY
7159 { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64,
7160 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 2,
7161 .fieldoffset =
7162 offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cval),
7163 .type = ARM_CP_IO, .access = PL2_RW,
7164 .writefn = gt_hv_cval_write, .raw_writefn = raw_write },
7165 { .name = "CNTHV_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
7166 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 0,
7167 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
7168 .resetfn = gt_hv_timer_reset,
7169 .readfn = gt_hv_tval_read, .writefn = gt_hv_tval_write },
7170 { .name = "CNTHV_CTL_EL2", .state = ARM_CP_STATE_BOTH,
7171 .type = ARM_CP_IO,
7172 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 1,
7173 .access = PL2_RW,
7174 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].ctl),
7175 .writefn = gt_hv_ctl_write, .raw_writefn = raw_write },
7176 { .name = "CNTP_CTL_EL02", .state = ARM_CP_STATE_AA64,
7177 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1,
7178 .type = ARM_CP_IO | ARM_CP_ALIAS,
7179 .access = PL2_RW, .accessfn = e2h_access,
7180 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
7181 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write },
7182 { .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64,
7183 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1,
7184 .type = ARM_CP_IO | ARM_CP_ALIAS,
7185 .access = PL2_RW, .accessfn = e2h_access,
7186 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
7187 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write },
7188 { .name = "CNTP_TVAL_EL02", .state = ARM_CP_STATE_AA64,
7189 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 0,
7190 .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS,
7191 .access = PL2_RW, .accessfn = e2h_access,
7192 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write },
7193 { .name = "CNTV_TVAL_EL02", .state = ARM_CP_STATE_AA64,
7194 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 0,
7195 .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS,
7196 .access = PL2_RW, .accessfn = e2h_access,
7197 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write },
7198 { .name = "CNTP_CVAL_EL02", .state = ARM_CP_STATE_AA64,
7199 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 2,
7200 .type = ARM_CP_IO | ARM_CP_ALIAS,
7201 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
7202 .access = PL2_RW, .accessfn = e2h_access,
7203 .writefn = gt_phys_cval_write, .raw_writefn = raw_write },
7204 { .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64,
7205 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2,
7206 .type = ARM_CP_IO | ARM_CP_ALIAS,
7207 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
7208 .access = PL2_RW, .accessfn = e2h_access,
7209 .writefn = gt_virt_cval_write, .raw_writefn = raw_write },
7210 #endif
7211 REGINFO_SENTINEL
7214 #ifndef CONFIG_USER_ONLY
7215 static const ARMCPRegInfo ats1e1_reginfo[] = {
7216 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
7217 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
7218 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
7219 .writefn = ats_write64 },
7220 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
7221 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
7222 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
7223 .writefn = ats_write64 },
7224 REGINFO_SENTINEL
7227 static const ARMCPRegInfo ats1cp_reginfo[] = {
7228 { .name = "ATS1CPRP",
7229 .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
7230 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
7231 .writefn = ats_write },
7232 { .name = "ATS1CPWP",
7233 .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
7234 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
7235 .writefn = ats_write },
7236 REGINFO_SENTINEL
7238 #endif
7241 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
7242 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
7243 * is non-zero, which is never for ARMv7, optionally in ARMv8
7244 * and mandatorily for ARMv8.2 and up.
7245 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
7246 * implementation is RAZ/WI we can ignore this detail, as we
7247 * do for ACTLR.
7249 static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = {
7250 { .name = "ACTLR2", .state = ARM_CP_STATE_AA32,
7251 .cp = 15, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 3,
7252 .access = PL1_RW, .accessfn = access_tacr,
7253 .type = ARM_CP_CONST, .resetvalue = 0 },
7254 { .name = "HACTLR2", .state = ARM_CP_STATE_AA32,
7255 .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
7256 .access = PL2_RW, .type = ARM_CP_CONST,
7257 .resetvalue = 0 },
7258 REGINFO_SENTINEL
7261 void register_cp_regs_for_features(ARMCPU *cpu)
7263 /* Register all the coprocessor registers based on feature bits */
7264 CPUARMState *env = &cpu->env;
7265 if (arm_feature(env, ARM_FEATURE_M)) {
7266 /* M profile has no coprocessor registers */
7267 return;
7270 define_arm_cp_regs(cpu, cp_reginfo);
7271 if (!arm_feature(env, ARM_FEATURE_V8)) {
7272 /* Must go early as it is full of wildcards that may be
7273 * overridden by later definitions.
7275 define_arm_cp_regs(cpu, not_v8_cp_reginfo);
7278 if (arm_feature(env, ARM_FEATURE_V6)) {
7279 /* The ID registers all have impdef reset values */
7280 ARMCPRegInfo v6_idregs[] = {
7281 { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
7282 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
7283 .access = PL1_R, .type = ARM_CP_CONST,
7284 .accessfn = access_aa32_tid3,
7285 .resetvalue = cpu->isar.id_pfr0 },
7286 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
7287 * the value of the GIC field until after we define these regs.
7289 { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
7290 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
7291 .access = PL1_R, .type = ARM_CP_NO_RAW,
7292 .accessfn = access_aa32_tid3,
7293 .readfn = id_pfr1_read,
7294 .writefn = arm_cp_write_ignore },
7295 { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
7296 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
7297 .access = PL1_R, .type = ARM_CP_CONST,
7298 .accessfn = access_aa32_tid3,
7299 .resetvalue = cpu->isar.id_dfr0 },
7300 { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
7301 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
7302 .access = PL1_R, .type = ARM_CP_CONST,
7303 .accessfn = access_aa32_tid3,
7304 .resetvalue = cpu->id_afr0 },
7305 { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
7306 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
7307 .access = PL1_R, .type = ARM_CP_CONST,
7308 .accessfn = access_aa32_tid3,
7309 .resetvalue = cpu->isar.id_mmfr0 },
7310 { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
7311 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
7312 .access = PL1_R, .type = ARM_CP_CONST,
7313 .accessfn = access_aa32_tid3,
7314 .resetvalue = cpu->isar.id_mmfr1 },
7315 { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
7316 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
7317 .access = PL1_R, .type = ARM_CP_CONST,
7318 .accessfn = access_aa32_tid3,
7319 .resetvalue = cpu->isar.id_mmfr2 },
7320 { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
7321 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
7322 .access = PL1_R, .type = ARM_CP_CONST,
7323 .accessfn = access_aa32_tid3,
7324 .resetvalue = cpu->isar.id_mmfr3 },
7325 { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
7326 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
7327 .access = PL1_R, .type = ARM_CP_CONST,
7328 .accessfn = access_aa32_tid3,
7329 .resetvalue = cpu->isar.id_isar0 },
7330 { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
7331 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
7332 .access = PL1_R, .type = ARM_CP_CONST,
7333 .accessfn = access_aa32_tid3,
7334 .resetvalue = cpu->isar.id_isar1 },
7335 { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
7336 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
7337 .access = PL1_R, .type = ARM_CP_CONST,
7338 .accessfn = access_aa32_tid3,
7339 .resetvalue = cpu->isar.id_isar2 },
7340 { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
7341 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
7342 .access = PL1_R, .type = ARM_CP_CONST,
7343 .accessfn = access_aa32_tid3,
7344 .resetvalue = cpu->isar.id_isar3 },
7345 { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
7346 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
7347 .access = PL1_R, .type = ARM_CP_CONST,
7348 .accessfn = access_aa32_tid3,
7349 .resetvalue = cpu->isar.id_isar4 },
7350 { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
7351 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
7352 .access = PL1_R, .type = ARM_CP_CONST,
7353 .accessfn = access_aa32_tid3,
7354 .resetvalue = cpu->isar.id_isar5 },
7355 { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
7356 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
7357 .access = PL1_R, .type = ARM_CP_CONST,
7358 .accessfn = access_aa32_tid3,
7359 .resetvalue = cpu->isar.id_mmfr4 },
7360 { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
7361 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
7362 .access = PL1_R, .type = ARM_CP_CONST,
7363 .accessfn = access_aa32_tid3,
7364 .resetvalue = cpu->isar.id_isar6 },
7365 REGINFO_SENTINEL
7367 define_arm_cp_regs(cpu, v6_idregs);
7368 define_arm_cp_regs(cpu, v6_cp_reginfo);
7369 } else {
7370 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
7372 if (arm_feature(env, ARM_FEATURE_V6K)) {
7373 define_arm_cp_regs(cpu, v6k_cp_reginfo);
7375 if (arm_feature(env, ARM_FEATURE_V7MP) &&
7376 !arm_feature(env, ARM_FEATURE_PMSA)) {
7377 define_arm_cp_regs(cpu, v7mp_cp_reginfo);
7379 if (arm_feature(env, ARM_FEATURE_V7VE)) {
7380 define_arm_cp_regs(cpu, pmovsset_cp_reginfo);
7382 if (arm_feature(env, ARM_FEATURE_V7)) {
7383 ARMCPRegInfo clidr = {
7384 .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
7385 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
7386 .access = PL1_R, .type = ARM_CP_CONST,
7387 .accessfn = access_aa64_tid2,
7388 .resetvalue = cpu->clidr
7390 define_one_arm_cp_reg(cpu, &clidr);
7391 define_arm_cp_regs(cpu, v7_cp_reginfo);
7392 define_debug_regs(cpu);
7393 define_pmu_regs(cpu);
7394 } else {
7395 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
7397 if (arm_feature(env, ARM_FEATURE_V8)) {
7398 /* AArch64 ID registers, which all have impdef reset values.
7399 * Note that within the ID register ranges the unused slots
7400 * must all RAZ, not UNDEF; future architecture versions may
7401 * define new registers here.
7403 ARMCPRegInfo v8_idregs[] = {
7405 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
7406 * emulation because we don't know the right value for the
7407 * GIC field until after we define these regs.
7409 { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
7410 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
7411 .access = PL1_R,
7412 #ifdef CONFIG_USER_ONLY
7413 .type = ARM_CP_CONST,
7414 .resetvalue = cpu->isar.id_aa64pfr0
7415 #else
7416 .type = ARM_CP_NO_RAW,
7417 .accessfn = access_aa64_tid3,
7418 .readfn = id_aa64pfr0_read,
7419 .writefn = arm_cp_write_ignore
7420 #endif
7422 { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
7423 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
7424 .access = PL1_R, .type = ARM_CP_CONST,
7425 .accessfn = access_aa64_tid3,
7426 .resetvalue = cpu->isar.id_aa64pfr1},
7427 { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7428 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
7429 .access = PL1_R, .type = ARM_CP_CONST,
7430 .accessfn = access_aa64_tid3,
7431 .resetvalue = 0 },
7432 { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7433 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
7434 .access = PL1_R, .type = ARM_CP_CONST,
7435 .accessfn = access_aa64_tid3,
7436 .resetvalue = 0 },
7437 { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64,
7438 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
7439 .access = PL1_R, .type = ARM_CP_CONST,
7440 .accessfn = access_aa64_tid3,
7441 /* At present, only SVEver == 0 is defined anyway. */
7442 .resetvalue = 0 },
7443 { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7444 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
7445 .access = PL1_R, .type = ARM_CP_CONST,
7446 .accessfn = access_aa64_tid3,
7447 .resetvalue = 0 },
7448 { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7449 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
7450 .access = PL1_R, .type = ARM_CP_CONST,
7451 .accessfn = access_aa64_tid3,
7452 .resetvalue = 0 },
7453 { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7454 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
7455 .access = PL1_R, .type = ARM_CP_CONST,
7456 .accessfn = access_aa64_tid3,
7457 .resetvalue = 0 },
7458 { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
7459 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
7460 .access = PL1_R, .type = ARM_CP_CONST,
7461 .accessfn = access_aa64_tid3,
7462 .resetvalue = cpu->isar.id_aa64dfr0 },
7463 { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
7464 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
7465 .access = PL1_R, .type = ARM_CP_CONST,
7466 .accessfn = access_aa64_tid3,
7467 .resetvalue = cpu->isar.id_aa64dfr1 },
7468 { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7469 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
7470 .access = PL1_R, .type = ARM_CP_CONST,
7471 .accessfn = access_aa64_tid3,
7472 .resetvalue = 0 },
7473 { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7474 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
7475 .access = PL1_R, .type = ARM_CP_CONST,
7476 .accessfn = access_aa64_tid3,
7477 .resetvalue = 0 },
7478 { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
7479 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
7480 .access = PL1_R, .type = ARM_CP_CONST,
7481 .accessfn = access_aa64_tid3,
7482 .resetvalue = cpu->id_aa64afr0 },
7483 { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
7484 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
7485 .access = PL1_R, .type = ARM_CP_CONST,
7486 .accessfn = access_aa64_tid3,
7487 .resetvalue = cpu->id_aa64afr1 },
7488 { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7489 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
7490 .access = PL1_R, .type = ARM_CP_CONST,
7491 .accessfn = access_aa64_tid3,
7492 .resetvalue = 0 },
7493 { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7494 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
7495 .access = PL1_R, .type = ARM_CP_CONST,
7496 .accessfn = access_aa64_tid3,
7497 .resetvalue = 0 },
7498 { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
7499 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
7500 .access = PL1_R, .type = ARM_CP_CONST,
7501 .accessfn = access_aa64_tid3,
7502 .resetvalue = cpu->isar.id_aa64isar0 },
7503 { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
7504 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
7505 .access = PL1_R, .type = ARM_CP_CONST,
7506 .accessfn = access_aa64_tid3,
7507 .resetvalue = cpu->isar.id_aa64isar1 },
7508 { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7509 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
7510 .access = PL1_R, .type = ARM_CP_CONST,
7511 .accessfn = access_aa64_tid3,
7512 .resetvalue = 0 },
7513 { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7514 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
7515 .access = PL1_R, .type = ARM_CP_CONST,
7516 .accessfn = access_aa64_tid3,
7517 .resetvalue = 0 },
7518 { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7519 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
7520 .access = PL1_R, .type = ARM_CP_CONST,
7521 .accessfn = access_aa64_tid3,
7522 .resetvalue = 0 },
7523 { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7524 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
7525 .access = PL1_R, .type = ARM_CP_CONST,
7526 .accessfn = access_aa64_tid3,
7527 .resetvalue = 0 },
7528 { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7529 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
7530 .access = PL1_R, .type = ARM_CP_CONST,
7531 .accessfn = access_aa64_tid3,
7532 .resetvalue = 0 },
7533 { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7534 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
7535 .access = PL1_R, .type = ARM_CP_CONST,
7536 .accessfn = access_aa64_tid3,
7537 .resetvalue = 0 },
7538 { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
7539 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
7540 .access = PL1_R, .type = ARM_CP_CONST,
7541 .accessfn = access_aa64_tid3,
7542 .resetvalue = cpu->isar.id_aa64mmfr0 },
7543 { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
7544 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
7545 .access = PL1_R, .type = ARM_CP_CONST,
7546 .accessfn = access_aa64_tid3,
7547 .resetvalue = cpu->isar.id_aa64mmfr1 },
7548 { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64,
7549 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
7550 .access = PL1_R, .type = ARM_CP_CONST,
7551 .accessfn = access_aa64_tid3,
7552 .resetvalue = cpu->isar.id_aa64mmfr2 },
7553 { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7554 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
7555 .access = PL1_R, .type = ARM_CP_CONST,
7556 .accessfn = access_aa64_tid3,
7557 .resetvalue = 0 },
7558 { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7559 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
7560 .access = PL1_R, .type = ARM_CP_CONST,
7561 .accessfn = access_aa64_tid3,
7562 .resetvalue = 0 },
7563 { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7564 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
7565 .access = PL1_R, .type = ARM_CP_CONST,
7566 .accessfn = access_aa64_tid3,
7567 .resetvalue = 0 },
7568 { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7569 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
7570 .access = PL1_R, .type = ARM_CP_CONST,
7571 .accessfn = access_aa64_tid3,
7572 .resetvalue = 0 },
7573 { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7574 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
7575 .access = PL1_R, .type = ARM_CP_CONST,
7576 .accessfn = access_aa64_tid3,
7577 .resetvalue = 0 },
7578 { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
7579 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
7580 .access = PL1_R, .type = ARM_CP_CONST,
7581 .accessfn = access_aa64_tid3,
7582 .resetvalue = cpu->isar.mvfr0 },
7583 { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
7584 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
7585 .access = PL1_R, .type = ARM_CP_CONST,
7586 .accessfn = access_aa64_tid3,
7587 .resetvalue = cpu->isar.mvfr1 },
7588 { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
7589 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
7590 .access = PL1_R, .type = ARM_CP_CONST,
7591 .accessfn = access_aa64_tid3,
7592 .resetvalue = cpu->isar.mvfr2 },
7593 { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7594 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
7595 .access = PL1_R, .type = ARM_CP_CONST,
7596 .accessfn = access_aa64_tid3,
7597 .resetvalue = 0 },
7598 { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7599 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
7600 .access = PL1_R, .type = ARM_CP_CONST,
7601 .accessfn = access_aa64_tid3,
7602 .resetvalue = 0 },
7603 { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7604 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
7605 .access = PL1_R, .type = ARM_CP_CONST,
7606 .accessfn = access_aa64_tid3,
7607 .resetvalue = 0 },
7608 { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7609 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
7610 .access = PL1_R, .type = ARM_CP_CONST,
7611 .accessfn = access_aa64_tid3,
7612 .resetvalue = 0 },
7613 { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7614 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
7615 .access = PL1_R, .type = ARM_CP_CONST,
7616 .accessfn = access_aa64_tid3,
7617 .resetvalue = 0 },
7618 { .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
7619 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
7620 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
7621 .resetvalue = extract64(cpu->pmceid0, 0, 32) },
7622 { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
7623 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
7624 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
7625 .resetvalue = cpu->pmceid0 },
7626 { .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
7627 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
7628 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
7629 .resetvalue = extract64(cpu->pmceid1, 0, 32) },
7630 { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
7631 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
7632 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
7633 .resetvalue = cpu->pmceid1 },
7634 REGINFO_SENTINEL
7636 #ifdef CONFIG_USER_ONLY
7637 ARMCPRegUserSpaceInfo v8_user_idregs[] = {
7638 { .name = "ID_AA64PFR0_EL1",
7639 .exported_bits = 0x000f000f00ff0000,
7640 .fixed_bits = 0x0000000000000011 },
7641 { .name = "ID_AA64PFR1_EL1",
7642 .exported_bits = 0x00000000000000f0 },
7643 { .name = "ID_AA64PFR*_EL1_RESERVED",
7644 .is_glob = true },
7645 { .name = "ID_AA64ZFR0_EL1" },
7646 { .name = "ID_AA64MMFR0_EL1",
7647 .fixed_bits = 0x00000000ff000000 },
7648 { .name = "ID_AA64MMFR1_EL1" },
7649 { .name = "ID_AA64MMFR*_EL1_RESERVED",
7650 .is_glob = true },
7651 { .name = "ID_AA64DFR0_EL1",
7652 .fixed_bits = 0x0000000000000006 },
7653 { .name = "ID_AA64DFR1_EL1" },
7654 { .name = "ID_AA64DFR*_EL1_RESERVED",
7655 .is_glob = true },
7656 { .name = "ID_AA64AFR*",
7657 .is_glob = true },
7658 { .name = "ID_AA64ISAR0_EL1",
7659 .exported_bits = 0x00fffffff0fffff0 },
7660 { .name = "ID_AA64ISAR1_EL1",
7661 .exported_bits = 0x000000f0ffffffff },
7662 { .name = "ID_AA64ISAR*_EL1_RESERVED",
7663 .is_glob = true },
7664 REGUSERINFO_SENTINEL
7666 modify_arm_cp_regs(v8_idregs, v8_user_idregs);
7667 #endif
7668 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
7669 if (!arm_feature(env, ARM_FEATURE_EL3) &&
7670 !arm_feature(env, ARM_FEATURE_EL2)) {
7671 ARMCPRegInfo rvbar = {
7672 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
7673 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
7674 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
7676 define_one_arm_cp_reg(cpu, &rvbar);
7678 define_arm_cp_regs(cpu, v8_idregs);
7679 define_arm_cp_regs(cpu, v8_cp_reginfo);
7681 if (arm_feature(env, ARM_FEATURE_EL2)) {
7682 uint64_t vmpidr_def = mpidr_read_val(env);
7683 ARMCPRegInfo vpidr_regs[] = {
7684 { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
7685 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
7686 .access = PL2_RW, .accessfn = access_el3_aa32ns,
7687 .resetvalue = cpu->midr, .type = ARM_CP_ALIAS,
7688 .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) },
7689 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
7690 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
7691 .access = PL2_RW, .resetvalue = cpu->midr,
7692 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
7693 { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
7694 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
7695 .access = PL2_RW, .accessfn = access_el3_aa32ns,
7696 .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
7697 .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
7698 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
7699 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
7700 .access = PL2_RW,
7701 .resetvalue = vmpidr_def,
7702 .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
7703 REGINFO_SENTINEL
7705 define_arm_cp_regs(cpu, vpidr_regs);
7706 define_arm_cp_regs(cpu, el2_cp_reginfo);
7707 if (arm_feature(env, ARM_FEATURE_V8)) {
7708 define_arm_cp_regs(cpu, el2_v8_cp_reginfo);
7710 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
7711 if (!arm_feature(env, ARM_FEATURE_EL3)) {
7712 ARMCPRegInfo rvbar = {
7713 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
7714 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
7715 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
7717 define_one_arm_cp_reg(cpu, &rvbar);
7719 } else {
7720 /* If EL2 is missing but higher ELs are enabled, we need to
7721 * register the no_el2 reginfos.
7723 if (arm_feature(env, ARM_FEATURE_EL3)) {
7724 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
7725 * of MIDR_EL1 and MPIDR_EL1.
7727 ARMCPRegInfo vpidr_regs[] = {
7728 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
7729 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
7730 .access = PL2_RW, .accessfn = access_el3_aa32ns,
7731 .type = ARM_CP_CONST, .resetvalue = cpu->midr,
7732 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
7733 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
7734 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
7735 .access = PL2_RW, .accessfn = access_el3_aa32ns,
7736 .type = ARM_CP_NO_RAW,
7737 .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
7738 REGINFO_SENTINEL
7740 define_arm_cp_regs(cpu, vpidr_regs);
7741 define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
7742 if (arm_feature(env, ARM_FEATURE_V8)) {
7743 define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
7747 if (arm_feature(env, ARM_FEATURE_EL3)) {
7748 define_arm_cp_regs(cpu, el3_cp_reginfo);
7749 ARMCPRegInfo el3_regs[] = {
7750 { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
7751 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
7752 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar },
7753 { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
7754 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
7755 .access = PL3_RW,
7756 .raw_writefn = raw_write, .writefn = sctlr_write,
7757 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
7758 .resetvalue = cpu->reset_sctlr },
7759 REGINFO_SENTINEL
7762 define_arm_cp_regs(cpu, el3_regs);
7764 /* The behaviour of NSACR is sufficiently various that we don't
7765 * try to describe it in a single reginfo:
7766 * if EL3 is 64 bit, then trap to EL3 from S EL1,
7767 * reads as constant 0xc00 from NS EL1 and NS EL2
7768 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
7769 * if v7 without EL3, register doesn't exist
7770 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
7772 if (arm_feature(env, ARM_FEATURE_EL3)) {
7773 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
7774 ARMCPRegInfo nsacr = {
7775 .name = "NSACR", .type = ARM_CP_CONST,
7776 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
7777 .access = PL1_RW, .accessfn = nsacr_access,
7778 .resetvalue = 0xc00
7780 define_one_arm_cp_reg(cpu, &nsacr);
7781 } else {
7782 ARMCPRegInfo nsacr = {
7783 .name = "NSACR",
7784 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
7785 .access = PL3_RW | PL1_R,
7786 .resetvalue = 0,
7787 .fieldoffset = offsetof(CPUARMState, cp15.nsacr)
7789 define_one_arm_cp_reg(cpu, &nsacr);
7791 } else {
7792 if (arm_feature(env, ARM_FEATURE_V8)) {
7793 ARMCPRegInfo nsacr = {
7794 .name = "NSACR", .type = ARM_CP_CONST,
7795 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
7796 .access = PL1_R,
7797 .resetvalue = 0xc00
7799 define_one_arm_cp_reg(cpu, &nsacr);
7803 if (arm_feature(env, ARM_FEATURE_PMSA)) {
7804 if (arm_feature(env, ARM_FEATURE_V6)) {
7805 /* PMSAv6 not implemented */
7806 assert(arm_feature(env, ARM_FEATURE_V7));
7807 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
7808 define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
7809 } else {
7810 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
7812 } else {
7813 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
7814 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
7815 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
7816 if (cpu_isar_feature(aa32_hpd, cpu)) {
7817 define_one_arm_cp_reg(cpu, &ttbcr2_reginfo);
7820 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
7821 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
7823 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
7824 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
7826 if (arm_feature(env, ARM_FEATURE_VAPA)) {
7827 define_arm_cp_regs(cpu, vapa_cp_reginfo);
7829 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
7830 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
7832 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
7833 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
7835 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
7836 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
7838 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
7839 define_arm_cp_regs(cpu, omap_cp_reginfo);
7841 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
7842 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
7844 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
7845 define_arm_cp_regs(cpu, xscale_cp_reginfo);
7847 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
7848 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
7850 if (arm_feature(env, ARM_FEATURE_LPAE)) {
7851 define_arm_cp_regs(cpu, lpae_cp_reginfo);
7853 if (cpu_isar_feature(aa32_jazelle, cpu)) {
7854 define_arm_cp_regs(cpu, jazelle_regs);
7856 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
7857 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
7858 * be read-only (ie write causes UNDEF exception).
7861 ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
7862 /* Pre-v8 MIDR space.
7863 * Note that the MIDR isn't a simple constant register because
7864 * of the TI925 behaviour where writes to another register can
7865 * cause the MIDR value to change.
7867 * Unimplemented registers in the c15 0 0 0 space default to
7868 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
7869 * and friends override accordingly.
7871 { .name = "MIDR",
7872 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
7873 .access = PL1_R, .resetvalue = cpu->midr,
7874 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
7875 .readfn = midr_read,
7876 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
7877 .type = ARM_CP_OVERRIDE },
7878 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
7879 { .name = "DUMMY",
7880 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
7881 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7882 { .name = "DUMMY",
7883 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
7884 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7885 { .name = "DUMMY",
7886 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
7887 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7888 { .name = "DUMMY",
7889 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
7890 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7891 { .name = "DUMMY",
7892 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
7893 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7894 REGINFO_SENTINEL
7896 ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
7897 { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
7898 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
7899 .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
7900 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
7901 .readfn = midr_read },
7902 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
7903 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
7904 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
7905 .access = PL1_R, .resetvalue = cpu->midr },
7906 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
7907 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
7908 .access = PL1_R, .resetvalue = cpu->midr },
7909 { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
7910 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
7911 .access = PL1_R,
7912 .accessfn = access_aa64_tid1,
7913 .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
7914 REGINFO_SENTINEL
7916 ARMCPRegInfo id_cp_reginfo[] = {
7917 /* These are common to v8 and pre-v8 */
7918 { .name = "CTR",
7919 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
7920 .access = PL1_R, .accessfn = ctr_el0_access,
7921 .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
7922 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
7923 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
7924 .access = PL0_R, .accessfn = ctr_el0_access,
7925 .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
7926 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
7927 { .name = "TCMTR",
7928 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
7929 .access = PL1_R,
7930 .accessfn = access_aa32_tid1,
7931 .type = ARM_CP_CONST, .resetvalue = 0 },
7932 REGINFO_SENTINEL
7934 /* TLBTR is specific to VMSA */
7935 ARMCPRegInfo id_tlbtr_reginfo = {
7936 .name = "TLBTR",
7937 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
7938 .access = PL1_R,
7939 .accessfn = access_aa32_tid1,
7940 .type = ARM_CP_CONST, .resetvalue = 0,
7942 /* MPUIR is specific to PMSA V6+ */
7943 ARMCPRegInfo id_mpuir_reginfo = {
7944 .name = "MPUIR",
7945 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
7946 .access = PL1_R, .type = ARM_CP_CONST,
7947 .resetvalue = cpu->pmsav7_dregion << 8
7949 ARMCPRegInfo crn0_wi_reginfo = {
7950 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
7951 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
7952 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
7954 #ifdef CONFIG_USER_ONLY
7955 ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
7956 { .name = "MIDR_EL1",
7957 .exported_bits = 0x00000000ffffffff },
7958 { .name = "REVIDR_EL1" },
7959 REGUSERINFO_SENTINEL
7961 modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
7962 #endif
7963 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
7964 arm_feature(env, ARM_FEATURE_STRONGARM)) {
7965 ARMCPRegInfo *r;
7966 /* Register the blanket "writes ignored" value first to cover the
7967 * whole space. Then update the specific ID registers to allow write
7968 * access, so that they ignore writes rather than causing them to
7969 * UNDEF.
7971 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
7972 for (r = id_pre_v8_midr_cp_reginfo;
7973 r->type != ARM_CP_SENTINEL; r++) {
7974 r->access = PL1_RW;
7976 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
7977 r->access = PL1_RW;
7979 id_mpuir_reginfo.access = PL1_RW;
7980 id_tlbtr_reginfo.access = PL1_RW;
7982 if (arm_feature(env, ARM_FEATURE_V8)) {
7983 define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
7984 } else {
7985 define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
7987 define_arm_cp_regs(cpu, id_cp_reginfo);
7988 if (!arm_feature(env, ARM_FEATURE_PMSA)) {
7989 define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
7990 } else if (arm_feature(env, ARM_FEATURE_V7)) {
7991 define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
7995 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
7996 ARMCPRegInfo mpidr_cp_reginfo[] = {
7997 { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH,
7998 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
7999 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
8000 REGINFO_SENTINEL
8002 #ifdef CONFIG_USER_ONLY
8003 ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
8004 { .name = "MPIDR_EL1",
8005 .fixed_bits = 0x0000000080000000 },
8006 REGUSERINFO_SENTINEL
8008 modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo);
8009 #endif
8010 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
8013 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
8014 ARMCPRegInfo auxcr_reginfo[] = {
8015 { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
8016 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
8017 .access = PL1_RW, .accessfn = access_tacr,
8018 .type = ARM_CP_CONST, .resetvalue = cpu->reset_auxcr },
8019 { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
8020 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
8021 .access = PL2_RW, .type = ARM_CP_CONST,
8022 .resetvalue = 0 },
8023 { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
8024 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
8025 .access = PL3_RW, .type = ARM_CP_CONST,
8026 .resetvalue = 0 },
8027 REGINFO_SENTINEL
8029 define_arm_cp_regs(cpu, auxcr_reginfo);
8030 if (cpu_isar_feature(aa32_ac2, cpu)) {
8031 define_arm_cp_regs(cpu, actlr2_hactlr2_reginfo);
8035 if (arm_feature(env, ARM_FEATURE_CBAR)) {
8037 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
8038 * There are two flavours:
8039 * (1) older 32-bit only cores have a simple 32-bit CBAR
8040 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
8041 * 32-bit register visible to AArch32 at a different encoding
8042 * to the "flavour 1" register and with the bits rearranged to
8043 * be able to squash a 64-bit address into the 32-bit view.
8044 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
8045 * in future if we support AArch32-only configs of some of the
8046 * AArch64 cores we might need to add a specific feature flag
8047 * to indicate cores with "flavour 2" CBAR.
8049 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
8050 /* 32 bit view is [31:18] 0...0 [43:32]. */
8051 uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
8052 | extract64(cpu->reset_cbar, 32, 12);
8053 ARMCPRegInfo cbar_reginfo[] = {
8054 { .name = "CBAR",
8055 .type = ARM_CP_CONST,
8056 .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0,
8057 .access = PL1_R, .resetvalue = cbar32 },
8058 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
8059 .type = ARM_CP_CONST,
8060 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
8061 .access = PL1_R, .resetvalue = cpu->reset_cbar },
8062 REGINFO_SENTINEL
8064 /* We don't implement a r/w 64 bit CBAR currently */
8065 assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
8066 define_arm_cp_regs(cpu, cbar_reginfo);
8067 } else {
8068 ARMCPRegInfo cbar = {
8069 .name = "CBAR",
8070 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
8071 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
8072 .fieldoffset = offsetof(CPUARMState,
8073 cp15.c15_config_base_address)
8075 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
8076 cbar.access = PL1_R;
8077 cbar.fieldoffset = 0;
8078 cbar.type = ARM_CP_CONST;
8080 define_one_arm_cp_reg(cpu, &cbar);
8084 if (arm_feature(env, ARM_FEATURE_VBAR)) {
8085 ARMCPRegInfo vbar_cp_reginfo[] = {
8086 { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
8087 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
8088 .access = PL1_RW, .writefn = vbar_write,
8089 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
8090 offsetof(CPUARMState, cp15.vbar_ns) },
8091 .resetvalue = 0 },
8092 REGINFO_SENTINEL
8094 define_arm_cp_regs(cpu, vbar_cp_reginfo);
8097 /* Generic registers whose values depend on the implementation */
8099 ARMCPRegInfo sctlr = {
8100 .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
8101 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
8102 .access = PL1_RW, .accessfn = access_tvm_trvm,
8103 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
8104 offsetof(CPUARMState, cp15.sctlr_ns) },
8105 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
8106 .raw_writefn = raw_write,
8108 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
8109 /* Normally we would always end the TB on an SCTLR write, but Linux
8110 * arch/arm/mach-pxa/sleep.S expects two instructions following
8111 * an MMU enable to execute from cache. Imitate this behaviour.
8113 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
8115 define_one_arm_cp_reg(cpu, &sctlr);
8118 if (cpu_isar_feature(aa64_lor, cpu)) {
8119 define_arm_cp_regs(cpu, lor_reginfo);
8121 if (cpu_isar_feature(aa64_pan, cpu)) {
8122 define_one_arm_cp_reg(cpu, &pan_reginfo);
8124 #ifndef CONFIG_USER_ONLY
8125 if (cpu_isar_feature(aa64_ats1e1, cpu)) {
8126 define_arm_cp_regs(cpu, ats1e1_reginfo);
8128 if (cpu_isar_feature(aa32_ats1e1, cpu)) {
8129 define_arm_cp_regs(cpu, ats1cp_reginfo);
8131 #endif
8132 if (cpu_isar_feature(aa64_uao, cpu)) {
8133 define_one_arm_cp_reg(cpu, &uao_reginfo);
8136 if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
8137 define_arm_cp_regs(cpu, vhe_reginfo);
8140 if (cpu_isar_feature(aa64_sve, cpu)) {
8141 define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
8142 if (arm_feature(env, ARM_FEATURE_EL2)) {
8143 define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
8144 } else {
8145 define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);
8147 if (arm_feature(env, ARM_FEATURE_EL3)) {
8148 define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
8152 #ifdef TARGET_AARCH64
8153 if (cpu_isar_feature(aa64_pauth, cpu)) {
8154 define_arm_cp_regs(cpu, pauth_reginfo);
8156 if (cpu_isar_feature(aa64_rndr, cpu)) {
8157 define_arm_cp_regs(cpu, rndr_reginfo);
8159 #ifndef CONFIG_USER_ONLY
8160 /* Data Cache clean instructions up to PoP */
8161 if (cpu_isar_feature(aa64_dcpop, cpu)) {
8162 define_one_arm_cp_reg(cpu, dcpop_reg);
8164 if (cpu_isar_feature(aa64_dcpodp, cpu)) {
8165 define_one_arm_cp_reg(cpu, dcpodp_reg);
8168 #endif /*CONFIG_USER_ONLY*/
8171 * If full MTE is enabled, add all of the system registers.
8172 * If only "instructions available at EL0" are enabled,
8173 * then define only a RAZ/WI version of PSTATE.TCO.
8175 if (cpu_isar_feature(aa64_mte, cpu)) {
8176 define_arm_cp_regs(cpu, mte_reginfo);
8177 define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
8178 } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) {
8179 define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
8180 define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
8182 #endif
8184 if (cpu_isar_feature(any_predinv, cpu)) {
8185 define_arm_cp_regs(cpu, predinv_reginfo);
8188 if (cpu_isar_feature(any_ccidx, cpu)) {
8189 define_arm_cp_regs(cpu, ccsidr2_reginfo);
8192 #ifndef CONFIG_USER_ONLY
8194 * Register redirections and aliases must be done last,
8195 * after the registers from the other extensions have been defined.
8197 if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
8198 define_arm_vh_e2h_redirects_aliases(cpu);
8200 #endif
8203 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
8205 CPUState *cs = CPU(cpu);
8206 CPUARMState *env = &cpu->env;
8208 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
8210 * The lower part of each SVE register aliases to the FPU
8211 * registers so we don't need to include both.
8213 #ifdef TARGET_AARCH64
8214 if (isar_feature_aa64_sve(&cpu->isar)) {
8215 gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
8216 arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
8217 "sve-registers.xml", 0);
8218 } else
8219 #endif
8221 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
8222 aarch64_fpu_gdb_set_reg,
8223 34, "aarch64-fpu.xml", 0);
8225 } else if (arm_feature(env, ARM_FEATURE_NEON)) {
8226 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
8227 51, "arm-neon.xml", 0);
8228 } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
8229 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
8230 35, "arm-vfp3.xml", 0);
8231 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
8232 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
8233 19, "arm-vfp.xml", 0);
8235 gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
8236 arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
8237 "system-registers.xml", 0);
8241 /* Sort alphabetically by type name, except for "any". */
8242 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
8244 ObjectClass *class_a = (ObjectClass *)a;
8245 ObjectClass *class_b = (ObjectClass *)b;
8246 const char *name_a, *name_b;
8248 name_a = object_class_get_name(class_a);
8249 name_b = object_class_get_name(class_b);
8250 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
8251 return 1;
8252 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
8253 return -1;
8254 } else {
8255 return strcmp(name_a, name_b);
8259 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
8261 ObjectClass *oc = data;
8262 const char *typename;
8263 char *name;
8265 typename = object_class_get_name(oc);
8266 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
8267 qemu_printf(" %s\n", name);
8268 g_free(name);
8271 void arm_cpu_list(void)
8273 GSList *list;
8275 list = object_class_get_list(TYPE_ARM_CPU, false);
8276 list = g_slist_sort(list, arm_cpu_list_compare);
8277 qemu_printf("Available CPUs:\n");
8278 g_slist_foreach(list, arm_cpu_list_entry, NULL);
8279 g_slist_free(list);
8282 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
8284 ObjectClass *oc = data;
8285 CpuDefinitionInfoList **cpu_list = user_data;
8286 CpuDefinitionInfo *info;
8287 const char *typename;
8289 typename = object_class_get_name(oc);
8290 info = g_malloc0(sizeof(*info));
8291 info->name = g_strndup(typename,
8292 strlen(typename) - strlen("-" TYPE_ARM_CPU));
8293 info->q_typename = g_strdup(typename);
8295 QAPI_LIST_PREPEND(*cpu_list, info);
8298 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
8300 CpuDefinitionInfoList *cpu_list = NULL;
8301 GSList *list;
8303 list = object_class_get_list(TYPE_ARM_CPU, false);
8304 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
8305 g_slist_free(list);
8307 return cpu_list;
8310 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
8311 void *opaque, int state, int secstate,
8312 int crm, int opc1, int opc2,
8313 const char *name)
8315 /* Private utility function for define_one_arm_cp_reg_with_opaque():
8316 * add a single reginfo struct to the hash table.
8318 uint32_t *key = g_new(uint32_t, 1);
8319 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
8320 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
8321 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
8323 r2->name = g_strdup(name);
8324 /* Reset the secure state to the specific incoming state. This is
8325 * necessary as the register may have been defined with both states.
8327 r2->secure = secstate;
8329 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
8330 /* Register is banked (using both entries in array).
8331 * Overwriting fieldoffset as the array is only used to define
8332 * banked registers but later only fieldoffset is used.
8334 r2->fieldoffset = r->bank_fieldoffsets[ns];
8337 if (state == ARM_CP_STATE_AA32) {
8338 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
8339 /* If the register is banked then we don't need to migrate or
8340 * reset the 32-bit instance in certain cases:
8342 * 1) If the register has both 32-bit and 64-bit instances then we
8343 * can count on the 64-bit instance taking care of the
8344 * non-secure bank.
8345 * 2) If ARMv8 is enabled then we can count on a 64-bit version
8346 * taking care of the secure bank. This requires that separate
8347 * 32 and 64-bit definitions are provided.
8349 if ((r->state == ARM_CP_STATE_BOTH && ns) ||
8350 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
8351 r2->type |= ARM_CP_ALIAS;
8353 } else if ((secstate != r->secure) && !ns) {
8354 /* The register is not banked so we only want to allow migration of
8355 * the non-secure instance.
8357 r2->type |= ARM_CP_ALIAS;
8360 if (r->state == ARM_CP_STATE_BOTH) {
8361 /* We assume it is a cp15 register if the .cp field is left unset.
8363 if (r2->cp == 0) {
8364 r2->cp = 15;
8367 #ifdef HOST_WORDS_BIGENDIAN
8368 if (r2->fieldoffset) {
8369 r2->fieldoffset += sizeof(uint32_t);
8371 #endif
8374 if (state == ARM_CP_STATE_AA64) {
8375 /* To allow abbreviation of ARMCPRegInfo
8376 * definitions, we treat cp == 0 as equivalent to
8377 * the value for "standard guest-visible sysreg".
8378 * STATE_BOTH definitions are also always "standard
8379 * sysreg" in their AArch64 view (the .cp value may
8380 * be non-zero for the benefit of the AArch32 view).
8382 if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
8383 r2->cp = CP_REG_ARM64_SYSREG_CP;
8385 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
8386 r2->opc0, opc1, opc2);
8387 } else {
8388 *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
8390 if (opaque) {
8391 r2->opaque = opaque;
8393 /* reginfo passed to helpers is correct for the actual access,
8394 * and is never ARM_CP_STATE_BOTH:
8396 r2->state = state;
8397 /* Make sure reginfo passed to helpers for wildcarded regs
8398 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
8400 r2->crm = crm;
8401 r2->opc1 = opc1;
8402 r2->opc2 = opc2;
8403 /* By convention, for wildcarded registers only the first
8404 * entry is used for migration; the others are marked as
8405 * ALIAS so we don't try to transfer the register
8406 * multiple times. Special registers (ie NOP/WFI) are
8407 * never migratable and not even raw-accessible.
8409 if ((r->type & ARM_CP_SPECIAL)) {
8410 r2->type |= ARM_CP_NO_RAW;
8412 if (((r->crm == CP_ANY) && crm != 0) ||
8413 ((r->opc1 == CP_ANY) && opc1 != 0) ||
8414 ((r->opc2 == CP_ANY) && opc2 != 0)) {
8415 r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB;
8418 /* Check that raw accesses are either forbidden or handled. Note that
8419 * we can't assert this earlier because the setup of fieldoffset for
8420 * banked registers has to be done first.
8422 if (!(r2->type & ARM_CP_NO_RAW)) {
8423 assert(!raw_accessors_invalid(r2));
8426 /* Overriding of an existing definition must be explicitly
8427 * requested.
8429 if (!(r->type & ARM_CP_OVERRIDE)) {
8430 ARMCPRegInfo *oldreg;
8431 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
8432 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
8433 fprintf(stderr, "Register redefined: cp=%d %d bit "
8434 "crn=%d crm=%d opc1=%d opc2=%d, "
8435 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
8436 r2->crn, r2->crm, r2->opc1, r2->opc2,
8437 oldreg->name, r2->name);
8438 g_assert_not_reached();
8441 g_hash_table_insert(cpu->cp_regs, key, r2);
8445 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
8446 const ARMCPRegInfo *r, void *opaque)
8448 /* Define implementations of coprocessor registers.
8449 * We store these in a hashtable because typically
8450 * there are less than 150 registers in a space which
8451 * is 16*16*16*8*8 = 262144 in size.
8452 * Wildcarding is supported for the crm, opc1 and opc2 fields.
8453 * If a register is defined twice then the second definition is
8454 * used, so this can be used to define some generic registers and
8455 * then override them with implementation specific variations.
8456 * At least one of the original and the second definition should
8457 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
8458 * against accidental use.
8460 * The state field defines whether the register is to be
8461 * visible in the AArch32 or AArch64 execution state. If the
8462 * state is set to ARM_CP_STATE_BOTH then we synthesise a
8463 * reginfo structure for the AArch32 view, which sees the lower
8464 * 32 bits of the 64 bit register.
8466 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
8467 * be wildcarded. AArch64 registers are always considered to be 64
8468 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
8469 * the register, if any.
8471 int crm, opc1, opc2, state;
8472 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
8473 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
8474 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
8475 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
8476 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
8477 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
8478 /* 64 bit registers have only CRm and Opc1 fields */
8479 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
8480 /* op0 only exists in the AArch64 encodings */
8481 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
8482 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
8483 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
8485 * This API is only for Arm's system coprocessors (14 and 15) or
8486 * (M-profile or v7A-and-earlier only) for implementation defined
8487 * coprocessors in the range 0..7. Our decode assumes this, since
8488 * 8..13 can be used for other insns including VFP and Neon. See
8489 * valid_cp() in translate.c. Assert here that we haven't tried
8490 * to use an invalid coprocessor number.
8492 switch (r->state) {
8493 case ARM_CP_STATE_BOTH:
8494 /* 0 has a special meaning, but otherwise the same rules as AA32. */
8495 if (r->cp == 0) {
8496 break;
8498 /* fall through */
8499 case ARM_CP_STATE_AA32:
8500 if (arm_feature(&cpu->env, ARM_FEATURE_V8) &&
8501 !arm_feature(&cpu->env, ARM_FEATURE_M)) {
8502 assert(r->cp >= 14 && r->cp <= 15);
8503 } else {
8504 assert(r->cp < 8 || (r->cp >= 14 && r->cp <= 15));
8506 break;
8507 case ARM_CP_STATE_AA64:
8508 assert(r->cp == 0 || r->cp == CP_REG_ARM64_SYSREG_CP);
8509 break;
8510 default:
8511 g_assert_not_reached();
8513 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
8514 * encodes a minimum access level for the register. We roll this
8515 * runtime check into our general permission check code, so check
8516 * here that the reginfo's specified permissions are strict enough
8517 * to encompass the generic architectural permission check.
8519 if (r->state != ARM_CP_STATE_AA32) {
8520 int mask = 0;
8521 switch (r->opc1) {
8522 case 0:
8523 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
8524 mask = PL0U_R | PL1_RW;
8525 break;
8526 case 1: case 2:
8527 /* min_EL EL1 */
8528 mask = PL1_RW;
8529 break;
8530 case 3:
8531 /* min_EL EL0 */
8532 mask = PL0_RW;
8533 break;
8534 case 4:
8535 case 5:
8536 /* min_EL EL2 */
8537 mask = PL2_RW;
8538 break;
8539 case 6:
8540 /* min_EL EL3 */
8541 mask = PL3_RW;
8542 break;
8543 case 7:
8544 /* min_EL EL1, secure mode only (we don't check the latter) */
8545 mask = PL1_RW;
8546 break;
8547 default:
8548 /* broken reginfo with out-of-range opc1 */
8549 assert(false);
8550 break;
8552 /* assert our permissions are not too lax (stricter is fine) */
8553 assert((r->access & ~mask) == 0);
8556 /* Check that the register definition has enough info to handle
8557 * reads and writes if they are permitted.
8559 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
8560 if (r->access & PL3_R) {
8561 assert((r->fieldoffset ||
8562 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
8563 r->readfn);
8565 if (r->access & PL3_W) {
8566 assert((r->fieldoffset ||
8567 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
8568 r->writefn);
8571 /* Bad type field probably means missing sentinel at end of reg list */
8572 assert(cptype_valid(r->type));
8573 for (crm = crmmin; crm <= crmmax; crm++) {
8574 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
8575 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
8576 for (state = ARM_CP_STATE_AA32;
8577 state <= ARM_CP_STATE_AA64; state++) {
8578 if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
8579 continue;
8581 if (state == ARM_CP_STATE_AA32) {
8582 /* Under AArch32 CP registers can be common
8583 * (same for secure and non-secure world) or banked.
8585 char *name;
8587 switch (r->secure) {
8588 case ARM_CP_SECSTATE_S:
8589 case ARM_CP_SECSTATE_NS:
8590 add_cpreg_to_hashtable(cpu, r, opaque, state,
8591 r->secure, crm, opc1, opc2,
8592 r->name);
8593 break;
8594 default:
8595 name = g_strdup_printf("%s_S", r->name);
8596 add_cpreg_to_hashtable(cpu, r, opaque, state,
8597 ARM_CP_SECSTATE_S,
8598 crm, opc1, opc2, name);
8599 g_free(name);
8600 add_cpreg_to_hashtable(cpu, r, opaque, state,
8601 ARM_CP_SECSTATE_NS,
8602 crm, opc1, opc2, r->name);
8603 break;
8605 } else {
8606 /* AArch64 registers get mapped to non-secure instance
8607 * of AArch32 */
8608 add_cpreg_to_hashtable(cpu, r, opaque, state,
8609 ARM_CP_SECSTATE_NS,
8610 crm, opc1, opc2, r->name);
8618 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
8619 const ARMCPRegInfo *regs, void *opaque)
8621 /* Define a whole list of registers */
8622 const ARMCPRegInfo *r;
8623 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
8624 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
8629 * Modify ARMCPRegInfo for access from userspace.
8631 * This is a data driven modification directed by
8632 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
8633 * user-space cannot alter any values and dynamic values pertaining to
8634 * execution state are hidden from user space view anyway.
8636 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods)
8638 const ARMCPRegUserSpaceInfo *m;
8639 ARMCPRegInfo *r;
8641 for (m = mods; m->name; m++) {
8642 GPatternSpec *pat = NULL;
8643 if (m->is_glob) {
8644 pat = g_pattern_spec_new(m->name);
8646 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
8647 if (pat && g_pattern_match_string(pat, r->name)) {
8648 r->type = ARM_CP_CONST;
8649 r->access = PL0U_R;
8650 r->resetvalue = 0;
8651 /* continue */
8652 } else if (strcmp(r->name, m->name) == 0) {
8653 r->type = ARM_CP_CONST;
8654 r->access = PL0U_R;
8655 r->resetvalue &= m->exported_bits;
8656 r->resetvalue |= m->fixed_bits;
8657 break;
8660 if (pat) {
8661 g_pattern_spec_free(pat);
8666 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
8668 return g_hash_table_lookup(cpregs, &encoded_cp);
8671 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
8672 uint64_t value)
8674 /* Helper coprocessor write function for write-ignore registers */
8677 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
8679 /* Helper coprocessor write function for read-as-zero registers */
8680 return 0;
8683 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
8685 /* Helper coprocessor reset function for do-nothing-on-reset registers */
8688 static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
8690 /* Return true if it is not valid for us to switch to
8691 * this CPU mode (ie all the UNPREDICTABLE cases in
8692 * the ARM ARM CPSRWriteByInstr pseudocode).
8695 /* Changes to or from Hyp via MSR and CPS are illegal. */
8696 if (write_type == CPSRWriteByInstr &&
8697 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP ||
8698 mode == ARM_CPU_MODE_HYP)) {
8699 return 1;
8702 switch (mode) {
8703 case ARM_CPU_MODE_USR:
8704 return 0;
8705 case ARM_CPU_MODE_SYS:
8706 case ARM_CPU_MODE_SVC:
8707 case ARM_CPU_MODE_ABT:
8708 case ARM_CPU_MODE_UND:
8709 case ARM_CPU_MODE_IRQ:
8710 case ARM_CPU_MODE_FIQ:
8711 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
8712 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
8714 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
8715 * and CPS are treated as illegal mode changes.
8717 if (write_type == CPSRWriteByInstr &&
8718 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON &&
8719 (arm_hcr_el2_eff(env) & HCR_TGE)) {
8720 return 1;
8722 return 0;
8723 case ARM_CPU_MODE_HYP:
8724 return !arm_feature(env, ARM_FEATURE_EL2)
8725 || arm_current_el(env) < 2 || arm_is_secure_below_el3(env);
8726 case ARM_CPU_MODE_MON:
8727 return arm_current_el(env) < 3;
8728 default:
8729 return 1;
8733 uint32_t cpsr_read(CPUARMState *env)
8735 int ZF;
8736 ZF = (env->ZF == 0);
8737 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
8738 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
8739 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
8740 | ((env->condexec_bits & 0xfc) << 8)
8741 | (env->GE << 16) | (env->daif & CPSR_AIF);
8744 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
8745 CPSRWriteType write_type)
8747 uint32_t changed_daif;
8749 if (mask & CPSR_NZCV) {
8750 env->ZF = (~val) & CPSR_Z;
8751 env->NF = val;
8752 env->CF = (val >> 29) & 1;
8753 env->VF = (val << 3) & 0x80000000;
8755 if (mask & CPSR_Q)
8756 env->QF = ((val & CPSR_Q) != 0);
8757 if (mask & CPSR_T)
8758 env->thumb = ((val & CPSR_T) != 0);
8759 if (mask & CPSR_IT_0_1) {
8760 env->condexec_bits &= ~3;
8761 env->condexec_bits |= (val >> 25) & 3;
8763 if (mask & CPSR_IT_2_7) {
8764 env->condexec_bits &= 3;
8765 env->condexec_bits |= (val >> 8) & 0xfc;
8767 if (mask & CPSR_GE) {
8768 env->GE = (val >> 16) & 0xf;
8771 /* In a V7 implementation that includes the security extensions but does
8772 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
8773 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
8774 * bits respectively.
8776 * In a V8 implementation, it is permitted for privileged software to
8777 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
8779 if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) &&
8780 arm_feature(env, ARM_FEATURE_EL3) &&
8781 !arm_feature(env, ARM_FEATURE_EL2) &&
8782 !arm_is_secure(env)) {
8784 changed_daif = (env->daif ^ val) & mask;
8786 if (changed_daif & CPSR_A) {
8787 /* Check to see if we are allowed to change the masking of async
8788 * abort exceptions from a non-secure state.
8790 if (!(env->cp15.scr_el3 & SCR_AW)) {
8791 qemu_log_mask(LOG_GUEST_ERROR,
8792 "Ignoring attempt to switch CPSR_A flag from "
8793 "non-secure world with SCR.AW bit clear\n");
8794 mask &= ~CPSR_A;
8798 if (changed_daif & CPSR_F) {
8799 /* Check to see if we are allowed to change the masking of FIQ
8800 * exceptions from a non-secure state.
8802 if (!(env->cp15.scr_el3 & SCR_FW)) {
8803 qemu_log_mask(LOG_GUEST_ERROR,
8804 "Ignoring attempt to switch CPSR_F flag from "
8805 "non-secure world with SCR.FW bit clear\n");
8806 mask &= ~CPSR_F;
8809 /* Check whether non-maskable FIQ (NMFI) support is enabled.
8810 * If this bit is set software is not allowed to mask
8811 * FIQs, but is allowed to set CPSR_F to 0.
8813 if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
8814 (val & CPSR_F)) {
8815 qemu_log_mask(LOG_GUEST_ERROR,
8816 "Ignoring attempt to enable CPSR_F flag "
8817 "(non-maskable FIQ [NMFI] support enabled)\n");
8818 mask &= ~CPSR_F;
8823 env->daif &= ~(CPSR_AIF & mask);
8824 env->daif |= val & CPSR_AIF & mask;
8826 if (write_type != CPSRWriteRaw &&
8827 ((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
8828 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) {
8829 /* Note that we can only get here in USR mode if this is a
8830 * gdb stub write; for this case we follow the architectural
8831 * behaviour for guest writes in USR mode of ignoring an attempt
8832 * to switch mode. (Those are caught by translate.c for writes
8833 * triggered by guest instructions.)
8835 mask &= ~CPSR_M;
8836 } else if (bad_mode_switch(env, val & CPSR_M, write_type)) {
8837 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
8838 * v7, and has defined behaviour in v8:
8839 * + leave CPSR.M untouched
8840 * + allow changes to the other CPSR fields
8841 * + set PSTATE.IL
8842 * For user changes via the GDB stub, we don't set PSTATE.IL,
8843 * as this would be unnecessarily harsh for a user error.
8845 mask &= ~CPSR_M;
8846 if (write_type != CPSRWriteByGDBStub &&
8847 arm_feature(env, ARM_FEATURE_V8)) {
8848 mask |= CPSR_IL;
8849 val |= CPSR_IL;
8851 qemu_log_mask(LOG_GUEST_ERROR,
8852 "Illegal AArch32 mode switch attempt from %s to %s\n",
8853 aarch32_mode_name(env->uncached_cpsr),
8854 aarch32_mode_name(val));
8855 } else {
8856 qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n",
8857 write_type == CPSRWriteExceptionReturn ?
8858 "Exception return from AArch32" :
8859 "AArch32 mode switch from",
8860 aarch32_mode_name(env->uncached_cpsr),
8861 aarch32_mode_name(val), env->regs[15]);
8862 switch_mode(env, val & CPSR_M);
8865 mask &= ~CACHED_CPSR_BITS;
8866 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
8869 /* Sign/zero extend */
8870 uint32_t HELPER(sxtb16)(uint32_t x)
8872 uint32_t res;
8873 res = (uint16_t)(int8_t)x;
8874 res |= (uint32_t)(int8_t)(x >> 16) << 16;
8875 return res;
8878 uint32_t HELPER(uxtb16)(uint32_t x)
8880 uint32_t res;
8881 res = (uint16_t)(uint8_t)x;
8882 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
8883 return res;
8886 int32_t HELPER(sdiv)(int32_t num, int32_t den)
8888 if (den == 0)
8889 return 0;
8890 if (num == INT_MIN && den == -1)
8891 return INT_MIN;
8892 return num / den;
8895 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
8897 if (den == 0)
8898 return 0;
8899 return num / den;
8902 uint32_t HELPER(rbit)(uint32_t x)
8904 return revbit32(x);
8907 #ifdef CONFIG_USER_ONLY
8909 static void switch_mode(CPUARMState *env, int mode)
8911 ARMCPU *cpu = env_archcpu(env);
8913 if (mode != ARM_CPU_MODE_USR) {
8914 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
8918 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
8919 uint32_t cur_el, bool secure)
8921 return 1;
8924 void aarch64_sync_64_to_32(CPUARMState *env)
8926 g_assert_not_reached();
8929 #else
8931 static void switch_mode(CPUARMState *env, int mode)
8933 int old_mode;
8934 int i;
8936 old_mode = env->uncached_cpsr & CPSR_M;
8937 if (mode == old_mode)
8938 return;
8940 if (old_mode == ARM_CPU_MODE_FIQ) {
8941 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8942 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
8943 } else if (mode == ARM_CPU_MODE_FIQ) {
8944 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8945 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
8948 i = bank_number(old_mode);
8949 env->banked_r13[i] = env->regs[13];
8950 env->banked_spsr[i] = env->spsr;
8952 i = bank_number(mode);
8953 env->regs[13] = env->banked_r13[i];
8954 env->spsr = env->banked_spsr[i];
8956 env->banked_r14[r14_bank_number(old_mode)] = env->regs[14];
8957 env->regs[14] = env->banked_r14[r14_bank_number(mode)];
8960 /* Physical Interrupt Target EL Lookup Table
8962 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
8964 * The below multi-dimensional table is used for looking up the target
8965 * exception level given numerous condition criteria. Specifically, the
8966 * target EL is based on SCR and HCR routing controls as well as the
8967 * currently executing EL and secure state.
8969 * Dimensions:
8970 * target_el_table[2][2][2][2][2][4]
8971 * | | | | | +--- Current EL
8972 * | | | | +------ Non-secure(0)/Secure(1)
8973 * | | | +--------- HCR mask override
8974 * | | +------------ SCR exec state control
8975 * | +--------------- SCR mask override
8976 * +------------------ 32-bit(0)/64-bit(1) EL3
8978 * The table values are as such:
8979 * 0-3 = EL0-EL3
8980 * -1 = Cannot occur
8982 * The ARM ARM target EL table includes entries indicating that an "exception
8983 * is not taken". The two cases where this is applicable are:
8984 * 1) An exception is taken from EL3 but the SCR does not have the exception
8985 * routed to EL3.
8986 * 2) An exception is taken from EL2 but the HCR does not have the exception
8987 * routed to EL2.
8988 * In these two cases, the below table contain a target of EL1. This value is
8989 * returned as it is expected that the consumer of the table data will check
8990 * for "target EL >= current EL" to ensure the exception is not taken.
8992 * SCR HCR
8993 * 64 EA AMO From
8994 * BIT IRQ IMO Non-secure Secure
8995 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
8997 static const int8_t target_el_table[2][2][2][2][2][4] = {
8998 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
8999 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
9000 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9001 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
9002 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9003 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
9004 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9005 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
9006 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
9007 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
9008 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
9009 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
9010 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
9011 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
9012 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
9013 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
9017 * Determine the target EL for physical exceptions
9019 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
9020 uint32_t cur_el, bool secure)
9022 CPUARMState *env = cs->env_ptr;
9023 bool rw;
9024 bool scr;
9025 bool hcr;
9026 int target_el;
9027 /* Is the highest EL AArch64? */
9028 bool is64 = arm_feature(env, ARM_FEATURE_AARCH64);
9029 uint64_t hcr_el2;
9031 if (arm_feature(env, ARM_FEATURE_EL3)) {
9032 rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
9033 } else {
9034 /* Either EL2 is the highest EL (and so the EL2 register width
9035 * is given by is64); or there is no EL2 or EL3, in which case
9036 * the value of 'rw' does not affect the table lookup anyway.
9038 rw = is64;
9041 hcr_el2 = arm_hcr_el2_eff(env);
9042 switch (excp_idx) {
9043 case EXCP_IRQ:
9044 scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
9045 hcr = hcr_el2 & HCR_IMO;
9046 break;
9047 case EXCP_FIQ:
9048 scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
9049 hcr = hcr_el2 & HCR_FMO;
9050 break;
9051 default:
9052 scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
9053 hcr = hcr_el2 & HCR_AMO;
9054 break;
9058 * For these purposes, TGE and AMO/IMO/FMO both force the
9059 * interrupt to EL2. Fold TGE into the bit extracted above.
9061 hcr |= (hcr_el2 & HCR_TGE) != 0;
9063 /* Perform a table-lookup for the target EL given the current state */
9064 target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
9066 assert(target_el > 0);
9068 return target_el;
9071 void arm_log_exception(int idx)
9073 if (qemu_loglevel_mask(CPU_LOG_INT)) {
9074 const char *exc = NULL;
9075 static const char * const excnames[] = {
9076 [EXCP_UDEF] = "Undefined Instruction",
9077 [EXCP_SWI] = "SVC",
9078 [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
9079 [EXCP_DATA_ABORT] = "Data Abort",
9080 [EXCP_IRQ] = "IRQ",
9081 [EXCP_FIQ] = "FIQ",
9082 [EXCP_BKPT] = "Breakpoint",
9083 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
9084 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
9085 [EXCP_HVC] = "Hypervisor Call",
9086 [EXCP_HYP_TRAP] = "Hypervisor Trap",
9087 [EXCP_SMC] = "Secure Monitor Call",
9088 [EXCP_VIRQ] = "Virtual IRQ",
9089 [EXCP_VFIQ] = "Virtual FIQ",
9090 [EXCP_SEMIHOST] = "Semihosting call",
9091 [EXCP_NOCP] = "v7M NOCP UsageFault",
9092 [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
9093 [EXCP_STKOF] = "v8M STKOF UsageFault",
9094 [EXCP_LAZYFP] = "v7M exception during lazy FP stacking",
9095 [EXCP_LSERR] = "v8M LSERR UsageFault",
9096 [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
9099 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
9100 exc = excnames[idx];
9102 if (!exc) {
9103 exc = "unknown";
9105 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
9110 * Function used to synchronize QEMU's AArch64 register set with AArch32
9111 * register set. This is necessary when switching between AArch32 and AArch64
9112 * execution state.
9114 void aarch64_sync_32_to_64(CPUARMState *env)
9116 int i;
9117 uint32_t mode = env->uncached_cpsr & CPSR_M;
9119 /* We can blanket copy R[0:7] to X[0:7] */
9120 for (i = 0; i < 8; i++) {
9121 env->xregs[i] = env->regs[i];
9125 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
9126 * Otherwise, they come from the banked user regs.
9128 if (mode == ARM_CPU_MODE_FIQ) {
9129 for (i = 8; i < 13; i++) {
9130 env->xregs[i] = env->usr_regs[i - 8];
9132 } else {
9133 for (i = 8; i < 13; i++) {
9134 env->xregs[i] = env->regs[i];
9139 * Registers x13-x23 are the various mode SP and FP registers. Registers
9140 * r13 and r14 are only copied if we are in that mode, otherwise we copy
9141 * from the mode banked register.
9143 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
9144 env->xregs[13] = env->regs[13];
9145 env->xregs[14] = env->regs[14];
9146 } else {
9147 env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
9148 /* HYP is an exception in that it is copied from r14 */
9149 if (mode == ARM_CPU_MODE_HYP) {
9150 env->xregs[14] = env->regs[14];
9151 } else {
9152 env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)];
9156 if (mode == ARM_CPU_MODE_HYP) {
9157 env->xregs[15] = env->regs[13];
9158 } else {
9159 env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
9162 if (mode == ARM_CPU_MODE_IRQ) {
9163 env->xregs[16] = env->regs[14];
9164 env->xregs[17] = env->regs[13];
9165 } else {
9166 env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)];
9167 env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
9170 if (mode == ARM_CPU_MODE_SVC) {
9171 env->xregs[18] = env->regs[14];
9172 env->xregs[19] = env->regs[13];
9173 } else {
9174 env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)];
9175 env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
9178 if (mode == ARM_CPU_MODE_ABT) {
9179 env->xregs[20] = env->regs[14];
9180 env->xregs[21] = env->regs[13];
9181 } else {
9182 env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)];
9183 env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
9186 if (mode == ARM_CPU_MODE_UND) {
9187 env->xregs[22] = env->regs[14];
9188 env->xregs[23] = env->regs[13];
9189 } else {
9190 env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)];
9191 env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
9195 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9196 * mode, then we can copy from r8-r14. Otherwise, we copy from the
9197 * FIQ bank for r8-r14.
9199 if (mode == ARM_CPU_MODE_FIQ) {
9200 for (i = 24; i < 31; i++) {
9201 env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */
9203 } else {
9204 for (i = 24; i < 29; i++) {
9205 env->xregs[i] = env->fiq_regs[i - 24];
9207 env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
9208 env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)];
9211 env->pc = env->regs[15];
9215 * Function used to synchronize QEMU's AArch32 register set with AArch64
9216 * register set. This is necessary when switching between AArch32 and AArch64
9217 * execution state.
9219 void aarch64_sync_64_to_32(CPUARMState *env)
9221 int i;
9222 uint32_t mode = env->uncached_cpsr & CPSR_M;
9224 /* We can blanket copy X[0:7] to R[0:7] */
9225 for (i = 0; i < 8; i++) {
9226 env->regs[i] = env->xregs[i];
9230 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
9231 * Otherwise, we copy x8-x12 into the banked user regs.
9233 if (mode == ARM_CPU_MODE_FIQ) {
9234 for (i = 8; i < 13; i++) {
9235 env->usr_regs[i - 8] = env->xregs[i];
9237 } else {
9238 for (i = 8; i < 13; i++) {
9239 env->regs[i] = env->xregs[i];
9244 * Registers r13 & r14 depend on the current mode.
9245 * If we are in a given mode, we copy the corresponding x registers to r13
9246 * and r14. Otherwise, we copy the x register to the banked r13 and r14
9247 * for the mode.
9249 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
9250 env->regs[13] = env->xregs[13];
9251 env->regs[14] = env->xregs[14];
9252 } else {
9253 env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
9256 * HYP is an exception in that it does not have its own banked r14 but
9257 * shares the USR r14
9259 if (mode == ARM_CPU_MODE_HYP) {
9260 env->regs[14] = env->xregs[14];
9261 } else {
9262 env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
9266 if (mode == ARM_CPU_MODE_HYP) {
9267 env->regs[13] = env->xregs[15];
9268 } else {
9269 env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
9272 if (mode == ARM_CPU_MODE_IRQ) {
9273 env->regs[14] = env->xregs[16];
9274 env->regs[13] = env->xregs[17];
9275 } else {
9276 env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
9277 env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
9280 if (mode == ARM_CPU_MODE_SVC) {
9281 env->regs[14] = env->xregs[18];
9282 env->regs[13] = env->xregs[19];
9283 } else {
9284 env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
9285 env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
9288 if (mode == ARM_CPU_MODE_ABT) {
9289 env->regs[14] = env->xregs[20];
9290 env->regs[13] = env->xregs[21];
9291 } else {
9292 env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
9293 env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
9296 if (mode == ARM_CPU_MODE_UND) {
9297 env->regs[14] = env->xregs[22];
9298 env->regs[13] = env->xregs[23];
9299 } else {
9300 env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
9301 env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
9304 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9305 * mode, then we can copy to r8-r14. Otherwise, we copy to the
9306 * FIQ bank for r8-r14.
9308 if (mode == ARM_CPU_MODE_FIQ) {
9309 for (i = 24; i < 31; i++) {
9310 env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */
9312 } else {
9313 for (i = 24; i < 29; i++) {
9314 env->fiq_regs[i - 24] = env->xregs[i];
9316 env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
9317 env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
9320 env->regs[15] = env->pc;
9323 static void take_aarch32_exception(CPUARMState *env, int new_mode,
9324 uint32_t mask, uint32_t offset,
9325 uint32_t newpc)
9327 int new_el;
9329 /* Change the CPU state so as to actually take the exception. */
9330 switch_mode(env, new_mode);
9333 * For exceptions taken to AArch32 we must clear the SS bit in both
9334 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
9336 env->uncached_cpsr &= ~PSTATE_SS;
9337 env->spsr = cpsr_read(env);
9338 /* Clear IT bits. */
9339 env->condexec_bits = 0;
9340 /* Switch to the new mode, and to the correct instruction set. */
9341 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
9343 /* This must be after mode switching. */
9344 new_el = arm_current_el(env);
9346 /* Set new mode endianness */
9347 env->uncached_cpsr &= ~CPSR_E;
9348 if (env->cp15.sctlr_el[new_el] & SCTLR_EE) {
9349 env->uncached_cpsr |= CPSR_E;
9351 /* J and IL must always be cleared for exception entry */
9352 env->uncached_cpsr &= ~(CPSR_IL | CPSR_J);
9353 env->daif |= mask;
9355 if (new_mode == ARM_CPU_MODE_HYP) {
9356 env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0;
9357 env->elr_el[2] = env->regs[15];
9358 } else {
9359 /* CPSR.PAN is normally preserved preserved unless... */
9360 if (cpu_isar_feature(aa32_pan, env_archcpu(env))) {
9361 switch (new_el) {
9362 case 3:
9363 if (!arm_is_secure_below_el3(env)) {
9364 /* ... the target is EL3, from non-secure state. */
9365 env->uncached_cpsr &= ~CPSR_PAN;
9366 break;
9368 /* ... the target is EL3, from secure state ... */
9369 /* fall through */
9370 case 1:
9371 /* ... the target is EL1 and SCTLR.SPAN is 0. */
9372 if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) {
9373 env->uncached_cpsr |= CPSR_PAN;
9375 break;
9379 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
9380 * and we should just guard the thumb mode on V4
9382 if (arm_feature(env, ARM_FEATURE_V4T)) {
9383 env->thumb =
9384 (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
9386 env->regs[14] = env->regs[15] + offset;
9388 env->regs[15] = newpc;
9389 arm_rebuild_hflags(env);
9392 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs)
9395 * Handle exception entry to Hyp mode; this is sufficiently
9396 * different to entry to other AArch32 modes that we handle it
9397 * separately here.
9399 * The vector table entry used is always the 0x14 Hyp mode entry point,
9400 * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp.
9401 * The offset applied to the preferred return address is always zero
9402 * (see DDI0487C.a section G1.12.3).
9403 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
9405 uint32_t addr, mask;
9406 ARMCPU *cpu = ARM_CPU(cs);
9407 CPUARMState *env = &cpu->env;
9409 switch (cs->exception_index) {
9410 case EXCP_UDEF:
9411 addr = 0x04;
9412 break;
9413 case EXCP_SWI:
9414 addr = 0x14;
9415 break;
9416 case EXCP_BKPT:
9417 /* Fall through to prefetch abort. */
9418 case EXCP_PREFETCH_ABORT:
9419 env->cp15.ifar_s = env->exception.vaddress;
9420 qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n",
9421 (uint32_t)env->exception.vaddress);
9422 addr = 0x0c;
9423 break;
9424 case EXCP_DATA_ABORT:
9425 env->cp15.dfar_s = env->exception.vaddress;
9426 qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n",
9427 (uint32_t)env->exception.vaddress);
9428 addr = 0x10;
9429 break;
9430 case EXCP_IRQ:
9431 addr = 0x18;
9432 break;
9433 case EXCP_FIQ:
9434 addr = 0x1c;
9435 break;
9436 case EXCP_HVC:
9437 addr = 0x08;
9438 break;
9439 case EXCP_HYP_TRAP:
9440 addr = 0x14;
9441 break;
9442 default:
9443 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
9446 if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) {
9447 if (!arm_feature(env, ARM_FEATURE_V8)) {
9449 * QEMU syndrome values are v8-style. v7 has the IL bit
9450 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
9451 * If this is a v7 CPU, squash the IL bit in those cases.
9453 if (cs->exception_index == EXCP_PREFETCH_ABORT ||
9454 (cs->exception_index == EXCP_DATA_ABORT &&
9455 !(env->exception.syndrome & ARM_EL_ISV)) ||
9456 syn_get_ec(env->exception.syndrome) == EC_UNCATEGORIZED) {
9457 env->exception.syndrome &= ~ARM_EL_IL;
9460 env->cp15.esr_el[2] = env->exception.syndrome;
9463 if (arm_current_el(env) != 2 && addr < 0x14) {
9464 addr = 0x14;
9467 mask = 0;
9468 if (!(env->cp15.scr_el3 & SCR_EA)) {
9469 mask |= CPSR_A;
9471 if (!(env->cp15.scr_el3 & SCR_IRQ)) {
9472 mask |= CPSR_I;
9474 if (!(env->cp15.scr_el3 & SCR_FIQ)) {
9475 mask |= CPSR_F;
9478 addr += env->cp15.hvbar;
9480 take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr);
9483 static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
9485 ARMCPU *cpu = ARM_CPU(cs);
9486 CPUARMState *env = &cpu->env;
9487 uint32_t addr;
9488 uint32_t mask;
9489 int new_mode;
9490 uint32_t offset;
9491 uint32_t moe;
9493 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
9494 switch (syn_get_ec(env->exception.syndrome)) {
9495 case EC_BREAKPOINT:
9496 case EC_BREAKPOINT_SAME_EL:
9497 moe = 1;
9498 break;
9499 case EC_WATCHPOINT:
9500 case EC_WATCHPOINT_SAME_EL:
9501 moe = 10;
9502 break;
9503 case EC_AA32_BKPT:
9504 moe = 3;
9505 break;
9506 case EC_VECTORCATCH:
9507 moe = 5;
9508 break;
9509 default:
9510 moe = 0;
9511 break;
9514 if (moe) {
9515 env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
9518 if (env->exception.target_el == 2) {
9519 arm_cpu_do_interrupt_aarch32_hyp(cs);
9520 return;
9523 switch (cs->exception_index) {
9524 case EXCP_UDEF:
9525 new_mode = ARM_CPU_MODE_UND;
9526 addr = 0x04;
9527 mask = CPSR_I;
9528 if (env->thumb)
9529 offset = 2;
9530 else
9531 offset = 4;
9532 break;
9533 case EXCP_SWI:
9534 new_mode = ARM_CPU_MODE_SVC;
9535 addr = 0x08;
9536 mask = CPSR_I;
9537 /* The PC already points to the next instruction. */
9538 offset = 0;
9539 break;
9540 case EXCP_BKPT:
9541 /* Fall through to prefetch abort. */
9542 case EXCP_PREFETCH_ABORT:
9543 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
9544 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
9545 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
9546 env->exception.fsr, (uint32_t)env->exception.vaddress);
9547 new_mode = ARM_CPU_MODE_ABT;
9548 addr = 0x0c;
9549 mask = CPSR_A | CPSR_I;
9550 offset = 4;
9551 break;
9552 case EXCP_DATA_ABORT:
9553 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
9554 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
9555 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
9556 env->exception.fsr,
9557 (uint32_t)env->exception.vaddress);
9558 new_mode = ARM_CPU_MODE_ABT;
9559 addr = 0x10;
9560 mask = CPSR_A | CPSR_I;
9561 offset = 8;
9562 break;
9563 case EXCP_IRQ:
9564 new_mode = ARM_CPU_MODE_IRQ;
9565 addr = 0x18;
9566 /* Disable IRQ and imprecise data aborts. */
9567 mask = CPSR_A | CPSR_I;
9568 offset = 4;
9569 if (env->cp15.scr_el3 & SCR_IRQ) {
9570 /* IRQ routed to monitor mode */
9571 new_mode = ARM_CPU_MODE_MON;
9572 mask |= CPSR_F;
9574 break;
9575 case EXCP_FIQ:
9576 new_mode = ARM_CPU_MODE_FIQ;
9577 addr = 0x1c;
9578 /* Disable FIQ, IRQ and imprecise data aborts. */
9579 mask = CPSR_A | CPSR_I | CPSR_F;
9580 if (env->cp15.scr_el3 & SCR_FIQ) {
9581 /* FIQ routed to monitor mode */
9582 new_mode = ARM_CPU_MODE_MON;
9584 offset = 4;
9585 break;
9586 case EXCP_VIRQ:
9587 new_mode = ARM_CPU_MODE_IRQ;
9588 addr = 0x18;
9589 /* Disable IRQ and imprecise data aborts. */
9590 mask = CPSR_A | CPSR_I;
9591 offset = 4;
9592 break;
9593 case EXCP_VFIQ:
9594 new_mode = ARM_CPU_MODE_FIQ;
9595 addr = 0x1c;
9596 /* Disable FIQ, IRQ and imprecise data aborts. */
9597 mask = CPSR_A | CPSR_I | CPSR_F;
9598 offset = 4;
9599 break;
9600 case EXCP_SMC:
9601 new_mode = ARM_CPU_MODE_MON;
9602 addr = 0x08;
9603 mask = CPSR_A | CPSR_I | CPSR_F;
9604 offset = 0;
9605 break;
9606 default:
9607 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
9608 return; /* Never happens. Keep compiler happy. */
9611 if (new_mode == ARM_CPU_MODE_MON) {
9612 addr += env->cp15.mvbar;
9613 } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
9614 /* High vectors. When enabled, base address cannot be remapped. */
9615 addr += 0xffff0000;
9616 } else {
9617 /* ARM v7 architectures provide a vector base address register to remap
9618 * the interrupt vector table.
9619 * This register is only followed in non-monitor mode, and is banked.
9620 * Note: only bits 31:5 are valid.
9622 addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
9625 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
9626 env->cp15.scr_el3 &= ~SCR_NS;
9629 take_aarch32_exception(env, new_mode, mask, offset, addr);
9632 static int aarch64_regnum(CPUARMState *env, int aarch32_reg)
9635 * Return the register number of the AArch64 view of the AArch32
9636 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
9637 * be that of the AArch32 mode the exception came from.
9639 int mode = env->uncached_cpsr & CPSR_M;
9641 switch (aarch32_reg) {
9642 case 0 ... 7:
9643 return aarch32_reg;
9644 case 8 ... 12:
9645 return mode == ARM_CPU_MODE_FIQ ? aarch32_reg + 16 : aarch32_reg;
9646 case 13:
9647 switch (mode) {
9648 case ARM_CPU_MODE_USR:
9649 case ARM_CPU_MODE_SYS:
9650 return 13;
9651 case ARM_CPU_MODE_HYP:
9652 return 15;
9653 case ARM_CPU_MODE_IRQ:
9654 return 17;
9655 case ARM_CPU_MODE_SVC:
9656 return 19;
9657 case ARM_CPU_MODE_ABT:
9658 return 21;
9659 case ARM_CPU_MODE_UND:
9660 return 23;
9661 case ARM_CPU_MODE_FIQ:
9662 return 29;
9663 default:
9664 g_assert_not_reached();
9666 case 14:
9667 switch (mode) {
9668 case ARM_CPU_MODE_USR:
9669 case ARM_CPU_MODE_SYS:
9670 case ARM_CPU_MODE_HYP:
9671 return 14;
9672 case ARM_CPU_MODE_IRQ:
9673 return 16;
9674 case ARM_CPU_MODE_SVC:
9675 return 18;
9676 case ARM_CPU_MODE_ABT:
9677 return 20;
9678 case ARM_CPU_MODE_UND:
9679 return 22;
9680 case ARM_CPU_MODE_FIQ:
9681 return 30;
9682 default:
9683 g_assert_not_reached();
9685 case 15:
9686 return 31;
9687 default:
9688 g_assert_not_reached();
9692 /* Handle exception entry to a target EL which is using AArch64 */
9693 static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
9695 ARMCPU *cpu = ARM_CPU(cs);
9696 CPUARMState *env = &cpu->env;
9697 unsigned int new_el = env->exception.target_el;
9698 target_ulong addr = env->cp15.vbar_el[new_el];
9699 unsigned int new_mode = aarch64_pstate_mode(new_el, true);
9700 unsigned int old_mode;
9701 unsigned int cur_el = arm_current_el(env);
9702 int rt;
9705 * Note that new_el can never be 0. If cur_el is 0, then
9706 * el0_a64 is is_a64(), else el0_a64 is ignored.
9708 aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
9710 if (cur_el < new_el) {
9711 /* Entry vector offset depends on whether the implemented EL
9712 * immediately lower than the target level is using AArch32 or AArch64
9714 bool is_aa64;
9715 uint64_t hcr;
9717 switch (new_el) {
9718 case 3:
9719 is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0;
9720 break;
9721 case 2:
9722 hcr = arm_hcr_el2_eff(env);
9723 if ((hcr & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
9724 is_aa64 = (hcr & HCR_RW) != 0;
9725 break;
9727 /* fall through */
9728 case 1:
9729 is_aa64 = is_a64(env);
9730 break;
9731 default:
9732 g_assert_not_reached();
9735 if (is_aa64) {
9736 addr += 0x400;
9737 } else {
9738 addr += 0x600;
9740 } else if (pstate_read(env) & PSTATE_SP) {
9741 addr += 0x200;
9744 switch (cs->exception_index) {
9745 case EXCP_PREFETCH_ABORT:
9746 case EXCP_DATA_ABORT:
9747 env->cp15.far_el[new_el] = env->exception.vaddress;
9748 qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
9749 env->cp15.far_el[new_el]);
9750 /* fall through */
9751 case EXCP_BKPT:
9752 case EXCP_UDEF:
9753 case EXCP_SWI:
9754 case EXCP_HVC:
9755 case EXCP_HYP_TRAP:
9756 case EXCP_SMC:
9757 switch (syn_get_ec(env->exception.syndrome)) {
9758 case EC_ADVSIMDFPACCESSTRAP:
9760 * QEMU internal FP/SIMD syndromes from AArch32 include the
9761 * TA and coproc fields which are only exposed if the exception
9762 * is taken to AArch32 Hyp mode. Mask them out to get a valid
9763 * AArch64 format syndrome.
9765 env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20);
9766 break;
9767 case EC_CP14RTTRAP:
9768 case EC_CP15RTTRAP:
9769 case EC_CP14DTTRAP:
9771 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
9772 * the raw register field from the insn; when taking this to
9773 * AArch64 we must convert it to the AArch64 view of the register
9774 * number. Notice that we read a 4-bit AArch32 register number and
9775 * write back a 5-bit AArch64 one.
9777 rt = extract32(env->exception.syndrome, 5, 4);
9778 rt = aarch64_regnum(env, rt);
9779 env->exception.syndrome = deposit32(env->exception.syndrome,
9780 5, 5, rt);
9781 break;
9782 case EC_CP15RRTTRAP:
9783 case EC_CP14RRTTRAP:
9784 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
9785 rt = extract32(env->exception.syndrome, 5, 4);
9786 rt = aarch64_regnum(env, rt);
9787 env->exception.syndrome = deposit32(env->exception.syndrome,
9788 5, 5, rt);
9789 rt = extract32(env->exception.syndrome, 10, 4);
9790 rt = aarch64_regnum(env, rt);
9791 env->exception.syndrome = deposit32(env->exception.syndrome,
9792 10, 5, rt);
9793 break;
9795 env->cp15.esr_el[new_el] = env->exception.syndrome;
9796 break;
9797 case EXCP_IRQ:
9798 case EXCP_VIRQ:
9799 addr += 0x80;
9800 break;
9801 case EXCP_FIQ:
9802 case EXCP_VFIQ:
9803 addr += 0x100;
9804 break;
9805 default:
9806 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
9809 if (is_a64(env)) {
9810 old_mode = pstate_read(env);
9811 aarch64_save_sp(env, arm_current_el(env));
9812 env->elr_el[new_el] = env->pc;
9813 } else {
9814 old_mode = cpsr_read(env);
9815 env->elr_el[new_el] = env->regs[15];
9817 aarch64_sync_32_to_64(env);
9819 env->condexec_bits = 0;
9821 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode;
9823 qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
9824 env->elr_el[new_el]);
9826 if (cpu_isar_feature(aa64_pan, cpu)) {
9827 /* The value of PSTATE.PAN is normally preserved, except when ... */
9828 new_mode |= old_mode & PSTATE_PAN;
9829 switch (new_el) {
9830 case 2:
9831 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
9832 if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE))
9833 != (HCR_E2H | HCR_TGE)) {
9834 break;
9836 /* fall through */
9837 case 1:
9838 /* ... the target is EL1 ... */
9839 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
9840 if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) == 0) {
9841 new_mode |= PSTATE_PAN;
9843 break;
9846 if (cpu_isar_feature(aa64_mte, cpu)) {
9847 new_mode |= PSTATE_TCO;
9850 pstate_write(env, PSTATE_DAIF | new_mode);
9851 env->aarch64 = 1;
9852 aarch64_restore_sp(env, new_el);
9853 helper_rebuild_hflags_a64(env, new_el);
9855 env->pc = addr;
9857 qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n",
9858 new_el, env->pc, pstate_read(env));
9862 * Do semihosting call and set the appropriate return value. All the
9863 * permission and validity checks have been done at translate time.
9865 * We only see semihosting exceptions in TCG only as they are not
9866 * trapped to the hypervisor in KVM.
9868 #ifdef CONFIG_TCG
9869 static void handle_semihosting(CPUState *cs)
9871 ARMCPU *cpu = ARM_CPU(cs);
9872 CPUARMState *env = &cpu->env;
9874 if (is_a64(env)) {
9875 qemu_log_mask(CPU_LOG_INT,
9876 "...handling as semihosting call 0x%" PRIx64 "\n",
9877 env->xregs[0]);
9878 env->xregs[0] = do_arm_semihosting(env);
9879 env->pc += 4;
9880 } else {
9881 qemu_log_mask(CPU_LOG_INT,
9882 "...handling as semihosting call 0x%x\n",
9883 env->regs[0]);
9884 env->regs[0] = do_arm_semihosting(env);
9885 env->regs[15] += env->thumb ? 2 : 4;
9888 #endif
9890 /* Handle a CPU exception for A and R profile CPUs.
9891 * Do any appropriate logging, handle PSCI calls, and then hand off
9892 * to the AArch64-entry or AArch32-entry function depending on the
9893 * target exception level's register width.
9895 void arm_cpu_do_interrupt(CPUState *cs)
9897 ARMCPU *cpu = ARM_CPU(cs);
9898 CPUARMState *env = &cpu->env;
9899 unsigned int new_el = env->exception.target_el;
9901 assert(!arm_feature(env, ARM_FEATURE_M));
9903 arm_log_exception(cs->exception_index);
9904 qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env),
9905 new_el);
9906 if (qemu_loglevel_mask(CPU_LOG_INT)
9907 && !excp_is_internal(cs->exception_index)) {
9908 qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n",
9909 syn_get_ec(env->exception.syndrome),
9910 env->exception.syndrome);
9913 if (arm_is_psci_call(cpu, cs->exception_index)) {
9914 arm_handle_psci_call(cpu);
9915 qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
9916 return;
9920 * Semihosting semantics depend on the register width of the code
9921 * that caused the exception, not the target exception level, so
9922 * must be handled here.
9924 #ifdef CONFIG_TCG
9925 if (cs->exception_index == EXCP_SEMIHOST) {
9926 handle_semihosting(cs);
9927 return;
9929 #endif
9931 /* Hooks may change global state so BQL should be held, also the
9932 * BQL needs to be held for any modification of
9933 * cs->interrupt_request.
9935 g_assert(qemu_mutex_iothread_locked());
9937 arm_call_pre_el_change_hook(cpu);
9939 assert(!excp_is_internal(cs->exception_index));
9940 if (arm_el_is_aa64(env, new_el)) {
9941 arm_cpu_do_interrupt_aarch64(cs);
9942 } else {
9943 arm_cpu_do_interrupt_aarch32(cs);
9946 arm_call_el_change_hook(cpu);
9948 if (!kvm_enabled()) {
9949 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
9952 #endif /* !CONFIG_USER_ONLY */
9954 uint64_t arm_sctlr(CPUARMState *env, int el)
9956 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
9957 if (el == 0) {
9958 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0);
9959 el = (mmu_idx == ARMMMUIdx_E20_0 ? 2 : 1);
9961 return env->cp15.sctlr_el[el];
9964 /* Return the SCTLR value which controls this address translation regime */
9965 static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
9967 return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
9970 #ifndef CONFIG_USER_ONLY
9972 /* Return true if the specified stage of address translation is disabled */
9973 static inline bool regime_translation_disabled(CPUARMState *env,
9974 ARMMMUIdx mmu_idx)
9976 if (arm_feature(env, ARM_FEATURE_M)) {
9977 switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] &
9978 (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) {
9979 case R_V7M_MPU_CTRL_ENABLE_MASK:
9980 /* Enabled, but not for HardFault and NMI */
9981 return mmu_idx & ARM_MMU_IDX_M_NEGPRI;
9982 case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK:
9983 /* Enabled for all cases */
9984 return false;
9985 case 0:
9986 default:
9987 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
9988 * we warned about that in armv7m_nvic.c when the guest set it.
9990 return true;
9994 if (mmu_idx == ARMMMUIdx_Stage2) {
9995 /* HCR.DC means HCR.VM behaves as 1 */
9996 return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) == 0;
9999 if (env->cp15.hcr_el2 & HCR_TGE) {
10000 /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
10001 if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) {
10002 return true;
10006 if ((env->cp15.hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) {
10007 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
10008 return true;
10011 return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
10014 static inline bool regime_translation_big_endian(CPUARMState *env,
10015 ARMMMUIdx mmu_idx)
10017 return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0;
10020 /* Return the TTBR associated with this translation regime */
10021 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
10022 int ttbrn)
10024 if (mmu_idx == ARMMMUIdx_Stage2) {
10025 return env->cp15.vttbr_el2;
10027 if (ttbrn == 0) {
10028 return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
10029 } else {
10030 return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
10034 #endif /* !CONFIG_USER_ONLY */
10036 /* Convert a possible stage1+2 MMU index into the appropriate
10037 * stage 1 MMU index
10039 static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
10041 switch (mmu_idx) {
10042 case ARMMMUIdx_E10_0:
10043 return ARMMMUIdx_Stage1_E0;
10044 case ARMMMUIdx_E10_1:
10045 return ARMMMUIdx_Stage1_E1;
10046 case ARMMMUIdx_E10_1_PAN:
10047 return ARMMMUIdx_Stage1_E1_PAN;
10048 default:
10049 return mmu_idx;
10053 /* Return true if the translation regime is using LPAE format page tables */
10054 static inline bool regime_using_lpae_format(CPUARMState *env,
10055 ARMMMUIdx mmu_idx)
10057 int el = regime_el(env, mmu_idx);
10058 if (el == 2 || arm_el_is_aa64(env, el)) {
10059 return true;
10061 if (arm_feature(env, ARM_FEATURE_LPAE)
10062 && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
10063 return true;
10065 return false;
10068 /* Returns true if the stage 1 translation regime is using LPAE format page
10069 * tables. Used when raising alignment exceptions, whose FSR changes depending
10070 * on whether the long or short descriptor format is in use. */
10071 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
10073 mmu_idx = stage_1_mmu_idx(mmu_idx);
10075 return regime_using_lpae_format(env, mmu_idx);
10078 #ifndef CONFIG_USER_ONLY
10079 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
10081 switch (mmu_idx) {
10082 case ARMMMUIdx_SE10_0:
10083 case ARMMMUIdx_E20_0:
10084 case ARMMMUIdx_Stage1_E0:
10085 case ARMMMUIdx_MUser:
10086 case ARMMMUIdx_MSUser:
10087 case ARMMMUIdx_MUserNegPri:
10088 case ARMMMUIdx_MSUserNegPri:
10089 return true;
10090 default:
10091 return false;
10092 case ARMMMUIdx_E10_0:
10093 case ARMMMUIdx_E10_1:
10094 case ARMMMUIdx_E10_1_PAN:
10095 g_assert_not_reached();
10099 /* Translate section/page access permissions to page
10100 * R/W protection flags
10102 * @env: CPUARMState
10103 * @mmu_idx: MMU index indicating required translation regime
10104 * @ap: The 3-bit access permissions (AP[2:0])
10105 * @domain_prot: The 2-bit domain access permissions
10107 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
10108 int ap, int domain_prot)
10110 bool is_user = regime_is_user(env, mmu_idx);
10112 if (domain_prot == 3) {
10113 return PAGE_READ | PAGE_WRITE;
10116 switch (ap) {
10117 case 0:
10118 if (arm_feature(env, ARM_FEATURE_V7)) {
10119 return 0;
10121 switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
10122 case SCTLR_S:
10123 return is_user ? 0 : PAGE_READ;
10124 case SCTLR_R:
10125 return PAGE_READ;
10126 default:
10127 return 0;
10129 case 1:
10130 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
10131 case 2:
10132 if (is_user) {
10133 return PAGE_READ;
10134 } else {
10135 return PAGE_READ | PAGE_WRITE;
10137 case 3:
10138 return PAGE_READ | PAGE_WRITE;
10139 case 4: /* Reserved. */
10140 return 0;
10141 case 5:
10142 return is_user ? 0 : PAGE_READ;
10143 case 6:
10144 return PAGE_READ;
10145 case 7:
10146 if (!arm_feature(env, ARM_FEATURE_V6K)) {
10147 return 0;
10149 return PAGE_READ;
10150 default:
10151 g_assert_not_reached();
10155 /* Translate section/page access permissions to page
10156 * R/W protection flags.
10158 * @ap: The 2-bit simple AP (AP[2:1])
10159 * @is_user: TRUE if accessing from PL0
10161 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
10163 switch (ap) {
10164 case 0:
10165 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
10166 case 1:
10167 return PAGE_READ | PAGE_WRITE;
10168 case 2:
10169 return is_user ? 0 : PAGE_READ;
10170 case 3:
10171 return PAGE_READ;
10172 default:
10173 g_assert_not_reached();
10177 static inline int
10178 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
10180 return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
10183 /* Translate S2 section/page access permissions to protection flags
10185 * @env: CPUARMState
10186 * @s2ap: The 2-bit stage2 access permissions (S2AP)
10187 * @xn: XN (execute-never) bits
10188 * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0
10190 static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0)
10192 int prot = 0;
10194 if (s2ap & 1) {
10195 prot |= PAGE_READ;
10197 if (s2ap & 2) {
10198 prot |= PAGE_WRITE;
10201 if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) {
10202 switch (xn) {
10203 case 0:
10204 prot |= PAGE_EXEC;
10205 break;
10206 case 1:
10207 if (s1_is_el0) {
10208 prot |= PAGE_EXEC;
10210 break;
10211 case 2:
10212 break;
10213 case 3:
10214 if (!s1_is_el0) {
10215 prot |= PAGE_EXEC;
10217 break;
10218 default:
10219 g_assert_not_reached();
10221 } else {
10222 if (!extract32(xn, 1, 1)) {
10223 if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {
10224 prot |= PAGE_EXEC;
10228 return prot;
10231 /* Translate section/page access permissions to protection flags
10233 * @env: CPUARMState
10234 * @mmu_idx: MMU index indicating required translation regime
10235 * @is_aa64: TRUE if AArch64
10236 * @ap: The 2-bit simple AP (AP[2:1])
10237 * @ns: NS (non-secure) bit
10238 * @xn: XN (execute-never) bit
10239 * @pxn: PXN (privileged execute-never) bit
10241 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
10242 int ap, int ns, int xn, int pxn)
10244 bool is_user = regime_is_user(env, mmu_idx);
10245 int prot_rw, user_rw;
10246 bool have_wxn;
10247 int wxn = 0;
10249 assert(mmu_idx != ARMMMUIdx_Stage2);
10251 user_rw = simple_ap_to_rw_prot_is_user(ap, true);
10252 if (is_user) {
10253 prot_rw = user_rw;
10254 } else {
10255 if (user_rw && regime_is_pan(env, mmu_idx)) {
10256 /* PAN forbids data accesses but doesn't affect insn fetch */
10257 prot_rw = 0;
10258 } else {
10259 prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
10263 if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
10264 return prot_rw;
10267 /* TODO have_wxn should be replaced with
10268 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
10269 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
10270 * compatible processors have EL2, which is required for [U]WXN.
10272 have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
10274 if (have_wxn) {
10275 wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
10278 if (is_aa64) {
10279 if (regime_has_2_ranges(mmu_idx) && !is_user) {
10280 xn = pxn || (user_rw & PAGE_WRITE);
10282 } else if (arm_feature(env, ARM_FEATURE_V7)) {
10283 switch (regime_el(env, mmu_idx)) {
10284 case 1:
10285 case 3:
10286 if (is_user) {
10287 xn = xn || !(user_rw & PAGE_READ);
10288 } else {
10289 int uwxn = 0;
10290 if (have_wxn) {
10291 uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
10293 xn = xn || !(prot_rw & PAGE_READ) || pxn ||
10294 (uwxn && (user_rw & PAGE_WRITE));
10296 break;
10297 case 2:
10298 break;
10300 } else {
10301 xn = wxn = 0;
10304 if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
10305 return prot_rw;
10307 return prot_rw | PAGE_EXEC;
10310 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
10311 uint32_t *table, uint32_t address)
10313 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
10314 TCR *tcr = regime_tcr(env, mmu_idx);
10316 if (address & tcr->mask) {
10317 if (tcr->raw_tcr & TTBCR_PD1) {
10318 /* Translation table walk disabled for TTBR1 */
10319 return false;
10321 *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
10322 } else {
10323 if (tcr->raw_tcr & TTBCR_PD0) {
10324 /* Translation table walk disabled for TTBR0 */
10325 return false;
10327 *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
10329 *table |= (address >> 18) & 0x3ffc;
10330 return true;
10333 /* Translate a S1 pagetable walk through S2 if needed. */
10334 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
10335 hwaddr addr, MemTxAttrs txattrs,
10336 ARMMMUFaultInfo *fi)
10338 if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
10339 !regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
10340 target_ulong s2size;
10341 hwaddr s2pa;
10342 int s2prot;
10343 int ret;
10344 ARMCacheAttrs cacheattrs = {};
10346 ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2,
10347 false,
10348 &s2pa, &txattrs, &s2prot, &s2size, fi,
10349 &cacheattrs);
10350 if (ret) {
10351 assert(fi->type != ARMFault_None);
10352 fi->s2addr = addr;
10353 fi->stage2 = true;
10354 fi->s1ptw = true;
10355 return ~0;
10357 if ((env->cp15.hcr_el2 & HCR_PTW) && (cacheattrs.attrs & 0xf0) == 0) {
10359 * PTW set and S1 walk touched S2 Device memory:
10360 * generate Permission fault.
10362 fi->type = ARMFault_Permission;
10363 fi->s2addr = addr;
10364 fi->stage2 = true;
10365 fi->s1ptw = true;
10366 return ~0;
10368 addr = s2pa;
10370 return addr;
10373 /* All loads done in the course of a page table walk go through here. */
10374 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
10375 ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
10377 ARMCPU *cpu = ARM_CPU(cs);
10378 CPUARMState *env = &cpu->env;
10379 MemTxAttrs attrs = {};
10380 MemTxResult result = MEMTX_OK;
10381 AddressSpace *as;
10382 uint32_t data;
10384 attrs.secure = is_secure;
10385 as = arm_addressspace(cs, attrs);
10386 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi);
10387 if (fi->s1ptw) {
10388 return 0;
10390 if (regime_translation_big_endian(env, mmu_idx)) {
10391 data = address_space_ldl_be(as, addr, attrs, &result);
10392 } else {
10393 data = address_space_ldl_le(as, addr, attrs, &result);
10395 if (result == MEMTX_OK) {
10396 return data;
10398 fi->type = ARMFault_SyncExternalOnWalk;
10399 fi->ea = arm_extabort_type(result);
10400 return 0;
10403 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
10404 ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
10406 ARMCPU *cpu = ARM_CPU(cs);
10407 CPUARMState *env = &cpu->env;
10408 MemTxAttrs attrs = {};
10409 MemTxResult result = MEMTX_OK;
10410 AddressSpace *as;
10411 uint64_t data;
10413 attrs.secure = is_secure;
10414 as = arm_addressspace(cs, attrs);
10415 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi);
10416 if (fi->s1ptw) {
10417 return 0;
10419 if (regime_translation_big_endian(env, mmu_idx)) {
10420 data = address_space_ldq_be(as, addr, attrs, &result);
10421 } else {
10422 data = address_space_ldq_le(as, addr, attrs, &result);
10424 if (result == MEMTX_OK) {
10425 return data;
10427 fi->type = ARMFault_SyncExternalOnWalk;
10428 fi->ea = arm_extabort_type(result);
10429 return 0;
10432 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
10433 MMUAccessType access_type, ARMMMUIdx mmu_idx,
10434 hwaddr *phys_ptr, int *prot,
10435 target_ulong *page_size,
10436 ARMMMUFaultInfo *fi)
10438 CPUState *cs = env_cpu(env);
10439 int level = 1;
10440 uint32_t table;
10441 uint32_t desc;
10442 int type;
10443 int ap;
10444 int domain = 0;
10445 int domain_prot;
10446 hwaddr phys_addr;
10447 uint32_t dacr;
10449 /* Pagetable walk. */
10450 /* Lookup l1 descriptor. */
10451 if (!get_level1_table_address(env, mmu_idx, &table, address)) {
10452 /* Section translation fault if page walk is disabled by PD0 or PD1 */
10453 fi->type = ARMFault_Translation;
10454 goto do_fault;
10456 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
10457 mmu_idx, fi);
10458 if (fi->type != ARMFault_None) {
10459 goto do_fault;
10461 type = (desc & 3);
10462 domain = (desc >> 5) & 0x0f;
10463 if (regime_el(env, mmu_idx) == 1) {
10464 dacr = env->cp15.dacr_ns;
10465 } else {
10466 dacr = env->cp15.dacr_s;
10468 domain_prot = (dacr >> (domain * 2)) & 3;
10469 if (type == 0) {
10470 /* Section translation fault. */
10471 fi->type = ARMFault_Translation;
10472 goto do_fault;
10474 if (type != 2) {
10475 level = 2;
10477 if (domain_prot == 0 || domain_prot == 2) {
10478 fi->type = ARMFault_Domain;
10479 goto do_fault;
10481 if (type == 2) {
10482 /* 1Mb section. */
10483 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
10484 ap = (desc >> 10) & 3;
10485 *page_size = 1024 * 1024;
10486 } else {
10487 /* Lookup l2 entry. */
10488 if (type == 1) {
10489 /* Coarse pagetable. */
10490 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
10491 } else {
10492 /* Fine pagetable. */
10493 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
10495 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
10496 mmu_idx, fi);
10497 if (fi->type != ARMFault_None) {
10498 goto do_fault;
10500 switch (desc & 3) {
10501 case 0: /* Page translation fault. */
10502 fi->type = ARMFault_Translation;
10503 goto do_fault;
10504 case 1: /* 64k page. */
10505 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
10506 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
10507 *page_size = 0x10000;
10508 break;
10509 case 2: /* 4k page. */
10510 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
10511 ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
10512 *page_size = 0x1000;
10513 break;
10514 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
10515 if (type == 1) {
10516 /* ARMv6/XScale extended small page format */
10517 if (arm_feature(env, ARM_FEATURE_XSCALE)
10518 || arm_feature(env, ARM_FEATURE_V6)) {
10519 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
10520 *page_size = 0x1000;
10521 } else {
10522 /* UNPREDICTABLE in ARMv5; we choose to take a
10523 * page translation fault.
10525 fi->type = ARMFault_Translation;
10526 goto do_fault;
10528 } else {
10529 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
10530 *page_size = 0x400;
10532 ap = (desc >> 4) & 3;
10533 break;
10534 default:
10535 /* Never happens, but compiler isn't smart enough to tell. */
10536 abort();
10539 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
10540 *prot |= *prot ? PAGE_EXEC : 0;
10541 if (!(*prot & (1 << access_type))) {
10542 /* Access permission fault. */
10543 fi->type = ARMFault_Permission;
10544 goto do_fault;
10546 *phys_ptr = phys_addr;
10547 return false;
10548 do_fault:
10549 fi->domain = domain;
10550 fi->level = level;
10551 return true;
10554 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
10555 MMUAccessType access_type, ARMMMUIdx mmu_idx,
10556 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
10557 target_ulong *page_size, ARMMMUFaultInfo *fi)
10559 CPUState *cs = env_cpu(env);
10560 ARMCPU *cpu = env_archcpu(env);
10561 int level = 1;
10562 uint32_t table;
10563 uint32_t desc;
10564 uint32_t xn;
10565 uint32_t pxn = 0;
10566 int type;
10567 int ap;
10568 int domain = 0;
10569 int domain_prot;
10570 hwaddr phys_addr;
10571 uint32_t dacr;
10572 bool ns;
10574 /* Pagetable walk. */
10575 /* Lookup l1 descriptor. */
10576 if (!get_level1_table_address(env, mmu_idx, &table, address)) {
10577 /* Section translation fault if page walk is disabled by PD0 or PD1 */
10578 fi->type = ARMFault_Translation;
10579 goto do_fault;
10581 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
10582 mmu_idx, fi);
10583 if (fi->type != ARMFault_None) {
10584 goto do_fault;
10586 type = (desc & 3);
10587 if (type == 0 || (type == 3 && !cpu_isar_feature(aa32_pxn, cpu))) {
10588 /* Section translation fault, or attempt to use the encoding
10589 * which is Reserved on implementations without PXN.
10591 fi->type = ARMFault_Translation;
10592 goto do_fault;
10594 if ((type == 1) || !(desc & (1 << 18))) {
10595 /* Page or Section. */
10596 domain = (desc >> 5) & 0x0f;
10598 if (regime_el(env, mmu_idx) == 1) {
10599 dacr = env->cp15.dacr_ns;
10600 } else {
10601 dacr = env->cp15.dacr_s;
10603 if (type == 1) {
10604 level = 2;
10606 domain_prot = (dacr >> (domain * 2)) & 3;
10607 if (domain_prot == 0 || domain_prot == 2) {
10608 /* Section or Page domain fault */
10609 fi->type = ARMFault_Domain;
10610 goto do_fault;
10612 if (type != 1) {
10613 if (desc & (1 << 18)) {
10614 /* Supersection. */
10615 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
10616 phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
10617 phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
10618 *page_size = 0x1000000;
10619 } else {
10620 /* Section. */
10621 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
10622 *page_size = 0x100000;
10624 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
10625 xn = desc & (1 << 4);
10626 pxn = desc & 1;
10627 ns = extract32(desc, 19, 1);
10628 } else {
10629 if (cpu_isar_feature(aa32_pxn, cpu)) {
10630 pxn = (desc >> 2) & 1;
10632 ns = extract32(desc, 3, 1);
10633 /* Lookup l2 entry. */
10634 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
10635 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
10636 mmu_idx, fi);
10637 if (fi->type != ARMFault_None) {
10638 goto do_fault;
10640 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
10641 switch (desc & 3) {
10642 case 0: /* Page translation fault. */
10643 fi->type = ARMFault_Translation;
10644 goto do_fault;
10645 case 1: /* 64k page. */
10646 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
10647 xn = desc & (1 << 15);
10648 *page_size = 0x10000;
10649 break;
10650 case 2: case 3: /* 4k page. */
10651 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
10652 xn = desc & 1;
10653 *page_size = 0x1000;
10654 break;
10655 default:
10656 /* Never happens, but compiler isn't smart enough to tell. */
10657 abort();
10660 if (domain_prot == 3) {
10661 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
10662 } else {
10663 if (pxn && !regime_is_user(env, mmu_idx)) {
10664 xn = 1;
10666 if (xn && access_type == MMU_INST_FETCH) {
10667 fi->type = ARMFault_Permission;
10668 goto do_fault;
10671 if (arm_feature(env, ARM_FEATURE_V6K) &&
10672 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
10673 /* The simplified model uses AP[0] as an access control bit. */
10674 if ((ap & 1) == 0) {
10675 /* Access flag fault. */
10676 fi->type = ARMFault_AccessFlag;
10677 goto do_fault;
10679 *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
10680 } else {
10681 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
10683 if (*prot && !xn) {
10684 *prot |= PAGE_EXEC;
10686 if (!(*prot & (1 << access_type))) {
10687 /* Access permission fault. */
10688 fi->type = ARMFault_Permission;
10689 goto do_fault;
10692 if (ns) {
10693 /* The NS bit will (as required by the architecture) have no effect if
10694 * the CPU doesn't support TZ or this is a non-secure translation
10695 * regime, because the attribute will already be non-secure.
10697 attrs->secure = false;
10699 *phys_ptr = phys_addr;
10700 return false;
10701 do_fault:
10702 fi->domain = domain;
10703 fi->level = level;
10704 return true;
10708 * check_s2_mmu_setup
10709 * @cpu: ARMCPU
10710 * @is_aa64: True if the translation regime is in AArch64 state
10711 * @startlevel: Suggested starting level
10712 * @inputsize: Bitsize of IPAs
10713 * @stride: Page-table stride (See the ARM ARM)
10715 * Returns true if the suggested S2 translation parameters are OK and
10716 * false otherwise.
10718 static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
10719 int inputsize, int stride)
10721 const int grainsize = stride + 3;
10722 int startsizecheck;
10724 /* Negative levels are never allowed. */
10725 if (level < 0) {
10726 return false;
10729 startsizecheck = inputsize - ((3 - level) * stride + grainsize);
10730 if (startsizecheck < 1 || startsizecheck > stride + 4) {
10731 return false;
10734 if (is_aa64) {
10735 CPUARMState *env = &cpu->env;
10736 unsigned int pamax = arm_pamax(cpu);
10738 switch (stride) {
10739 case 13: /* 64KB Pages. */
10740 if (level == 0 || (level == 1 && pamax <= 42)) {
10741 return false;
10743 break;
10744 case 11: /* 16KB Pages. */
10745 if (level == 0 || (level == 1 && pamax <= 40)) {
10746 return false;
10748 break;
10749 case 9: /* 4KB Pages. */
10750 if (level == 0 && pamax <= 42) {
10751 return false;
10753 break;
10754 default:
10755 g_assert_not_reached();
10758 /* Inputsize checks. */
10759 if (inputsize > pamax &&
10760 (arm_el_is_aa64(env, 1) || inputsize > 40)) {
10761 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
10762 return false;
10764 } else {
10765 /* AArch32 only supports 4KB pages. Assert on that. */
10766 assert(stride == 9);
10768 if (level == 0) {
10769 return false;
10772 return true;
10775 /* Translate from the 4-bit stage 2 representation of
10776 * memory attributes (without cache-allocation hints) to
10777 * the 8-bit representation of the stage 1 MAIR registers
10778 * (which includes allocation hints).
10780 * ref: shared/translation/attrs/S2AttrDecode()
10781 * .../S2ConvertAttrsHints()
10783 static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
10785 uint8_t hiattr = extract32(s2attrs, 2, 2);
10786 uint8_t loattr = extract32(s2attrs, 0, 2);
10787 uint8_t hihint = 0, lohint = 0;
10789 if (hiattr != 0) { /* normal memory */
10790 if ((env->cp15.hcr_el2 & HCR_CD) != 0) { /* cache disabled */
10791 hiattr = loattr = 1; /* non-cacheable */
10792 } else {
10793 if (hiattr != 1) { /* Write-through or write-back */
10794 hihint = 3; /* RW allocate */
10796 if (loattr != 1) { /* Write-through or write-back */
10797 lohint = 3; /* RW allocate */
10802 return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint;
10804 #endif /* !CONFIG_USER_ONLY */
10806 static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx)
10808 if (regime_has_2_ranges(mmu_idx)) {
10809 return extract64(tcr, 37, 2);
10810 } else if (mmu_idx == ARMMMUIdx_Stage2) {
10811 return 0; /* VTCR_EL2 */
10812 } else {
10813 /* Replicate the single TBI bit so we always have 2 bits. */
10814 return extract32(tcr, 20, 1) * 3;
10818 static int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx)
10820 if (regime_has_2_ranges(mmu_idx)) {
10821 return extract64(tcr, 51, 2);
10822 } else if (mmu_idx == ARMMMUIdx_Stage2) {
10823 return 0; /* VTCR_EL2 */
10824 } else {
10825 /* Replicate the single TBID bit so we always have 2 bits. */
10826 return extract32(tcr, 29, 1) * 3;
10830 static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx)
10832 if (regime_has_2_ranges(mmu_idx)) {
10833 return extract64(tcr, 57, 2);
10834 } else {
10835 /* Replicate the single TCMA bit so we always have 2 bits. */
10836 return extract32(tcr, 30, 1) * 3;
10840 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
10841 ARMMMUIdx mmu_idx, bool data)
10843 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
10844 bool epd, hpd, using16k, using64k;
10845 int select, tsz, tbi;
10847 if (!regime_has_2_ranges(mmu_idx)) {
10848 select = 0;
10849 tsz = extract32(tcr, 0, 6);
10850 using64k = extract32(tcr, 14, 1);
10851 using16k = extract32(tcr, 15, 1);
10852 if (mmu_idx == ARMMMUIdx_Stage2) {
10853 /* VTCR_EL2 */
10854 hpd = false;
10855 } else {
10856 hpd = extract32(tcr, 24, 1);
10858 epd = false;
10859 } else {
10861 * Bit 55 is always between the two regions, and is canonical for
10862 * determining if address tagging is enabled.
10864 select = extract64(va, 55, 1);
10865 if (!select) {
10866 tsz = extract32(tcr, 0, 6);
10867 epd = extract32(tcr, 7, 1);
10868 using64k = extract32(tcr, 14, 1);
10869 using16k = extract32(tcr, 15, 1);
10870 hpd = extract64(tcr, 41, 1);
10871 } else {
10872 int tg = extract32(tcr, 30, 2);
10873 using16k = tg == 1;
10874 using64k = tg == 3;
10875 tsz = extract32(tcr, 16, 6);
10876 epd = extract32(tcr, 23, 1);
10877 hpd = extract64(tcr, 42, 1);
10880 tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */
10881 tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
10883 /* Present TBI as a composite with TBID. */
10884 tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
10885 if (!data) {
10886 tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
10888 tbi = (tbi >> select) & 1;
10890 return (ARMVAParameters) {
10891 .tsz = tsz,
10892 .select = select,
10893 .tbi = tbi,
10894 .epd = epd,
10895 .hpd = hpd,
10896 .using16k = using16k,
10897 .using64k = using64k,
10901 #ifndef CONFIG_USER_ONLY
10902 static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
10903 ARMMMUIdx mmu_idx)
10905 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
10906 uint32_t el = regime_el(env, mmu_idx);
10907 int select, tsz;
10908 bool epd, hpd;
10910 if (mmu_idx == ARMMMUIdx_Stage2) {
10911 /* VTCR */
10912 bool sext = extract32(tcr, 4, 1);
10913 bool sign = extract32(tcr, 3, 1);
10916 * If the sign-extend bit is not the same as t0sz[3], the result
10917 * is unpredictable. Flag this as a guest error.
10919 if (sign != sext) {
10920 qemu_log_mask(LOG_GUEST_ERROR,
10921 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
10923 tsz = sextract32(tcr, 0, 4) + 8;
10924 select = 0;
10925 hpd = false;
10926 epd = false;
10927 } else if (el == 2) {
10928 /* HTCR */
10929 tsz = extract32(tcr, 0, 3);
10930 select = 0;
10931 hpd = extract64(tcr, 24, 1);
10932 epd = false;
10933 } else {
10934 int t0sz = extract32(tcr, 0, 3);
10935 int t1sz = extract32(tcr, 16, 3);
10937 if (t1sz == 0) {
10938 select = va > (0xffffffffu >> t0sz);
10939 } else {
10940 /* Note that we will detect errors later. */
10941 select = va >= ~(0xffffffffu >> t1sz);
10943 if (!select) {
10944 tsz = t0sz;
10945 epd = extract32(tcr, 7, 1);
10946 hpd = extract64(tcr, 41, 1);
10947 } else {
10948 tsz = t1sz;
10949 epd = extract32(tcr, 23, 1);
10950 hpd = extract64(tcr, 42, 1);
10952 /* For aarch32, hpd0 is not enabled without t2e as well. */
10953 hpd &= extract32(tcr, 6, 1);
10956 return (ARMVAParameters) {
10957 .tsz = tsz,
10958 .select = select,
10959 .epd = epd,
10960 .hpd = hpd,
10965 * get_phys_addr_lpae: perform one stage of page table walk, LPAE format
10967 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
10968 * prot and page_size may not be filled in, and the populated fsr value provides
10969 * information on why the translation aborted, in the format of a long-format
10970 * DFSR/IFSR fault register, with the following caveats:
10971 * * the WnR bit is never set (the caller must do this).
10973 * @env: CPUARMState
10974 * @address: virtual address to get physical address for
10975 * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
10976 * @mmu_idx: MMU index indicating required translation regime
10977 * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page table
10978 * walk), must be true if this is stage 2 of a stage 1+2 walk for an
10979 * EL0 access). If @mmu_idx is anything else, @s1_is_el0 is ignored.
10980 * @phys_ptr: set to the physical address corresponding to the virtual address
10981 * @attrs: set to the memory transaction attributes to use
10982 * @prot: set to the permissions for the page containing phys_ptr
10983 * @page_size_ptr: set to the size of the page containing phys_ptr
10984 * @fi: set to fault info if the translation fails
10985 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
10987 static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
10988 MMUAccessType access_type, ARMMMUIdx mmu_idx,
10989 bool s1_is_el0,
10990 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
10991 target_ulong *page_size_ptr,
10992 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
10994 ARMCPU *cpu = env_archcpu(env);
10995 CPUState *cs = CPU(cpu);
10996 /* Read an LPAE long-descriptor translation table. */
10997 ARMFaultType fault_type = ARMFault_Translation;
10998 uint32_t level;
10999 ARMVAParameters param;
11000 uint64_t ttbr;
11001 hwaddr descaddr, indexmask, indexmask_grainsize;
11002 uint32_t tableattrs;
11003 target_ulong page_size;
11004 uint32_t attrs;
11005 int32_t stride;
11006 int addrsize, inputsize;
11007 TCR *tcr = regime_tcr(env, mmu_idx);
11008 int ap, ns, xn, pxn;
11009 uint32_t el = regime_el(env, mmu_idx);
11010 uint64_t descaddrmask;
11011 bool aarch64 = arm_el_is_aa64(env, el);
11012 bool guarded = false;
11014 /* TODO: This code does not support shareability levels. */
11015 if (aarch64) {
11016 param = aa64_va_parameters(env, address, mmu_idx,
11017 access_type != MMU_INST_FETCH);
11018 level = 0;
11019 addrsize = 64 - 8 * param.tbi;
11020 inputsize = 64 - param.tsz;
11021 } else {
11022 param = aa32_va_parameters(env, address, mmu_idx);
11023 level = 1;
11024 addrsize = (mmu_idx == ARMMMUIdx_Stage2 ? 40 : 32);
11025 inputsize = addrsize - param.tsz;
11029 * We determined the region when collecting the parameters, but we
11030 * have not yet validated that the address is valid for the region.
11031 * Extract the top bits and verify that they all match select.
11033 * For aa32, if inputsize == addrsize, then we have selected the
11034 * region by exclusion in aa32_va_parameters and there is no more
11035 * validation to do here.
11037 if (inputsize < addrsize) {
11038 target_ulong top_bits = sextract64(address, inputsize,
11039 addrsize - inputsize);
11040 if (-top_bits != param.select) {
11041 /* The gap between the two regions is a Translation fault */
11042 fault_type = ARMFault_Translation;
11043 goto do_fault;
11047 if (param.using64k) {
11048 stride = 13;
11049 } else if (param.using16k) {
11050 stride = 11;
11051 } else {
11052 stride = 9;
11055 /* Note that QEMU ignores shareability and cacheability attributes,
11056 * so we don't need to do anything with the SH, ORGN, IRGN fields
11057 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
11058 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
11059 * implement any ASID-like capability so we can ignore it (instead
11060 * we will always flush the TLB any time the ASID is changed).
11062 ttbr = regime_ttbr(env, mmu_idx, param.select);
11064 /* Here we should have set up all the parameters for the translation:
11065 * inputsize, ttbr, epd, stride, tbi
11068 if (param.epd) {
11069 /* Translation table walk disabled => Translation fault on TLB miss
11070 * Note: This is always 0 on 64-bit EL2 and EL3.
11072 goto do_fault;
11075 if (mmu_idx != ARMMMUIdx_Stage2) {
11076 /* The starting level depends on the virtual address size (which can
11077 * be up to 48 bits) and the translation granule size. It indicates
11078 * the number of strides (stride bits at a time) needed to
11079 * consume the bits of the input address. In the pseudocode this is:
11080 * level = 4 - RoundUp((inputsize - grainsize) / stride)
11081 * where their 'inputsize' is our 'inputsize', 'grainsize' is
11082 * our 'stride + 3' and 'stride' is our 'stride'.
11083 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
11084 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
11085 * = 4 - (inputsize - 4) / stride;
11087 level = 4 - (inputsize - 4) / stride;
11088 } else {
11089 /* For stage 2 translations the starting level is specified by the
11090 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
11092 uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2);
11093 uint32_t startlevel;
11094 bool ok;
11096 if (!aarch64 || stride == 9) {
11097 /* AArch32 or 4KB pages */
11098 startlevel = 2 - sl0;
11099 } else {
11100 /* 16KB or 64KB pages */
11101 startlevel = 3 - sl0;
11104 /* Check that the starting level is valid. */
11105 ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
11106 inputsize, stride);
11107 if (!ok) {
11108 fault_type = ARMFault_Translation;
11109 goto do_fault;
11111 level = startlevel;
11114 indexmask_grainsize = (1ULL << (stride + 3)) - 1;
11115 indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1;
11117 /* Now we can extract the actual base address from the TTBR */
11118 descaddr = extract64(ttbr, 0, 48);
11120 * We rely on this masking to clear the RES0 bits at the bottom of the TTBR
11121 * and also to mask out CnP (bit 0) which could validly be non-zero.
11123 descaddr &= ~indexmask;
11125 /* The address field in the descriptor goes up to bit 39 for ARMv7
11126 * but up to bit 47 for ARMv8, but we use the descaddrmask
11127 * up to bit 39 for AArch32, because we don't need other bits in that case
11128 * to construct next descriptor address (anyway they should be all zeroes).
11130 descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) &
11131 ~indexmask_grainsize;
11133 /* Secure accesses start with the page table in secure memory and
11134 * can be downgraded to non-secure at any step. Non-secure accesses
11135 * remain non-secure. We implement this by just ORing in the NSTable/NS
11136 * bits at each step.
11138 tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
11139 for (;;) {
11140 uint64_t descriptor;
11141 bool nstable;
11143 descaddr |= (address >> (stride * (4 - level))) & indexmask;
11144 descaddr &= ~7ULL;
11145 nstable = extract32(tableattrs, 4, 1);
11146 descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi);
11147 if (fi->type != ARMFault_None) {
11148 goto do_fault;
11151 if (!(descriptor & 1) ||
11152 (!(descriptor & 2) && (level == 3))) {
11153 /* Invalid, or the Reserved level 3 encoding */
11154 goto do_fault;
11156 descaddr = descriptor & descaddrmask;
11158 if ((descriptor & 2) && (level < 3)) {
11159 /* Table entry. The top five bits are attributes which may
11160 * propagate down through lower levels of the table (and
11161 * which are all arranged so that 0 means "no effect", so
11162 * we can gather them up by ORing in the bits at each level).
11164 tableattrs |= extract64(descriptor, 59, 5);
11165 level++;
11166 indexmask = indexmask_grainsize;
11167 continue;
11169 /* Block entry at level 1 or 2, or page entry at level 3.
11170 * These are basically the same thing, although the number
11171 * of bits we pull in from the vaddr varies.
11173 page_size = (1ULL << ((stride * (4 - level)) + 3));
11174 descaddr |= (address & (page_size - 1));
11175 /* Extract attributes from the descriptor */
11176 attrs = extract64(descriptor, 2, 10)
11177 | (extract64(descriptor, 52, 12) << 10);
11179 if (mmu_idx == ARMMMUIdx_Stage2) {
11180 /* Stage 2 table descriptors do not include any attribute fields */
11181 break;
11183 /* Merge in attributes from table descriptors */
11184 attrs |= nstable << 3; /* NS */
11185 guarded = extract64(descriptor, 50, 1); /* GP */
11186 if (param.hpd) {
11187 /* HPD disables all the table attributes except NSTable. */
11188 break;
11190 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
11191 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
11192 * means "force PL1 access only", which means forcing AP[1] to 0.
11194 attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */
11195 attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */
11196 break;
11198 /* Here descaddr is the final physical address, and attributes
11199 * are all in attrs.
11201 fault_type = ARMFault_AccessFlag;
11202 if ((attrs & (1 << 8)) == 0) {
11203 /* Access flag */
11204 goto do_fault;
11207 ap = extract32(attrs, 4, 2);
11209 if (mmu_idx == ARMMMUIdx_Stage2) {
11210 ns = true;
11211 xn = extract32(attrs, 11, 2);
11212 *prot = get_S2prot(env, ap, xn, s1_is_el0);
11213 } else {
11214 ns = extract32(attrs, 3, 1);
11215 xn = extract32(attrs, 12, 1);
11216 pxn = extract32(attrs, 11, 1);
11217 *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
11220 fault_type = ARMFault_Permission;
11221 if (!(*prot & (1 << access_type))) {
11222 goto do_fault;
11225 if (ns) {
11226 /* The NS bit will (as required by the architecture) have no effect if
11227 * the CPU doesn't support TZ or this is a non-secure translation
11228 * regime, because the attribute will already be non-secure.
11230 txattrs->secure = false;
11232 /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
11233 if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) {
11234 arm_tlb_bti_gp(txattrs) = true;
11237 if (mmu_idx == ARMMMUIdx_Stage2) {
11238 cacheattrs->attrs = convert_stage2_attrs(env, extract32(attrs, 0, 4));
11239 } else {
11240 /* Index into MAIR registers for cache attributes */
11241 uint8_t attrindx = extract32(attrs, 0, 3);
11242 uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
11243 assert(attrindx <= 7);
11244 cacheattrs->attrs = extract64(mair, attrindx * 8, 8);
11246 cacheattrs->shareability = extract32(attrs, 6, 2);
11248 *phys_ptr = descaddr;
11249 *page_size_ptr = page_size;
11250 return false;
11252 do_fault:
11253 fi->type = fault_type;
11254 fi->level = level;
11255 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
11256 fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_Stage2);
11257 return true;
11260 static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
11261 ARMMMUIdx mmu_idx,
11262 int32_t address, int *prot)
11264 if (!arm_feature(env, ARM_FEATURE_M)) {
11265 *prot = PAGE_READ | PAGE_WRITE;
11266 switch (address) {
11267 case 0xF0000000 ... 0xFFFFFFFF:
11268 if (regime_sctlr(env, mmu_idx) & SCTLR_V) {
11269 /* hivecs execing is ok */
11270 *prot |= PAGE_EXEC;
11272 break;
11273 case 0x00000000 ... 0x7FFFFFFF:
11274 *prot |= PAGE_EXEC;
11275 break;
11277 } else {
11278 /* Default system address map for M profile cores.
11279 * The architecture specifies which regions are execute-never;
11280 * at the MPU level no other checks are defined.
11282 switch (address) {
11283 case 0x00000000 ... 0x1fffffff: /* ROM */
11284 case 0x20000000 ... 0x3fffffff: /* SRAM */
11285 case 0x60000000 ... 0x7fffffff: /* RAM */
11286 case 0x80000000 ... 0x9fffffff: /* RAM */
11287 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
11288 break;
11289 case 0x40000000 ... 0x5fffffff: /* Peripheral */
11290 case 0xa0000000 ... 0xbfffffff: /* Device */
11291 case 0xc0000000 ... 0xdfffffff: /* Device */
11292 case 0xe0000000 ... 0xffffffff: /* System */
11293 *prot = PAGE_READ | PAGE_WRITE;
11294 break;
11295 default:
11296 g_assert_not_reached();
11301 static bool pmsav7_use_background_region(ARMCPU *cpu,
11302 ARMMMUIdx mmu_idx, bool is_user)
11304 /* Return true if we should use the default memory map as a
11305 * "background" region if there are no hits against any MPU regions.
11307 CPUARMState *env = &cpu->env;
11309 if (is_user) {
11310 return false;
11313 if (arm_feature(env, ARM_FEATURE_M)) {
11314 return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)]
11315 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
11316 } else {
11317 return regime_sctlr(env, mmu_idx) & SCTLR_BR;
11321 static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address)
11323 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
11324 return arm_feature(env, ARM_FEATURE_M) &&
11325 extract32(address, 20, 12) == 0xe00;
11328 static inline bool m_is_system_region(CPUARMState *env, uint32_t address)
11330 /* True if address is in the M profile system region
11331 * 0xe0000000 - 0xffffffff
11333 return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7;
11336 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
11337 MMUAccessType access_type, ARMMMUIdx mmu_idx,
11338 hwaddr *phys_ptr, int *prot,
11339 target_ulong *page_size,
11340 ARMMMUFaultInfo *fi)
11342 ARMCPU *cpu = env_archcpu(env);
11343 int n;
11344 bool is_user = regime_is_user(env, mmu_idx);
11346 *phys_ptr = address;
11347 *page_size = TARGET_PAGE_SIZE;
11348 *prot = 0;
11350 if (regime_translation_disabled(env, mmu_idx) ||
11351 m_is_ppb_region(env, address)) {
11352 /* MPU disabled or M profile PPB access: use default memory map.
11353 * The other case which uses the default memory map in the
11354 * v7M ARM ARM pseudocode is exception vector reads from the vector
11355 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
11356 * which always does a direct read using address_space_ldl(), rather
11357 * than going via this function, so we don't need to check that here.
11359 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
11360 } else { /* MPU enabled */
11361 for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
11362 /* region search */
11363 uint32_t base = env->pmsav7.drbar[n];
11364 uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
11365 uint32_t rmask;
11366 bool srdis = false;
11368 if (!(env->pmsav7.drsr[n] & 0x1)) {
11369 continue;
11372 if (!rsize) {
11373 qemu_log_mask(LOG_GUEST_ERROR,
11374 "DRSR[%d]: Rsize field cannot be 0\n", n);
11375 continue;
11377 rsize++;
11378 rmask = (1ull << rsize) - 1;
11380 if (base & rmask) {
11381 qemu_log_mask(LOG_GUEST_ERROR,
11382 "DRBAR[%d]: 0x%" PRIx32 " misaligned "
11383 "to DRSR region size, mask = 0x%" PRIx32 "\n",
11384 n, base, rmask);
11385 continue;
11388 if (address < base || address > base + rmask) {
11390 * Address not in this region. We must check whether the
11391 * region covers addresses in the same page as our address.
11392 * In that case we must not report a size that covers the
11393 * whole page for a subsequent hit against a different MPU
11394 * region or the background region, because it would result in
11395 * incorrect TLB hits for subsequent accesses to addresses that
11396 * are in this MPU region.
11398 if (ranges_overlap(base, rmask,
11399 address & TARGET_PAGE_MASK,
11400 TARGET_PAGE_SIZE)) {
11401 *page_size = 1;
11403 continue;
11406 /* Region matched */
11408 if (rsize >= 8) { /* no subregions for regions < 256 bytes */
11409 int i, snd;
11410 uint32_t srdis_mask;
11412 rsize -= 3; /* sub region size (power of 2) */
11413 snd = ((address - base) >> rsize) & 0x7;
11414 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
11416 srdis_mask = srdis ? 0x3 : 0x0;
11417 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
11418 /* This will check in groups of 2, 4 and then 8, whether
11419 * the subregion bits are consistent. rsize is incremented
11420 * back up to give the region size, considering consistent
11421 * adjacent subregions as one region. Stop testing if rsize
11422 * is already big enough for an entire QEMU page.
11424 int snd_rounded = snd & ~(i - 1);
11425 uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
11426 snd_rounded + 8, i);
11427 if (srdis_mask ^ srdis_multi) {
11428 break;
11430 srdis_mask = (srdis_mask << i) | srdis_mask;
11431 rsize++;
11434 if (srdis) {
11435 continue;
11437 if (rsize < TARGET_PAGE_BITS) {
11438 *page_size = 1 << rsize;
11440 break;
11443 if (n == -1) { /* no hits */
11444 if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
11445 /* background fault */
11446 fi->type = ARMFault_Background;
11447 return true;
11449 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
11450 } else { /* a MPU hit! */
11451 uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
11452 uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1);
11454 if (m_is_system_region(env, address)) {
11455 /* System space is always execute never */
11456 xn = 1;
11459 if (is_user) { /* User mode AP bit decoding */
11460 switch (ap) {
11461 case 0:
11462 case 1:
11463 case 5:
11464 break; /* no access */
11465 case 3:
11466 *prot |= PAGE_WRITE;
11467 /* fall through */
11468 case 2:
11469 case 6:
11470 *prot |= PAGE_READ | PAGE_EXEC;
11471 break;
11472 case 7:
11473 /* for v7M, same as 6; for R profile a reserved value */
11474 if (arm_feature(env, ARM_FEATURE_M)) {
11475 *prot |= PAGE_READ | PAGE_EXEC;
11476 break;
11478 /* fall through */
11479 default:
11480 qemu_log_mask(LOG_GUEST_ERROR,
11481 "DRACR[%d]: Bad value for AP bits: 0x%"
11482 PRIx32 "\n", n, ap);
11484 } else { /* Priv. mode AP bits decoding */
11485 switch (ap) {
11486 case 0:
11487 break; /* no access */
11488 case 1:
11489 case 2:
11490 case 3:
11491 *prot |= PAGE_WRITE;
11492 /* fall through */
11493 case 5:
11494 case 6:
11495 *prot |= PAGE_READ | PAGE_EXEC;
11496 break;
11497 case 7:
11498 /* for v7M, same as 6; for R profile a reserved value */
11499 if (arm_feature(env, ARM_FEATURE_M)) {
11500 *prot |= PAGE_READ | PAGE_EXEC;
11501 break;
11503 /* fall through */
11504 default:
11505 qemu_log_mask(LOG_GUEST_ERROR,
11506 "DRACR[%d]: Bad value for AP bits: 0x%"
11507 PRIx32 "\n", n, ap);
11511 /* execute never */
11512 if (xn) {
11513 *prot &= ~PAGE_EXEC;
11518 fi->type = ARMFault_Permission;
11519 fi->level = 1;
11520 return !(*prot & (1 << access_type));
11523 static bool v8m_is_sau_exempt(CPUARMState *env,
11524 uint32_t address, MMUAccessType access_type)
11526 /* The architecture specifies that certain address ranges are
11527 * exempt from v8M SAU/IDAU checks.
11529 return
11530 (access_type == MMU_INST_FETCH && m_is_system_region(env, address)) ||
11531 (address >= 0xe0000000 && address <= 0xe0002fff) ||
11532 (address >= 0xe000e000 && address <= 0xe000efff) ||
11533 (address >= 0xe002e000 && address <= 0xe002efff) ||
11534 (address >= 0xe0040000 && address <= 0xe0041fff) ||
11535 (address >= 0xe00ff000 && address <= 0xe00fffff);
11538 void v8m_security_lookup(CPUARMState *env, uint32_t address,
11539 MMUAccessType access_type, ARMMMUIdx mmu_idx,
11540 V8M_SAttributes *sattrs)
11542 /* Look up the security attributes for this address. Compare the
11543 * pseudocode SecurityCheck() function.
11544 * We assume the caller has zero-initialized *sattrs.
11546 ARMCPU *cpu = env_archcpu(env);
11547 int r;
11548 bool idau_exempt = false, idau_ns = true, idau_nsc = true;
11549 int idau_region = IREGION_NOTVALID;
11550 uint32_t addr_page_base = address & TARGET_PAGE_MASK;
11551 uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
11553 if (cpu->idau) {
11554 IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau);
11555 IDAUInterface *ii = IDAU_INTERFACE(cpu->idau);
11557 iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns,
11558 &idau_nsc);
11561 if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) {
11562 /* 0xf0000000..0xffffffff is always S for insn fetches */
11563 return;
11566 if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) {
11567 sattrs->ns = !regime_is_secure(env, mmu_idx);
11568 return;
11571 if (idau_region != IREGION_NOTVALID) {
11572 sattrs->irvalid = true;
11573 sattrs->iregion = idau_region;
11576 switch (env->sau.ctrl & 3) {
11577 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
11578 break;
11579 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
11580 sattrs->ns = true;
11581 break;
11582 default: /* SAU.ENABLE == 1 */
11583 for (r = 0; r < cpu->sau_sregion; r++) {
11584 if (env->sau.rlar[r] & 1) {
11585 uint32_t base = env->sau.rbar[r] & ~0x1f;
11586 uint32_t limit = env->sau.rlar[r] | 0x1f;
11588 if (base <= address && limit >= address) {
11589 if (base > addr_page_base || limit < addr_page_limit) {
11590 sattrs->subpage = true;
11592 if (sattrs->srvalid) {
11593 /* If we hit in more than one region then we must report
11594 * as Secure, not NS-Callable, with no valid region
11595 * number info.
11597 sattrs->ns = false;
11598 sattrs->nsc = false;
11599 sattrs->sregion = 0;
11600 sattrs->srvalid = false;
11601 break;
11602 } else {
11603 if (env->sau.rlar[r] & 2) {
11604 sattrs->nsc = true;
11605 } else {
11606 sattrs->ns = true;
11608 sattrs->srvalid = true;
11609 sattrs->sregion = r;
11611 } else {
11613 * Address not in this region. We must check whether the
11614 * region covers addresses in the same page as our address.
11615 * In that case we must not report a size that covers the
11616 * whole page for a subsequent hit against a different MPU
11617 * region or the background region, because it would result
11618 * in incorrect TLB hits for subsequent accesses to
11619 * addresses that are in this MPU region.
11621 if (limit >= base &&
11622 ranges_overlap(base, limit - base + 1,
11623 addr_page_base,
11624 TARGET_PAGE_SIZE)) {
11625 sattrs->subpage = true;
11630 break;
11634 * The IDAU will override the SAU lookup results if it specifies
11635 * higher security than the SAU does.
11637 if (!idau_ns) {
11638 if (sattrs->ns || (!idau_nsc && sattrs->nsc)) {
11639 sattrs->ns = false;
11640 sattrs->nsc = idau_nsc;
11645 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
11646 MMUAccessType access_type, ARMMMUIdx mmu_idx,
11647 hwaddr *phys_ptr, MemTxAttrs *txattrs,
11648 int *prot, bool *is_subpage,
11649 ARMMMUFaultInfo *fi, uint32_t *mregion)
11651 /* Perform a PMSAv8 MPU lookup (without also doing the SAU check
11652 * that a full phys-to-virt translation does).
11653 * mregion is (if not NULL) set to the region number which matched,
11654 * or -1 if no region number is returned (MPU off, address did not
11655 * hit a region, address hit in multiple regions).
11656 * We set is_subpage to true if the region hit doesn't cover the
11657 * entire TARGET_PAGE the address is within.
11659 ARMCPU *cpu = env_archcpu(env);
11660 bool is_user = regime_is_user(env, mmu_idx);
11661 uint32_t secure = regime_is_secure(env, mmu_idx);
11662 int n;
11663 int matchregion = -1;
11664 bool hit = false;
11665 uint32_t addr_page_base = address & TARGET_PAGE_MASK;
11666 uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
11668 *is_subpage = false;
11669 *phys_ptr = address;
11670 *prot = 0;
11671 if (mregion) {
11672 *mregion = -1;
11675 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
11676 * was an exception vector read from the vector table (which is always
11677 * done using the default system address map), because those accesses
11678 * are done in arm_v7m_load_vector(), which always does a direct
11679 * read using address_space_ldl(), rather than going via this function.
11681 if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
11682 hit = true;
11683 } else if (m_is_ppb_region(env, address)) {
11684 hit = true;
11685 } else {
11686 if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
11687 hit = true;
11690 for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
11691 /* region search */
11692 /* Note that the base address is bits [31:5] from the register
11693 * with bits [4:0] all zeroes, but the limit address is bits
11694 * [31:5] from the register with bits [4:0] all ones.
11696 uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f;
11697 uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f;
11699 if (!(env->pmsav8.rlar[secure][n] & 0x1)) {
11700 /* Region disabled */
11701 continue;
11704 if (address < base || address > limit) {
11706 * Address not in this region. We must check whether the
11707 * region covers addresses in the same page as our address.
11708 * In that case we must not report a size that covers the
11709 * whole page for a subsequent hit against a different MPU
11710 * region or the background region, because it would result in
11711 * incorrect TLB hits for subsequent accesses to addresses that
11712 * are in this MPU region.
11714 if (limit >= base &&
11715 ranges_overlap(base, limit - base + 1,
11716 addr_page_base,
11717 TARGET_PAGE_SIZE)) {
11718 *is_subpage = true;
11720 continue;
11723 if (base > addr_page_base || limit < addr_page_limit) {
11724 *is_subpage = true;
11727 if (matchregion != -1) {
11728 /* Multiple regions match -- always a failure (unlike
11729 * PMSAv7 where highest-numbered-region wins)
11731 fi->type = ARMFault_Permission;
11732 fi->level = 1;
11733 return true;
11736 matchregion = n;
11737 hit = true;
11741 if (!hit) {
11742 /* background fault */
11743 fi->type = ARMFault_Background;
11744 return true;
11747 if (matchregion == -1) {
11748 /* hit using the background region */
11749 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
11750 } else {
11751 uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
11752 uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
11753 bool pxn = false;
11755 if (arm_feature(env, ARM_FEATURE_V8_1M)) {
11756 pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1);
11759 if (m_is_system_region(env, address)) {
11760 /* System space is always execute never */
11761 xn = 1;
11764 *prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
11765 if (*prot && !xn && !(pxn && !is_user)) {
11766 *prot |= PAGE_EXEC;
11768 /* We don't need to look the attribute up in the MAIR0/MAIR1
11769 * registers because that only tells us about cacheability.
11771 if (mregion) {
11772 *mregion = matchregion;
11776 fi->type = ARMFault_Permission;
11777 fi->level = 1;
11778 return !(*prot & (1 << access_type));
11782 static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
11783 MMUAccessType access_type, ARMMMUIdx mmu_idx,
11784 hwaddr *phys_ptr, MemTxAttrs *txattrs,
11785 int *prot, target_ulong *page_size,
11786 ARMMMUFaultInfo *fi)
11788 uint32_t secure = regime_is_secure(env, mmu_idx);
11789 V8M_SAttributes sattrs = {};
11790 bool ret;
11791 bool mpu_is_subpage;
11793 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
11794 v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs);
11795 if (access_type == MMU_INST_FETCH) {
11796 /* Instruction fetches always use the MMU bank and the
11797 * transaction attribute determined by the fetch address,
11798 * regardless of CPU state. This is painful for QEMU
11799 * to handle, because it would mean we need to encode
11800 * into the mmu_idx not just the (user, negpri) information
11801 * for the current security state but also that for the
11802 * other security state, which would balloon the number
11803 * of mmu_idx values needed alarmingly.
11804 * Fortunately we can avoid this because it's not actually
11805 * possible to arbitrarily execute code from memory with
11806 * the wrong security attribute: it will always generate
11807 * an exception of some kind or another, apart from the
11808 * special case of an NS CPU executing an SG instruction
11809 * in S&NSC memory. So we always just fail the translation
11810 * here and sort things out in the exception handler
11811 * (including possibly emulating an SG instruction).
11813 if (sattrs.ns != !secure) {
11814 if (sattrs.nsc) {
11815 fi->type = ARMFault_QEMU_NSCExec;
11816 } else {
11817 fi->type = ARMFault_QEMU_SFault;
11819 *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
11820 *phys_ptr = address;
11821 *prot = 0;
11822 return true;
11824 } else {
11825 /* For data accesses we always use the MMU bank indicated
11826 * by the current CPU state, but the security attributes
11827 * might downgrade a secure access to nonsecure.
11829 if (sattrs.ns) {
11830 txattrs->secure = false;
11831 } else if (!secure) {
11832 /* NS access to S memory must fault.
11833 * Architecturally we should first check whether the
11834 * MPU information for this address indicates that we
11835 * are doing an unaligned access to Device memory, which
11836 * should generate a UsageFault instead. QEMU does not
11837 * currently check for that kind of unaligned access though.
11838 * If we added it we would need to do so as a special case
11839 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
11841 fi->type = ARMFault_QEMU_SFault;
11842 *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
11843 *phys_ptr = address;
11844 *prot = 0;
11845 return true;
11850 ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr,
11851 txattrs, prot, &mpu_is_subpage, fi, NULL);
11852 *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
11853 return ret;
11856 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
11857 MMUAccessType access_type, ARMMMUIdx mmu_idx,
11858 hwaddr *phys_ptr, int *prot,
11859 ARMMMUFaultInfo *fi)
11861 int n;
11862 uint32_t mask;
11863 uint32_t base;
11864 bool is_user = regime_is_user(env, mmu_idx);
11866 if (regime_translation_disabled(env, mmu_idx)) {
11867 /* MPU disabled. */
11868 *phys_ptr = address;
11869 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
11870 return false;
11873 *phys_ptr = address;
11874 for (n = 7; n >= 0; n--) {
11875 base = env->cp15.c6_region[n];
11876 if ((base & 1) == 0) {
11877 continue;
11879 mask = 1 << ((base >> 1) & 0x1f);
11880 /* Keep this shift separate from the above to avoid an
11881 (undefined) << 32. */
11882 mask = (mask << 1) - 1;
11883 if (((base ^ address) & ~mask) == 0) {
11884 break;
11887 if (n < 0) {
11888 fi->type = ARMFault_Background;
11889 return true;
11892 if (access_type == MMU_INST_FETCH) {
11893 mask = env->cp15.pmsav5_insn_ap;
11894 } else {
11895 mask = env->cp15.pmsav5_data_ap;
11897 mask = (mask >> (n * 4)) & 0xf;
11898 switch (mask) {
11899 case 0:
11900 fi->type = ARMFault_Permission;
11901 fi->level = 1;
11902 return true;
11903 case 1:
11904 if (is_user) {
11905 fi->type = ARMFault_Permission;
11906 fi->level = 1;
11907 return true;
11909 *prot = PAGE_READ | PAGE_WRITE;
11910 break;
11911 case 2:
11912 *prot = PAGE_READ;
11913 if (!is_user) {
11914 *prot |= PAGE_WRITE;
11916 break;
11917 case 3:
11918 *prot = PAGE_READ | PAGE_WRITE;
11919 break;
11920 case 5:
11921 if (is_user) {
11922 fi->type = ARMFault_Permission;
11923 fi->level = 1;
11924 return true;
11926 *prot = PAGE_READ;
11927 break;
11928 case 6:
11929 *prot = PAGE_READ;
11930 break;
11931 default:
11932 /* Bad permission. */
11933 fi->type = ARMFault_Permission;
11934 fi->level = 1;
11935 return true;
11937 *prot |= PAGE_EXEC;
11938 return false;
11941 /* Combine either inner or outer cacheability attributes for normal
11942 * memory, according to table D4-42 and pseudocode procedure
11943 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
11945 * NB: only stage 1 includes allocation hints (RW bits), leading to
11946 * some asymmetry.
11948 static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2)
11950 if (s1 == 4 || s2 == 4) {
11951 /* non-cacheable has precedence */
11952 return 4;
11953 } else if (extract32(s1, 2, 2) == 0 || extract32(s1, 2, 2) == 2) {
11954 /* stage 1 write-through takes precedence */
11955 return s1;
11956 } else if (extract32(s2, 2, 2) == 2) {
11957 /* stage 2 write-through takes precedence, but the allocation hint
11958 * is still taken from stage 1
11960 return (2 << 2) | extract32(s1, 0, 2);
11961 } else { /* write-back */
11962 return s1;
11966 /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
11967 * and CombineS1S2Desc()
11969 * @s1: Attributes from stage 1 walk
11970 * @s2: Attributes from stage 2 walk
11972 static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2)
11974 uint8_t s1lo, s2lo, s1hi, s2hi;
11975 ARMCacheAttrs ret;
11976 bool tagged = false;
11978 if (s1.attrs == 0xf0) {
11979 tagged = true;
11980 s1.attrs = 0xff;
11983 s1lo = extract32(s1.attrs, 0, 4);
11984 s2lo = extract32(s2.attrs, 0, 4);
11985 s1hi = extract32(s1.attrs, 4, 4);
11986 s2hi = extract32(s2.attrs, 4, 4);
11988 /* Combine shareability attributes (table D4-43) */
11989 if (s1.shareability == 2 || s2.shareability == 2) {
11990 /* if either are outer-shareable, the result is outer-shareable */
11991 ret.shareability = 2;
11992 } else if (s1.shareability == 3 || s2.shareability == 3) {
11993 /* if either are inner-shareable, the result is inner-shareable */
11994 ret.shareability = 3;
11995 } else {
11996 /* both non-shareable */
11997 ret.shareability = 0;
12000 /* Combine memory type and cacheability attributes */
12001 if (s1hi == 0 || s2hi == 0) {
12002 /* Device has precedence over normal */
12003 if (s1lo == 0 || s2lo == 0) {
12004 /* nGnRnE has precedence over anything */
12005 ret.attrs = 0;
12006 } else if (s1lo == 4 || s2lo == 4) {
12007 /* non-Reordering has precedence over Reordering */
12008 ret.attrs = 4; /* nGnRE */
12009 } else if (s1lo == 8 || s2lo == 8) {
12010 /* non-Gathering has precedence over Gathering */
12011 ret.attrs = 8; /* nGRE */
12012 } else {
12013 ret.attrs = 0xc; /* GRE */
12016 /* Any location for which the resultant memory type is any
12017 * type of Device memory is always treated as Outer Shareable.
12019 ret.shareability = 2;
12020 } else { /* Normal memory */
12021 /* Outer/inner cacheability combine independently */
12022 ret.attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4
12023 | combine_cacheattr_nibble(s1lo, s2lo);
12025 if (ret.attrs == 0x44) {
12026 /* Any location for which the resultant memory type is Normal
12027 * Inner Non-cacheable, Outer Non-cacheable is always treated
12028 * as Outer Shareable.
12030 ret.shareability = 2;
12034 /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */
12035 if (tagged && ret.attrs == 0xff) {
12036 ret.attrs = 0xf0;
12039 return ret;
12043 /* get_phys_addr - get the physical address for this virtual address
12045 * Find the physical address corresponding to the given virtual address,
12046 * by doing a translation table walk on MMU based systems or using the
12047 * MPU state on MPU based systems.
12049 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
12050 * prot and page_size may not be filled in, and the populated fsr value provides
12051 * information on why the translation aborted, in the format of a
12052 * DFSR/IFSR fault register, with the following caveats:
12053 * * we honour the short vs long DFSR format differences.
12054 * * the WnR bit is never set (the caller must do this).
12055 * * for PSMAv5 based systems we don't bother to return a full FSR format
12056 * value.
12058 * @env: CPUARMState
12059 * @address: virtual address to get physical address for
12060 * @access_type: 0 for read, 1 for write, 2 for execute
12061 * @mmu_idx: MMU index indicating required translation regime
12062 * @phys_ptr: set to the physical address corresponding to the virtual address
12063 * @attrs: set to the memory transaction attributes to use
12064 * @prot: set to the permissions for the page containing phys_ptr
12065 * @page_size: set to the size of the page containing phys_ptr
12066 * @fi: set to fault info if the translation fails
12067 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
12069 bool get_phys_addr(CPUARMState *env, target_ulong address,
12070 MMUAccessType access_type, ARMMMUIdx mmu_idx,
12071 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
12072 target_ulong *page_size,
12073 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
12075 if (mmu_idx == ARMMMUIdx_E10_0 ||
12076 mmu_idx == ARMMMUIdx_E10_1 ||
12077 mmu_idx == ARMMMUIdx_E10_1_PAN) {
12078 /* Call ourselves recursively to do the stage 1 and then stage 2
12079 * translations.
12081 if (arm_feature(env, ARM_FEATURE_EL2)) {
12082 hwaddr ipa;
12083 int s2_prot;
12084 int ret;
12085 ARMCacheAttrs cacheattrs2 = {};
12087 ret = get_phys_addr(env, address, access_type,
12088 stage_1_mmu_idx(mmu_idx), &ipa, attrs,
12089 prot, page_size, fi, cacheattrs);
12091 /* If S1 fails or S2 is disabled, return early. */
12092 if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
12093 *phys_ptr = ipa;
12094 return ret;
12097 /* S1 is done. Now do S2 translation. */
12098 ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_Stage2,
12099 mmu_idx == ARMMMUIdx_E10_0,
12100 phys_ptr, attrs, &s2_prot,
12101 page_size, fi, &cacheattrs2);
12102 fi->s2addr = ipa;
12103 /* Combine the S1 and S2 perms. */
12104 *prot &= s2_prot;
12106 /* If S2 fails, return early. */
12107 if (ret) {
12108 return ret;
12111 /* Combine the S1 and S2 cache attributes. */
12112 if (env->cp15.hcr_el2 & HCR_DC) {
12114 * HCR.DC forces the first stage attributes to
12115 * Normal Non-Shareable,
12116 * Inner Write-Back Read-Allocate Write-Allocate,
12117 * Outer Write-Back Read-Allocate Write-Allocate.
12118 * Do not overwrite Tagged within attrs.
12120 if (cacheattrs->attrs != 0xf0) {
12121 cacheattrs->attrs = 0xff;
12123 cacheattrs->shareability = 0;
12125 *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2);
12126 return 0;
12127 } else {
12129 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
12131 mmu_idx = stage_1_mmu_idx(mmu_idx);
12135 /* The page table entries may downgrade secure to non-secure, but
12136 * cannot upgrade an non-secure translation regime's attributes
12137 * to secure.
12139 attrs->secure = regime_is_secure(env, mmu_idx);
12140 attrs->user = regime_is_user(env, mmu_idx);
12142 /* Fast Context Switch Extension. This doesn't exist at all in v8.
12143 * In v7 and earlier it affects all stage 1 translations.
12145 if (address < 0x02000000 && mmu_idx != ARMMMUIdx_Stage2
12146 && !arm_feature(env, ARM_FEATURE_V8)) {
12147 if (regime_el(env, mmu_idx) == 3) {
12148 address += env->cp15.fcseidr_s;
12149 } else {
12150 address += env->cp15.fcseidr_ns;
12154 if (arm_feature(env, ARM_FEATURE_PMSA)) {
12155 bool ret;
12156 *page_size = TARGET_PAGE_SIZE;
12158 if (arm_feature(env, ARM_FEATURE_V8)) {
12159 /* PMSAv8 */
12160 ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
12161 phys_ptr, attrs, prot, page_size, fi);
12162 } else if (arm_feature(env, ARM_FEATURE_V7)) {
12163 /* PMSAv7 */
12164 ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
12165 phys_ptr, prot, page_size, fi);
12166 } else {
12167 /* Pre-v7 MPU */
12168 ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
12169 phys_ptr, prot, fi);
12171 qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
12172 " mmu_idx %u -> %s (prot %c%c%c)\n",
12173 access_type == MMU_DATA_LOAD ? "reading" :
12174 (access_type == MMU_DATA_STORE ? "writing" : "execute"),
12175 (uint32_t)address, mmu_idx,
12176 ret ? "Miss" : "Hit",
12177 *prot & PAGE_READ ? 'r' : '-',
12178 *prot & PAGE_WRITE ? 'w' : '-',
12179 *prot & PAGE_EXEC ? 'x' : '-');
12181 return ret;
12184 /* Definitely a real MMU, not an MPU */
12186 if (regime_translation_disabled(env, mmu_idx)) {
12187 uint64_t hcr;
12188 uint8_t memattr;
12191 * MMU disabled. S1 addresses within aa64 translation regimes are
12192 * still checked for bounds -- see AArch64.TranslateAddressS1Off.
12194 if (mmu_idx != ARMMMUIdx_Stage2) {
12195 int r_el = regime_el(env, mmu_idx);
12196 if (arm_el_is_aa64(env, r_el)) {
12197 int pamax = arm_pamax(env_archcpu(env));
12198 uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr;
12199 int addrtop, tbi;
12201 tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
12202 if (access_type == MMU_INST_FETCH) {
12203 tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
12205 tbi = (tbi >> extract64(address, 55, 1)) & 1;
12206 addrtop = (tbi ? 55 : 63);
12208 if (extract64(address, pamax, addrtop - pamax + 1) != 0) {
12209 fi->type = ARMFault_AddressSize;
12210 fi->level = 0;
12211 fi->stage2 = false;
12212 return 1;
12216 * When TBI is disabled, we've just validated that all of the
12217 * bits above PAMax are zero, so logically we only need to
12218 * clear the top byte for TBI. But it's clearer to follow
12219 * the pseudocode set of addrdesc.paddress.
12221 address = extract64(address, 0, 52);
12224 *phys_ptr = address;
12225 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
12226 *page_size = TARGET_PAGE_SIZE;
12228 /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
12229 hcr = arm_hcr_el2_eff(env);
12230 cacheattrs->shareability = 0;
12231 if (hcr & HCR_DC) {
12232 if (hcr & HCR_DCT) {
12233 memattr = 0xf0; /* Tagged, Normal, WB, RWA */
12234 } else {
12235 memattr = 0xff; /* Normal, WB, RWA */
12237 } else if (access_type == MMU_INST_FETCH) {
12238 if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
12239 memattr = 0xee; /* Normal, WT, RA, NT */
12240 } else {
12241 memattr = 0x44; /* Normal, NC, No */
12243 cacheattrs->shareability = 2; /* outer sharable */
12244 } else {
12245 memattr = 0x00; /* Device, nGnRnE */
12247 cacheattrs->attrs = memattr;
12248 return 0;
12251 if (regime_using_lpae_format(env, mmu_idx)) {
12252 return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
12253 phys_ptr, attrs, prot, page_size,
12254 fi, cacheattrs);
12255 } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
12256 return get_phys_addr_v6(env, address, access_type, mmu_idx,
12257 phys_ptr, attrs, prot, page_size, fi);
12258 } else {
12259 return get_phys_addr_v5(env, address, access_type, mmu_idx,
12260 phys_ptr, prot, page_size, fi);
12264 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
12265 MemTxAttrs *attrs)
12267 ARMCPU *cpu = ARM_CPU(cs);
12268 CPUARMState *env = &cpu->env;
12269 hwaddr phys_addr;
12270 target_ulong page_size;
12271 int prot;
12272 bool ret;
12273 ARMMMUFaultInfo fi = {};
12274 ARMMMUIdx mmu_idx = arm_mmu_idx(env);
12275 ARMCacheAttrs cacheattrs = {};
12277 *attrs = (MemTxAttrs) {};
12279 ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr,
12280 attrs, &prot, &page_size, &fi, &cacheattrs);
12282 if (ret) {
12283 return -1;
12285 return phys_addr;
12288 #endif
12290 /* Note that signed overflow is undefined in C. The following routines are
12291 careful to use unsigned types where modulo arithmetic is required.
12292 Failure to do so _will_ break on newer gcc. */
12294 /* Signed saturating arithmetic. */
12296 /* Perform 16-bit signed saturating addition. */
12297 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
12299 uint16_t res;
12301 res = a + b;
12302 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
12303 if (a & 0x8000)
12304 res = 0x8000;
12305 else
12306 res = 0x7fff;
12308 return res;
12311 /* Perform 8-bit signed saturating addition. */
12312 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
12314 uint8_t res;
12316 res = a + b;
12317 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
12318 if (a & 0x80)
12319 res = 0x80;
12320 else
12321 res = 0x7f;
12323 return res;
12326 /* Perform 16-bit signed saturating subtraction. */
12327 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
12329 uint16_t res;
12331 res = a - b;
12332 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
12333 if (a & 0x8000)
12334 res = 0x8000;
12335 else
12336 res = 0x7fff;
12338 return res;
12341 /* Perform 8-bit signed saturating subtraction. */
12342 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
12344 uint8_t res;
12346 res = a - b;
12347 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
12348 if (a & 0x80)
12349 res = 0x80;
12350 else
12351 res = 0x7f;
12353 return res;
12356 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
12357 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
12358 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
12359 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
12360 #define PFX q
12362 #include "op_addsub.h"
12364 /* Unsigned saturating arithmetic. */
12365 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
12367 uint16_t res;
12368 res = a + b;
12369 if (res < a)
12370 res = 0xffff;
12371 return res;
12374 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
12376 if (a > b)
12377 return a - b;
12378 else
12379 return 0;
12382 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
12384 uint8_t res;
12385 res = a + b;
12386 if (res < a)
12387 res = 0xff;
12388 return res;
12391 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
12393 if (a > b)
12394 return a - b;
12395 else
12396 return 0;
12399 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
12400 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
12401 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
12402 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
12403 #define PFX uq
12405 #include "op_addsub.h"
12407 /* Signed modulo arithmetic. */
12408 #define SARITH16(a, b, n, op) do { \
12409 int32_t sum; \
12410 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
12411 RESULT(sum, n, 16); \
12412 if (sum >= 0) \
12413 ge |= 3 << (n * 2); \
12414 } while(0)
12416 #define SARITH8(a, b, n, op) do { \
12417 int32_t sum; \
12418 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
12419 RESULT(sum, n, 8); \
12420 if (sum >= 0) \
12421 ge |= 1 << n; \
12422 } while(0)
12425 #define ADD16(a, b, n) SARITH16(a, b, n, +)
12426 #define SUB16(a, b, n) SARITH16(a, b, n, -)
12427 #define ADD8(a, b, n) SARITH8(a, b, n, +)
12428 #define SUB8(a, b, n) SARITH8(a, b, n, -)
12429 #define PFX s
12430 #define ARITH_GE
12432 #include "op_addsub.h"
12434 /* Unsigned modulo arithmetic. */
12435 #define ADD16(a, b, n) do { \
12436 uint32_t sum; \
12437 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
12438 RESULT(sum, n, 16); \
12439 if ((sum >> 16) == 1) \
12440 ge |= 3 << (n * 2); \
12441 } while(0)
12443 #define ADD8(a, b, n) do { \
12444 uint32_t sum; \
12445 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
12446 RESULT(sum, n, 8); \
12447 if ((sum >> 8) == 1) \
12448 ge |= 1 << n; \
12449 } while(0)
12451 #define SUB16(a, b, n) do { \
12452 uint32_t sum; \
12453 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
12454 RESULT(sum, n, 16); \
12455 if ((sum >> 16) == 0) \
12456 ge |= 3 << (n * 2); \
12457 } while(0)
12459 #define SUB8(a, b, n) do { \
12460 uint32_t sum; \
12461 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
12462 RESULT(sum, n, 8); \
12463 if ((sum >> 8) == 0) \
12464 ge |= 1 << n; \
12465 } while(0)
12467 #define PFX u
12468 #define ARITH_GE
12470 #include "op_addsub.h"
12472 /* Halved signed arithmetic. */
12473 #define ADD16(a, b, n) \
12474 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
12475 #define SUB16(a, b, n) \
12476 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
12477 #define ADD8(a, b, n) \
12478 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
12479 #define SUB8(a, b, n) \
12480 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
12481 #define PFX sh
12483 #include "op_addsub.h"
12485 /* Halved unsigned arithmetic. */
12486 #define ADD16(a, b, n) \
12487 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
12488 #define SUB16(a, b, n) \
12489 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
12490 #define ADD8(a, b, n) \
12491 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
12492 #define SUB8(a, b, n) \
12493 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
12494 #define PFX uh
12496 #include "op_addsub.h"
12498 static inline uint8_t do_usad(uint8_t a, uint8_t b)
12500 if (a > b)
12501 return a - b;
12502 else
12503 return b - a;
12506 /* Unsigned sum of absolute byte differences. */
12507 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
12509 uint32_t sum;
12510 sum = do_usad(a, b);
12511 sum += do_usad(a >> 8, b >> 8);
12512 sum += do_usad(a >> 16, b >> 16);
12513 sum += do_usad(a >> 24, b >> 24);
12514 return sum;
12517 /* For ARMv6 SEL instruction. */
12518 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
12520 uint32_t mask;
12522 mask = 0;
12523 if (flags & 1)
12524 mask |= 0xff;
12525 if (flags & 2)
12526 mask |= 0xff00;
12527 if (flags & 4)
12528 mask |= 0xff0000;
12529 if (flags & 8)
12530 mask |= 0xff000000;
12531 return (a & mask) | (b & ~mask);
12534 /* CRC helpers.
12535 * The upper bytes of val (above the number specified by 'bytes') must have
12536 * been zeroed out by the caller.
12538 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
12540 uint8_t buf[4];
12542 stl_le_p(buf, val);
12544 /* zlib crc32 converts the accumulator and output to one's complement. */
12545 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
12548 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
12550 uint8_t buf[4];
12552 stl_le_p(buf, val);
12554 /* Linux crc32c converts the output to one's complement. */
12555 return crc32c(acc, buf, bytes) ^ 0xffffffff;
12558 /* Return the exception level to which FP-disabled exceptions should
12559 * be taken, or 0 if FP is enabled.
12561 int fp_exception_el(CPUARMState *env, int cur_el)
12563 #ifndef CONFIG_USER_ONLY
12564 /* CPACR and the CPTR registers don't exist before v6, so FP is
12565 * always accessible
12567 if (!arm_feature(env, ARM_FEATURE_V6)) {
12568 return 0;
12571 if (arm_feature(env, ARM_FEATURE_M)) {
12572 /* CPACR can cause a NOCP UsageFault taken to current security state */
12573 if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) {
12574 return 1;
12577 if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) {
12578 if (!extract32(env->v7m.nsacr, 10, 1)) {
12579 /* FP insns cause a NOCP UsageFault taken to Secure */
12580 return 3;
12584 return 0;
12587 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
12588 * 0, 2 : trap EL0 and EL1/PL1 accesses
12589 * 1 : trap only EL0 accesses
12590 * 3 : trap no accesses
12591 * This register is ignored if E2H+TGE are both set.
12593 if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
12594 int fpen = extract32(env->cp15.cpacr_el1, 20, 2);
12596 switch (fpen) {
12597 case 0:
12598 case 2:
12599 if (cur_el == 0 || cur_el == 1) {
12600 /* Trap to PL1, which might be EL1 or EL3 */
12601 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
12602 return 3;
12604 return 1;
12606 if (cur_el == 3 && !is_a64(env)) {
12607 /* Secure PL1 running at EL3 */
12608 return 3;
12610 break;
12611 case 1:
12612 if (cur_el == 0) {
12613 return 1;
12615 break;
12616 case 3:
12617 break;
12622 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
12623 * to control non-secure access to the FPU. It doesn't have any
12624 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
12626 if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
12627 cur_el <= 2 && !arm_is_secure_below_el3(env))) {
12628 if (!extract32(env->cp15.nsacr, 10, 1)) {
12629 /* FP insns act as UNDEF */
12630 return cur_el == 2 ? 2 : 1;
12634 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
12635 * check because zero bits in the registers mean "don't trap".
12638 /* CPTR_EL2 : present in v7VE or v8 */
12639 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1)
12640 && !arm_is_secure_below_el3(env)) {
12641 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
12642 return 2;
12645 /* CPTR_EL3 : present in v8 */
12646 if (extract32(env->cp15.cptr_el[3], 10, 1)) {
12647 /* Trap all FP ops to EL3 */
12648 return 3;
12650 #endif
12651 return 0;
12654 /* Return the exception level we're running at if this is our mmu_idx */
12655 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
12657 if (mmu_idx & ARM_MMU_IDX_M) {
12658 return mmu_idx & ARM_MMU_IDX_M_PRIV;
12661 switch (mmu_idx) {
12662 case ARMMMUIdx_E10_0:
12663 case ARMMMUIdx_E20_0:
12664 case ARMMMUIdx_SE10_0:
12665 return 0;
12666 case ARMMMUIdx_E10_1:
12667 case ARMMMUIdx_E10_1_PAN:
12668 case ARMMMUIdx_SE10_1:
12669 case ARMMMUIdx_SE10_1_PAN:
12670 return 1;
12671 case ARMMMUIdx_E2:
12672 case ARMMMUIdx_E20_2:
12673 case ARMMMUIdx_E20_2_PAN:
12674 return 2;
12675 case ARMMMUIdx_SE3:
12676 return 3;
12677 default:
12678 g_assert_not_reached();
12682 #ifndef CONFIG_TCG
12683 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
12685 g_assert_not_reached();
12687 #endif
12689 ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
12691 if (arm_feature(env, ARM_FEATURE_M)) {
12692 return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
12695 /* See ARM pseudo-function ELIsInHost. */
12696 switch (el) {
12697 case 0:
12698 if (arm_is_secure_below_el3(env)) {
12699 return ARMMMUIdx_SE10_0;
12701 if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)
12702 && arm_el_is_aa64(env, 2)) {
12703 return ARMMMUIdx_E20_0;
12705 return ARMMMUIdx_E10_0;
12706 case 1:
12707 if (arm_is_secure_below_el3(env)) {
12708 if (env->pstate & PSTATE_PAN) {
12709 return ARMMMUIdx_SE10_1_PAN;
12711 return ARMMMUIdx_SE10_1;
12713 if (env->pstate & PSTATE_PAN) {
12714 return ARMMMUIdx_E10_1_PAN;
12716 return ARMMMUIdx_E10_1;
12717 case 2:
12718 /* TODO: ARMv8.4-SecEL2 */
12719 /* Note that TGE does not apply at EL2. */
12720 if ((env->cp15.hcr_el2 & HCR_E2H) && arm_el_is_aa64(env, 2)) {
12721 if (env->pstate & PSTATE_PAN) {
12722 return ARMMMUIdx_E20_2_PAN;
12724 return ARMMMUIdx_E20_2;
12726 return ARMMMUIdx_E2;
12727 case 3:
12728 return ARMMMUIdx_SE3;
12729 default:
12730 g_assert_not_reached();
12734 ARMMMUIdx arm_mmu_idx(CPUARMState *env)
12736 return arm_mmu_idx_el(env, arm_current_el(env));
12739 #ifndef CONFIG_USER_ONLY
12740 ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
12742 return stage_1_mmu_idx(arm_mmu_idx(env));
12744 #endif
12746 static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el,
12747 ARMMMUIdx mmu_idx, uint32_t flags)
12749 flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el);
12750 flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX,
12751 arm_to_core_mmu_idx(mmu_idx));
12753 if (arm_singlestep_active(env)) {
12754 flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1);
12756 return flags;
12759 static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el,
12760 ARMMMUIdx mmu_idx, uint32_t flags)
12762 bool sctlr_b = arm_sctlr_b(env);
12764 if (sctlr_b) {
12765 flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, 1);
12767 if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) {
12768 flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1);
12770 flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env));
12772 return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
12775 static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el,
12776 ARMMMUIdx mmu_idx)
12778 uint32_t flags = 0;
12780 if (arm_v7m_is_handler_mode(env)) {
12781 flags = FIELD_DP32(flags, TBFLAG_M32, HANDLER, 1);
12785 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
12786 * is suppressing them because the requested execution priority
12787 * is less than 0.
12789 if (arm_feature(env, ARM_FEATURE_V8) &&
12790 !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
12791 (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
12792 flags = FIELD_DP32(flags, TBFLAG_M32, STACKCHECK, 1);
12795 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
12798 static uint32_t rebuild_hflags_aprofile(CPUARMState *env)
12800 int flags = 0;
12802 flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL,
12803 arm_debug_target_el(env));
12804 return flags;
12807 static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el,
12808 ARMMMUIdx mmu_idx)
12810 uint32_t flags = rebuild_hflags_aprofile(env);
12812 if (arm_el_is_aa64(env, 1)) {
12813 flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
12816 if (arm_current_el(env) < 2 && env->cp15.hstr_el2 &&
12817 (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
12818 flags = FIELD_DP32(flags, TBFLAG_A32, HSTR_ACTIVE, 1);
12821 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
12824 static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
12825 ARMMMUIdx mmu_idx)
12827 uint32_t flags = rebuild_hflags_aprofile(env);
12828 ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
12829 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
12830 uint64_t sctlr;
12831 int tbii, tbid;
12833 flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
12835 /* Get control bits for tagged addresses. */
12836 tbid = aa64_va_parameter_tbi(tcr, mmu_idx);
12837 tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx);
12839 flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii);
12840 flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid);
12842 if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
12843 int sve_el = sve_exception_el(env, el);
12844 uint32_t zcr_len;
12847 * If SVE is disabled, but FP is enabled,
12848 * then the effective len is 0.
12850 if (sve_el != 0 && fp_el == 0) {
12851 zcr_len = 0;
12852 } else {
12853 zcr_len = sve_zcr_len_for_el(env, el);
12855 flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el);
12856 flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
12859 sctlr = regime_sctlr(env, stage1);
12861 if (arm_cpu_data_is_big_endian_a64(el, sctlr)) {
12862 flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1);
12865 if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) {
12867 * In order to save space in flags, we record only whether
12868 * pauth is "inactive", meaning all insns are implemented as
12869 * a nop, or "active" when some action must be performed.
12870 * The decision of which action to take is left to a helper.
12872 if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
12873 flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1);
12877 if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
12878 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
12879 if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
12880 flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1);
12884 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
12885 if (!(env->pstate & PSTATE_UAO)) {
12886 switch (mmu_idx) {
12887 case ARMMMUIdx_E10_1:
12888 case ARMMMUIdx_E10_1_PAN:
12889 case ARMMMUIdx_SE10_1:
12890 case ARMMMUIdx_SE10_1_PAN:
12891 /* TODO: ARMv8.3-NV */
12892 flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1);
12893 break;
12894 case ARMMMUIdx_E20_2:
12895 case ARMMMUIdx_E20_2_PAN:
12896 /* TODO: ARMv8.4-SecEL2 */
12898 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
12899 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
12901 if (env->cp15.hcr_el2 & HCR_TGE) {
12902 flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1);
12904 break;
12905 default:
12906 break;
12910 if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
12912 * Set MTE_ACTIVE if any access may be Checked, and leave clear
12913 * if all accesses must be Unchecked:
12914 * 1) If no TBI, then there are no tags in the address to check,
12915 * 2) If Tag Check Override, then all accesses are Unchecked,
12916 * 3) If Tag Check Fail == 0, then Checked access have no effect,
12917 * 4) If no Allocation Tag Access, then all accesses are Unchecked.
12919 if (allocation_tag_access_enabled(env, el, sctlr)) {
12920 flags = FIELD_DP32(flags, TBFLAG_A64, ATA, 1);
12921 if (tbid
12922 && !(env->pstate & PSTATE_TCO)
12923 && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) {
12924 flags = FIELD_DP32(flags, TBFLAG_A64, MTE_ACTIVE, 1);
12927 /* And again for unprivileged accesses, if required. */
12928 if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV)
12929 && tbid
12930 && !(env->pstate & PSTATE_TCO)
12931 && (sctlr & SCTLR_TCF0)
12932 && allocation_tag_access_enabled(env, 0, sctlr)) {
12933 flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1);
12935 /* Cache TCMA as well as TBI. */
12936 flags = FIELD_DP32(flags, TBFLAG_A64, TCMA,
12937 aa64_va_parameter_tcma(tcr, mmu_idx));
12940 return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
12943 static uint32_t rebuild_hflags_internal(CPUARMState *env)
12945 int el = arm_current_el(env);
12946 int fp_el = fp_exception_el(env, el);
12947 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
12949 if (is_a64(env)) {
12950 return rebuild_hflags_a64(env, el, fp_el, mmu_idx);
12951 } else if (arm_feature(env, ARM_FEATURE_M)) {
12952 return rebuild_hflags_m32(env, fp_el, mmu_idx);
12953 } else {
12954 return rebuild_hflags_a32(env, fp_el, mmu_idx);
12958 void arm_rebuild_hflags(CPUARMState *env)
12960 env->hflags = rebuild_hflags_internal(env);
12964 * If we have triggered a EL state change we can't rely on the
12965 * translator having passed it to us, we need to recompute.
12967 void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env)
12969 int el = arm_current_el(env);
12970 int fp_el = fp_exception_el(env, el);
12971 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
12972 env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
12975 void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
12977 int fp_el = fp_exception_el(env, el);
12978 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
12980 env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
12984 * If we have triggered a EL state change we can't rely on the
12985 * translator having passed it to us, we need to recompute.
12987 void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env)
12989 int el = arm_current_el(env);
12990 int fp_el = fp_exception_el(env, el);
12991 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
12992 env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
12995 void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el)
12997 int fp_el = fp_exception_el(env, el);
12998 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
13000 env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
13003 void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el)
13005 int fp_el = fp_exception_el(env, el);
13006 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
13008 env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx);
13011 static inline void assert_hflags_rebuild_correctly(CPUARMState *env)
13013 #ifdef CONFIG_DEBUG_TCG
13014 uint32_t env_flags_current = env->hflags;
13015 uint32_t env_flags_rebuilt = rebuild_hflags_internal(env);
13017 if (unlikely(env_flags_current != env_flags_rebuilt)) {
13018 fprintf(stderr, "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n",
13019 env_flags_current, env_flags_rebuilt);
13020 abort();
13022 #endif
13025 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
13026 target_ulong *cs_base, uint32_t *pflags)
13028 uint32_t flags = env->hflags;
13029 uint32_t pstate_for_ss;
13031 *cs_base = 0;
13032 assert_hflags_rebuild_correctly(env);
13034 if (FIELD_EX32(flags, TBFLAG_ANY, AARCH64_STATE)) {
13035 *pc = env->pc;
13036 if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
13037 flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype);
13039 pstate_for_ss = env->pstate;
13040 } else {
13041 *pc = env->regs[15];
13043 if (arm_feature(env, ARM_FEATURE_M)) {
13044 if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
13045 FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S)
13046 != env->v7m.secure) {
13047 flags = FIELD_DP32(flags, TBFLAG_M32, FPCCR_S_WRONG, 1);
13050 if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) &&
13051 (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) ||
13052 (env->v7m.secure &&
13053 !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) {
13055 * ASPEN is set, but FPCA/SFPA indicate that there is no
13056 * active FP context; we must create a new FP context before
13057 * executing any FP insn.
13059 flags = FIELD_DP32(flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED, 1);
13062 bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK;
13063 if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) {
13064 flags = FIELD_DP32(flags, TBFLAG_M32, LSPACT, 1);
13066 } else {
13068 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
13069 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
13071 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
13072 flags = FIELD_DP32(flags, TBFLAG_A32,
13073 XSCALE_CPAR, env->cp15.c15_cpar);
13074 } else {
13075 flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN,
13076 env->vfp.vec_len);
13077 flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE,
13078 env->vfp.vec_stride);
13080 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
13081 flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
13085 flags = FIELD_DP32(flags, TBFLAG_AM32, THUMB, env->thumb);
13086 flags = FIELD_DP32(flags, TBFLAG_AM32, CONDEXEC, env->condexec_bits);
13087 pstate_for_ss = env->uncached_cpsr;
13091 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
13092 * states defined in the ARM ARM for software singlestep:
13093 * SS_ACTIVE PSTATE.SS State
13094 * 0 x Inactive (the TB flag for SS is always 0)
13095 * 1 0 Active-pending
13096 * 1 1 Active-not-pending
13097 * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB.
13099 if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) &&
13100 (pstate_for_ss & PSTATE_SS)) {
13101 flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1);
13104 *pflags = flags;
13107 #ifdef TARGET_AARCH64
13109 * The manual says that when SVE is enabled and VQ is widened the
13110 * implementation is allowed to zero the previously inaccessible
13111 * portion of the registers. The corollary to that is that when
13112 * SVE is enabled and VQ is narrowed we are also allowed to zero
13113 * the now inaccessible portion of the registers.
13115 * The intent of this is that no predicate bit beyond VQ is ever set.
13116 * Which means that some operations on predicate registers themselves
13117 * may operate on full uint64_t or even unrolled across the maximum
13118 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
13119 * may well be cheaper than conditionals to restrict the operation
13120 * to the relevant portion of a uint16_t[16].
13122 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
13124 int i, j;
13125 uint64_t pmask;
13127 assert(vq >= 1 && vq <= ARM_MAX_VQ);
13128 assert(vq <= env_archcpu(env)->sve_max_vq);
13130 /* Zap the high bits of the zregs. */
13131 for (i = 0; i < 32; i++) {
13132 memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq));
13135 /* Zap the high bits of the pregs and ffr. */
13136 pmask = 0;
13137 if (vq & 3) {
13138 pmask = ~(-1ULL << (16 * (vq & 3)));
13140 for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) {
13141 for (i = 0; i < 17; ++i) {
13142 env->vfp.pregs[i].p[j] &= pmask;
13144 pmask = 0;
13149 * Notice a change in SVE vector size when changing EL.
13151 void aarch64_sve_change_el(CPUARMState *env, int old_el,
13152 int new_el, bool el0_a64)
13154 ARMCPU *cpu = env_archcpu(env);
13155 int old_len, new_len;
13156 bool old_a64, new_a64;
13158 /* Nothing to do if no SVE. */
13159 if (!cpu_isar_feature(aa64_sve, cpu)) {
13160 return;
13163 /* Nothing to do if FP is disabled in either EL. */
13164 if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) {
13165 return;
13169 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
13170 * at ELx, or not available because the EL is in AArch32 state, then
13171 * for all purposes other than a direct read, the ZCR_ELx.LEN field
13172 * has an effective value of 0".
13174 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
13175 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
13176 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
13177 * we already have the correct register contents when encountering the
13178 * vq0->vq0 transition between EL0->EL1.
13180 old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64;
13181 old_len = (old_a64 && !sve_exception_el(env, old_el)
13182 ? sve_zcr_len_for_el(env, old_el) : 0);
13183 new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64;
13184 new_len = (new_a64 && !sve_exception_el(env, new_el)
13185 ? sve_zcr_len_for_el(env, new_el) : 0);
13187 /* When changing vector length, clear inaccessible state. */
13188 if (new_len < old_len) {
13189 aarch64_sve_narrow_vq(env, new_len + 1);
13192 #endif