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gitlab-CI: Test 32-bit builds with the fedora-i386-cross container
[qemu/ar7.git] / hw / sparc / sun4m.c
blob8686371318262c6094bfd616fd0bb01583305eed
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qapi/error.h"
28 #include "qemu/datadir.h"
29 #include "qemu-common.h"
30 #include "cpu.h"
31 #include "hw/sysbus.h"
32 #include "qemu/error-report.h"
33 #include "qemu/timer.h"
34 #include "hw/sparc/sun4m_iommu.h"
35 #include "hw/rtc/m48t59.h"
36 #include "migration/vmstate.h"
37 #include "hw/sparc/sparc32_dma.h"
38 #include "hw/block/fdc.h"
39 #include "sysemu/reset.h"
40 #include "sysemu/runstate.h"
41 #include "sysemu/sysemu.h"
42 #include "net/net.h"
43 #include "hw/boards.h"
44 #include "hw/scsi/esp.h"
45 #include "hw/nvram/sun_nvram.h"
46 #include "hw/qdev-properties.h"
47 #include "hw/nvram/chrp_nvram.h"
48 #include "hw/nvram/fw_cfg.h"
49 #include "hw/char/escc.h"
50 #include "hw/misc/empty_slot.h"
51 #include "hw/misc/unimp.h"
52 #include "hw/irq.h"
53 #include "hw/loader.h"
54 #include "elf.h"
55 #include "trace.h"
56 #include "qom/object.h"
57
58 /*
59 * Sun4m architecture was used in the following machines:
60 *
61 * SPARCserver 6xxMP/xx
62 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
63 * SPARCclassic X (4/10)
64 * SPARCstation LX/ZX (4/30)
65 * SPARCstation Voyager
66 * SPARCstation 10/xx, SPARCserver 10/xx
67 * SPARCstation 5, SPARCserver 5
68 * SPARCstation 20/xx, SPARCserver 20
69 * SPARCstation 4
70 *
71 * See for example: http://www.sunhelp.org/faq/sunref1.html
72 */
73
74 #define KERNEL_LOAD_ADDR 0x00004000
75 #define CMDLINE_ADDR 0x007ff000
76 #define INITRD_LOAD_ADDR 0x00800000
77 #define PROM_SIZE_MAX (1 * MiB)
78 #define PROM_VADDR 0xffd00000
79 #define PROM_FILENAME "openbios-sparc32"
80 #define CFG_ADDR 0xd00000510ULL
81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
82 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
83 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
84
85 #define MAX_CPUS 16
86 #define MAX_PILS 16
87 #define MAX_VSIMMS 4
88
89 #define ESCC_CLOCK 4915200
90
91 struct sun4m_hwdef {
92 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
93 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
94 hwaddr serial_base, fd_base;
95 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
96 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
97 hwaddr bpp_base, dbri_base, sx_base;
98 struct {
99 hwaddr reg_base, vram_base;
100 } vsimm[MAX_VSIMMS];
101 hwaddr ecc_base;
102 uint64_t max_mem;
103 uint32_t ecc_version;
104 uint32_t iommu_version;
105 uint16_t machine_id;
106 uint8_t nvram_machine_id;
107 };
108
109 const char *fw_cfg_arch_key_name(uint16_t key)
110 {
111 static const struct {
112 uint16_t key;
113 const char *name;
114 } fw_cfg_arch_wellknown_keys[] = {
115 {FW_CFG_SUN4M_DEPTH, "depth"},
116 {FW_CFG_SUN4M_WIDTH, "width"},
117 {FW_CFG_SUN4M_HEIGHT, "height"},
118 };
119
120 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
121 if (fw_cfg_arch_wellknown_keys[i].key == key) {
122 return fw_cfg_arch_wellknown_keys[i].name;
123 }
124 }
125 return NULL;
126 }
127
128 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
129 Error **errp)
130 {
131 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
132 }
133
134 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
135 const char *cmdline, const char *boot_devices,
136 ram_addr_t RAM_size, uint32_t kernel_size,
137 int width, int height, int depth,
138 int nvram_machine_id, const char *arch)
139 {
140 unsigned int i;
141 int sysp_end;
142 uint8_t image[0x1ff0];
143 NvramClass *k = NVRAM_GET_CLASS(nvram);
144
145 memset(image, '\0', sizeof(image));
146
147 /* OpenBIOS nvram variables partition */
148 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0);
149
150 /* Free space partition */
151 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
152
153 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
154 nvram_machine_id);
155
156 for (i = 0; i < sizeof(image); i++) {
157 (k->write)(nvram, i, image[i]);
158 }
159 }
160
161 void cpu_check_irqs(CPUSPARCState *env)
162 {
163 CPUState *cs;
164
165 /* We should be holding the BQL before we mess with IRQs */
166 g_assert(qemu_mutex_iothread_locked());
167
168 if (env->pil_in && (env->interrupt_index == 0 ||
169 (env->interrupt_index & ~15) == TT_EXTINT)) {
170 unsigned int i;
171
172 for (i = 15; i > 0; i--) {
173 if (env->pil_in & (1 << i)) {
174 int old_interrupt = env->interrupt_index;
175
176 env->interrupt_index = TT_EXTINT | i;
177 if (old_interrupt != env->interrupt_index) {
178 cs = env_cpu(env);
179 trace_sun4m_cpu_interrupt(i);
180 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
181 }
182 break;
183 }
184 }
185 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
186 cs = env_cpu(env);
187 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
188 env->interrupt_index = 0;
189 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
190 }
191 }
192
193 static void cpu_kick_irq(SPARCCPU *cpu)
194 {
195 CPUSPARCState *env = &cpu->env;
196 CPUState *cs = CPU(cpu);
197
198 cs->halted = 0;
199 cpu_check_irqs(env);
200 qemu_cpu_kick(cs);
201 }
202
203 static void cpu_set_irq(void *opaque, int irq, int level)
204 {
205 SPARCCPU *cpu = opaque;
206 CPUSPARCState *env = &cpu->env;
207
208 if (level) {
209 trace_sun4m_cpu_set_irq_raise(irq);
210 env->pil_in |= 1 << irq;
211 cpu_kick_irq(cpu);
212 } else {
213 trace_sun4m_cpu_set_irq_lower(irq);
214 env->pil_in &= ~(1 << irq);
215 cpu_check_irqs(env);
216 }
217 }
218
219 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
220 {
221 }
222
223 static void sun4m_cpu_reset(void *opaque)
224 {
225 SPARCCPU *cpu = opaque;
226 CPUState *cs = CPU(cpu);
227
228 cpu_reset(cs);
229 }
230
231 static void cpu_halt_signal(void *opaque, int irq, int level)
232 {
233 if (level && current_cpu) {
234 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
235 }
236 }
237
238 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
239 {
240 return addr - 0xf0000000ULL;
241 }
242
243 static unsigned long sun4m_load_kernel(const char *kernel_filename,
244 const char *initrd_filename,
245 ram_addr_t RAM_size,
246 uint32_t *initrd_size)
247 {
248 int linux_boot;
249 unsigned int i;
250 long kernel_size;
251 uint8_t *ptr;
252
253 linux_boot = (kernel_filename != NULL);
254
255 kernel_size = 0;
256 if (linux_boot) {
257 int bswap_needed;
258
259 #ifdef BSWAP_NEEDED
260 bswap_needed = 1;
261 #else
262 bswap_needed = 0;
263 #endif
264 kernel_size = load_elf(kernel_filename, NULL,
265 translate_kernel_address, NULL,
266 NULL, NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
267 if (kernel_size < 0)
268 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
269 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
270 TARGET_PAGE_SIZE);
271 if (kernel_size < 0)
272 kernel_size = load_image_targphys(kernel_filename,
273 KERNEL_LOAD_ADDR,
274 RAM_size - KERNEL_LOAD_ADDR);
275 if (kernel_size < 0) {
276 error_report("could not load kernel '%s'", kernel_filename);
277 exit(1);
278 }
279
280 /* load initrd */
281 *initrd_size = 0;
282 if (initrd_filename) {
283 *initrd_size = load_image_targphys(initrd_filename,
284 INITRD_LOAD_ADDR,
285 RAM_size - INITRD_LOAD_ADDR);
286 if ((int)*initrd_size < 0) {
287 error_report("could not load initial ram disk '%s'",
288 initrd_filename);
289 exit(1);
290 }
291 }
292 if (*initrd_size > 0) {
293 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
294 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24);
295 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */
296 stl_p(ptr + 16, INITRD_LOAD_ADDR);
297 stl_p(ptr + 20, *initrd_size);
298 break;
299 }
300 }
301 }
302 }
303 return kernel_size;
304 }
305
306 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
307 {
308 DeviceState *dev;
309 SysBusDevice *s;
310
311 dev = qdev_new(TYPE_SUN4M_IOMMU);
312 qdev_prop_set_uint32(dev, "version", version);
313 s = SYS_BUS_DEVICE(dev);
314 sysbus_realize_and_unref(s, &error_fatal);
315 sysbus_connect_irq(s, 0, irq);
316 sysbus_mmio_map(s, 0, addr);
317
318 return s;
319 }
320
321 static void *sparc32_dma_init(hwaddr dma_base,
322 hwaddr esp_base, qemu_irq espdma_irq,
323 hwaddr le_base, qemu_irq ledma_irq, NICInfo *nd)
324 {
325 DeviceState *dma;
326 ESPDMADeviceState *espdma;
327 LEDMADeviceState *ledma;
328 SysBusESPState *esp;
329 SysBusPCNetState *lance;
330
331 dma = qdev_new(TYPE_SPARC32_DMA);
332 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
333 OBJECT(dma), "espdma"));
334 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
335
336 esp = ESP(object_resolve_path_component(OBJECT(espdma), "esp"));
337
338 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
339 OBJECT(dma), "ledma"));
340 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
341
342 lance = SYSBUS_PCNET(object_resolve_path_component(
343 OBJECT(ledma), "lance"));
344 qdev_set_nic_properties(DEVICE(lance), nd);
345
346 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
347 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
348
349 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
350 scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
351
352 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
353
354 return dma;
355 }
356
357 static DeviceState *slavio_intctl_init(hwaddr addr,
358 hwaddr addrg,
359 qemu_irq **parent_irq)
360 {
361 DeviceState *dev;
362 SysBusDevice *s;
363 unsigned int i, j;
364
365 dev = qdev_new("slavio_intctl");
366
367 s = SYS_BUS_DEVICE(dev);
368 sysbus_realize_and_unref(s, &error_fatal);
369
370 for (i = 0; i < MAX_CPUS; i++) {
371 for (j = 0; j < MAX_PILS; j++) {
372 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
373 }
374 }
375 sysbus_mmio_map(s, 0, addrg);
376 for (i = 0; i < MAX_CPUS; i++) {
377 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
378 }
379
380 return dev;
381 }
382
383 #define SYS_TIMER_OFFSET 0x10000ULL
384 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
385
386 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
387 qemu_irq *cpu_irqs, unsigned int num_cpus)
388 {
389 DeviceState *dev;
390 SysBusDevice *s;
391 unsigned int i;
392
393 dev = qdev_new("slavio_timer");
394 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
395 s = SYS_BUS_DEVICE(dev);
396 sysbus_realize_and_unref(s, &error_fatal);
397 sysbus_connect_irq(s, 0, master_irq);
398 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
399
400 for (i = 0; i < MAX_CPUS; i++) {
401 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
402 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
403 }
404 }
405
406 static qemu_irq slavio_system_powerdown;
407
408 static void slavio_powerdown_req(Notifier *n, void *opaque)
409 {
410 qemu_irq_raise(slavio_system_powerdown);
411 }
412
413 static Notifier slavio_system_powerdown_notifier = {
414 .notify = slavio_powerdown_req
415 };
416
417 #define MISC_LEDS 0x01600000
418 #define MISC_CFG 0x01800000
419 #define MISC_DIAG 0x01a00000
420 #define MISC_MDM 0x01b00000
421 #define MISC_SYS 0x01f00000
422
423 static void slavio_misc_init(hwaddr base,
424 hwaddr aux1_base,
425 hwaddr aux2_base, qemu_irq irq,
426 qemu_irq fdc_tc)
427 {
428 DeviceState *dev;
429 SysBusDevice *s;
430
431 dev = qdev_new("slavio_misc");
432 s = SYS_BUS_DEVICE(dev);
433 sysbus_realize_and_unref(s, &error_fatal);
434 if (base) {
435 /* 8 bit registers */
436 /* Slavio control */
437 sysbus_mmio_map(s, 0, base + MISC_CFG);
438 /* Diagnostics */
439 sysbus_mmio_map(s, 1, base + MISC_DIAG);
440 /* Modem control */
441 sysbus_mmio_map(s, 2, base + MISC_MDM);
442 /* 16 bit registers */
443 /* ss600mp diag LEDs */
444 sysbus_mmio_map(s, 3, base + MISC_LEDS);
445 /* 32 bit registers */
446 /* System control */
447 sysbus_mmio_map(s, 4, base + MISC_SYS);
448 }
449 if (aux1_base) {
450 /* AUX 1 (Misc System Functions) */
451 sysbus_mmio_map(s, 5, aux1_base);
452 }
453 if (aux2_base) {
454 /* AUX 2 (Software Powerdown Control) */
455 sysbus_mmio_map(s, 6, aux2_base);
456 }
457 sysbus_connect_irq(s, 0, irq);
458 sysbus_connect_irq(s, 1, fdc_tc);
459 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
460 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
461 }
462
463 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
464 {
465 DeviceState *dev;
466 SysBusDevice *s;
467
468 dev = qdev_new("eccmemctl");
469 qdev_prop_set_uint32(dev, "version", version);
470 s = SYS_BUS_DEVICE(dev);
471 sysbus_realize_and_unref(s, &error_fatal);
472 sysbus_connect_irq(s, 0, irq);
473 sysbus_mmio_map(s, 0, base);
474 if (version == 0) { // SS-600MP only
475 sysbus_mmio_map(s, 1, base + 0x1000);
476 }
477 }
478
479 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
480 {
481 DeviceState *dev;
482 SysBusDevice *s;
483
484 dev = qdev_new("apc");
485 s = SYS_BUS_DEVICE(dev);
486 sysbus_realize_and_unref(s, &error_fatal);
487 /* Power management (APC) XXX: not a Slavio device */
488 sysbus_mmio_map(s, 0, power_base);
489 sysbus_connect_irq(s, 0, cpu_halt);
490 }
491
492 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
493 int height, int depth)
494 {
495 DeviceState *dev;
496 SysBusDevice *s;
497
498 dev = qdev_new("SUNW,tcx");
499 qdev_prop_set_uint32(dev, "vram_size", vram_size);
500 qdev_prop_set_uint16(dev, "width", width);
501 qdev_prop_set_uint16(dev, "height", height);
502 qdev_prop_set_uint16(dev, "depth", depth);
503 s = SYS_BUS_DEVICE(dev);
504 sysbus_realize_and_unref(s, &error_fatal);
505
506 /* 10/ROM : FCode ROM */
507 sysbus_mmio_map(s, 0, addr);
508 /* 2/STIP : Stipple */
509 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
510 /* 3/BLIT : Blitter */
511 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
512 /* 5/RSTIP : Raw Stipple */
513 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
514 /* 6/RBLIT : Raw Blitter */
515 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
516 /* 7/TEC : Transform Engine */
517 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
518 /* 8/CMAP : DAC */
519 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
520 /* 9/THC : */
521 if (depth == 8) {
522 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
523 } else {
524 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
525 }
526 /* 11/DHC : */
527 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
528 /* 12/ALT : */
529 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
530 /* 0/DFB8 : 8-bit plane */
531 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
532 /* 1/DFB24 : 24bit plane */
533 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
534 /* 4/RDFB32: Raw framebuffer. Control plane */
535 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
536 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
537 if (depth == 8) {
538 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
539 }
540
541 sysbus_connect_irq(s, 0, irq);
542 }
543
544 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
545 int height, int depth)
546 {
547 DeviceState *dev;
548 SysBusDevice *s;
549
550 dev = qdev_new("cgthree");
551 qdev_prop_set_uint32(dev, "vram-size", vram_size);
552 qdev_prop_set_uint16(dev, "width", width);
553 qdev_prop_set_uint16(dev, "height", height);
554 qdev_prop_set_uint16(dev, "depth", depth);
555 s = SYS_BUS_DEVICE(dev);
556 sysbus_realize_and_unref(s, &error_fatal);
557
558 /* FCode ROM */
559 sysbus_mmio_map(s, 0, addr);
560 /* DAC */
561 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
562 /* 8-bit plane */
563 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
564
565 sysbus_connect_irq(s, 0, irq);
566 }
567
568 /* NCR89C100/MACIO Internal ID register */
569
570 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
571
572 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
573
574 static void idreg_init(hwaddr addr)
575 {
576 DeviceState *dev;
577 SysBusDevice *s;
578
579 dev = qdev_new(TYPE_MACIO_ID_REGISTER);
580 s = SYS_BUS_DEVICE(dev);
581 sysbus_realize_and_unref(s, &error_fatal);
582
583 sysbus_mmio_map(s, 0, addr);
584 address_space_write_rom(&address_space_memory, addr,
585 MEMTXATTRS_UNSPECIFIED,
586 idreg_data, sizeof(idreg_data));
587 }
588
589 OBJECT_DECLARE_SIMPLE_TYPE(IDRegState, MACIO_ID_REGISTER)
590
591 struct IDRegState {
592 SysBusDevice parent_obj;
593
594 MemoryRegion mem;
595 };
596
597 static void idreg_realize(DeviceState *ds, Error **errp)
598 {
599 IDRegState *s = MACIO_ID_REGISTER(ds);
600 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
601 Error *local_err = NULL;
602
603 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg",
604 sizeof(idreg_data), &local_err);
605 if (local_err) {
606 error_propagate(errp, local_err);
607 return;
608 }
609
610 vmstate_register_ram_global(&s->mem);
611 memory_region_set_readonly(&s->mem, true);
612 sysbus_init_mmio(dev, &s->mem);
613 }
614
615 static void idreg_class_init(ObjectClass *oc, void *data)
616 {
617 DeviceClass *dc = DEVICE_CLASS(oc);
618
619 dc->realize = idreg_realize;
620 }
621
622 static const TypeInfo idreg_info = {
623 .name = TYPE_MACIO_ID_REGISTER,
624 .parent = TYPE_SYS_BUS_DEVICE,
625 .instance_size = sizeof(IDRegState),
626 .class_init = idreg_class_init,
627 };
628
629 #define TYPE_TCX_AFX "tcx_afx"
630 OBJECT_DECLARE_SIMPLE_TYPE(AFXState, TCX_AFX)
631
632 struct AFXState {
633 SysBusDevice parent_obj;
634
635 MemoryRegion mem;
636 };
637
638 /* SS-5 TCX AFX register */
639 static void afx_init(hwaddr addr)
640 {
641 DeviceState *dev;
642 SysBusDevice *s;
643
644 dev = qdev_new(TYPE_TCX_AFX);
645 s = SYS_BUS_DEVICE(dev);
646 sysbus_realize_and_unref(s, &error_fatal);
647
648 sysbus_mmio_map(s, 0, addr);
649 }
650
651 static void afx_realize(DeviceState *ds, Error **errp)
652 {
653 AFXState *s = TCX_AFX(ds);
654 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
655 Error *local_err = NULL;
656
657 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4,
658 &local_err);
659 if (local_err) {
660 error_propagate(errp, local_err);
661 return;
662 }
663
664 vmstate_register_ram_global(&s->mem);
665 sysbus_init_mmio(dev, &s->mem);
666 }
667
668 static void afx_class_init(ObjectClass *oc, void *data)
669 {
670 DeviceClass *dc = DEVICE_CLASS(oc);
671
672 dc->realize = afx_realize;
673 }
674
675 static const TypeInfo afx_info = {
676 .name = TYPE_TCX_AFX,
677 .parent = TYPE_SYS_BUS_DEVICE,
678 .instance_size = sizeof(AFXState),
679 .class_init = afx_class_init,
680 };
681
682 #define TYPE_OPENPROM "openprom"
683 typedef struct PROMState PROMState;
684 DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM,
685 TYPE_OPENPROM)
686
687 struct PROMState {
688 SysBusDevice parent_obj;
689
690 MemoryRegion prom;
691 };
692
693 /* Boot PROM (OpenBIOS) */
694 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
695 {
696 hwaddr *base_addr = (hwaddr *)opaque;
697 return addr + *base_addr - PROM_VADDR;
698 }
699
700 static void prom_init(hwaddr addr, const char *bios_name)
701 {
702 DeviceState *dev;
703 SysBusDevice *s;
704 char *filename;
705 int ret;
706
707 dev = qdev_new(TYPE_OPENPROM);
708 s = SYS_BUS_DEVICE(dev);
709 sysbus_realize_and_unref(s, &error_fatal);
710
711 sysbus_mmio_map(s, 0, addr);
712
713 /* load boot prom */
714 if (bios_name == NULL) {
715 bios_name = PROM_FILENAME;
716 }
717 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
718 if (filename) {
719 ret = load_elf(filename, NULL,
720 translate_prom_address, &addr, NULL,
721 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
722 if (ret < 0 || ret > PROM_SIZE_MAX) {
723 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
724 }
725 g_free(filename);
726 } else {
727 ret = -1;
728 }
729 if (ret < 0 || ret > PROM_SIZE_MAX) {
730 error_report("could not load prom '%s'", bios_name);
731 exit(1);
732 }
733 }
734
735 static void prom_realize(DeviceState *ds, Error **errp)
736 {
737 PROMState *s = OPENPROM(ds);
738 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
739 Error *local_err = NULL;
740
741 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom",
742 PROM_SIZE_MAX, &local_err);
743 if (local_err) {
744 error_propagate(errp, local_err);
745 return;
746 }
747
748 vmstate_register_ram_global(&s->prom);
749 memory_region_set_readonly(&s->prom, true);
750 sysbus_init_mmio(dev, &s->prom);
751 }
752
753 static Property prom_properties[] = {
754 {/* end of property list */},
755 };
756
757 static void prom_class_init(ObjectClass *klass, void *data)
758 {
759 DeviceClass *dc = DEVICE_CLASS(klass);
760
761 device_class_set_props(dc, prom_properties);
762 dc->realize = prom_realize;
763 }
764
765 static const TypeInfo prom_info = {
766 .name = TYPE_OPENPROM,
767 .parent = TYPE_SYS_BUS_DEVICE,
768 .instance_size = sizeof(PROMState),
769 .class_init = prom_class_init,
770 };
771
772 #define TYPE_SUN4M_MEMORY "memory"
773 typedef struct RamDevice RamDevice;
774 DECLARE_INSTANCE_CHECKER(RamDevice, SUN4M_RAM,
775 TYPE_SUN4M_MEMORY)
776
777 struct RamDevice {
778 SysBusDevice parent_obj;
779 HostMemoryBackend *memdev;
780 };
781
782 /* System RAM */
783 static void ram_realize(DeviceState *dev, Error **errp)
784 {
785 RamDevice *d = SUN4M_RAM(dev);
786 MemoryRegion *ram = host_memory_backend_get_memory(d->memdev);
787
788 sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram);
789 }
790
791 static void ram_initfn(Object *obj)
792 {
793 RamDevice *d = SUN4M_RAM(obj);
794 object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND,
795 (Object **)&d->memdev,
796 object_property_allow_set_link,
797 OBJ_PROP_LINK_STRONG);
798 object_property_set_description(obj, "memdev", "Set RAM backend"
799 "Valid value is ID of a hostmem backend");
800 }
801
802 static void ram_class_init(ObjectClass *klass, void *data)
803 {
804 DeviceClass *dc = DEVICE_CLASS(klass);
805
806 dc->realize = ram_realize;
807 }
808
809 static const TypeInfo ram_info = {
810 .name = TYPE_SUN4M_MEMORY,
811 .parent = TYPE_SYS_BUS_DEVICE,
812 .instance_size = sizeof(RamDevice),
813 .instance_init = ram_initfn,
814 .class_init = ram_class_init,
815 };
816
817 static void cpu_devinit(const char *cpu_type, unsigned int id,
818 uint64_t prom_addr, qemu_irq **cpu_irqs)
819 {
820 SPARCCPU *cpu;
821 CPUSPARCState *env;
822
823 cpu = SPARC_CPU(object_new(cpu_type));
824 env = &cpu->env;
825
826 cpu_sparc_set_id(env, id);
827 qemu_register_reset(sun4m_cpu_reset, cpu);
828 object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0,
829 &error_fatal);
830 qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal);
831 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
832 env->prom_addr = prom_addr;
833 }
834
835 static void dummy_fdc_tc(void *opaque, int irq, int level)
836 {
837 }
838
839 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
840 MachineState *machine)
841 {
842 DeviceState *slavio_intctl;
843 unsigned int i;
844 Nvram *nvram;
845 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
846 qemu_irq fdc_tc;
847 unsigned long kernel_size;
848 uint32_t initrd_size;
849 DriveInfo *fd[MAX_FD];
850 FWCfgState *fw_cfg;
851 DeviceState *dev;
852 SysBusDevice *s;
853 unsigned int smp_cpus = machine->smp.cpus;
854 unsigned int max_cpus = machine->smp.max_cpus;
855 Object *ram_memdev = object_resolve_path_type(machine->ram_memdev_id,
856 TYPE_MEMORY_BACKEND, NULL);
857 NICInfo *nd = &nd_table[0];
858
859 if (machine->ram_size > hwdef->max_mem) {
860 error_report("Too much memory for this machine: %" PRId64 ","
861 " maximum %" PRId64,
862 machine->ram_size / MiB, hwdef->max_mem / MiB);
863 exit(1);
864 }
865
866 /* init CPUs */
867 for(i = 0; i < smp_cpus; i++) {
868 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
869 }
870
871 for (i = smp_cpus; i < MAX_CPUS; i++)
872 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
873
874 /* Create and map RAM frontend */
875 dev = qdev_new("memory");
876 object_property_set_link(OBJECT(dev), "memdev", ram_memdev, &error_fatal);
877 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
878 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0);
879
880 /* models without ECC don't trap when missing ram is accessed */
881 if (!hwdef->ecc_base) {
882 empty_slot_init("ecc", machine->ram_size,
883 hwdef->max_mem - machine->ram_size);
884 }
885
886 prom_init(hwdef->slavio_base, machine->firmware);
887
888 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
889 hwdef->intctl_base + 0x10000ULL,
890 cpu_irqs);
891
892 for (i = 0; i < 32; i++) {
893 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
894 }
895 for (i = 0; i < MAX_CPUS; i++) {
896 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
897 }
898
899 if (hwdef->idreg_base) {
900 idreg_init(hwdef->idreg_base);
901 }
902
903 if (hwdef->afx_base) {
904 afx_init(hwdef->afx_base);
905 }
906
907 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
908
909 if (hwdef->iommu_pad_base) {
910 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
911 Software shouldn't use aliased addresses, neither should it crash
912 when does. Using empty_slot instead of aliasing can help with
913 debugging such accesses */
914 empty_slot_init("iommu.alias",
915 hwdef->iommu_pad_base, hwdef->iommu_pad_len);
916 }
917
918 qemu_check_nic_model(nd, TYPE_LANCE);
919 sparc32_dma_init(hwdef->dma_base,
920 hwdef->esp_base, slavio_irq[18],
921 hwdef->le_base, slavio_irq[16], nd);
922
923 if (graphic_depth != 8 && graphic_depth != 24) {
924 error_report("Unsupported depth: %d", graphic_depth);
925 exit (1);
926 }
927 if (vga_interface_type != VGA_NONE) {
928 if (vga_interface_type == VGA_CG3) {
929 if (graphic_depth != 8) {
930 error_report("Unsupported depth: %d", graphic_depth);
931 exit(1);
932 }
933
934 if (!(graphic_width == 1024 && graphic_height == 768) &&
935 !(graphic_width == 1152 && graphic_height == 900)) {
936 error_report("Unsupported resolution: %d x %d", graphic_width,
937 graphic_height);
938 exit(1);
939 }
940
941 /* sbus irq 5 */
942 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
943 graphic_width, graphic_height, graphic_depth);
944 } else {
945 /* If no display specified, default to TCX */
946 if (graphic_depth != 8 && graphic_depth != 24) {
947 error_report("Unsupported depth: %d", graphic_depth);
948 exit(1);
949 }
950
951 if (!(graphic_width == 1024 && graphic_height == 768)) {
952 error_report("Unsupported resolution: %d x %d",
953 graphic_width, graphic_height);
954 exit(1);
955 }
956
957 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
958 graphic_width, graphic_height, graphic_depth);
959 }
960 }
961
962 for (i = 0; i < MAX_VSIMMS; i++) {
963 /* vsimm registers probed by OBP */
964 if (hwdef->vsimm[i].reg_base) {
965 char *name = g_strdup_printf("vsimm[%d]", i);
966 empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000);
967 g_free(name);
968 }
969 }
970
971 if (hwdef->sx_base) {
972 create_unimplemented_device("SUNW,sx", hwdef->sx_base, 0x2000);
973 }
974
975 dev = qdev_new("sysbus-m48t08");
976 qdev_prop_set_int32(dev, "base-year", 1968);
977 s = SYS_BUS_DEVICE(dev);
978 sysbus_realize_and_unref(s, &error_fatal);
979 sysbus_connect_irq(s, 0, slavio_irq[0]);
980 sysbus_mmio_map(s, 0, hwdef->nvram_base);
981 nvram = NVRAM(dev);
982
983 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
984
985 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
986 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
987 dev = qdev_new(TYPE_ESCC);
988 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
989 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
990 qdev_prop_set_uint32(dev, "it_shift", 1);
991 qdev_prop_set_chr(dev, "chrB", NULL);
992 qdev_prop_set_chr(dev, "chrA", NULL);
993 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
994 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
995 s = SYS_BUS_DEVICE(dev);
996 sysbus_realize_and_unref(s, &error_fatal);
997 sysbus_connect_irq(s, 0, slavio_irq[14]);
998 sysbus_connect_irq(s, 1, slavio_irq[14]);
999 sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
1000
1001 dev = qdev_new(TYPE_ESCC);
1002 qdev_prop_set_uint32(dev, "disabled", 0);
1003 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
1004 qdev_prop_set_uint32(dev, "it_shift", 1);
1005 qdev_prop_set_chr(dev, "chrB", serial_hd(1));
1006 qdev_prop_set_chr(dev, "chrA", serial_hd(0));
1007 qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
1008 qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
1009
1010 s = SYS_BUS_DEVICE(dev);
1011 sysbus_realize_and_unref(s, &error_fatal);
1012 sysbus_connect_irq(s, 0, slavio_irq[15]);
1013 sysbus_connect_irq(s, 1, slavio_irq[15]);
1014 sysbus_mmio_map(s, 0, hwdef->serial_base);
1015
1016 if (hwdef->apc_base) {
1017 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
1018 }
1019
1020 if (hwdef->fd_base) {
1021 /* there is zero or one floppy drive */
1022 memset(fd, 0, sizeof(fd));
1023 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1024 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1025 &fdc_tc);
1026 } else {
1027 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1028 }
1029
1030 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1031 slavio_irq[30], fdc_tc);
1032
1033 if (hwdef->cs_base) {
1034 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1035 slavio_irq[5]);
1036 }
1037
1038 if (hwdef->dbri_base) {
1039 /* ISDN chip with attached CS4215 audio codec */
1040 /* prom space */
1041 create_unimplemented_device("SUNW,DBRI.prom",
1042 hwdef->dbri_base + 0x1000, 0x30);
1043 /* reg space */
1044 create_unimplemented_device("SUNW,DBRI",
1045 hwdef->dbri_base + 0x10000, 0x100);
1046 }
1047
1048 if (hwdef->bpp_base) {
1049 /* parallel port */
1050 create_unimplemented_device("SUNW,bpp", hwdef->bpp_base, 0x20);
1051 }
1052
1053 initrd_size = 0;
1054 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1055 machine->initrd_filename,
1056 machine->ram_size, &initrd_size);
1057
1058 nvram_init(nvram, (uint8_t *)&nd->macaddr, machine->kernel_cmdline,
1059 machine->boot_order, machine->ram_size, kernel_size,
1060 graphic_width, graphic_height, graphic_depth,
1061 hwdef->nvram_machine_id, "Sun4m");
1062
1063 if (hwdef->ecc_base)
1064 ecc_init(hwdef->ecc_base, slavio_irq[28],
1065 hwdef->ecc_version);
1066
1067 dev = qdev_new(TYPE_FW_CFG_MEM);
1068 fw_cfg = FW_CFG(dev);
1069 qdev_prop_set_uint32(dev, "data_width", 1);
1070 qdev_prop_set_bit(dev, "dma_enabled", false);
1071 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1072 OBJECT(fw_cfg));
1073 s = SYS_BUS_DEVICE(dev);
1074 sysbus_realize_and_unref(s, &error_fatal);
1075 sysbus_mmio_map(s, 0, CFG_ADDR);
1076 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
1077
1078 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1079 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1080 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
1081 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1082 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1083 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1084 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1085 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1086 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1087 if (machine->kernel_cmdline) {
1088 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1089 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1090 machine->kernel_cmdline);
1091 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1092 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1093 strlen(machine->kernel_cmdline) + 1);
1094 } else {
1095 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1096 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1097 }
1098 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1099 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1100 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1101 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1102 }
1103
1104 enum {
1105 ss5_id = 32,
1106 vger_id,
1107 lx_id,
1108 ss4_id,
1109 scls_id,
1110 sbook_id,
1111 ss10_id = 64,
1112 ss20_id,
1113 ss600mp_id,
1114 };
1115
1116 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1117 /* SS-5 */
1118 {
1119 .iommu_base = 0x10000000,
1120 .iommu_pad_base = 0x10004000,
1121 .iommu_pad_len = 0x0fffb000,
1122 .tcx_base = 0x50000000,
1123 .cs_base = 0x6c000000,
1124 .slavio_base = 0x70000000,
1125 .ms_kb_base = 0x71000000,
1126 .serial_base = 0x71100000,
1127 .nvram_base = 0x71200000,
1128 .fd_base = 0x71400000,
1129 .counter_base = 0x71d00000,
1130 .intctl_base = 0x71e00000,
1131 .idreg_base = 0x78000000,
1132 .dma_base = 0x78400000,
1133 .esp_base = 0x78800000,
1134 .le_base = 0x78c00000,
1135 .apc_base = 0x6a000000,
1136 .afx_base = 0x6e000000,
1137 .aux1_base = 0x71900000,
1138 .aux2_base = 0x71910000,
1139 .nvram_machine_id = 0x80,
1140 .machine_id = ss5_id,
1141 .iommu_version = 0x05000000,
1142 .max_mem = 0x10000000,
1143 },
1144 /* SS-10 */
1145 {
1146 .iommu_base = 0xfe0000000ULL,
1147 .tcx_base = 0xe20000000ULL,
1148 .slavio_base = 0xff0000000ULL,
1149 .ms_kb_base = 0xff1000000ULL,
1150 .serial_base = 0xff1100000ULL,
1151 .nvram_base = 0xff1200000ULL,
1152 .fd_base = 0xff1700000ULL,
1153 .counter_base = 0xff1300000ULL,
1154 .intctl_base = 0xff1400000ULL,
1155 .idreg_base = 0xef0000000ULL,
1156 .dma_base = 0xef0400000ULL,
1157 .esp_base = 0xef0800000ULL,
1158 .le_base = 0xef0c00000ULL,
1159 .apc_base = 0xefa000000ULL, // XXX should not exist
1160 .aux1_base = 0xff1800000ULL,
1161 .aux2_base = 0xff1a01000ULL,
1162 .ecc_base = 0xf00000000ULL,
1163 .ecc_version = 0x10000000, // version 0, implementation 1
1164 .nvram_machine_id = 0x72,
1165 .machine_id = ss10_id,
1166 .iommu_version = 0x03000000,
1167 .max_mem = 0xf00000000ULL,
1168 },
1169 /* SS-600MP */
1170 {
1171 .iommu_base = 0xfe0000000ULL,
1172 .tcx_base = 0xe20000000ULL,
1173 .slavio_base = 0xff0000000ULL,
1174 .ms_kb_base = 0xff1000000ULL,
1175 .serial_base = 0xff1100000ULL,
1176 .nvram_base = 0xff1200000ULL,
1177 .counter_base = 0xff1300000ULL,
1178 .intctl_base = 0xff1400000ULL,
1179 .dma_base = 0xef0081000ULL,
1180 .esp_base = 0xef0080000ULL,
1181 .le_base = 0xef0060000ULL,
1182 .apc_base = 0xefa000000ULL, // XXX should not exist
1183 .aux1_base = 0xff1800000ULL,
1184 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1185 .ecc_base = 0xf00000000ULL,
1186 .ecc_version = 0x00000000, // version 0, implementation 0
1187 .nvram_machine_id = 0x71,
1188 .machine_id = ss600mp_id,
1189 .iommu_version = 0x01000000,
1190 .max_mem = 0xf00000000ULL,
1191 },
1192 /* SS-20 */
1193 {
1194 .iommu_base = 0xfe0000000ULL,
1195 .tcx_base = 0xe20000000ULL,
1196 .slavio_base = 0xff0000000ULL,
1197 .ms_kb_base = 0xff1000000ULL,
1198 .serial_base = 0xff1100000ULL,
1199 .nvram_base = 0xff1200000ULL,
1200 .fd_base = 0xff1700000ULL,
1201 .counter_base = 0xff1300000ULL,
1202 .intctl_base = 0xff1400000ULL,
1203 .idreg_base = 0xef0000000ULL,
1204 .dma_base = 0xef0400000ULL,
1205 .esp_base = 0xef0800000ULL,
1206 .le_base = 0xef0c00000ULL,
1207 .bpp_base = 0xef4800000ULL,
1208 .apc_base = 0xefa000000ULL, // XXX should not exist
1209 .aux1_base = 0xff1800000ULL,
1210 .aux2_base = 0xff1a01000ULL,
1211 .dbri_base = 0xee0000000ULL,
1212 .sx_base = 0xf80000000ULL,
1213 .vsimm = {
1214 {
1215 .reg_base = 0x9c000000ULL,
1216 .vram_base = 0xfc000000ULL
1217 }, {
1218 .reg_base = 0x90000000ULL,
1219 .vram_base = 0xf0000000ULL
1220 }, {
1221 .reg_base = 0x94000000ULL
1222 }, {
1223 .reg_base = 0x98000000ULL
1224 }
1225 },
1226 .ecc_base = 0xf00000000ULL,
1227 .ecc_version = 0x20000000, // version 0, implementation 2
1228 .nvram_machine_id = 0x72,
1229 .machine_id = ss20_id,
1230 .iommu_version = 0x13000000,
1231 .max_mem = 0xf00000000ULL,
1232 },
1233 /* Voyager */
1234 {
1235 .iommu_base = 0x10000000,
1236 .tcx_base = 0x50000000,
1237 .slavio_base = 0x70000000,
1238 .ms_kb_base = 0x71000000,
1239 .serial_base = 0x71100000,
1240 .nvram_base = 0x71200000,
1241 .fd_base = 0x71400000,
1242 .counter_base = 0x71d00000,
1243 .intctl_base = 0x71e00000,
1244 .idreg_base = 0x78000000,
1245 .dma_base = 0x78400000,
1246 .esp_base = 0x78800000,
1247 .le_base = 0x78c00000,
1248 .apc_base = 0x71300000, // pmc
1249 .aux1_base = 0x71900000,
1250 .aux2_base = 0x71910000,
1251 .nvram_machine_id = 0x80,
1252 .machine_id = vger_id,
1253 .iommu_version = 0x05000000,
1254 .max_mem = 0x10000000,
1255 },
1256 /* LX */
1257 {
1258 .iommu_base = 0x10000000,
1259 .iommu_pad_base = 0x10004000,
1260 .iommu_pad_len = 0x0fffb000,
1261 .tcx_base = 0x50000000,
1262 .slavio_base = 0x70000000,
1263 .ms_kb_base = 0x71000000,
1264 .serial_base = 0x71100000,
1265 .nvram_base = 0x71200000,
1266 .fd_base = 0x71400000,
1267 .counter_base = 0x71d00000,
1268 .intctl_base = 0x71e00000,
1269 .idreg_base = 0x78000000,
1270 .dma_base = 0x78400000,
1271 .esp_base = 0x78800000,
1272 .le_base = 0x78c00000,
1273 .aux1_base = 0x71900000,
1274 .aux2_base = 0x71910000,
1275 .nvram_machine_id = 0x80,
1276 .machine_id = lx_id,
1277 .iommu_version = 0x04000000,
1278 .max_mem = 0x10000000,
1279 },
1280 /* SS-4 */
1281 {
1282 .iommu_base = 0x10000000,
1283 .tcx_base = 0x50000000,
1284 .cs_base = 0x6c000000,
1285 .slavio_base = 0x70000000,
1286 .ms_kb_base = 0x71000000,
1287 .serial_base = 0x71100000,
1288 .nvram_base = 0x71200000,
1289 .fd_base = 0x71400000,
1290 .counter_base = 0x71d00000,
1291 .intctl_base = 0x71e00000,
1292 .idreg_base = 0x78000000,
1293 .dma_base = 0x78400000,
1294 .esp_base = 0x78800000,
1295 .le_base = 0x78c00000,
1296 .apc_base = 0x6a000000,
1297 .aux1_base = 0x71900000,
1298 .aux2_base = 0x71910000,
1299 .nvram_machine_id = 0x80,
1300 .machine_id = ss4_id,
1301 .iommu_version = 0x05000000,
1302 .max_mem = 0x10000000,
1303 },
1304 /* SPARCClassic */
1305 {
1306 .iommu_base = 0x10000000,
1307 .tcx_base = 0x50000000,
1308 .slavio_base = 0x70000000,
1309 .ms_kb_base = 0x71000000,
1310 .serial_base = 0x71100000,
1311 .nvram_base = 0x71200000,
1312 .fd_base = 0x71400000,
1313 .counter_base = 0x71d00000,
1314 .intctl_base = 0x71e00000,
1315 .idreg_base = 0x78000000,
1316 .dma_base = 0x78400000,
1317 .esp_base = 0x78800000,
1318 .le_base = 0x78c00000,
1319 .apc_base = 0x6a000000,
1320 .aux1_base = 0x71900000,
1321 .aux2_base = 0x71910000,
1322 .nvram_machine_id = 0x80,
1323 .machine_id = scls_id,
1324 .iommu_version = 0x05000000,
1325 .max_mem = 0x10000000,
1326 },
1327 /* SPARCbook */
1328 {
1329 .iommu_base = 0x10000000,
1330 .tcx_base = 0x50000000, // XXX
1331 .slavio_base = 0x70000000,
1332 .ms_kb_base = 0x71000000,
1333 .serial_base = 0x71100000,
1334 .nvram_base = 0x71200000,
1335 .fd_base = 0x71400000,
1336 .counter_base = 0x71d00000,
1337 .intctl_base = 0x71e00000,
1338 .idreg_base = 0x78000000,
1339 .dma_base = 0x78400000,
1340 .esp_base = 0x78800000,
1341 .le_base = 0x78c00000,
1342 .apc_base = 0x6a000000,
1343 .aux1_base = 0x71900000,
1344 .aux2_base = 0x71910000,
1345 .nvram_machine_id = 0x80,
1346 .machine_id = sbook_id,
1347 .iommu_version = 0x05000000,
1348 .max_mem = 0x10000000,
1349 },
1350 };
1351
1352 /* SPARCstation 5 hardware initialisation */
1353 static void ss5_init(MachineState *machine)
1354 {
1355 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1356 }
1357
1358 /* SPARCstation 10 hardware initialisation */
1359 static void ss10_init(MachineState *machine)
1360 {
1361 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1362 }
1363
1364 /* SPARCserver 600MP hardware initialisation */
1365 static void ss600mp_init(MachineState *machine)
1366 {
1367 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1368 }
1369
1370 /* SPARCstation 20 hardware initialisation */
1371 static void ss20_init(MachineState *machine)
1372 {
1373 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1374 }
1375
1376 /* SPARCstation Voyager hardware initialisation */
1377 static void vger_init(MachineState *machine)
1378 {
1379 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1380 }
1381
1382 /* SPARCstation LX hardware initialisation */
1383 static void ss_lx_init(MachineState *machine)
1384 {
1385 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1386 }
1387
1388 /* SPARCstation 4 hardware initialisation */
1389 static void ss4_init(MachineState *machine)
1390 {
1391 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1392 }
1393
1394 /* SPARCClassic hardware initialisation */
1395 static void scls_init(MachineState *machine)
1396 {
1397 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1398 }
1399
1400 /* SPARCbook hardware initialisation */
1401 static void sbook_init(MachineState *machine)
1402 {
1403 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1404 }
1405
1406 static void ss5_class_init(ObjectClass *oc, void *data)
1407 {
1408 MachineClass *mc = MACHINE_CLASS(oc);
1409
1410 mc->desc = "Sun4m platform, SPARCstation 5";
1411 mc->init = ss5_init;
1412 mc->block_default_type = IF_SCSI;
1413 mc->is_default = true;
1414 mc->default_boot_order = "c";
1415 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1416 mc->default_display = "tcx";
1417 mc->default_ram_id = "sun4m.ram";
1418 }
1419
1420 static const TypeInfo ss5_type = {
1421 .name = MACHINE_TYPE_NAME("SS-5"),
1422 .parent = TYPE_MACHINE,
1423 .class_init = ss5_class_init,
1424 };
1425
1426 static void ss10_class_init(ObjectClass *oc, void *data)
1427 {
1428 MachineClass *mc = MACHINE_CLASS(oc);
1429
1430 mc->desc = "Sun4m platform, SPARCstation 10";
1431 mc->init = ss10_init;
1432 mc->block_default_type = IF_SCSI;
1433 mc->max_cpus = 4;
1434 mc->default_boot_order = "c";
1435 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1436 mc->default_display = "tcx";
1437 mc->default_ram_id = "sun4m.ram";
1438 }
1439
1440 static const TypeInfo ss10_type = {
1441 .name = MACHINE_TYPE_NAME("SS-10"),
1442 .parent = TYPE_MACHINE,
1443 .class_init = ss10_class_init,
1444 };
1445
1446 static void ss600mp_class_init(ObjectClass *oc, void *data)
1447 {
1448 MachineClass *mc = MACHINE_CLASS(oc);
1449
1450 mc->desc = "Sun4m platform, SPARCserver 600MP";
1451 mc->init = ss600mp_init;
1452 mc->block_default_type = IF_SCSI;
1453 mc->max_cpus = 4;
1454 mc->default_boot_order = "c";
1455 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1456 mc->default_display = "tcx";
1457 mc->default_ram_id = "sun4m.ram";
1458 }
1459
1460 static const TypeInfo ss600mp_type = {
1461 .name = MACHINE_TYPE_NAME("SS-600MP"),
1462 .parent = TYPE_MACHINE,
1463 .class_init = ss600mp_class_init,
1464 };
1465
1466 static void ss20_class_init(ObjectClass *oc, void *data)
1467 {
1468 MachineClass *mc = MACHINE_CLASS(oc);
1469
1470 mc->desc = "Sun4m platform, SPARCstation 20";
1471 mc->init = ss20_init;
1472 mc->block_default_type = IF_SCSI;
1473 mc->max_cpus = 4;
1474 mc->default_boot_order = "c";
1475 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1476 mc->default_display = "tcx";
1477 mc->default_ram_id = "sun4m.ram";
1478 }
1479
1480 static const TypeInfo ss20_type = {
1481 .name = MACHINE_TYPE_NAME("SS-20"),
1482 .parent = TYPE_MACHINE,
1483 .class_init = ss20_class_init,
1484 };
1485
1486 static void voyager_class_init(ObjectClass *oc, void *data)
1487 {
1488 MachineClass *mc = MACHINE_CLASS(oc);
1489
1490 mc->desc = "Sun4m platform, SPARCstation Voyager";
1491 mc->init = vger_init;
1492 mc->block_default_type = IF_SCSI;
1493 mc->default_boot_order = "c";
1494 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1495 mc->default_display = "tcx";
1496 mc->default_ram_id = "sun4m.ram";
1497 }
1498
1499 static const TypeInfo voyager_type = {
1500 .name = MACHINE_TYPE_NAME("Voyager"),
1501 .parent = TYPE_MACHINE,
1502 .class_init = voyager_class_init,
1503 };
1504
1505 static void ss_lx_class_init(ObjectClass *oc, void *data)
1506 {
1507 MachineClass *mc = MACHINE_CLASS(oc);
1508
1509 mc->desc = "Sun4m platform, SPARCstation LX";
1510 mc->init = ss_lx_init;
1511 mc->block_default_type = IF_SCSI;
1512 mc->default_boot_order = "c";
1513 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1514 mc->default_display = "tcx";
1515 mc->default_ram_id = "sun4m.ram";
1516 }
1517
1518 static const TypeInfo ss_lx_type = {
1519 .name = MACHINE_TYPE_NAME("LX"),
1520 .parent = TYPE_MACHINE,
1521 .class_init = ss_lx_class_init,
1522 };
1523
1524 static void ss4_class_init(ObjectClass *oc, void *data)
1525 {
1526 MachineClass *mc = MACHINE_CLASS(oc);
1527
1528 mc->desc = "Sun4m platform, SPARCstation 4";
1529 mc->init = ss4_init;
1530 mc->block_default_type = IF_SCSI;
1531 mc->default_boot_order = "c";
1532 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1533 mc->default_display = "tcx";
1534 mc->default_ram_id = "sun4m.ram";
1535 }
1536
1537 static const TypeInfo ss4_type = {
1538 .name = MACHINE_TYPE_NAME("SS-4"),
1539 .parent = TYPE_MACHINE,
1540 .class_init = ss4_class_init,
1541 };
1542
1543 static void scls_class_init(ObjectClass *oc, void *data)
1544 {
1545 MachineClass *mc = MACHINE_CLASS(oc);
1546
1547 mc->desc = "Sun4m platform, SPARCClassic";
1548 mc->init = scls_init;
1549 mc->block_default_type = IF_SCSI;
1550 mc->default_boot_order = "c";
1551 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1552 mc->default_display = "tcx";
1553 mc->default_ram_id = "sun4m.ram";
1554 }
1555
1556 static const TypeInfo scls_type = {
1557 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1558 .parent = TYPE_MACHINE,
1559 .class_init = scls_class_init,
1560 };
1561
1562 static void sbook_class_init(ObjectClass *oc, void *data)
1563 {
1564 MachineClass *mc = MACHINE_CLASS(oc);
1565
1566 mc->desc = "Sun4m platform, SPARCbook";
1567 mc->init = sbook_init;
1568 mc->block_default_type = IF_SCSI;
1569 mc->default_boot_order = "c";
1570 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1571 mc->default_display = "tcx";
1572 mc->default_ram_id = "sun4m.ram";
1573 }
1574
1575 static const TypeInfo sbook_type = {
1576 .name = MACHINE_TYPE_NAME("SPARCbook"),
1577 .parent = TYPE_MACHINE,
1578 .class_init = sbook_class_init,
1579 };
1580
1581 static void sun4m_register_types(void)
1582 {
1583 type_register_static(&idreg_info);
1584 type_register_static(&afx_info);
1585 type_register_static(&prom_info);
1586 type_register_static(&ram_info);
1587
1588 type_register_static(&ss5_type);
1589 type_register_static(&ss10_type);
1590 type_register_static(&ss600mp_type);
1591 type_register_static(&ss20_type);
1592 type_register_static(&voyager_type);
1593 type_register_static(&ss_lx_type);
1594 type_register_static(&ss4_type);
1595 type_register_static(&scls_type);
1596 type_register_static(&sbook_type);
1597 }
1598
1599 type_init(sun4m_register_types)
AR7 emulation for QEMU