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target-s390x: fix CC computation for EX instruction
[qemu/ar7.git] / target-s390x / translate.c
blob497733dbcc842f95bb7c1dd08331dbe596ea9f9d
1 /*
2 * S/390 translation
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* #define DEBUG_INLINE_BRANCHES */
22 #define S390X_DEBUG_DISAS
23 /* #define S390X_DEBUG_DISAS_VERBOSE */
24
25 #ifdef S390X_DEBUG_DISAS_VERBOSE
26 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
27 #else
28 # define LOG_DISAS(...) do { } while (0)
29 #endif
30
31 #include "cpu.h"
32 #include "disas/disas.h"
33 #include "tcg-op.h"
34 #include "qemu/log.h"
35 #include "qemu/host-utils.h"
36 #include "exec/cpu_ldst.h"
37
38 /* global register indexes */
39 static TCGv_ptr cpu_env;
40
41 #include "exec/gen-icount.h"
42 #include "exec/helper-proto.h"
43 #include "exec/helper-gen.h"
44
45 #include "trace-tcg.h"
46
47
48 /* Information that (most) every instruction needs to manipulate. */
49 typedef struct DisasContext DisasContext;
50 typedef struct DisasInsn DisasInsn;
51 typedef struct DisasFields DisasFields;
52
53 struct DisasContext {
54 struct TranslationBlock *tb;
55 const DisasInsn *insn;
56 DisasFields *fields;
57 uint64_t pc, next_pc;
58 enum cc_op cc_op;
59 bool singlestep_enabled;
60 };
61
62 /* Information carried about a condition to be evaluated. */
63 typedef struct {
64 TCGCond cond:8;
65 bool is_64;
66 bool g1;
67 bool g2;
68 union {
69 struct { TCGv_i64 a, b; } s64;
70 struct { TCGv_i32 a, b; } s32;
71 } u;
72 } DisasCompare;
73
74 #define DISAS_EXCP 4
75
76 #ifdef DEBUG_INLINE_BRANCHES
77 static uint64_t inline_branch_hit[CC_OP_MAX];
78 static uint64_t inline_branch_miss[CC_OP_MAX];
79 #endif
80
81 static uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
82 {
83 if (!(s->tb->flags & FLAG_MASK_64)) {
84 if (s->tb->flags & FLAG_MASK_32) {
85 return pc | 0x80000000;
86 }
87 }
88 return pc;
89 }
90
91 void s390_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
92 int flags)
93 {
94 S390CPU *cpu = S390_CPU(cs);
95 CPUS390XState *env = &cpu->env;
96 int i;
97
98 if (env->cc_op > 3) {
99 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
100 env->psw.mask, env->psw.addr, cc_name(env->cc_op));
101 } else {
102 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
103 env->psw.mask, env->psw.addr, env->cc_op);
104 }
105
106 for (i = 0; i < 16; i++) {
107 cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
108 if ((i % 4) == 3) {
109 cpu_fprintf(f, "\n");
110 } else {
111 cpu_fprintf(f, " ");
112 }
113 }
114
115 for (i = 0; i < 16; i++) {
116 cpu_fprintf(f, "F%02d=%016" PRIx64, i, get_freg(env, i)->ll);
117 if ((i % 4) == 3) {
118 cpu_fprintf(f, "\n");
119 } else {
120 cpu_fprintf(f, " ");
121 }
122 }
123
124 for (i = 0; i < 32; i++) {
125 cpu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64, i,
126 env->vregs[i][0].ll, env->vregs[i][1].ll);
127 cpu_fprintf(f, (i % 2) ? " " : "\n");
128 }
129
130 #ifndef CONFIG_USER_ONLY
131 for (i = 0; i < 16; i++) {
132 cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
133 if ((i % 4) == 3) {
134 cpu_fprintf(f, "\n");
135 } else {
136 cpu_fprintf(f, " ");
137 }
138 }
139 #endif
140
141 #ifdef DEBUG_INLINE_BRANCHES
142 for (i = 0; i < CC_OP_MAX; i++) {
143 cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
144 inline_branch_miss[i], inline_branch_hit[i]);
145 }
146 #endif
147
148 cpu_fprintf(f, "\n");
149 }
150
151 static TCGv_i64 psw_addr;
152 static TCGv_i64 psw_mask;
153
154 static TCGv_i32 cc_op;
155 static TCGv_i64 cc_src;
156 static TCGv_i64 cc_dst;
157 static TCGv_i64 cc_vr;
158
159 static char cpu_reg_names[32][4];
160 static TCGv_i64 regs[16];
161 static TCGv_i64 fregs[16];
162
163 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
164
165 void s390x_translate_init(void)
166 {
167 int i;
168
169 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
170 psw_addr = tcg_global_mem_new_i64(TCG_AREG0,
171 offsetof(CPUS390XState, psw.addr),
172 "psw_addr");
173 psw_mask = tcg_global_mem_new_i64(TCG_AREG0,
174 offsetof(CPUS390XState, psw.mask),
175 "psw_mask");
176
177 cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUS390XState, cc_op),
178 "cc_op");
179 cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_src),
180 "cc_src");
181 cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_dst),
182 "cc_dst");
183 cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_vr),
184 "cc_vr");
185
186 for (i = 0; i < 16; i++) {
187 snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i);
188 regs[i] = tcg_global_mem_new(TCG_AREG0,
189 offsetof(CPUS390XState, regs[i]),
190 cpu_reg_names[i]);
191 }
192
193 for (i = 0; i < 16; i++) {
194 snprintf(cpu_reg_names[i + 16], sizeof(cpu_reg_names[0]), "f%d", i);
195 fregs[i] = tcg_global_mem_new(TCG_AREG0,
196 offsetof(CPUS390XState, vregs[i][0].d),
197 cpu_reg_names[i + 16]);
198 }
199 }
200
201 static TCGv_i64 load_reg(int reg)
202 {
203 TCGv_i64 r = tcg_temp_new_i64();
204 tcg_gen_mov_i64(r, regs[reg]);
205 return r;
206 }
207
208 static TCGv_i64 load_freg32_i64(int reg)
209 {
210 TCGv_i64 r = tcg_temp_new_i64();
211 tcg_gen_shri_i64(r, fregs[reg], 32);
212 return r;
213 }
214
215 static void store_reg(int reg, TCGv_i64 v)
216 {
217 tcg_gen_mov_i64(regs[reg], v);
218 }
219
220 static void store_freg(int reg, TCGv_i64 v)
221 {
222 tcg_gen_mov_i64(fregs[reg], v);
223 }
224
225 static void store_reg32_i64(int reg, TCGv_i64 v)
226 {
227 /* 32 bit register writes keep the upper half */
228 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
229 }
230
231 static void store_reg32h_i64(int reg, TCGv_i64 v)
232 {
233 tcg_gen_deposit_i64(regs[reg], regs[reg], v, 32, 32);
234 }
235
236 static void store_freg32_i64(int reg, TCGv_i64 v)
237 {
238 tcg_gen_deposit_i64(fregs[reg], fregs[reg], v, 32, 32);
239 }
240
241 static void return_low128(TCGv_i64 dest)
242 {
243 tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl));
244 }
245
246 static void update_psw_addr(DisasContext *s)
247 {
248 /* psw.addr */
249 tcg_gen_movi_i64(psw_addr, s->pc);
250 }
251
252 static void update_cc_op(DisasContext *s)
253 {
254 if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
255 tcg_gen_movi_i32(cc_op, s->cc_op);
256 }
257 }
258
259 static void potential_page_fault(DisasContext *s)
260 {
261 update_psw_addr(s);
262 update_cc_op(s);
263 }
264
265 static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
266 {
267 return (uint64_t)cpu_lduw_code(env, pc);
268 }
269
270 static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
271 {
272 return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
273 }
274
275 static int get_mem_index(DisasContext *s)
276 {
277 switch (s->tb->flags & FLAG_MASK_ASC) {
278 case PSW_ASC_PRIMARY >> 32:
279 return 0;
280 case PSW_ASC_SECONDARY >> 32:
281 return 1;
282 case PSW_ASC_HOME >> 32:
283 return 2;
284 default:
285 tcg_abort();
286 break;
287 }
288 }
289
290 static void gen_exception(int excp)
291 {
292 TCGv_i32 tmp = tcg_const_i32(excp);
293 gen_helper_exception(cpu_env, tmp);
294 tcg_temp_free_i32(tmp);
295 }
296
297 static void gen_program_exception(DisasContext *s, int code)
298 {
299 TCGv_i32 tmp;
300
301 /* Remember what pgm exeption this was. */
302 tmp = tcg_const_i32(code);
303 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
304 tcg_temp_free_i32(tmp);
305
306 tmp = tcg_const_i32(s->next_pc - s->pc);
307 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen));
308 tcg_temp_free_i32(tmp);
309
310 /* Advance past instruction. */
311 s->pc = s->next_pc;
312 update_psw_addr(s);
313
314 /* Save off cc. */
315 update_cc_op(s);
316
317 /* Trigger exception. */
318 gen_exception(EXCP_PGM);
319 }
320
321 static inline void gen_illegal_opcode(DisasContext *s)
322 {
323 gen_program_exception(s, PGM_SPECIFICATION);
324 }
325
326 #ifndef CONFIG_USER_ONLY
327 static void check_privileged(DisasContext *s)
328 {
329 if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
330 gen_program_exception(s, PGM_PRIVILEGED);
331 }
332 }
333 #endif
334
335 static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
336 {
337 TCGv_i64 tmp = tcg_temp_new_i64();
338 bool need_31 = !(s->tb->flags & FLAG_MASK_64);
339
340 /* Note that d2 is limited to 20 bits, signed. If we crop negative
341 displacements early we create larger immedate addends. */
342
343 /* Note that addi optimizes the imm==0 case. */
344 if (b2 && x2) {
345 tcg_gen_add_i64(tmp, regs[b2], regs[x2]);
346 tcg_gen_addi_i64(tmp, tmp, d2);
347 } else if (b2) {
348 tcg_gen_addi_i64(tmp, regs[b2], d2);
349 } else if (x2) {
350 tcg_gen_addi_i64(tmp, regs[x2], d2);
351 } else {
352 if (need_31) {
353 d2 &= 0x7fffffff;
354 need_31 = false;
355 }
356 tcg_gen_movi_i64(tmp, d2);
357 }
358 if (need_31) {
359 tcg_gen_andi_i64(tmp, tmp, 0x7fffffff);
360 }
361
362 return tmp;
363 }
364
365 static inline bool live_cc_data(DisasContext *s)
366 {
367 return (s->cc_op != CC_OP_DYNAMIC
368 && s->cc_op != CC_OP_STATIC
369 && s->cc_op > 3);
370 }
371
372 static inline void gen_op_movi_cc(DisasContext *s, uint32_t val)
373 {
374 if (live_cc_data(s)) {
375 tcg_gen_discard_i64(cc_src);
376 tcg_gen_discard_i64(cc_dst);
377 tcg_gen_discard_i64(cc_vr);
378 }
379 s->cc_op = CC_OP_CONST0 + val;
380 }
381
382 static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
383 {
384 if (live_cc_data(s)) {
385 tcg_gen_discard_i64(cc_src);
386 tcg_gen_discard_i64(cc_vr);
387 }
388 tcg_gen_mov_i64(cc_dst, dst);
389 s->cc_op = op;
390 }
391
392 static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
393 TCGv_i64 dst)
394 {
395 if (live_cc_data(s)) {
396 tcg_gen_discard_i64(cc_vr);
397 }
398 tcg_gen_mov_i64(cc_src, src);
399 tcg_gen_mov_i64(cc_dst, dst);
400 s->cc_op = op;
401 }
402
403 static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
404 TCGv_i64 dst, TCGv_i64 vr)
405 {
406 tcg_gen_mov_i64(cc_src, src);
407 tcg_gen_mov_i64(cc_dst, dst);
408 tcg_gen_mov_i64(cc_vr, vr);
409 s->cc_op = op;
410 }
411
412 static void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
413 {
414 gen_op_update1_cc_i64(s, CC_OP_NZ, val);
415 }
416
417 static void gen_set_cc_nz_f32(DisasContext *s, TCGv_i64 val)
418 {
419 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, val);
420 }
421
422 static void gen_set_cc_nz_f64(DisasContext *s, TCGv_i64 val)
423 {
424 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, val);
425 }
426
427 static void gen_set_cc_nz_f128(DisasContext *s, TCGv_i64 vh, TCGv_i64 vl)
428 {
429 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, vh, vl);
430 }
431
432 /* CC value is in env->cc_op */
433 static void set_cc_static(DisasContext *s)
434 {
435 if (live_cc_data(s)) {
436 tcg_gen_discard_i64(cc_src);
437 tcg_gen_discard_i64(cc_dst);
438 tcg_gen_discard_i64(cc_vr);
439 }
440 s->cc_op = CC_OP_STATIC;
441 }
442
443 /* calculates cc into cc_op */
444 static void gen_op_calc_cc(DisasContext *s)
445 {
446 TCGv_i32 local_cc_op;
447 TCGv_i64 dummy;
448
449 TCGV_UNUSED_I32(local_cc_op);
450 TCGV_UNUSED_I64(dummy);
451 switch (s->cc_op) {
452 default:
453 dummy = tcg_const_i64(0);
454 /* FALLTHRU */
455 case CC_OP_ADD_64:
456 case CC_OP_ADDU_64:
457 case CC_OP_ADDC_64:
458 case CC_OP_SUB_64:
459 case CC_OP_SUBU_64:
460 case CC_OP_SUBB_64:
461 case CC_OP_ADD_32:
462 case CC_OP_ADDU_32:
463 case CC_OP_ADDC_32:
464 case CC_OP_SUB_32:
465 case CC_OP_SUBU_32:
466 case CC_OP_SUBB_32:
467 local_cc_op = tcg_const_i32(s->cc_op);
468 break;
469 case CC_OP_CONST0:
470 case CC_OP_CONST1:
471 case CC_OP_CONST2:
472 case CC_OP_CONST3:
473 case CC_OP_STATIC:
474 case CC_OP_DYNAMIC:
475 break;
476 }
477
478 switch (s->cc_op) {
479 case CC_OP_CONST0:
480 case CC_OP_CONST1:
481 case CC_OP_CONST2:
482 case CC_OP_CONST3:
483 /* s->cc_op is the cc value */
484 tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
485 break;
486 case CC_OP_STATIC:
487 /* env->cc_op already is the cc value */
488 break;
489 case CC_OP_NZ:
490 case CC_OP_ABS_64:
491 case CC_OP_NABS_64:
492 case CC_OP_ABS_32:
493 case CC_OP_NABS_32:
494 case CC_OP_LTGT0_32:
495 case CC_OP_LTGT0_64:
496 case CC_OP_COMP_32:
497 case CC_OP_COMP_64:
498 case CC_OP_NZ_F32:
499 case CC_OP_NZ_F64:
500 case CC_OP_FLOGR:
501 /* 1 argument */
502 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dummy);
503 break;
504 case CC_OP_ICM:
505 case CC_OP_LTGT_32:
506 case CC_OP_LTGT_64:
507 case CC_OP_LTUGTU_32:
508 case CC_OP_LTUGTU_64:
509 case CC_OP_TM_32:
510 case CC_OP_TM_64:
511 case CC_OP_SLA_32:
512 case CC_OP_SLA_64:
513 case CC_OP_NZ_F128:
514 /* 2 arguments */
515 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
516 break;
517 case CC_OP_ADD_64:
518 case CC_OP_ADDU_64:
519 case CC_OP_ADDC_64:
520 case CC_OP_SUB_64:
521 case CC_OP_SUBU_64:
522 case CC_OP_SUBB_64:
523 case CC_OP_ADD_32:
524 case CC_OP_ADDU_32:
525 case CC_OP_ADDC_32:
526 case CC_OP_SUB_32:
527 case CC_OP_SUBU_32:
528 case CC_OP_SUBB_32:
529 /* 3 arguments */
530 gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc_vr);
531 break;
532 case CC_OP_DYNAMIC:
533 /* unknown operation - assume 3 arguments and cc_op in env */
534 gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr);
535 break;
536 default:
537 tcg_abort();
538 }
539
540 if (!TCGV_IS_UNUSED_I32(local_cc_op)) {
541 tcg_temp_free_i32(local_cc_op);
542 }
543 if (!TCGV_IS_UNUSED_I64(dummy)) {
544 tcg_temp_free_i64(dummy);
545 }
546
547 /* We now have cc in cc_op as constant */
548 set_cc_static(s);
549 }
550
551 static int use_goto_tb(DisasContext *s, uint64_t dest)
552 {
553 /* NOTE: we handle the case where the TB spans two pages here */
554 return (((dest & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK)
555 || (dest & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK))
556 && !s->singlestep_enabled
557 && !(s->tb->cflags & CF_LAST_IO));
558 }
559
560 static void account_noninline_branch(DisasContext *s, int cc_op)
561 {
562 #ifdef DEBUG_INLINE_BRANCHES
563 inline_branch_miss[cc_op]++;
564 #endif
565 }
566
567 static void account_inline_branch(DisasContext *s, int cc_op)
568 {
569 #ifdef DEBUG_INLINE_BRANCHES
570 inline_branch_hit[cc_op]++;
571 #endif
572 }
573
574 /* Table of mask values to comparison codes, given a comparison as input.
575 For such, CC=3 should not be possible. */
576 static const TCGCond ltgt_cond[16] = {
577 TCG_COND_NEVER, TCG_COND_NEVER, /* | | | x */
578 TCG_COND_GT, TCG_COND_GT, /* | | GT | x */
579 TCG_COND_LT, TCG_COND_LT, /* | LT | | x */
580 TCG_COND_NE, TCG_COND_NE, /* | LT | GT | x */
581 TCG_COND_EQ, TCG_COND_EQ, /* EQ | | | x */
582 TCG_COND_GE, TCG_COND_GE, /* EQ | | GT | x */
583 TCG_COND_LE, TCG_COND_LE, /* EQ | LT | | x */
584 TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | LT | GT | x */
585 };
586
587 /* Table of mask values to comparison codes, given a logic op as input.
588 For such, only CC=0 and CC=1 should be possible. */
589 static const TCGCond nz_cond[16] = {
590 TCG_COND_NEVER, TCG_COND_NEVER, /* | | x | x */
591 TCG_COND_NEVER, TCG_COND_NEVER,
592 TCG_COND_NE, TCG_COND_NE, /* | NE | x | x */
593 TCG_COND_NE, TCG_COND_NE,
594 TCG_COND_EQ, TCG_COND_EQ, /* EQ | | x | x */
595 TCG_COND_EQ, TCG_COND_EQ,
596 TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | NE | x | x */
597 TCG_COND_ALWAYS, TCG_COND_ALWAYS,
598 };
599
600 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
601 details required to generate a TCG comparison. */
602 static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
603 {
604 TCGCond cond;
605 enum cc_op old_cc_op = s->cc_op;
606
607 if (mask == 15 || mask == 0) {
608 c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER);
609 c->u.s32.a = cc_op;
610 c->u.s32.b = cc_op;
611 c->g1 = c->g2 = true;
612 c->is_64 = false;
613 return;
614 }
615
616 /* Find the TCG condition for the mask + cc op. */
617 switch (old_cc_op) {
618 case CC_OP_LTGT0_32:
619 case CC_OP_LTGT0_64:
620 case CC_OP_LTGT_32:
621 case CC_OP_LTGT_64:
622 cond = ltgt_cond[mask];
623 if (cond == TCG_COND_NEVER) {
624 goto do_dynamic;
625 }
626 account_inline_branch(s, old_cc_op);
627 break;
628
629 case CC_OP_LTUGTU_32:
630 case CC_OP_LTUGTU_64:
631 cond = tcg_unsigned_cond(ltgt_cond[mask]);
632 if (cond == TCG_COND_NEVER) {
633 goto do_dynamic;
634 }
635 account_inline_branch(s, old_cc_op);
636 break;
637
638 case CC_OP_NZ:
639 cond = nz_cond[mask];
640 if (cond == TCG_COND_NEVER) {
641 goto do_dynamic;
642 }
643 account_inline_branch(s, old_cc_op);
644 break;
645
646 case CC_OP_TM_32:
647 case CC_OP_TM_64:
648 switch (mask) {
649 case 8:
650 cond = TCG_COND_EQ;
651 break;
652 case 4 | 2 | 1:
653 cond = TCG_COND_NE;
654 break;
655 default:
656 goto do_dynamic;
657 }
658 account_inline_branch(s, old_cc_op);
659 break;
660
661 case CC_OP_ICM:
662 switch (mask) {
663 case 8:
664 cond = TCG_COND_EQ;
665 break;
666 case 4 | 2 | 1:
667 case 4 | 2:
668 cond = TCG_COND_NE;
669 break;
670 default:
671 goto do_dynamic;
672 }
673 account_inline_branch(s, old_cc_op);
674 break;
675
676 case CC_OP_FLOGR:
677 switch (mask & 0xa) {
678 case 8: /* src == 0 -> no one bit found */
679 cond = TCG_COND_EQ;
680 break;
681 case 2: /* src != 0 -> one bit found */
682 cond = TCG_COND_NE;
683 break;
684 default:
685 goto do_dynamic;
686 }
687 account_inline_branch(s, old_cc_op);
688 break;
689
690 case CC_OP_ADDU_32:
691 case CC_OP_ADDU_64:
692 switch (mask) {
693 case 8 | 2: /* vr == 0 */
694 cond = TCG_COND_EQ;
695 break;
696 case 4 | 1: /* vr != 0 */
697 cond = TCG_COND_NE;
698 break;
699 case 8 | 4: /* no carry -> vr >= src */
700 cond = TCG_COND_GEU;
701 break;
702 case 2 | 1: /* carry -> vr < src */
703 cond = TCG_COND_LTU;
704 break;
705 default:
706 goto do_dynamic;
707 }
708 account_inline_branch(s, old_cc_op);
709 break;
710
711 case CC_OP_SUBU_32:
712 case CC_OP_SUBU_64:
713 /* Note that CC=0 is impossible; treat it as dont-care. */
714 switch (mask & 7) {
715 case 2: /* zero -> op1 == op2 */
716 cond = TCG_COND_EQ;
717 break;
718 case 4 | 1: /* !zero -> op1 != op2 */
719 cond = TCG_COND_NE;
720 break;
721 case 4: /* borrow (!carry) -> op1 < op2 */
722 cond = TCG_COND_LTU;
723 break;
724 case 2 | 1: /* !borrow (carry) -> op1 >= op2 */
725 cond = TCG_COND_GEU;
726 break;
727 default:
728 goto do_dynamic;
729 }
730 account_inline_branch(s, old_cc_op);
731 break;
732
733 default:
734 do_dynamic:
735 /* Calculate cc value. */
736 gen_op_calc_cc(s);
737 /* FALLTHRU */
738
739 case CC_OP_STATIC:
740 /* Jump based on CC. We'll load up the real cond below;
741 the assignment here merely avoids a compiler warning. */
742 account_noninline_branch(s, old_cc_op);
743 old_cc_op = CC_OP_STATIC;
744 cond = TCG_COND_NEVER;
745 break;
746 }
747
748 /* Load up the arguments of the comparison. */
749 c->is_64 = true;
750 c->g1 = c->g2 = false;
751 switch (old_cc_op) {
752 case CC_OP_LTGT0_32:
753 c->is_64 = false;
754 c->u.s32.a = tcg_temp_new_i32();
755 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_dst);
756 c->u.s32.b = tcg_const_i32(0);
757 break;
758 case CC_OP_LTGT_32:
759 case CC_OP_LTUGTU_32:
760 case CC_OP_SUBU_32:
761 c->is_64 = false;
762 c->u.s32.a = tcg_temp_new_i32();
763 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_src);
764 c->u.s32.b = tcg_temp_new_i32();
765 tcg_gen_trunc_i64_i32(c->u.s32.b, cc_dst);
766 break;
767
768 case CC_OP_LTGT0_64:
769 case CC_OP_NZ:
770 case CC_OP_FLOGR:
771 c->u.s64.a = cc_dst;
772 c->u.s64.b = tcg_const_i64(0);
773 c->g1 = true;
774 break;
775 case CC_OP_LTGT_64:
776 case CC_OP_LTUGTU_64:
777 case CC_OP_SUBU_64:
778 c->u.s64.a = cc_src;
779 c->u.s64.b = cc_dst;
780 c->g1 = c->g2 = true;
781 break;
782
783 case CC_OP_TM_32:
784 case CC_OP_TM_64:
785 case CC_OP_ICM:
786 c->u.s64.a = tcg_temp_new_i64();
787 c->u.s64.b = tcg_const_i64(0);
788 tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst);
789 break;
790
791 case CC_OP_ADDU_32:
792 c->is_64 = false;
793 c->u.s32.a = tcg_temp_new_i32();
794 c->u.s32.b = tcg_temp_new_i32();
795 tcg_gen_trunc_i64_i32(c->u.s32.a, cc_vr);
796 if (cond == TCG_COND_EQ || cond == TCG_COND_NE) {
797 tcg_gen_movi_i32(c->u.s32.b, 0);
798 } else {
799 tcg_gen_trunc_i64_i32(c->u.s32.b, cc_src);
800 }
801 break;
802
803 case CC_OP_ADDU_64:
804 c->u.s64.a = cc_vr;
805 c->g1 = true;
806 if (cond == TCG_COND_EQ || cond == TCG_COND_NE) {
807 c->u.s64.b = tcg_const_i64(0);
808 } else {
809 c->u.s64.b = cc_src;
810 c->g2 = true;
811 }
812 break;
813
814 case CC_OP_STATIC:
815 c->is_64 = false;
816 c->u.s32.a = cc_op;
817 c->g1 = true;
818 switch (mask) {
819 case 0x8 | 0x4 | 0x2: /* cc != 3 */
820 cond = TCG_COND_NE;
821 c->u.s32.b = tcg_const_i32(3);
822 break;
823 case 0x8 | 0x4 | 0x1: /* cc != 2 */
824 cond = TCG_COND_NE;
825 c->u.s32.b = tcg_const_i32(2);
826 break;
827 case 0x8 | 0x2 | 0x1: /* cc != 1 */
828 cond = TCG_COND_NE;
829 c->u.s32.b = tcg_const_i32(1);
830 break;
831 case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
832 cond = TCG_COND_EQ;
833 c->g1 = false;
834 c->u.s32.a = tcg_temp_new_i32();
835 c->u.s32.b = tcg_const_i32(0);
836 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
837 break;
838 case 0x8 | 0x4: /* cc < 2 */
839 cond = TCG_COND_LTU;
840 c->u.s32.b = tcg_const_i32(2);
841 break;
842 case 0x8: /* cc == 0 */
843 cond = TCG_COND_EQ;
844 c->u.s32.b = tcg_const_i32(0);
845 break;
846 case 0x4 | 0x2 | 0x1: /* cc != 0 */
847 cond = TCG_COND_NE;
848 c->u.s32.b = tcg_const_i32(0);
849 break;
850 case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
851 cond = TCG_COND_NE;
852 c->g1 = false;
853 c->u.s32.a = tcg_temp_new_i32();
854 c->u.s32.b = tcg_const_i32(0);
855 tcg_gen_andi_i32(c->u.s32.a, cc_op, 1);
856 break;
857 case 0x4: /* cc == 1 */
858 cond = TCG_COND_EQ;
859 c->u.s32.b = tcg_const_i32(1);
860 break;
861 case 0x2 | 0x1: /* cc > 1 */
862 cond = TCG_COND_GTU;
863 c->u.s32.b = tcg_const_i32(1);
864 break;
865 case 0x2: /* cc == 2 */
866 cond = TCG_COND_EQ;
867 c->u.s32.b = tcg_const_i32(2);
868 break;
869 case 0x1: /* cc == 3 */
870 cond = TCG_COND_EQ;
871 c->u.s32.b = tcg_const_i32(3);
872 break;
873 default:
874 /* CC is masked by something else: (8 >> cc) & mask. */
875 cond = TCG_COND_NE;
876 c->g1 = false;
877 c->u.s32.a = tcg_const_i32(8);
878 c->u.s32.b = tcg_const_i32(0);
879 tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op);
880 tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask);
881 break;
882 }
883 break;
884
885 default:
886 abort();
887 }
888 c->cond = cond;
889 }
890
891 static void free_compare(DisasCompare *c)
892 {
893 if (!c->g1) {
894 if (c->is_64) {
895 tcg_temp_free_i64(c->u.s64.a);
896 } else {
897 tcg_temp_free_i32(c->u.s32.a);
898 }
899 }
900 if (!c->g2) {
901 if (c->is_64) {
902 tcg_temp_free_i64(c->u.s64.b);
903 } else {
904 tcg_temp_free_i32(c->u.s32.b);
905 }
906 }
907 }
908
909 /* ====================================================================== */
910 /* Define the insn format enumeration. */
911 #define F0(N) FMT_##N,
912 #define F1(N, X1) F0(N)
913 #define F2(N, X1, X2) F0(N)
914 #define F3(N, X1, X2, X3) F0(N)
915 #define F4(N, X1, X2, X3, X4) F0(N)
916 #define F5(N, X1, X2, X3, X4, X5) F0(N)
917
918 typedef enum {
919 #include "insn-format.def"
920 } DisasFormat;
921
922 #undef F0
923 #undef F1
924 #undef F2
925 #undef F3
926 #undef F4
927 #undef F5
928
929 /* Define a structure to hold the decoded fields. We'll store each inside
930 an array indexed by an enum. In order to conserve memory, we'll arrange
931 for fields that do not exist at the same time to overlap, thus the "C"
932 for compact. For checking purposes there is an "O" for original index
933 as well that will be applied to availability bitmaps. */
934
935 enum DisasFieldIndexO {
936 FLD_O_r1,
937 FLD_O_r2,
938 FLD_O_r3,
939 FLD_O_m1,
940 FLD_O_m3,
941 FLD_O_m4,
942 FLD_O_b1,
943 FLD_O_b2,
944 FLD_O_b4,
945 FLD_O_d1,
946 FLD_O_d2,
947 FLD_O_d4,
948 FLD_O_x2,
949 FLD_O_l1,
950 FLD_O_l2,
951 FLD_O_i1,
952 FLD_O_i2,
953 FLD_O_i3,
954 FLD_O_i4,
955 FLD_O_i5
956 };
957
958 enum DisasFieldIndexC {
959 FLD_C_r1 = 0,
960 FLD_C_m1 = 0,
961 FLD_C_b1 = 0,
962 FLD_C_i1 = 0,
963
964 FLD_C_r2 = 1,
965 FLD_C_b2 = 1,
966 FLD_C_i2 = 1,
967
968 FLD_C_r3 = 2,
969 FLD_C_m3 = 2,
970 FLD_C_i3 = 2,
971
972 FLD_C_m4 = 3,
973 FLD_C_b4 = 3,
974 FLD_C_i4 = 3,
975 FLD_C_l1 = 3,
976
977 FLD_C_i5 = 4,
978 FLD_C_d1 = 4,
979
980 FLD_C_d2 = 5,
981
982 FLD_C_d4 = 6,
983 FLD_C_x2 = 6,
984 FLD_C_l2 = 6,
985
986 NUM_C_FIELD = 7
987 };
988
989 struct DisasFields {
990 unsigned op:8;
991 unsigned op2:8;
992 unsigned presentC:16;
993 unsigned int presentO;
994 int c[NUM_C_FIELD];
995 };
996
997 /* This is the way fields are to be accessed out of DisasFields. */
998 #define have_field(S, F) have_field1((S), FLD_O_##F)
999 #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
1000
1001 static bool have_field1(const DisasFields *f, enum DisasFieldIndexO c)
1002 {
1003 return (f->presentO >> c) & 1;
1004 }
1005
1006 static int get_field1(const DisasFields *f, enum DisasFieldIndexO o,
1007 enum DisasFieldIndexC c)
1008 {
1009 assert(have_field1(f, o));
1010 return f->c[c];
1011 }
1012
1013 /* Describe the layout of each field in each format. */
1014 typedef struct DisasField {
1015 unsigned int beg:8;
1016 unsigned int size:8;
1017 unsigned int type:2;
1018 unsigned int indexC:6;
1019 enum DisasFieldIndexO indexO:8;
1020 } DisasField;
1021
1022 typedef struct DisasFormatInfo {
1023 DisasField op[NUM_C_FIELD];
1024 } DisasFormatInfo;
1025
1026 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
1027 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
1028 #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1029 { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
1030 #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1031 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1032 { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
1033 #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1034 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1035 #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1036 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1037 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1038 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
1039 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
1040
1041 #define F0(N) { { } },
1042 #define F1(N, X1) { { X1 } },
1043 #define F2(N, X1, X2) { { X1, X2 } },
1044 #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
1045 #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
1046 #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
1047
1048 static const DisasFormatInfo format_info[] = {
1049 #include "insn-format.def"
1050 };
1051
1052 #undef F0
1053 #undef F1
1054 #undef F2
1055 #undef F3
1056 #undef F4
1057 #undef F5
1058 #undef R
1059 #undef M
1060 #undef BD
1061 #undef BXD
1062 #undef BDL
1063 #undef BXDL
1064 #undef I
1065 #undef L
1066
1067 /* Generally, we'll extract operands into this structures, operate upon
1068 them, and store them back. See the "in1", "in2", "prep", "wout" sets
1069 of routines below for more details. */
1070 typedef struct {
1071 bool g_out, g_out2, g_in1, g_in2;
1072 TCGv_i64 out, out2, in1, in2;
1073 TCGv_i64 addr1;
1074 } DisasOps;
1075
1076 /* Instructions can place constraints on their operands, raising specification
1077 exceptions if they are violated. To make this easy to automate, each "in1",
1078 "in2", "prep", "wout" helper will have a SPEC_<name> define that equals one
1079 of the following, or 0. To make this easy to document, we'll put the
1080 SPEC_<name> defines next to <name>. */
1081
1082 #define SPEC_r1_even 1
1083 #define SPEC_r2_even 2
1084 #define SPEC_r3_even 4
1085 #define SPEC_r1_f128 8
1086 #define SPEC_r2_f128 16
1087
1088 /* Return values from translate_one, indicating the state of the TB. */
1089 typedef enum {
1090 /* Continue the TB. */
1091 NO_EXIT,
1092 /* We have emitted one or more goto_tb. No fixup required. */
1093 EXIT_GOTO_TB,
1094 /* We are not using a goto_tb (for whatever reason), but have updated
1095 the PC (for whatever reason), so there's no need to do it again on
1096 exiting the TB. */
1097 EXIT_PC_UPDATED,
1098 /* We are exiting the TB, but have neither emitted a goto_tb, nor
1099 updated the PC for the next instruction to be executed. */
1100 EXIT_PC_STALE,
1101 /* We are ending the TB with a noreturn function call, e.g. longjmp.
1102 No following code will be executed. */
1103 EXIT_NORETURN,
1104 } ExitStatus;
1105
1106 typedef enum DisasFacility {
1107 FAC_Z, /* zarch (default) */
1108 FAC_CASS, /* compare and swap and store */
1109 FAC_CASS2, /* compare and swap and store 2*/
1110 FAC_DFP, /* decimal floating point */
1111 FAC_DFPR, /* decimal floating point rounding */
1112 FAC_DO, /* distinct operands */
1113 FAC_EE, /* execute extensions */
1114 FAC_EI, /* extended immediate */
1115 FAC_FPE, /* floating point extension */
1116 FAC_FPSSH, /* floating point support sign handling */
1117 FAC_FPRGR, /* FPR-GR transfer */
1118 FAC_GIE, /* general instructions extension */
1119 FAC_HFP_MA, /* HFP multiply-and-add/subtract */
1120 FAC_HW, /* high-word */
1121 FAC_IEEEE_SIM, /* IEEE exception sumilation */
1122 FAC_LOC, /* load/store on condition */
1123 FAC_LD, /* long displacement */
1124 FAC_PC, /* population count */
1125 FAC_SCF, /* store clock fast */
1126 FAC_SFLE, /* store facility list extended */
1127 FAC_ILA, /* interlocked access facility 1 */
1128 } DisasFacility;
1129
1130 struct DisasInsn {
1131 unsigned opc:16;
1132 DisasFormat fmt:8;
1133 DisasFacility fac:8;
1134 unsigned spec:8;
1135
1136 const char *name;
1137
1138 void (*help_in1)(DisasContext *, DisasFields *, DisasOps *);
1139 void (*help_in2)(DisasContext *, DisasFields *, DisasOps *);
1140 void (*help_prep)(DisasContext *, DisasFields *, DisasOps *);
1141 void (*help_wout)(DisasContext *, DisasFields *, DisasOps *);
1142 void (*help_cout)(DisasContext *, DisasOps *);
1143 ExitStatus (*help_op)(DisasContext *, DisasOps *);
1144
1145 uint64_t data;
1146 };
1147
1148 /* ====================================================================== */
1149 /* Miscellaneous helpers, used by several operations. */
1150
1151 static void help_l2_shift(DisasContext *s, DisasFields *f,
1152 DisasOps *o, int mask)
1153 {
1154 int b2 = get_field(f, b2);
1155 int d2 = get_field(f, d2);
1156
1157 if (b2 == 0) {
1158 o->in2 = tcg_const_i64(d2 & mask);
1159 } else {
1160 o->in2 = get_address(s, 0, b2, d2);
1161 tcg_gen_andi_i64(o->in2, o->in2, mask);
1162 }
1163 }
1164
1165 static ExitStatus help_goto_direct(DisasContext *s, uint64_t dest)
1166 {
1167 if (dest == s->next_pc) {
1168 return NO_EXIT;
1169 }
1170 if (use_goto_tb(s, dest)) {
1171 update_cc_op(s);
1172 tcg_gen_goto_tb(0);
1173 tcg_gen_movi_i64(psw_addr, dest);
1174 tcg_gen_exit_tb((uintptr_t)s->tb);
1175 return EXIT_GOTO_TB;
1176 } else {
1177 tcg_gen_movi_i64(psw_addr, dest);
1178 return EXIT_PC_UPDATED;
1179 }
1180 }
1181
1182 static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
1183 bool is_imm, int imm, TCGv_i64 cdest)
1184 {
1185 ExitStatus ret;
1186 uint64_t dest = s->pc + 2 * imm;
1187 TCGLabel *lab;
1188
1189 /* Take care of the special cases first. */
1190 if (c->cond == TCG_COND_NEVER) {
1191 ret = NO_EXIT;
1192 goto egress;
1193 }
1194 if (is_imm) {
1195 if (dest == s->next_pc) {
1196 /* Branch to next. */
1197 ret = NO_EXIT;
1198 goto egress;
1199 }
1200 if (c->cond == TCG_COND_ALWAYS) {
1201 ret = help_goto_direct(s, dest);
1202 goto egress;
1203 }
1204 } else {
1205 if (TCGV_IS_UNUSED_I64(cdest)) {
1206 /* E.g. bcr %r0 -> no branch. */
1207 ret = NO_EXIT;
1208 goto egress;
1209 }
1210 if (c->cond == TCG_COND_ALWAYS) {
1211 tcg_gen_mov_i64(psw_addr, cdest);
1212 ret = EXIT_PC_UPDATED;
1213 goto egress;
1214 }
1215 }
1216
1217 if (use_goto_tb(s, s->next_pc)) {
1218 if (is_imm && use_goto_tb(s, dest)) {
1219 /* Both exits can use goto_tb. */
1220 update_cc_op(s);
1221
1222 lab = gen_new_label();
1223 if (c->is_64) {
1224 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1225 } else {
1226 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1227 }
1228
1229 /* Branch not taken. */
1230 tcg_gen_goto_tb(0);
1231 tcg_gen_movi_i64(psw_addr, s->next_pc);
1232 tcg_gen_exit_tb((uintptr_t)s->tb + 0);
1233
1234 /* Branch taken. */
1235 gen_set_label(lab);
1236 tcg_gen_goto_tb(1);
1237 tcg_gen_movi_i64(psw_addr, dest);
1238 tcg_gen_exit_tb((uintptr_t)s->tb + 1);
1239
1240 ret = EXIT_GOTO_TB;
1241 } else {
1242 /* Fallthru can use goto_tb, but taken branch cannot. */
1243 /* Store taken branch destination before the brcond. This
1244 avoids having to allocate a new local temp to hold it.
1245 We'll overwrite this in the not taken case anyway. */
1246 if (!is_imm) {
1247 tcg_gen_mov_i64(psw_addr, cdest);
1248 }
1249
1250 lab = gen_new_label();
1251 if (c->is_64) {
1252 tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
1253 } else {
1254 tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
1255 }
1256
1257 /* Branch not taken. */
1258 update_cc_op(s);
1259 tcg_gen_goto_tb(0);
1260 tcg_gen_movi_i64(psw_addr, s->next_pc);
1261 tcg_gen_exit_tb((uintptr_t)s->tb + 0);
1262
1263 gen_set_label(lab);
1264 if (is_imm) {
1265 tcg_gen_movi_i64(psw_addr, dest);
1266 }
1267 ret = EXIT_PC_UPDATED;
1268 }
1269 } else {
1270 /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
1271 Most commonly we're single-stepping or some other condition that
1272 disables all use of goto_tb. Just update the PC and exit. */
1273
1274 TCGv_i64 next = tcg_const_i64(s->next_pc);
1275 if (is_imm) {
1276 cdest = tcg_const_i64(dest);
1277 }
1278
1279 if (c->is_64) {
1280 tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b,
1281 cdest, next);
1282 } else {
1283 TCGv_i32 t0 = tcg_temp_new_i32();
1284 TCGv_i64 t1 = tcg_temp_new_i64();
1285 TCGv_i64 z = tcg_const_i64(0);
1286 tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b);
1287 tcg_gen_extu_i32_i64(t1, t0);
1288 tcg_temp_free_i32(t0);
1289 tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next);
1290 tcg_temp_free_i64(t1);
1291 tcg_temp_free_i64(z);
1292 }
1293
1294 if (is_imm) {
1295 tcg_temp_free_i64(cdest);
1296 }
1297 tcg_temp_free_i64(next);
1298
1299 ret = EXIT_PC_UPDATED;
1300 }
1301
1302 egress:
1303 free_compare(c);
1304 return ret;
1305 }
1306
1307 /* ====================================================================== */
1308 /* The operations. These perform the bulk of the work for any insn,
1309 usually after the operands have been loaded and output initialized. */
1310
1311 static ExitStatus op_abs(DisasContext *s, DisasOps *o)
1312 {
1313 gen_helper_abs_i64(o->out, o->in2);
1314 return NO_EXIT;
1315 }
1316
1317 static ExitStatus op_absf32(DisasContext *s, DisasOps *o)
1318 {
1319 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffull);
1320 return NO_EXIT;
1321 }
1322
1323 static ExitStatus op_absf64(DisasContext *s, DisasOps *o)
1324 {
1325 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull);
1326 return NO_EXIT;
1327 }
1328
1329 static ExitStatus op_absf128(DisasContext *s, DisasOps *o)
1330 {
1331 tcg_gen_andi_i64(o->out, o->in1, 0x7fffffffffffffffull);
1332 tcg_gen_mov_i64(o->out2, o->in2);
1333 return NO_EXIT;
1334 }
1335
1336 static ExitStatus op_add(DisasContext *s, DisasOps *o)
1337 {
1338 tcg_gen_add_i64(o->out, o->in1, o->in2);
1339 return NO_EXIT;
1340 }
1341
1342 static ExitStatus op_addc(DisasContext *s, DisasOps *o)
1343 {
1344 DisasCompare cmp;
1345 TCGv_i64 carry;
1346
1347 tcg_gen_add_i64(o->out, o->in1, o->in2);
1348
1349 /* The carry flag is the msb of CC, therefore the branch mask that would
1350 create that comparison is 3. Feeding the generated comparison to
1351 setcond produces the carry flag that we desire. */
1352 disas_jcc(s, &cmp, 3);
1353 carry = tcg_temp_new_i64();
1354 if (cmp.is_64) {
1355 tcg_gen_setcond_i64(cmp.cond, carry, cmp.u.s64.a, cmp.u.s64.b);
1356 } else {
1357 TCGv_i32 t = tcg_temp_new_i32();
1358 tcg_gen_setcond_i32(cmp.cond, t, cmp.u.s32.a, cmp.u.s32.b);
1359 tcg_gen_extu_i32_i64(carry, t);
1360 tcg_temp_free_i32(t);
1361 }
1362 free_compare(&cmp);
1363
1364 tcg_gen_add_i64(o->out, o->out, carry);
1365 tcg_temp_free_i64(carry);
1366 return NO_EXIT;
1367 }
1368
1369 static ExitStatus op_aeb(DisasContext *s, DisasOps *o)
1370 {
1371 gen_helper_aeb(o->out, cpu_env, o->in1, o->in2);
1372 return NO_EXIT;
1373 }
1374
1375 static ExitStatus op_adb(DisasContext *s, DisasOps *o)
1376 {
1377 gen_helper_adb(o->out, cpu_env, o->in1, o->in2);
1378 return NO_EXIT;
1379 }
1380
1381 static ExitStatus op_axb(DisasContext *s, DisasOps *o)
1382 {
1383 gen_helper_axb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
1384 return_low128(o->out2);
1385 return NO_EXIT;
1386 }
1387
1388 static ExitStatus op_and(DisasContext *s, DisasOps *o)
1389 {
1390 tcg_gen_and_i64(o->out, o->in1, o->in2);
1391 return NO_EXIT;
1392 }
1393
1394 static ExitStatus op_andi(DisasContext *s, DisasOps *o)
1395 {
1396 int shift = s->insn->data & 0xff;
1397 int size = s->insn->data >> 8;
1398 uint64_t mask = ((1ull << size) - 1) << shift;
1399
1400 assert(!o->g_in2);
1401 tcg_gen_shli_i64(o->in2, o->in2, shift);
1402 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
1403 tcg_gen_and_i64(o->out, o->in1, o->in2);
1404
1405 /* Produce the CC from only the bits manipulated. */
1406 tcg_gen_andi_i64(cc_dst, o->out, mask);
1407 set_cc_nz_u64(s, cc_dst);
1408 return NO_EXIT;
1409 }
1410
1411 static ExitStatus op_bas(DisasContext *s, DisasOps *o)
1412 {
1413 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1414 if (!TCGV_IS_UNUSED_I64(o->in2)) {
1415 tcg_gen_mov_i64(psw_addr, o->in2);
1416 return EXIT_PC_UPDATED;
1417 } else {
1418 return NO_EXIT;
1419 }
1420 }
1421
1422 static ExitStatus op_basi(DisasContext *s, DisasOps *o)
1423 {
1424 tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
1425 return help_goto_direct(s, s->pc + 2 * get_field(s->fields, i2));
1426 }
1427
1428 static ExitStatus op_bc(DisasContext *s, DisasOps *o)
1429 {
1430 int m1 = get_field(s->fields, m1);
1431 bool is_imm = have_field(s->fields, i2);
1432 int imm = is_imm ? get_field(s->fields, i2) : 0;
1433 DisasCompare c;
1434
1435 disas_jcc(s, &c, m1);
1436 return help_branch(s, &c, is_imm, imm, o->in2);
1437 }
1438
1439 static ExitStatus op_bct32(DisasContext *s, DisasOps *o)
1440 {
1441 int r1 = get_field(s->fields, r1);
1442 bool is_imm = have_field(s->fields, i2);
1443 int imm = is_imm ? get_field(s->fields, i2) : 0;
1444 DisasCompare c;
1445 TCGv_i64 t;
1446
1447 c.cond = TCG_COND_NE;
1448 c.is_64 = false;
1449 c.g1 = false;
1450 c.g2 = false;
1451
1452 t = tcg_temp_new_i64();
1453 tcg_gen_subi_i64(t, regs[r1], 1);
1454 store_reg32_i64(r1, t);
1455 c.u.s32.a = tcg_temp_new_i32();
1456 c.u.s32.b = tcg_const_i32(0);
1457 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
1458 tcg_temp_free_i64(t);
1459
1460 return help_branch(s, &c, is_imm, imm, o->in2);
1461 }
1462
1463 static ExitStatus op_bct64(DisasContext *s, DisasOps *o)
1464 {
1465 int r1 = get_field(s->fields, r1);
1466 bool is_imm = have_field(s->fields, i2);
1467 int imm = is_imm ? get_field(s->fields, i2) : 0;
1468 DisasCompare c;
1469
1470 c.cond = TCG_COND_NE;
1471 c.is_64 = true;
1472 c.g1 = true;
1473 c.g2 = false;
1474
1475 tcg_gen_subi_i64(regs[r1], regs[r1], 1);
1476 c.u.s64.a = regs[r1];
1477 c.u.s64.b = tcg_const_i64(0);
1478
1479 return help_branch(s, &c, is_imm, imm, o->in2);
1480 }
1481
1482 static ExitStatus op_bx32(DisasContext *s, DisasOps *o)
1483 {
1484 int r1 = get_field(s->fields, r1);
1485 int r3 = get_field(s->fields, r3);
1486 bool is_imm = have_field(s->fields, i2);
1487 int imm = is_imm ? get_field(s->fields, i2) : 0;
1488 DisasCompare c;
1489 TCGv_i64 t;
1490
1491 c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT);
1492 c.is_64 = false;
1493 c.g1 = false;
1494 c.g2 = false;
1495
1496 t = tcg_temp_new_i64();
1497 tcg_gen_add_i64(t, regs[r1], regs[r3]);
1498 c.u.s32.a = tcg_temp_new_i32();
1499 c.u.s32.b = tcg_temp_new_i32();
1500 tcg_gen_trunc_i64_i32(c.u.s32.a, t);
1501 tcg_gen_trunc_i64_i32(c.u.s32.b, regs[r3 | 1]);
1502 store_reg32_i64(r1, t);
1503 tcg_temp_free_i64(t);
1504
1505 return help_branch(s, &c, is_imm, imm, o->in2);
1506 }
1507
1508 static ExitStatus op_bx64(DisasContext *s, DisasOps *o)
1509 {
1510 int r1 = get_field(s->fields, r1);
1511 int r3 = get_field(s->fields, r3);
1512 bool is_imm = have_field(s->fields, i2);
1513 int imm = is_imm ? get_field(s->fields, i2) : 0;
1514 DisasCompare c;
1515
1516 c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT);
1517 c.is_64 = true;
1518
1519 if (r1 == (r3 | 1)) {
1520 c.u.s64.b = load_reg(r3 | 1);
1521 c.g2 = false;
1522 } else {
1523 c.u.s64.b = regs[r3 | 1];
1524 c.g2 = true;
1525 }
1526
1527 tcg_gen_add_i64(regs[r1], regs[r1], regs[r3]);
1528 c.u.s64.a = regs[r1];
1529 c.g1 = true;
1530
1531 return help_branch(s, &c, is_imm, imm, o->in2);
1532 }
1533
1534 static ExitStatus op_cj(DisasContext *s, DisasOps *o)
1535 {
1536 int imm, m3 = get_field(s->fields, m3);
1537 bool is_imm;
1538 DisasCompare c;
1539
1540 c.cond = ltgt_cond[m3];
1541 if (s->insn->data) {
1542 c.cond = tcg_unsigned_cond(c.cond);
1543 }
1544 c.is_64 = c.g1 = c.g2 = true;
1545 c.u.s64.a = o->in1;
1546 c.u.s64.b = o->in2;
1547
1548 is_imm = have_field(s->fields, i4);
1549 if (is_imm) {
1550 imm = get_field(s->fields, i4);
1551 } else {
1552 imm = 0;
1553 o->out = get_address(s, 0, get_field(s->fields, b4),
1554 get_field(s->fields, d4));
1555 }
1556
1557 return help_branch(s, &c, is_imm, imm, o->out);
1558 }
1559
1560 static ExitStatus op_ceb(DisasContext *s, DisasOps *o)
1561 {
1562 gen_helper_ceb(cc_op, cpu_env, o->in1, o->in2);
1563 set_cc_static(s);
1564 return NO_EXIT;
1565 }
1566
1567 static ExitStatus op_cdb(DisasContext *s, DisasOps *o)
1568 {
1569 gen_helper_cdb(cc_op, cpu_env, o->in1, o->in2);
1570 set_cc_static(s);
1571 return NO_EXIT;
1572 }
1573
1574 static ExitStatus op_cxb(DisasContext *s, DisasOps *o)
1575 {
1576 gen_helper_cxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2);
1577 set_cc_static(s);
1578 return NO_EXIT;
1579 }
1580
1581 static ExitStatus op_cfeb(DisasContext *s, DisasOps *o)
1582 {
1583 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1584 gen_helper_cfeb(o->out, cpu_env, o->in2, m3);
1585 tcg_temp_free_i32(m3);
1586 gen_set_cc_nz_f32(s, o->in2);
1587 return NO_EXIT;
1588 }
1589
1590 static ExitStatus op_cfdb(DisasContext *s, DisasOps *o)
1591 {
1592 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1593 gen_helper_cfdb(o->out, cpu_env, o->in2, m3);
1594 tcg_temp_free_i32(m3);
1595 gen_set_cc_nz_f64(s, o->in2);
1596 return NO_EXIT;
1597 }
1598
1599 static ExitStatus op_cfxb(DisasContext *s, DisasOps *o)
1600 {
1601 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1602 gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m3);
1603 tcg_temp_free_i32(m3);
1604 gen_set_cc_nz_f128(s, o->in1, o->in2);
1605 return NO_EXIT;
1606 }
1607
1608 static ExitStatus op_cgeb(DisasContext *s, DisasOps *o)
1609 {
1610 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1611 gen_helper_cgeb(o->out, cpu_env, o->in2, m3);
1612 tcg_temp_free_i32(m3);
1613 gen_set_cc_nz_f32(s, o->in2);
1614 return NO_EXIT;
1615 }
1616
1617 static ExitStatus op_cgdb(DisasContext *s, DisasOps *o)
1618 {
1619 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1620 gen_helper_cgdb(o->out, cpu_env, o->in2, m3);
1621 tcg_temp_free_i32(m3);
1622 gen_set_cc_nz_f64(s, o->in2);
1623 return NO_EXIT;
1624 }
1625
1626 static ExitStatus op_cgxb(DisasContext *s, DisasOps *o)
1627 {
1628 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1629 gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m3);
1630 tcg_temp_free_i32(m3);
1631 gen_set_cc_nz_f128(s, o->in1, o->in2);
1632 return NO_EXIT;
1633 }
1634
1635 static ExitStatus op_clfeb(DisasContext *s, DisasOps *o)
1636 {
1637 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1638 gen_helper_clfeb(o->out, cpu_env, o->in2, m3);
1639 tcg_temp_free_i32(m3);
1640 gen_set_cc_nz_f32(s, o->in2);
1641 return NO_EXIT;
1642 }
1643
1644 static ExitStatus op_clfdb(DisasContext *s, DisasOps *o)
1645 {
1646 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1647 gen_helper_clfdb(o->out, cpu_env, o->in2, m3);
1648 tcg_temp_free_i32(m3);
1649 gen_set_cc_nz_f64(s, o->in2);
1650 return NO_EXIT;
1651 }
1652
1653 static ExitStatus op_clfxb(DisasContext *s, DisasOps *o)
1654 {
1655 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1656 gen_helper_clfxb(o->out, cpu_env, o->in1, o->in2, m3);
1657 tcg_temp_free_i32(m3);
1658 gen_set_cc_nz_f128(s, o->in1, o->in2);
1659 return NO_EXIT;
1660 }
1661
1662 static ExitStatus op_clgeb(DisasContext *s, DisasOps *o)
1663 {
1664 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1665 gen_helper_clgeb(o->out, cpu_env, o->in2, m3);
1666 tcg_temp_free_i32(m3);
1667 gen_set_cc_nz_f32(s, o->in2);
1668 return NO_EXIT;
1669 }
1670
1671 static ExitStatus op_clgdb(DisasContext *s, DisasOps *o)
1672 {
1673 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1674 gen_helper_clgdb(o->out, cpu_env, o->in2, m3);
1675 tcg_temp_free_i32(m3);
1676 gen_set_cc_nz_f64(s, o->in2);
1677 return NO_EXIT;
1678 }
1679
1680 static ExitStatus op_clgxb(DisasContext *s, DisasOps *o)
1681 {
1682 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1683 gen_helper_clgxb(o->out, cpu_env, o->in1, o->in2, m3);
1684 tcg_temp_free_i32(m3);
1685 gen_set_cc_nz_f128(s, o->in1, o->in2);
1686 return NO_EXIT;
1687 }
1688
1689 static ExitStatus op_cegb(DisasContext *s, DisasOps *o)
1690 {
1691 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1692 gen_helper_cegb(o->out, cpu_env, o->in2, m3);
1693 tcg_temp_free_i32(m3);
1694 return NO_EXIT;
1695 }
1696
1697 static ExitStatus op_cdgb(DisasContext *s, DisasOps *o)
1698 {
1699 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1700 gen_helper_cdgb(o->out, cpu_env, o->in2, m3);
1701 tcg_temp_free_i32(m3);
1702 return NO_EXIT;
1703 }
1704
1705 static ExitStatus op_cxgb(DisasContext *s, DisasOps *o)
1706 {
1707 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1708 gen_helper_cxgb(o->out, cpu_env, o->in2, m3);
1709 tcg_temp_free_i32(m3);
1710 return_low128(o->out2);
1711 return NO_EXIT;
1712 }
1713
1714 static ExitStatus op_celgb(DisasContext *s, DisasOps *o)
1715 {
1716 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1717 gen_helper_celgb(o->out, cpu_env, o->in2, m3);
1718 tcg_temp_free_i32(m3);
1719 return NO_EXIT;
1720 }
1721
1722 static ExitStatus op_cdlgb(DisasContext *s, DisasOps *o)
1723 {
1724 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1725 gen_helper_cdlgb(o->out, cpu_env, o->in2, m3);
1726 tcg_temp_free_i32(m3);
1727 return NO_EXIT;
1728 }
1729
1730 static ExitStatus op_cxlgb(DisasContext *s, DisasOps *o)
1731 {
1732 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1733 gen_helper_cxlgb(o->out, cpu_env, o->in2, m3);
1734 tcg_temp_free_i32(m3);
1735 return_low128(o->out2);
1736 return NO_EXIT;
1737 }
1738
1739 static ExitStatus op_cksm(DisasContext *s, DisasOps *o)
1740 {
1741 int r2 = get_field(s->fields, r2);
1742 TCGv_i64 len = tcg_temp_new_i64();
1743
1744 potential_page_fault(s);
1745 gen_helper_cksm(len, cpu_env, o->in1, o->in2, regs[r2 + 1]);
1746 set_cc_static(s);
1747 return_low128(o->out);
1748
1749 tcg_gen_add_i64(regs[r2], regs[r2], len);
1750 tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len);
1751 tcg_temp_free_i64(len);
1752
1753 return NO_EXIT;
1754 }
1755
1756 static ExitStatus op_clc(DisasContext *s, DisasOps *o)
1757 {
1758 int l = get_field(s->fields, l1);
1759 TCGv_i32 vl;
1760
1761 switch (l + 1) {
1762 case 1:
1763 tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s));
1764 tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s));
1765 break;
1766 case 2:
1767 tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s));
1768 tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s));
1769 break;
1770 case 4:
1771 tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s));
1772 tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s));
1773 break;
1774 case 8:
1775 tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s));
1776 tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
1777 break;
1778 default:
1779 potential_page_fault(s);
1780 vl = tcg_const_i32(l);
1781 gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
1782 tcg_temp_free_i32(vl);
1783 set_cc_static(s);
1784 return NO_EXIT;
1785 }
1786 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
1787 return NO_EXIT;
1788 }
1789
1790 static ExitStatus op_clcle(DisasContext *s, DisasOps *o)
1791 {
1792 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1793 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
1794 potential_page_fault(s);
1795 gen_helper_clcle(cc_op, cpu_env, r1, o->in2, r3);
1796 tcg_temp_free_i32(r1);
1797 tcg_temp_free_i32(r3);
1798 set_cc_static(s);
1799 return NO_EXIT;
1800 }
1801
1802 static ExitStatus op_clm(DisasContext *s, DisasOps *o)
1803 {
1804 TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
1805 TCGv_i32 t1 = tcg_temp_new_i32();
1806 tcg_gen_trunc_i64_i32(t1, o->in1);
1807 potential_page_fault(s);
1808 gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2);
1809 set_cc_static(s);
1810 tcg_temp_free_i32(t1);
1811 tcg_temp_free_i32(m3);
1812 return NO_EXIT;
1813 }
1814
1815 static ExitStatus op_clst(DisasContext *s, DisasOps *o)
1816 {
1817 potential_page_fault(s);
1818 gen_helper_clst(o->in1, cpu_env, regs[0], o->in1, o->in2);
1819 set_cc_static(s);
1820 return_low128(o->in2);
1821 return NO_EXIT;
1822 }
1823
1824 static ExitStatus op_cps(DisasContext *s, DisasOps *o)
1825 {
1826 TCGv_i64 t = tcg_temp_new_i64();
1827 tcg_gen_andi_i64(t, o->in1, 0x8000000000000000ull);
1828 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull);
1829 tcg_gen_or_i64(o->out, o->out, t);
1830 tcg_temp_free_i64(t);
1831 return NO_EXIT;
1832 }
1833
1834 static ExitStatus op_cs(DisasContext *s, DisasOps *o)
1835 {
1836 /* FIXME: needs an atomic solution for CONFIG_USER_ONLY. */
1837 int d2 = get_field(s->fields, d2);
1838 int b2 = get_field(s->fields, b2);
1839 int is_64 = s->insn->data;
1840 TCGv_i64 addr, mem, cc, z;
1841
1842 /* Note that in1 = R3 (new value) and
1843 in2 = (zero-extended) R1 (expected value). */
1844
1845 /* Load the memory into the (temporary) output. While the PoO only talks
1846 about moving the memory to R1 on inequality, if we include equality it
1847 means that R1 is equal to the memory in all conditions. */
1848 addr = get_address(s, 0, b2, d2);
1849 if (is_64) {
1850 tcg_gen_qemu_ld64(o->out, addr, get_mem_index(s));
1851 } else {
1852 tcg_gen_qemu_ld32u(o->out, addr, get_mem_index(s));
1853 }
1854
1855 /* Are the memory and expected values (un)equal? Note that this setcond
1856 produces the output CC value, thus the NE sense of the test. */
1857 cc = tcg_temp_new_i64();
1858 tcg_gen_setcond_i64(TCG_COND_NE, cc, o->in2, o->out);
1859
1860 /* If the memory and expected values are equal (CC==0), copy R3 to MEM.
1861 Recall that we are allowed to unconditionally issue the store (and
1862 thus any possible write trap), so (re-)store the original contents
1863 of MEM in case of inequality. */
1864 z = tcg_const_i64(0);
1865 mem = tcg_temp_new_i64();
1866 tcg_gen_movcond_i64(TCG_COND_EQ, mem, cc, z, o->in1, o->out);
1867 if (is_64) {
1868 tcg_gen_qemu_st64(mem, addr, get_mem_index(s));
1869 } else {
1870 tcg_gen_qemu_st32(mem, addr, get_mem_index(s));
1871 }
1872 tcg_temp_free_i64(z);
1873 tcg_temp_free_i64(mem);
1874 tcg_temp_free_i64(addr);
1875
1876 /* Store CC back to cc_op. Wait until after the store so that any
1877 exception gets the old cc_op value. */
1878 tcg_gen_trunc_i64_i32(cc_op, cc);
1879 tcg_temp_free_i64(cc);
1880 set_cc_static(s);
1881 return NO_EXIT;
1882 }
1883
1884 static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
1885 {
1886 /* FIXME: needs an atomic solution for CONFIG_USER_ONLY. */
1887 int r1 = get_field(s->fields, r1);
1888 int r3 = get_field(s->fields, r3);
1889 int d2 = get_field(s->fields, d2);
1890 int b2 = get_field(s->fields, b2);
1891 TCGv_i64 addrh, addrl, memh, meml, outh, outl, cc, z;
1892
1893 /* Note that R1:R1+1 = expected value and R3:R3+1 = new value. */
1894
1895 addrh = get_address(s, 0, b2, d2);
1896 addrl = get_address(s, 0, b2, d2 + 8);
1897 outh = tcg_temp_new_i64();
1898 outl = tcg_temp_new_i64();
1899
1900 tcg_gen_qemu_ld64(outh, addrh, get_mem_index(s));
1901 tcg_gen_qemu_ld64(outl, addrl, get_mem_index(s));
1902
1903 /* Fold the double-word compare with arithmetic. */
1904 cc = tcg_temp_new_i64();
1905 z = tcg_temp_new_i64();
1906 tcg_gen_xor_i64(cc, outh, regs[r1]);
1907 tcg_gen_xor_i64(z, outl, regs[r1 + 1]);
1908 tcg_gen_or_i64(cc, cc, z);
1909 tcg_gen_movi_i64(z, 0);
1910 tcg_gen_setcond_i64(TCG_COND_NE, cc, cc, z);
1911
1912 memh = tcg_temp_new_i64();
1913 meml = tcg_temp_new_i64();
1914 tcg_gen_movcond_i64(TCG_COND_EQ, memh, cc, z, regs[r3], outh);
1915 tcg_gen_movcond_i64(TCG_COND_EQ, meml, cc, z, regs[r3 + 1], outl);
1916 tcg_temp_free_i64(z);
1917
1918 tcg_gen_qemu_st64(memh, addrh, get_mem_index(s));
1919 tcg_gen_qemu_st64(meml, addrl, get_mem_index(s));
1920 tcg_temp_free_i64(memh);
1921 tcg_temp_free_i64(meml);
1922 tcg_temp_free_i64(addrh);
1923 tcg_temp_free_i64(addrl);
1924
1925 /* Save back state now that we've passed all exceptions. */
1926 tcg_gen_mov_i64(regs[r1], outh);
1927 tcg_gen_mov_i64(regs[r1 + 1], outl);
1928 tcg_gen_trunc_i64_i32(cc_op, cc);
1929 tcg_temp_free_i64(outh);
1930 tcg_temp_free_i64(outl);
1931 tcg_temp_free_i64(cc);
1932 set_cc_static(s);
1933 return NO_EXIT;
1934 }
1935
1936 #ifndef CONFIG_USER_ONLY
1937 static ExitStatus op_csp(DisasContext *s, DisasOps *o)
1938 {
1939 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
1940 check_privileged(s);
1941 gen_helper_csp(cc_op, cpu_env, r1, o->in2);
1942 tcg_temp_free_i32(r1);
1943 set_cc_static(s);
1944 return NO_EXIT;
1945 }
1946 #endif
1947
1948 static ExitStatus op_cvd(DisasContext *s, DisasOps *o)
1949 {
1950 TCGv_i64 t1 = tcg_temp_new_i64();
1951 TCGv_i32 t2 = tcg_temp_new_i32();
1952 tcg_gen_trunc_i64_i32(t2, o->in1);
1953 gen_helper_cvd(t1, t2);
1954 tcg_temp_free_i32(t2);
1955 tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
1956 tcg_temp_free_i64(t1);
1957 return NO_EXIT;
1958 }
1959
1960 static ExitStatus op_ct(DisasContext *s, DisasOps *o)
1961 {
1962 int m3 = get_field(s->fields, m3);
1963 TCGLabel *lab = gen_new_label();
1964 TCGv_i32 t;
1965 TCGCond c;
1966
1967 c = tcg_invert_cond(ltgt_cond[m3]);
1968 if (s->insn->data) {
1969 c = tcg_unsigned_cond(c);
1970 }
1971 tcg_gen_brcond_i64(c, o->in1, o->in2, lab);
1972
1973 /* Set DXC to 0xff. */
1974 t = tcg_temp_new_i32();
1975 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUS390XState, fpc));
1976 tcg_gen_ori_i32(t, t, 0xff00);
1977 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, fpc));
1978 tcg_temp_free_i32(t);
1979
1980 /* Trap. */
1981 gen_program_exception(s, PGM_DATA);
1982
1983 gen_set_label(lab);
1984 return NO_EXIT;
1985 }
1986
1987 #ifndef CONFIG_USER_ONLY
1988 static ExitStatus op_diag(DisasContext *s, DisasOps *o)
1989 {
1990 TCGv_i32 tmp;
1991
1992 check_privileged(s);
1993 potential_page_fault(s);
1994
1995 /* We pretend the format is RX_a so that D2 is the field we want. */
1996 tmp = tcg_const_i32(get_field(s->fields, d2) & 0xfff);
1997 gen_helper_diag(regs[2], cpu_env, tmp, regs[2], regs[1]);
1998 tcg_temp_free_i32(tmp);
1999 return NO_EXIT;
2000 }
2001 #endif
2002
2003 static ExitStatus op_divs32(DisasContext *s, DisasOps *o)
2004 {
2005 gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2);
2006 return_low128(o->out);
2007 return NO_EXIT;
2008 }
2009
2010 static ExitStatus op_divu32(DisasContext *s, DisasOps *o)
2011 {
2012 gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2);
2013 return_low128(o->out);
2014 return NO_EXIT;
2015 }
2016
2017 static ExitStatus op_divs64(DisasContext *s, DisasOps *o)
2018 {
2019 gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2);
2020 return_low128(o->out);
2021 return NO_EXIT;
2022 }
2023
2024 static ExitStatus op_divu64(DisasContext *s, DisasOps *o)
2025 {
2026 gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2);
2027 return_low128(o->out);
2028 return NO_EXIT;
2029 }
2030
2031 static ExitStatus op_deb(DisasContext *s, DisasOps *o)
2032 {
2033 gen_helper_deb(o->out, cpu_env, o->in1, o->in2);
2034 return NO_EXIT;
2035 }
2036
2037 static ExitStatus op_ddb(DisasContext *s, DisasOps *o)
2038 {
2039 gen_helper_ddb(o->out, cpu_env, o->in1, o->in2);
2040 return NO_EXIT;
2041 }
2042
2043 static ExitStatus op_dxb(DisasContext *s, DisasOps *o)
2044 {
2045 gen_helper_dxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2046 return_low128(o->out2);
2047 return NO_EXIT;
2048 }
2049
2050 static ExitStatus op_ear(DisasContext *s, DisasOps *o)
2051 {
2052 int r2 = get_field(s->fields, r2);
2053 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, aregs[r2]));
2054 return NO_EXIT;
2055 }
2056
2057 static ExitStatus op_ecag(DisasContext *s, DisasOps *o)
2058 {
2059 /* No cache information provided. */
2060 tcg_gen_movi_i64(o->out, -1);
2061 return NO_EXIT;
2062 }
2063
2064 static ExitStatus op_efpc(DisasContext *s, DisasOps *o)
2065 {
2066 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, fpc));
2067 return NO_EXIT;
2068 }
2069
2070 static ExitStatus op_epsw(DisasContext *s, DisasOps *o)
2071 {
2072 int r1 = get_field(s->fields, r1);
2073 int r2 = get_field(s->fields, r2);
2074 TCGv_i64 t = tcg_temp_new_i64();
2075
2076 /* Note the "subsequently" in the PoO, which implies a defined result
2077 if r1 == r2. Thus we cannot defer these writes to an output hook. */
2078 tcg_gen_shri_i64(t, psw_mask, 32);
2079 store_reg32_i64(r1, t);
2080 if (r2 != 0) {
2081 store_reg32_i64(r2, psw_mask);
2082 }
2083
2084 tcg_temp_free_i64(t);
2085 return NO_EXIT;
2086 }
2087
2088 static ExitStatus op_ex(DisasContext *s, DisasOps *o)
2089 {
2090 /* ??? Perhaps a better way to implement EXECUTE is to set a bit in
2091 tb->flags, (ab)use the tb->cs_base field as the address of
2092 the template in memory, and grab 8 bits of tb->flags/cflags for
2093 the contents of the register. We would then recognize all this
2094 in gen_intermediate_code_internal, generating code for exactly
2095 one instruction. This new TB then gets executed normally.
2096
2097 On the other hand, this seems to be mostly used for modifying
2098 MVC inside of memcpy, which needs a helper call anyway. So
2099 perhaps this doesn't bear thinking about any further. */
2100
2101 TCGv_i64 tmp;
2102
2103 update_psw_addr(s);
2104 gen_op_calc_cc(s);
2105
2106 tmp = tcg_const_i64(s->next_pc);
2107 gen_helper_ex(cc_op, cpu_env, cc_op, o->in1, o->in2, tmp);
2108 tcg_temp_free_i64(tmp);
2109
2110 return NO_EXIT;
2111 }
2112
2113 static ExitStatus op_flogr(DisasContext *s, DisasOps *o)
2114 {
2115 /* We'll use the original input for cc computation, since we get to
2116 compare that against 0, which ought to be better than comparing
2117 the real output against 64. It also lets cc_dst be a convenient
2118 temporary during our computation. */
2119 gen_op_update1_cc_i64(s, CC_OP_FLOGR, o->in2);
2120
2121 /* R1 = IN ? CLZ(IN) : 64. */
2122 gen_helper_clz(o->out, o->in2);
2123
2124 /* R1+1 = IN & ~(found bit). Note that we may attempt to shift this
2125 value by 64, which is undefined. But since the shift is 64 iff the
2126 input is zero, we still get the correct result after and'ing. */
2127 tcg_gen_movi_i64(o->out2, 0x8000000000000000ull);
2128 tcg_gen_shr_i64(o->out2, o->out2, o->out);
2129 tcg_gen_andc_i64(o->out2, cc_dst, o->out2);
2130 return NO_EXIT;
2131 }
2132
2133 static ExitStatus op_icm(DisasContext *s, DisasOps *o)
2134 {
2135 int m3 = get_field(s->fields, m3);
2136 int pos, len, base = s->insn->data;
2137 TCGv_i64 tmp = tcg_temp_new_i64();
2138 uint64_t ccm;
2139
2140 switch (m3) {
2141 case 0xf:
2142 /* Effectively a 32-bit load. */
2143 tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
2144 len = 32;
2145 goto one_insert;
2146
2147 case 0xc:
2148 case 0x6:
2149 case 0x3:
2150 /* Effectively a 16-bit load. */
2151 tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
2152 len = 16;
2153 goto one_insert;
2154
2155 case 0x8:
2156 case 0x4:
2157 case 0x2:
2158 case 0x1:
2159 /* Effectively an 8-bit load. */
2160 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2161 len = 8;
2162 goto one_insert;
2163
2164 one_insert:
2165 pos = base + ctz32(m3) * 8;
2166 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len);
2167 ccm = ((1ull << len) - 1) << pos;
2168 break;
2169
2170 default:
2171 /* This is going to be a sequence of loads and inserts. */
2172 pos = base + 32 - 8;
2173 ccm = 0;
2174 while (m3) {
2175 if (m3 & 0x8) {
2176 tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
2177 tcg_gen_addi_i64(o->in2, o->in2, 1);
2178 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
2179 ccm |= 0xff << pos;
2180 }
2181 m3 = (m3 << 1) & 0xf;
2182 pos -= 8;
2183 }
2184 break;
2185 }
2186
2187 tcg_gen_movi_i64(tmp, ccm);
2188 gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out);
2189 tcg_temp_free_i64(tmp);
2190 return NO_EXIT;
2191 }
2192
2193 static ExitStatus op_insi(DisasContext *s, DisasOps *o)
2194 {
2195 int shift = s->insn->data & 0xff;
2196 int size = s->insn->data >> 8;
2197 tcg_gen_deposit_i64(o->out, o->in1, o->in2, shift, size);
2198 return NO_EXIT;
2199 }
2200
2201 static ExitStatus op_ipm(DisasContext *s, DisasOps *o)
2202 {
2203 TCGv_i64 t1;
2204
2205 gen_op_calc_cc(s);
2206 tcg_gen_andi_i64(o->out, o->out, ~0xff000000ull);
2207
2208 t1 = tcg_temp_new_i64();
2209 tcg_gen_shli_i64(t1, psw_mask, 20);
2210 tcg_gen_shri_i64(t1, t1, 36);
2211 tcg_gen_or_i64(o->out, o->out, t1);
2212
2213 tcg_gen_extu_i32_i64(t1, cc_op);
2214 tcg_gen_shli_i64(t1, t1, 28);
2215 tcg_gen_or_i64(o->out, o->out, t1);
2216 tcg_temp_free_i64(t1);
2217 return NO_EXIT;
2218 }
2219
2220 #ifndef CONFIG_USER_ONLY
2221 static ExitStatus op_ipte(DisasContext *s, DisasOps *o)
2222 {
2223 check_privileged(s);
2224 gen_helper_ipte(cpu_env, o->in1, o->in2);
2225 return NO_EXIT;
2226 }
2227
2228 static ExitStatus op_iske(DisasContext *s, DisasOps *o)
2229 {
2230 check_privileged(s);
2231 gen_helper_iske(o->out, cpu_env, o->in2);
2232 return NO_EXIT;
2233 }
2234 #endif
2235
2236 static ExitStatus op_ldeb(DisasContext *s, DisasOps *o)
2237 {
2238 gen_helper_ldeb(o->out, cpu_env, o->in2);
2239 return NO_EXIT;
2240 }
2241
2242 static ExitStatus op_ledb(DisasContext *s, DisasOps *o)
2243 {
2244 gen_helper_ledb(o->out, cpu_env, o->in2);
2245 return NO_EXIT;
2246 }
2247
2248 static ExitStatus op_ldxb(DisasContext *s, DisasOps *o)
2249 {
2250 gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2);
2251 return NO_EXIT;
2252 }
2253
2254 static ExitStatus op_lexb(DisasContext *s, DisasOps *o)
2255 {
2256 gen_helper_lexb(o->out, cpu_env, o->in1, o->in2);
2257 return NO_EXIT;
2258 }
2259
2260 static ExitStatus op_lxdb(DisasContext *s, DisasOps *o)
2261 {
2262 gen_helper_lxdb(o->out, cpu_env, o->in2);
2263 return_low128(o->out2);
2264 return NO_EXIT;
2265 }
2266
2267 static ExitStatus op_lxeb(DisasContext *s, DisasOps *o)
2268 {
2269 gen_helper_lxeb(o->out, cpu_env, o->in2);
2270 return_low128(o->out2);
2271 return NO_EXIT;
2272 }
2273
2274 static ExitStatus op_llgt(DisasContext *s, DisasOps *o)
2275 {
2276 tcg_gen_andi_i64(o->out, o->in2, 0x7fffffff);
2277 return NO_EXIT;
2278 }
2279
2280 static ExitStatus op_ld8s(DisasContext *s, DisasOps *o)
2281 {
2282 tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
2283 return NO_EXIT;
2284 }
2285
2286 static ExitStatus op_ld8u(DisasContext *s, DisasOps *o)
2287 {
2288 tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
2289 return NO_EXIT;
2290 }
2291
2292 static ExitStatus op_ld16s(DisasContext *s, DisasOps *o)
2293 {
2294 tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
2295 return NO_EXIT;
2296 }
2297
2298 static ExitStatus op_ld16u(DisasContext *s, DisasOps *o)
2299 {
2300 tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
2301 return NO_EXIT;
2302 }
2303
2304 static ExitStatus op_ld32s(DisasContext *s, DisasOps *o)
2305 {
2306 tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s));
2307 return NO_EXIT;
2308 }
2309
2310 static ExitStatus op_ld32u(DisasContext *s, DisasOps *o)
2311 {
2312 tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
2313 return NO_EXIT;
2314 }
2315
2316 static ExitStatus op_ld64(DisasContext *s, DisasOps *o)
2317 {
2318 tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
2319 return NO_EXIT;
2320 }
2321
2322 static ExitStatus op_loc(DisasContext *s, DisasOps *o)
2323 {
2324 DisasCompare c;
2325
2326 disas_jcc(s, &c, get_field(s->fields, m3));
2327
2328 if (c.is_64) {
2329 tcg_gen_movcond_i64(c.cond, o->out, c.u.s64.a, c.u.s64.b,
2330 o->in2, o->in1);
2331 free_compare(&c);
2332 } else {
2333 TCGv_i32 t32 = tcg_temp_new_i32();
2334 TCGv_i64 t, z;
2335
2336 tcg_gen_setcond_i32(c.cond, t32, c.u.s32.a, c.u.s32.b);
2337 free_compare(&c);
2338
2339 t = tcg_temp_new_i64();
2340 tcg_gen_extu_i32_i64(t, t32);
2341 tcg_temp_free_i32(t32);
2342
2343 z = tcg_const_i64(0);
2344 tcg_gen_movcond_i64(TCG_COND_NE, o->out, t, z, o->in2, o->in1);
2345 tcg_temp_free_i64(t);
2346 tcg_temp_free_i64(z);
2347 }
2348
2349 return NO_EXIT;
2350 }
2351
2352 #ifndef CONFIG_USER_ONLY
2353 static ExitStatus op_lctl(DisasContext *s, DisasOps *o)
2354 {
2355 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2356 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2357 check_privileged(s);
2358 potential_page_fault(s);
2359 gen_helper_lctl(cpu_env, r1, o->in2, r3);
2360 tcg_temp_free_i32(r1);
2361 tcg_temp_free_i32(r3);
2362 return NO_EXIT;
2363 }
2364
2365 static ExitStatus op_lctlg(DisasContext *s, DisasOps *o)
2366 {
2367 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2368 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2369 check_privileged(s);
2370 potential_page_fault(s);
2371 gen_helper_lctlg(cpu_env, r1, o->in2, r3);
2372 tcg_temp_free_i32(r1);
2373 tcg_temp_free_i32(r3);
2374 return NO_EXIT;
2375 }
2376 static ExitStatus op_lra(DisasContext *s, DisasOps *o)
2377 {
2378 check_privileged(s);
2379 potential_page_fault(s);
2380 gen_helper_lra(o->out, cpu_env, o->in2);
2381 set_cc_static(s);
2382 return NO_EXIT;
2383 }
2384
2385 static ExitStatus op_lpsw(DisasContext *s, DisasOps *o)
2386 {
2387 TCGv_i64 t1, t2;
2388
2389 check_privileged(s);
2390
2391 t1 = tcg_temp_new_i64();
2392 t2 = tcg_temp_new_i64();
2393 tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
2394 tcg_gen_addi_i64(o->in2, o->in2, 4);
2395 tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s));
2396 /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
2397 tcg_gen_shli_i64(t1, t1, 32);
2398 gen_helper_load_psw(cpu_env, t1, t2);
2399 tcg_temp_free_i64(t1);
2400 tcg_temp_free_i64(t2);
2401 return EXIT_NORETURN;
2402 }
2403
2404 static ExitStatus op_lpswe(DisasContext *s, DisasOps *o)
2405 {
2406 TCGv_i64 t1, t2;
2407
2408 check_privileged(s);
2409
2410 t1 = tcg_temp_new_i64();
2411 t2 = tcg_temp_new_i64();
2412 tcg_gen_qemu_ld64(t1, o->in2, get_mem_index(s));
2413 tcg_gen_addi_i64(o->in2, o->in2, 8);
2414 tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s));
2415 gen_helper_load_psw(cpu_env, t1, t2);
2416 tcg_temp_free_i64(t1);
2417 tcg_temp_free_i64(t2);
2418 return EXIT_NORETURN;
2419 }
2420 #endif
2421
2422 static ExitStatus op_lam(DisasContext *s, DisasOps *o)
2423 {
2424 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2425 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2426 potential_page_fault(s);
2427 gen_helper_lam(cpu_env, r1, o->in2, r3);
2428 tcg_temp_free_i32(r1);
2429 tcg_temp_free_i32(r3);
2430 return NO_EXIT;
2431 }
2432
2433 static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
2434 {
2435 int r1 = get_field(s->fields, r1);
2436 int r3 = get_field(s->fields, r3);
2437 TCGv_i64 t = tcg_temp_new_i64();
2438 TCGv_i64 t4 = tcg_const_i64(4);
2439
2440 while (1) {
2441 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2442 store_reg32_i64(r1, t);
2443 if (r1 == r3) {
2444 break;
2445 }
2446 tcg_gen_add_i64(o->in2, o->in2, t4);
2447 r1 = (r1 + 1) & 15;
2448 }
2449
2450 tcg_temp_free_i64(t);
2451 tcg_temp_free_i64(t4);
2452 return NO_EXIT;
2453 }
2454
2455 static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
2456 {
2457 int r1 = get_field(s->fields, r1);
2458 int r3 = get_field(s->fields, r3);
2459 TCGv_i64 t = tcg_temp_new_i64();
2460 TCGv_i64 t4 = tcg_const_i64(4);
2461
2462 while (1) {
2463 tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
2464 store_reg32h_i64(r1, t);
2465 if (r1 == r3) {
2466 break;
2467 }
2468 tcg_gen_add_i64(o->in2, o->in2, t4);
2469 r1 = (r1 + 1) & 15;
2470 }
2471
2472 tcg_temp_free_i64(t);
2473 tcg_temp_free_i64(t4);
2474 return NO_EXIT;
2475 }
2476
2477 static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
2478 {
2479 int r1 = get_field(s->fields, r1);
2480 int r3 = get_field(s->fields, r3);
2481 TCGv_i64 t8 = tcg_const_i64(8);
2482
2483 while (1) {
2484 tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
2485 if (r1 == r3) {
2486 break;
2487 }
2488 tcg_gen_add_i64(o->in2, o->in2, t8);
2489 r1 = (r1 + 1) & 15;
2490 }
2491
2492 tcg_temp_free_i64(t8);
2493 return NO_EXIT;
2494 }
2495
2496 #ifndef CONFIG_USER_ONLY
2497 static ExitStatus op_lura(DisasContext *s, DisasOps *o)
2498 {
2499 check_privileged(s);
2500 potential_page_fault(s);
2501 gen_helper_lura(o->out, cpu_env, o->in2);
2502 return NO_EXIT;
2503 }
2504
2505 static ExitStatus op_lurag(DisasContext *s, DisasOps *o)
2506 {
2507 check_privileged(s);
2508 potential_page_fault(s);
2509 gen_helper_lurag(o->out, cpu_env, o->in2);
2510 return NO_EXIT;
2511 }
2512 #endif
2513
2514 static ExitStatus op_mov2(DisasContext *s, DisasOps *o)
2515 {
2516 o->out = o->in2;
2517 o->g_out = o->g_in2;
2518 TCGV_UNUSED_I64(o->in2);
2519 o->g_in2 = false;
2520 return NO_EXIT;
2521 }
2522
2523 static ExitStatus op_movx(DisasContext *s, DisasOps *o)
2524 {
2525 o->out = o->in1;
2526 o->out2 = o->in2;
2527 o->g_out = o->g_in1;
2528 o->g_out2 = o->g_in2;
2529 TCGV_UNUSED_I64(o->in1);
2530 TCGV_UNUSED_I64(o->in2);
2531 o->g_in1 = o->g_in2 = false;
2532 return NO_EXIT;
2533 }
2534
2535 static ExitStatus op_mvc(DisasContext *s, DisasOps *o)
2536 {
2537 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2538 potential_page_fault(s);
2539 gen_helper_mvc(cpu_env, l, o->addr1, o->in2);
2540 tcg_temp_free_i32(l);
2541 return NO_EXIT;
2542 }
2543
2544 static ExitStatus op_mvcl(DisasContext *s, DisasOps *o)
2545 {
2546 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2547 TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
2548 potential_page_fault(s);
2549 gen_helper_mvcl(cc_op, cpu_env, r1, r2);
2550 tcg_temp_free_i32(r1);
2551 tcg_temp_free_i32(r2);
2552 set_cc_static(s);
2553 return NO_EXIT;
2554 }
2555
2556 static ExitStatus op_mvcle(DisasContext *s, DisasOps *o)
2557 {
2558 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
2559 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
2560 potential_page_fault(s);
2561 gen_helper_mvcle(cc_op, cpu_env, r1, o->in2, r3);
2562 tcg_temp_free_i32(r1);
2563 tcg_temp_free_i32(r3);
2564 set_cc_static(s);
2565 return NO_EXIT;
2566 }
2567
2568 #ifndef CONFIG_USER_ONLY
2569 static ExitStatus op_mvcp(DisasContext *s, DisasOps *o)
2570 {
2571 int r1 = get_field(s->fields, l1);
2572 check_privileged(s);
2573 potential_page_fault(s);
2574 gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2575 set_cc_static(s);
2576 return NO_EXIT;
2577 }
2578
2579 static ExitStatus op_mvcs(DisasContext *s, DisasOps *o)
2580 {
2581 int r1 = get_field(s->fields, l1);
2582 check_privileged(s);
2583 potential_page_fault(s);
2584 gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
2585 set_cc_static(s);
2586 return NO_EXIT;
2587 }
2588 #endif
2589
2590 static ExitStatus op_mvpg(DisasContext *s, DisasOps *o)
2591 {
2592 potential_page_fault(s);
2593 gen_helper_mvpg(cpu_env, regs[0], o->in1, o->in2);
2594 set_cc_static(s);
2595 return NO_EXIT;
2596 }
2597
2598 static ExitStatus op_mvst(DisasContext *s, DisasOps *o)
2599 {
2600 potential_page_fault(s);
2601 gen_helper_mvst(o->in1, cpu_env, regs[0], o->in1, o->in2);
2602 set_cc_static(s);
2603 return_low128(o->in2);
2604 return NO_EXIT;
2605 }
2606
2607 static ExitStatus op_mul(DisasContext *s, DisasOps *o)
2608 {
2609 tcg_gen_mul_i64(o->out, o->in1, o->in2);
2610 return NO_EXIT;
2611 }
2612
2613 static ExitStatus op_mul128(DisasContext *s, DisasOps *o)
2614 {
2615 tcg_gen_mulu2_i64(o->out2, o->out, o->in1, o->in2);
2616 return NO_EXIT;
2617 }
2618
2619 static ExitStatus op_meeb(DisasContext *s, DisasOps *o)
2620 {
2621 gen_helper_meeb(o->out, cpu_env, o->in1, o->in2);
2622 return NO_EXIT;
2623 }
2624
2625 static ExitStatus op_mdeb(DisasContext *s, DisasOps *o)
2626 {
2627 gen_helper_mdeb(o->out, cpu_env, o->in1, o->in2);
2628 return NO_EXIT;
2629 }
2630
2631 static ExitStatus op_mdb(DisasContext *s, DisasOps *o)
2632 {
2633 gen_helper_mdb(o->out, cpu_env, o->in1, o->in2);
2634 return NO_EXIT;
2635 }
2636
2637 static ExitStatus op_mxb(DisasContext *s, DisasOps *o)
2638 {
2639 gen_helper_mxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
2640 return_low128(o->out2);
2641 return NO_EXIT;
2642 }
2643
2644 static ExitStatus op_mxdb(DisasContext *s, DisasOps *o)
2645 {
2646 gen_helper_mxdb(o->out, cpu_env, o->out, o->out2, o->in2);
2647 return_low128(o->out2);
2648 return NO_EXIT;
2649 }
2650
2651 static ExitStatus op_maeb(DisasContext *s, DisasOps *o)
2652 {
2653 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2654 gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3);
2655 tcg_temp_free_i64(r3);
2656 return NO_EXIT;
2657 }
2658
2659 static ExitStatus op_madb(DisasContext *s, DisasOps *o)
2660 {
2661 int r3 = get_field(s->fields, r3);
2662 gen_helper_madb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2663 return NO_EXIT;
2664 }
2665
2666 static ExitStatus op_mseb(DisasContext *s, DisasOps *o)
2667 {
2668 TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
2669 gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3);
2670 tcg_temp_free_i64(r3);
2671 return NO_EXIT;
2672 }
2673
2674 static ExitStatus op_msdb(DisasContext *s, DisasOps *o)
2675 {
2676 int r3 = get_field(s->fields, r3);
2677 gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, fregs[r3]);
2678 return NO_EXIT;
2679 }
2680
2681 static ExitStatus op_nabs(DisasContext *s, DisasOps *o)
2682 {
2683 gen_helper_nabs_i64(o->out, o->in2);
2684 return NO_EXIT;
2685 }
2686
2687 static ExitStatus op_nabsf32(DisasContext *s, DisasOps *o)
2688 {
2689 tcg_gen_ori_i64(o->out, o->in2, 0x80000000ull);
2690 return NO_EXIT;
2691 }
2692
2693 static ExitStatus op_nabsf64(DisasContext *s, DisasOps *o)
2694 {
2695 tcg_gen_ori_i64(o->out, o->in2, 0x8000000000000000ull);
2696 return NO_EXIT;
2697 }
2698
2699 static ExitStatus op_nabsf128(DisasContext *s, DisasOps *o)
2700 {
2701 tcg_gen_ori_i64(o->out, o->in1, 0x8000000000000000ull);
2702 tcg_gen_mov_i64(o->out2, o->in2);
2703 return NO_EXIT;
2704 }
2705
2706 static ExitStatus op_nc(DisasContext *s, DisasOps *o)
2707 {
2708 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2709 potential_page_fault(s);
2710 gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2);
2711 tcg_temp_free_i32(l);
2712 set_cc_static(s);
2713 return NO_EXIT;
2714 }
2715
2716 static ExitStatus op_neg(DisasContext *s, DisasOps *o)
2717 {
2718 tcg_gen_neg_i64(o->out, o->in2);
2719 return NO_EXIT;
2720 }
2721
2722 static ExitStatus op_negf32(DisasContext *s, DisasOps *o)
2723 {
2724 tcg_gen_xori_i64(o->out, o->in2, 0x80000000ull);
2725 return NO_EXIT;
2726 }
2727
2728 static ExitStatus op_negf64(DisasContext *s, DisasOps *o)
2729 {
2730 tcg_gen_xori_i64(o->out, o->in2, 0x8000000000000000ull);
2731 return NO_EXIT;
2732 }
2733
2734 static ExitStatus op_negf128(DisasContext *s, DisasOps *o)
2735 {
2736 tcg_gen_xori_i64(o->out, o->in1, 0x8000000000000000ull);
2737 tcg_gen_mov_i64(o->out2, o->in2);
2738 return NO_EXIT;
2739 }
2740
2741 static ExitStatus op_oc(DisasContext *s, DisasOps *o)
2742 {
2743 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
2744 potential_page_fault(s);
2745 gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2);
2746 tcg_temp_free_i32(l);
2747 set_cc_static(s);
2748 return NO_EXIT;
2749 }
2750
2751 static ExitStatus op_or(DisasContext *s, DisasOps *o)
2752 {
2753 tcg_gen_or_i64(o->out, o->in1, o->in2);
2754 return NO_EXIT;
2755 }
2756
2757 static ExitStatus op_ori(DisasContext *s, DisasOps *o)
2758 {
2759 int shift = s->insn->data & 0xff;
2760 int size = s->insn->data >> 8;
2761 uint64_t mask = ((1ull << size) - 1) << shift;
2762
2763 assert(!o->g_in2);
2764 tcg_gen_shli_i64(o->in2, o->in2, shift);
2765 tcg_gen_or_i64(o->out, o->in1, o->in2);
2766
2767 /* Produce the CC from only the bits manipulated. */
2768 tcg_gen_andi_i64(cc_dst, o->out, mask);
2769 set_cc_nz_u64(s, cc_dst);
2770 return NO_EXIT;
2771 }
2772
2773 static ExitStatus op_popcnt(DisasContext *s, DisasOps *o)
2774 {
2775 gen_helper_popcnt(o->out, o->in2);
2776 return NO_EXIT;
2777 }
2778
2779 #ifndef CONFIG_USER_ONLY
2780 static ExitStatus op_ptlb(DisasContext *s, DisasOps *o)
2781 {
2782 check_privileged(s);
2783 gen_helper_ptlb(cpu_env);
2784 return NO_EXIT;
2785 }
2786 #endif
2787
2788 static ExitStatus op_risbg(DisasContext *s, DisasOps *o)
2789 {
2790 int i3 = get_field(s->fields, i3);
2791 int i4 = get_field(s->fields, i4);
2792 int i5 = get_field(s->fields, i5);
2793 int do_zero = i4 & 0x80;
2794 uint64_t mask, imask, pmask;
2795 int pos, len, rot;
2796
2797 /* Adjust the arguments for the specific insn. */
2798 switch (s->fields->op2) {
2799 case 0x55: /* risbg */
2800 i3 &= 63;
2801 i4 &= 63;
2802 pmask = ~0;
2803 break;
2804 case 0x5d: /* risbhg */
2805 i3 &= 31;
2806 i4 &= 31;
2807 pmask = 0xffffffff00000000ull;
2808 break;
2809 case 0x51: /* risblg */
2810 i3 &= 31;
2811 i4 &= 31;
2812 pmask = 0x00000000ffffffffull;
2813 break;
2814 default:
2815 abort();
2816 }
2817
2818 /* MASK is the set of bits to be inserted from R2.
2819 Take care for I3/I4 wraparound. */
2820 mask = pmask >> i3;
2821 if (i3 <= i4) {
2822 mask ^= pmask >> i4 >> 1;
2823 } else {
2824 mask |= ~(pmask >> i4 >> 1);
2825 }
2826 mask &= pmask;
2827
2828 /* IMASK is the set of bits to be kept from R1. In the case of the high/low
2829 insns, we need to keep the other half of the register. */
2830 imask = ~mask | ~pmask;
2831 if (do_zero) {
2832 if (s->fields->op2 == 0x55) {
2833 imask = 0;
2834 } else {
2835 imask = ~pmask;
2836 }
2837 }
2838
2839 /* In some cases we can implement this with deposit, which can be more
2840 efficient on some hosts. */
2841 if (~mask == imask && i3 <= i4) {
2842 if (s->fields->op2 == 0x5d) {
2843 i3 += 32, i4 += 32;
2844 }
2845 /* Note that we rotate the bits to be inserted to the lsb, not to
2846 the position as described in the PoO. */
2847 len = i4 - i3 + 1;
2848 pos = 63 - i4;
2849 rot = (i5 - pos) & 63;
2850 } else {
2851 pos = len = -1;
2852 rot = i5 & 63;
2853 }
2854
2855 /* Rotate the input as necessary. */
2856 tcg_gen_rotli_i64(o->in2, o->in2, rot);
2857
2858 /* Insert the selected bits into the output. */
2859 if (pos >= 0) {
2860 tcg_gen_deposit_i64(o->out, o->out, o->in2, pos, len);
2861 } else if (imask == 0) {
2862 tcg_gen_andi_i64(o->out, o->in2, mask);
2863 } else {
2864 tcg_gen_andi_i64(o->in2, o->in2, mask);
2865 tcg_gen_andi_i64(o->out, o->out, imask);
2866 tcg_gen_or_i64(o->out, o->out, o->in2);
2867 }
2868 return NO_EXIT;
2869 }
2870
2871 static ExitStatus op_rosbg(DisasContext *s, DisasOps *o)
2872 {
2873 int i3 = get_field(s->fields, i3);
2874 int i4 = get_field(s->fields, i4);
2875 int i5 = get_field(s->fields, i5);
2876 uint64_t mask;
2877
2878 /* If this is a test-only form, arrange to discard the result. */
2879 if (i3 & 0x80) {
2880 o->out = tcg_temp_new_i64();
2881 o->g_out = false;
2882 }
2883
2884 i3 &= 63;
2885 i4 &= 63;
2886 i5 &= 63;
2887
2888 /* MASK is the set of bits to be operated on from R2.
2889 Take care for I3/I4 wraparound. */
2890 mask = ~0ull >> i3;
2891 if (i3 <= i4) {
2892 mask ^= ~0ull >> i4 >> 1;
2893 } else {
2894 mask |= ~(~0ull >> i4 >> 1);
2895 }
2896
2897 /* Rotate the input as necessary. */
2898 tcg_gen_rotli_i64(o->in2, o->in2, i5);
2899
2900 /* Operate. */
2901 switch (s->fields->op2) {
2902 case 0x55: /* AND */
2903 tcg_gen_ori_i64(o->in2, o->in2, ~mask);
2904 tcg_gen_and_i64(o->out, o->out, o->in2);
2905 break;
2906 case 0x56: /* OR */
2907 tcg_gen_andi_i64(o->in2, o->in2, mask);
2908 tcg_gen_or_i64(o->out, o->out, o->in2);
2909 break;
2910 case 0x57: /* XOR */
2911 tcg_gen_andi_i64(o->in2, o->in2, mask);
2912 tcg_gen_xor_i64(o->out, o->out, o->in2);
2913 break;
2914 default:
2915 abort();
2916 }
2917
2918 /* Set the CC. */
2919 tcg_gen_andi_i64(cc_dst, o->out, mask);
2920 set_cc_nz_u64(s, cc_dst);
2921 return NO_EXIT;
2922 }
2923
2924 static ExitStatus op_rev16(DisasContext *s, DisasOps *o)
2925 {
2926 tcg_gen_bswap16_i64(o->out, o->in2);
2927 return NO_EXIT;
2928 }
2929
2930 static ExitStatus op_rev32(DisasContext *s, DisasOps *o)
2931 {
2932 tcg_gen_bswap32_i64(o->out, o->in2);
2933 return NO_EXIT;
2934 }
2935
2936 static ExitStatus op_rev64(DisasContext *s, DisasOps *o)
2937 {
2938 tcg_gen_bswap64_i64(o->out, o->in2);
2939 return NO_EXIT;
2940 }
2941
2942 static ExitStatus op_rll32(DisasContext *s, DisasOps *o)
2943 {
2944 TCGv_i32 t1 = tcg_temp_new_i32();
2945 TCGv_i32 t2 = tcg_temp_new_i32();
2946 TCGv_i32 to = tcg_temp_new_i32();
2947 tcg_gen_trunc_i64_i32(t1, o->in1);
2948 tcg_gen_trunc_i64_i32(t2, o->in2);
2949 tcg_gen_rotl_i32(to, t1, t2);
2950 tcg_gen_extu_i32_i64(o->out, to);
2951 tcg_temp_free_i32(t1);
2952 tcg_temp_free_i32(t2);
2953 tcg_temp_free_i32(to);
2954 return NO_EXIT;
2955 }
2956
2957 static ExitStatus op_rll64(DisasContext *s, DisasOps *o)
2958 {
2959 tcg_gen_rotl_i64(o->out, o->in1, o->in2);
2960 return NO_EXIT;
2961 }
2962
2963 #ifndef CONFIG_USER_ONLY
2964 static ExitStatus op_rrbe(DisasContext *s, DisasOps *o)
2965 {
2966 check_privileged(s);
2967 gen_helper_rrbe(cc_op, cpu_env, o->in2);
2968 set_cc_static(s);
2969 return NO_EXIT;
2970 }
2971
2972 static ExitStatus op_sacf(DisasContext *s, DisasOps *o)
2973 {
2974 check_privileged(s);
2975 gen_helper_sacf(cpu_env, o->in2);
2976 /* Addressing mode has changed, so end the block. */
2977 return EXIT_PC_STALE;
2978 }
2979 #endif
2980
2981 static ExitStatus op_sam(DisasContext *s, DisasOps *o)
2982 {
2983 int sam = s->insn->data;
2984 TCGv_i64 tsam;
2985 uint64_t mask;
2986
2987 switch (sam) {
2988 case 0:
2989 mask = 0xffffff;
2990 break;
2991 case 1:
2992 mask = 0x7fffffff;
2993 break;
2994 default:
2995 mask = -1;
2996 break;
2997 }
2998
2999 /* Bizarre but true, we check the address of the current insn for the
3000 specification exception, not the next to be executed. Thus the PoO
3001 documents that Bad Things Happen two bytes before the end. */
3002 if (s->pc & ~mask) {
3003 gen_program_exception(s, PGM_SPECIFICATION);
3004 return EXIT_NORETURN;
3005 }
3006 s->next_pc &= mask;
3007
3008 tsam = tcg_const_i64(sam);
3009 tcg_gen_deposit_i64(psw_mask, psw_mask, tsam, 31, 2);
3010 tcg_temp_free_i64(tsam);
3011
3012 /* Always exit the TB, since we (may have) changed execution mode. */
3013 return EXIT_PC_STALE;
3014 }
3015
3016 static ExitStatus op_sar(DisasContext *s, DisasOps *o)
3017 {
3018 int r1 = get_field(s->fields, r1);
3019 tcg_gen_st32_i64(o->in2, cpu_env, offsetof(CPUS390XState, aregs[r1]));
3020 return NO_EXIT;
3021 }
3022
3023 static ExitStatus op_seb(DisasContext *s, DisasOps *o)
3024 {
3025 gen_helper_seb(o->out, cpu_env, o->in1, o->in2);
3026 return NO_EXIT;
3027 }
3028
3029 static ExitStatus op_sdb(DisasContext *s, DisasOps *o)
3030 {
3031 gen_helper_sdb(o->out, cpu_env, o->in1, o->in2);
3032 return NO_EXIT;
3033 }
3034
3035 static ExitStatus op_sxb(DisasContext *s, DisasOps *o)
3036 {
3037 gen_helper_sxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2);
3038 return_low128(o->out2);
3039 return NO_EXIT;
3040 }
3041
3042 static ExitStatus op_sqeb(DisasContext *s, DisasOps *o)
3043 {
3044 gen_helper_sqeb(o->out, cpu_env, o->in2);
3045 return NO_EXIT;
3046 }
3047
3048 static ExitStatus op_sqdb(DisasContext *s, DisasOps *o)
3049 {
3050 gen_helper_sqdb(o->out, cpu_env, o->in2);
3051 return NO_EXIT;
3052 }
3053
3054 static ExitStatus op_sqxb(DisasContext *s, DisasOps *o)
3055 {
3056 gen_helper_sqxb(o->out, cpu_env, o->in1, o->in2);
3057 return_low128(o->out2);
3058 return NO_EXIT;
3059 }
3060
3061 #ifndef CONFIG_USER_ONLY
3062 static ExitStatus op_servc(DisasContext *s, DisasOps *o)
3063 {
3064 check_privileged(s);
3065 potential_page_fault(s);
3066 gen_helper_servc(cc_op, cpu_env, o->in2, o->in1);
3067 set_cc_static(s);
3068 return NO_EXIT;
3069 }
3070
3071 static ExitStatus op_sigp(DisasContext *s, DisasOps *o)
3072 {
3073 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3074 check_privileged(s);
3075 potential_page_fault(s);
3076 gen_helper_sigp(cc_op, cpu_env, o->in2, r1, o->in1);
3077 tcg_temp_free_i32(r1);
3078 return NO_EXIT;
3079 }
3080 #endif
3081
3082 static ExitStatus op_soc(DisasContext *s, DisasOps *o)
3083 {
3084 DisasCompare c;
3085 TCGv_i64 a;
3086 TCGLabel *lab;
3087 int r1;
3088
3089 disas_jcc(s, &c, get_field(s->fields, m3));
3090
3091 /* We want to store when the condition is fulfilled, so branch
3092 out when it's not */
3093 c.cond = tcg_invert_cond(c.cond);
3094
3095 lab = gen_new_label();
3096 if (c.is_64) {
3097 tcg_gen_brcond_i64(c.cond, c.u.s64.a, c.u.s64.b, lab);
3098 } else {
3099 tcg_gen_brcond_i32(c.cond, c.u.s32.a, c.u.s32.b, lab);
3100 }
3101 free_compare(&c);
3102
3103 r1 = get_field(s->fields, r1);
3104 a = get_address(s, 0, get_field(s->fields, b2), get_field(s->fields, d2));
3105 if (s->insn->data) {
3106 tcg_gen_qemu_st64(regs[r1], a, get_mem_index(s));
3107 } else {
3108 tcg_gen_qemu_st32(regs[r1], a, get_mem_index(s));
3109 }
3110 tcg_temp_free_i64(a);
3111
3112 gen_set_label(lab);
3113 return NO_EXIT;
3114 }
3115
3116 static ExitStatus op_sla(DisasContext *s, DisasOps *o)
3117 {
3118 uint64_t sign = 1ull << s->insn->data;
3119 enum cc_op cco = s->insn->data == 31 ? CC_OP_SLA_32 : CC_OP_SLA_64;
3120 gen_op_update2_cc_i64(s, cco, o->in1, o->in2);
3121 tcg_gen_shl_i64(o->out, o->in1, o->in2);
3122 /* The arithmetic left shift is curious in that it does not affect
3123 the sign bit. Copy that over from the source unchanged. */
3124 tcg_gen_andi_i64(o->out, o->out, ~sign);
3125 tcg_gen_andi_i64(o->in1, o->in1, sign);
3126 tcg_gen_or_i64(o->out, o->out, o->in1);
3127 return NO_EXIT;
3128 }
3129
3130 static ExitStatus op_sll(DisasContext *s, DisasOps *o)
3131 {
3132 tcg_gen_shl_i64(o->out, o->in1, o->in2);
3133 return NO_EXIT;
3134 }
3135
3136 static ExitStatus op_sra(DisasContext *s, DisasOps *o)
3137 {
3138 tcg_gen_sar_i64(o->out, o->in1, o->in2);
3139 return NO_EXIT;
3140 }
3141
3142 static ExitStatus op_srl(DisasContext *s, DisasOps *o)
3143 {
3144 tcg_gen_shr_i64(o->out, o->in1, o->in2);
3145 return NO_EXIT;
3146 }
3147
3148 static ExitStatus op_sfpc(DisasContext *s, DisasOps *o)
3149 {
3150 gen_helper_sfpc(cpu_env, o->in2);
3151 return NO_EXIT;
3152 }
3153
3154 static ExitStatus op_sfas(DisasContext *s, DisasOps *o)
3155 {
3156 gen_helper_sfas(cpu_env, o->in2);
3157 return NO_EXIT;
3158 }
3159
3160 static ExitStatus op_srnm(DisasContext *s, DisasOps *o)
3161 {
3162 int b2 = get_field(s->fields, b2);
3163 int d2 = get_field(s->fields, d2);
3164 TCGv_i64 t1 = tcg_temp_new_i64();
3165 TCGv_i64 t2 = tcg_temp_new_i64();
3166 int mask, pos, len;
3167
3168 switch (s->fields->op2) {
3169 case 0x99: /* SRNM */
3170 pos = 0, len = 2;
3171 break;
3172 case 0xb8: /* SRNMB */
3173 pos = 0, len = 3;
3174 break;
3175 case 0xb9: /* SRNMT */
3176 pos = 4, len = 3;
3177 break;
3178 default:
3179 tcg_abort();
3180 }
3181 mask = (1 << len) - 1;
3182
3183 /* Insert the value into the appropriate field of the FPC. */
3184 if (b2 == 0) {
3185 tcg_gen_movi_i64(t1, d2 & mask);
3186 } else {
3187 tcg_gen_addi_i64(t1, regs[b2], d2);
3188 tcg_gen_andi_i64(t1, t1, mask);
3189 }
3190 tcg_gen_ld32u_i64(t2, cpu_env, offsetof(CPUS390XState, fpc));
3191 tcg_gen_deposit_i64(t2, t2, t1, pos, len);
3192 tcg_temp_free_i64(t1);
3193
3194 /* Then install the new FPC to set the rounding mode in fpu_status. */
3195 gen_helper_sfpc(cpu_env, t2);
3196 tcg_temp_free_i64(t2);
3197 return NO_EXIT;
3198 }
3199
3200 #ifndef CONFIG_USER_ONLY
3201 static ExitStatus op_spka(DisasContext *s, DisasOps *o)
3202 {
3203 check_privileged(s);
3204 tcg_gen_shri_i64(o->in2, o->in2, 4);
3205 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY - 4, 4);
3206 return NO_EXIT;
3207 }
3208
3209 static ExitStatus op_sske(DisasContext *s, DisasOps *o)
3210 {
3211 check_privileged(s);
3212 gen_helper_sske(cpu_env, o->in1, o->in2);
3213 return NO_EXIT;
3214 }
3215
3216 static ExitStatus op_ssm(DisasContext *s, DisasOps *o)
3217 {
3218 check_privileged(s);
3219 tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8);
3220 return NO_EXIT;
3221 }
3222
3223 static ExitStatus op_stap(DisasContext *s, DisasOps *o)
3224 {
3225 check_privileged(s);
3226 /* ??? Surely cpu address != cpu number. In any case the previous
3227 version of this stored more than the required half-word, so it
3228 is unlikely this has ever been tested. */
3229 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num));
3230 return NO_EXIT;
3231 }
3232
3233 static ExitStatus op_stck(DisasContext *s, DisasOps *o)
3234 {
3235 gen_helper_stck(o->out, cpu_env);
3236 /* ??? We don't implement clock states. */
3237 gen_op_movi_cc(s, 0);
3238 return NO_EXIT;
3239 }
3240
3241 static ExitStatus op_stcke(DisasContext *s, DisasOps *o)
3242 {
3243 TCGv_i64 c1 = tcg_temp_new_i64();
3244 TCGv_i64 c2 = tcg_temp_new_i64();
3245 gen_helper_stck(c1, cpu_env);
3246 /* Shift the 64-bit value into its place as a zero-extended
3247 104-bit value. Note that "bit positions 64-103 are always
3248 non-zero so that they compare differently to STCK"; we set
3249 the least significant bit to 1. */
3250 tcg_gen_shli_i64(c2, c1, 56);
3251 tcg_gen_shri_i64(c1, c1, 8);
3252 tcg_gen_ori_i64(c2, c2, 0x10000);
3253 tcg_gen_qemu_st64(c1, o->in2, get_mem_index(s));
3254 tcg_gen_addi_i64(o->in2, o->in2, 8);
3255 tcg_gen_qemu_st64(c2, o->in2, get_mem_index(s));
3256 tcg_temp_free_i64(c1);
3257 tcg_temp_free_i64(c2);
3258 /* ??? We don't implement clock states. */
3259 gen_op_movi_cc(s, 0);
3260 return NO_EXIT;
3261 }
3262
3263 static ExitStatus op_sckc(DisasContext *s, DisasOps *o)
3264 {
3265 check_privileged(s);
3266 gen_helper_sckc(cpu_env, o->in2);
3267 return NO_EXIT;
3268 }
3269
3270 static ExitStatus op_stckc(DisasContext *s, DisasOps *o)
3271 {
3272 check_privileged(s);
3273 gen_helper_stckc(o->out, cpu_env);
3274 return NO_EXIT;
3275 }
3276
3277 static ExitStatus op_stctg(DisasContext *s, DisasOps *o)
3278 {
3279 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3280 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
3281 check_privileged(s);
3282 potential_page_fault(s);
3283 gen_helper_stctg(cpu_env, r1, o->in2, r3);
3284 tcg_temp_free_i32(r1);
3285 tcg_temp_free_i32(r3);
3286 return NO_EXIT;
3287 }
3288
3289 static ExitStatus op_stctl(DisasContext *s, DisasOps *o)
3290 {
3291 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3292 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
3293 check_privileged(s);
3294 potential_page_fault(s);
3295 gen_helper_stctl(cpu_env, r1, o->in2, r3);
3296 tcg_temp_free_i32(r1);
3297 tcg_temp_free_i32(r3);
3298 return NO_EXIT;
3299 }
3300
3301 static ExitStatus op_stidp(DisasContext *s, DisasOps *o)
3302 {
3303 TCGv_i64 t1 = tcg_temp_new_i64();
3304
3305 check_privileged(s);
3306 tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num));
3307 tcg_gen_ld32u_i64(t1, cpu_env, offsetof(CPUS390XState, machine_type));
3308 tcg_gen_deposit_i64(o->out, o->out, t1, 32, 32);
3309 tcg_temp_free_i64(t1);
3310
3311 return NO_EXIT;
3312 }
3313
3314 static ExitStatus op_spt(DisasContext *s, DisasOps *o)
3315 {
3316 check_privileged(s);
3317 gen_helper_spt(cpu_env, o->in2);
3318 return NO_EXIT;
3319 }
3320
3321 static ExitStatus op_stfl(DisasContext *s, DisasOps *o)
3322 {
3323 TCGv_i64 f, a;
3324 /* We really ought to have more complete indication of facilities
3325 that we implement. Address this when STFLE is implemented. */
3326 check_privileged(s);
3327 f = tcg_const_i64(0xc0000000);
3328 a = tcg_const_i64(200);
3329 tcg_gen_qemu_st32(f, a, get_mem_index(s));
3330 tcg_temp_free_i64(f);
3331 tcg_temp_free_i64(a);
3332 return NO_EXIT;
3333 }
3334
3335 static ExitStatus op_stpt(DisasContext *s, DisasOps *o)
3336 {
3337 check_privileged(s);
3338 gen_helper_stpt(o->out, cpu_env);
3339 return NO_EXIT;
3340 }
3341
3342 static ExitStatus op_stsi(DisasContext *s, DisasOps *o)
3343 {
3344 check_privileged(s);
3345 potential_page_fault(s);
3346 gen_helper_stsi(cc_op, cpu_env, o->in2, regs[0], regs[1]);
3347 set_cc_static(s);
3348 return NO_EXIT;
3349 }
3350
3351 static ExitStatus op_spx(DisasContext *s, DisasOps *o)
3352 {
3353 check_privileged(s);
3354 gen_helper_spx(cpu_env, o->in2);
3355 return NO_EXIT;
3356 }
3357
3358 static ExitStatus op_subchannel(DisasContext *s, DisasOps *o)
3359 {
3360 check_privileged(s);
3361 /* Not operational. */
3362 gen_op_movi_cc(s, 3);
3363 return NO_EXIT;
3364 }
3365
3366 static ExitStatus op_stpx(DisasContext *s, DisasOps *o)
3367 {
3368 check_privileged(s);
3369 tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, psa));
3370 tcg_gen_andi_i64(o->out, o->out, 0x7fffe000);
3371 return NO_EXIT;
3372 }
3373
3374 static ExitStatus op_stnosm(DisasContext *s, DisasOps *o)
3375 {
3376 uint64_t i2 = get_field(s->fields, i2);
3377 TCGv_i64 t;
3378
3379 check_privileged(s);
3380
3381 /* It is important to do what the instruction name says: STORE THEN.
3382 If we let the output hook perform the store then if we fault and
3383 restart, we'll have the wrong SYSTEM MASK in place. */
3384 t = tcg_temp_new_i64();
3385 tcg_gen_shri_i64(t, psw_mask, 56);
3386 tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
3387 tcg_temp_free_i64(t);
3388
3389 if (s->fields->op == 0xac) {
3390 tcg_gen_andi_i64(psw_mask, psw_mask,
3391 (i2 << 56) | 0x00ffffffffffffffull);
3392 } else {
3393 tcg_gen_ori_i64(psw_mask, psw_mask, i2 << 56);
3394 }
3395 return NO_EXIT;
3396 }
3397
3398 static ExitStatus op_stura(DisasContext *s, DisasOps *o)
3399 {
3400 check_privileged(s);
3401 potential_page_fault(s);
3402 gen_helper_stura(cpu_env, o->in2, o->in1);
3403 return NO_EXIT;
3404 }
3405
3406 static ExitStatus op_sturg(DisasContext *s, DisasOps *o)
3407 {
3408 check_privileged(s);
3409 potential_page_fault(s);
3410 gen_helper_sturg(cpu_env, o->in2, o->in1);
3411 return NO_EXIT;
3412 }
3413 #endif
3414
3415 static ExitStatus op_st8(DisasContext *s, DisasOps *o)
3416 {
3417 tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
3418 return NO_EXIT;
3419 }
3420
3421 static ExitStatus op_st16(DisasContext *s, DisasOps *o)
3422 {
3423 tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
3424 return NO_EXIT;
3425 }
3426
3427 static ExitStatus op_st32(DisasContext *s, DisasOps *o)
3428 {
3429 tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s));
3430 return NO_EXIT;
3431 }
3432
3433 static ExitStatus op_st64(DisasContext *s, DisasOps *o)
3434 {
3435 tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
3436 return NO_EXIT;
3437 }
3438
3439 static ExitStatus op_stam(DisasContext *s, DisasOps *o)
3440 {
3441 TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
3442 TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
3443 potential_page_fault(s);
3444 gen_helper_stam(cpu_env, r1, o->in2, r3);
3445 tcg_temp_free_i32(r1);
3446 tcg_temp_free_i32(r3);
3447 return NO_EXIT;
3448 }
3449
3450 static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
3451 {
3452 int m3 = get_field(s->fields, m3);
3453 int pos, base = s->insn->data;
3454 TCGv_i64 tmp = tcg_temp_new_i64();
3455
3456 pos = base + ctz32(m3) * 8;
3457 switch (m3) {
3458 case 0xf:
3459 /* Effectively a 32-bit store. */
3460 tcg_gen_shri_i64(tmp, o->in1, pos);
3461 tcg_gen_qemu_st32(tmp, o->in2, get_mem_index(s));
3462 break;
3463
3464 case 0xc:
3465 case 0x6:
3466 case 0x3:
3467 /* Effectively a 16-bit store. */
3468 tcg_gen_shri_i64(tmp, o->in1, pos);
3469 tcg_gen_qemu_st16(tmp, o->in2, get_mem_index(s));
3470 break;
3471
3472 case 0x8:
3473 case 0x4:
3474 case 0x2:
3475 case 0x1:
3476 /* Effectively an 8-bit store. */
3477 tcg_gen_shri_i64(tmp, o->in1, pos);
3478 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3479 break;
3480
3481 default:
3482 /* This is going to be a sequence of shifts and stores. */
3483 pos = base + 32 - 8;
3484 while (m3) {
3485 if (m3 & 0x8) {
3486 tcg_gen_shri_i64(tmp, o->in1, pos);
3487 tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
3488 tcg_gen_addi_i64(o->in2, o->in2, 1);
3489 }
3490 m3 = (m3 << 1) & 0xf;
3491 pos -= 8;
3492 }
3493 break;
3494 }
3495 tcg_temp_free_i64(tmp);
3496 return NO_EXIT;
3497 }
3498
3499 static ExitStatus op_stm(DisasContext *s, DisasOps *o)
3500 {
3501 int r1 = get_field(s->fields, r1);
3502 int r3 = get_field(s->fields, r3);
3503 int size = s->insn->data;
3504 TCGv_i64 tsize = tcg_const_i64(size);
3505
3506 while (1) {
3507 if (size == 8) {
3508 tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
3509 } else {
3510 tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s));
3511 }
3512 if (r1 == r3) {
3513 break;
3514 }
3515 tcg_gen_add_i64(o->in2, o->in2, tsize);
3516 r1 = (r1 + 1) & 15;
3517 }
3518
3519 tcg_temp_free_i64(tsize);
3520 return NO_EXIT;
3521 }
3522
3523 static ExitStatus op_stmh(DisasContext *s, DisasOps *o)
3524 {
3525 int r1 = get_field(s->fields, r1);
3526 int r3 = get_field(s->fields, r3);
3527 TCGv_i64 t = tcg_temp_new_i64();
3528 TCGv_i64 t4 = tcg_const_i64(4);
3529 TCGv_i64 t32 = tcg_const_i64(32);
3530
3531 while (1) {
3532 tcg_gen_shl_i64(t, regs[r1], t32);
3533 tcg_gen_qemu_st32(t, o->in2, get_mem_index(s));
3534 if (r1 == r3) {
3535 break;
3536 }
3537 tcg_gen_add_i64(o->in2, o->in2, t4);
3538 r1 = (r1 + 1) & 15;
3539 }
3540
3541 tcg_temp_free_i64(t);
3542 tcg_temp_free_i64(t4);
3543 tcg_temp_free_i64(t32);
3544 return NO_EXIT;
3545 }
3546
3547 static ExitStatus op_srst(DisasContext *s, DisasOps *o)
3548 {
3549 potential_page_fault(s);
3550 gen_helper_srst(o->in1, cpu_env, regs[0], o->in1, o->in2);
3551 set_cc_static(s);
3552 return_low128(o->in2);
3553 return NO_EXIT;
3554 }
3555
3556 static ExitStatus op_sub(DisasContext *s, DisasOps *o)
3557 {
3558 tcg_gen_sub_i64(o->out, o->in1, o->in2);
3559 return NO_EXIT;
3560 }
3561
3562 static ExitStatus op_subb(DisasContext *s, DisasOps *o)
3563 {
3564 DisasCompare cmp;
3565 TCGv_i64 borrow;
3566
3567 tcg_gen_sub_i64(o->out, o->in1, o->in2);
3568
3569 /* The !borrow flag is the msb of CC. Since we want the inverse of
3570 that, we ask for a comparison of CC=0 | CC=1 -> mask of 8 | 4. */
3571 disas_jcc(s, &cmp, 8 | 4);
3572 borrow = tcg_temp_new_i64();
3573 if (cmp.is_64) {
3574 tcg_gen_setcond_i64(cmp.cond, borrow, cmp.u.s64.a, cmp.u.s64.b);
3575 } else {
3576 TCGv_i32 t = tcg_temp_new_i32();
3577 tcg_gen_setcond_i32(cmp.cond, t, cmp.u.s32.a, cmp.u.s32.b);
3578 tcg_gen_extu_i32_i64(borrow, t);
3579 tcg_temp_free_i32(t);
3580 }
3581 free_compare(&cmp);
3582
3583 tcg_gen_sub_i64(o->out, o->out, borrow);
3584 tcg_temp_free_i64(borrow);
3585 return NO_EXIT;
3586 }
3587
3588 static ExitStatus op_svc(DisasContext *s, DisasOps *o)
3589 {
3590 TCGv_i32 t;
3591
3592 update_psw_addr(s);
3593 update_cc_op(s);
3594
3595 t = tcg_const_i32(get_field(s->fields, i1) & 0xff);
3596 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code));
3597 tcg_temp_free_i32(t);
3598
3599 t = tcg_const_i32(s->next_pc - s->pc);
3600 tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen));
3601 tcg_temp_free_i32(t);
3602
3603 gen_exception(EXCP_SVC);
3604 return EXIT_NORETURN;
3605 }
3606
3607 static ExitStatus op_tceb(DisasContext *s, DisasOps *o)
3608 {
3609 gen_helper_tceb(cc_op, o->in1, o->in2);
3610 set_cc_static(s);
3611 return NO_EXIT;
3612 }
3613
3614 static ExitStatus op_tcdb(DisasContext *s, DisasOps *o)
3615 {
3616 gen_helper_tcdb(cc_op, o->in1, o->in2);
3617 set_cc_static(s);
3618 return NO_EXIT;
3619 }
3620
3621 static ExitStatus op_tcxb(DisasContext *s, DisasOps *o)
3622 {
3623 gen_helper_tcxb(cc_op, o->out, o->out2, o->in2);
3624 set_cc_static(s);
3625 return NO_EXIT;
3626 }
3627
3628 #ifndef CONFIG_USER_ONLY
3629 static ExitStatus op_tprot(DisasContext *s, DisasOps *o)
3630 {
3631 potential_page_fault(s);
3632 gen_helper_tprot(cc_op, o->addr1, o->in2);
3633 set_cc_static(s);
3634 return NO_EXIT;
3635 }
3636 #endif
3637
3638 static ExitStatus op_tr(DisasContext *s, DisasOps *o)
3639 {
3640 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3641 potential_page_fault(s);
3642 gen_helper_tr(cpu_env, l, o->addr1, o->in2);
3643 tcg_temp_free_i32(l);
3644 set_cc_static(s);
3645 return NO_EXIT;
3646 }
3647
3648 static ExitStatus op_unpk(DisasContext *s, DisasOps *o)
3649 {
3650 TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
3651 potential_page_fault(s);
3652 gen_helper_unpk(cpu_env, l, o->addr1, o->in2);
3653 tcg_temp_free_i32(l);
3654 return NO_EXIT;
3655 }
3656
3657 static ExitStatus op_xc(DisasContext *s, DisasOps *o)
3658 {
3659 int d1 = get_field(s->fields, d1);
3660 int d2 = get_field(s->fields, d2);
3661 int b1 = get_field(s->fields, b1);
3662 int b2 = get_field(s->fields, b2);
3663 int l = get_field(s->fields, l1);
3664 TCGv_i32 t32;
3665
3666 o->addr1 = get_address(s, 0, b1, d1);
3667
3668 /* If the addresses are identical, this is a store/memset of zero. */
3669 if (b1 == b2 && d1 == d2 && (l + 1) <= 32) {
3670 o->in2 = tcg_const_i64(0);
3671
3672 l++;
3673 while (l >= 8) {
3674 tcg_gen_qemu_st64(o->in2, o->addr1, get_mem_index(s));
3675 l -= 8;
3676 if (l > 0) {
3677 tcg_gen_addi_i64(o->addr1, o->addr1, 8);
3678 }
3679 }
3680 if (l >= 4) {
3681 tcg_gen_qemu_st32(o->in2, o->addr1, get_mem_index(s));
3682 l -= 4;
3683 if (l > 0) {
3684 tcg_gen_addi_i64(o->addr1, o->addr1, 4);
3685 }
3686 }
3687 if (l >= 2) {
3688 tcg_gen_qemu_st16(o->in2, o->addr1, get_mem_index(s));
3689 l -= 2;
3690 if (l > 0) {
3691 tcg_gen_addi_i64(o->addr1, o->addr1, 2);
3692 }
3693 }
3694 if (l) {
3695 tcg_gen_qemu_st8(o->in2, o->addr1, get_mem_index(s));
3696 }
3697 gen_op_movi_cc(s, 0);
3698 return NO_EXIT;
3699 }
3700
3701 /* But in general we'll defer to a helper. */
3702 o->in2 = get_address(s, 0, b2, d2);
3703 t32 = tcg_const_i32(l);
3704 potential_page_fault(s);
3705 gen_helper_xc(cc_op, cpu_env, t32, o->addr1, o->in2);
3706 tcg_temp_free_i32(t32);
3707 set_cc_static(s);
3708 return NO_EXIT;
3709 }
3710
3711 static ExitStatus op_xor(DisasContext *s, DisasOps *o)
3712 {
3713 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3714 return NO_EXIT;
3715 }
3716
3717 static ExitStatus op_xori(DisasContext *s, DisasOps *o)
3718 {
3719 int shift = s->insn->data & 0xff;
3720 int size = s->insn->data >> 8;
3721 uint64_t mask = ((1ull << size) - 1) << shift;
3722
3723 assert(!o->g_in2);
3724 tcg_gen_shli_i64(o->in2, o->in2, shift);
3725 tcg_gen_xor_i64(o->out, o->in1, o->in2);
3726
3727 /* Produce the CC from only the bits manipulated. */
3728 tcg_gen_andi_i64(cc_dst, o->out, mask);
3729 set_cc_nz_u64(s, cc_dst);
3730 return NO_EXIT;
3731 }
3732
3733 static ExitStatus op_zero(DisasContext *s, DisasOps *o)
3734 {
3735 o->out = tcg_const_i64(0);
3736 return NO_EXIT;
3737 }
3738
3739 static ExitStatus op_zero2(DisasContext *s, DisasOps *o)
3740 {
3741 o->out = tcg_const_i64(0);
3742 o->out2 = o->out;
3743 o->g_out2 = true;
3744 return NO_EXIT;
3745 }
3746
3747 /* ====================================================================== */
3748 /* The "Cc OUTput" generators. Given the generated output (and in some cases
3749 the original inputs), update the various cc data structures in order to
3750 be able to compute the new condition code. */
3751
3752 static void cout_abs32(DisasContext *s, DisasOps *o)
3753 {
3754 gen_op_update1_cc_i64(s, CC_OP_ABS_32, o->out);
3755 }
3756
3757 static void cout_abs64(DisasContext *s, DisasOps *o)
3758 {
3759 gen_op_update1_cc_i64(s, CC_OP_ABS_64, o->out);
3760 }
3761
3762 static void cout_adds32(DisasContext *s, DisasOps *o)
3763 {
3764 gen_op_update3_cc_i64(s, CC_OP_ADD_32, o->in1, o->in2, o->out);
3765 }
3766
3767 static void cout_adds64(DisasContext *s, DisasOps *o)
3768 {
3769 gen_op_update3_cc_i64(s, CC_OP_ADD_64, o->in1, o->in2, o->out);
3770 }
3771
3772 static void cout_addu32(DisasContext *s, DisasOps *o)
3773 {
3774 gen_op_update3_cc_i64(s, CC_OP_ADDU_32, o->in1, o->in2, o->out);
3775 }
3776
3777 static void cout_addu64(DisasContext *s, DisasOps *o)
3778 {
3779 gen_op_update3_cc_i64(s, CC_OP_ADDU_64, o->in1, o->in2, o->out);
3780 }
3781
3782 static void cout_addc32(DisasContext *s, DisasOps *o)
3783 {
3784 gen_op_update3_cc_i64(s, CC_OP_ADDC_32, o->in1, o->in2, o->out);
3785 }
3786
3787 static void cout_addc64(DisasContext *s, DisasOps *o)
3788 {
3789 gen_op_update3_cc_i64(s, CC_OP_ADDC_64, o->in1, o->in2, o->out);
3790 }
3791
3792 static void cout_cmps32(DisasContext *s, DisasOps *o)
3793 {
3794 gen_op_update2_cc_i64(s, CC_OP_LTGT_32, o->in1, o->in2);
3795 }
3796
3797 static void cout_cmps64(DisasContext *s, DisasOps *o)
3798 {
3799 gen_op_update2_cc_i64(s, CC_OP_LTGT_64, o->in1, o->in2);
3800 }
3801
3802 static void cout_cmpu32(DisasContext *s, DisasOps *o)
3803 {
3804 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_32, o->in1, o->in2);
3805 }
3806
3807 static void cout_cmpu64(DisasContext *s, DisasOps *o)
3808 {
3809 gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, o->in1, o->in2);
3810 }
3811
3812 static void cout_f32(DisasContext *s, DisasOps *o)
3813 {
3814 gen_op_update1_cc_i64(s, CC_OP_NZ_F32, o->out);
3815 }
3816
3817 static void cout_f64(DisasContext *s, DisasOps *o)
3818 {
3819 gen_op_update1_cc_i64(s, CC_OP_NZ_F64, o->out);
3820 }
3821
3822 static void cout_f128(DisasContext *s, DisasOps *o)
3823 {
3824 gen_op_update2_cc_i64(s, CC_OP_NZ_F128, o->out, o->out2);
3825 }
3826
3827 static void cout_nabs32(DisasContext *s, DisasOps *o)
3828 {
3829 gen_op_update1_cc_i64(s, CC_OP_NABS_32, o->out);
3830 }
3831
3832 static void cout_nabs64(DisasContext *s, DisasOps *o)
3833 {
3834 gen_op_update1_cc_i64(s, CC_OP_NABS_64, o->out);
3835 }
3836
3837 static void cout_neg32(DisasContext *s, DisasOps *o)
3838 {
3839 gen_op_update1_cc_i64(s, CC_OP_COMP_32, o->out);
3840 }
3841
3842 static void cout_neg64(DisasContext *s, DisasOps *o)
3843 {
3844 gen_op_update1_cc_i64(s, CC_OP_COMP_64, o->out);
3845 }
3846
3847 static void cout_nz32(DisasContext *s, DisasOps *o)
3848 {
3849 tcg_gen_ext32u_i64(cc_dst, o->out);
3850 gen_op_update1_cc_i64(s, CC_OP_NZ, cc_dst);
3851 }
3852
3853 static void cout_nz64(DisasContext *s, DisasOps *o)
3854 {
3855 gen_op_update1_cc_i64(s, CC_OP_NZ, o->out);
3856 }
3857
3858 static void cout_s32(DisasContext *s, DisasOps *o)
3859 {
3860 gen_op_update1_cc_i64(s, CC_OP_LTGT0_32, o->out);
3861 }
3862
3863 static void cout_s64(DisasContext *s, DisasOps *o)
3864 {
3865 gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, o->out);
3866 }
3867
3868 static void cout_subs32(DisasContext *s, DisasOps *o)
3869 {
3870 gen_op_update3_cc_i64(s, CC_OP_SUB_32, o->in1, o->in2, o->out);
3871 }
3872
3873 static void cout_subs64(DisasContext *s, DisasOps *o)
3874 {
3875 gen_op_update3_cc_i64(s, CC_OP_SUB_64, o->in1, o->in2, o->out);
3876 }
3877
3878 static void cout_subu32(DisasContext *s, DisasOps *o)
3879 {
3880 gen_op_update3_cc_i64(s, CC_OP_SUBU_32, o->in1, o->in2, o->out);
3881 }
3882
3883 static void cout_subu64(DisasContext *s, DisasOps *o)
3884 {
3885 gen_op_update3_cc_i64(s, CC_OP_SUBU_64, o->in1, o->in2, o->out);
3886 }
3887
3888 static void cout_subb32(DisasContext *s, DisasOps *o)
3889 {
3890 gen_op_update3_cc_i64(s, CC_OP_SUBB_32, o->in1, o->in2, o->out);
3891 }
3892
3893 static void cout_subb64(DisasContext *s, DisasOps *o)
3894 {
3895 gen_op_update3_cc_i64(s, CC_OP_SUBB_64, o->in1, o->in2, o->out);
3896 }
3897
3898 static void cout_tm32(DisasContext *s, DisasOps *o)
3899 {
3900 gen_op_update2_cc_i64(s, CC_OP_TM_32, o->in1, o->in2);
3901 }
3902
3903 static void cout_tm64(DisasContext *s, DisasOps *o)
3904 {
3905 gen_op_update2_cc_i64(s, CC_OP_TM_64, o->in1, o->in2);
3906 }
3907
3908 /* ====================================================================== */
3909 /* The "PREParation" generators. These initialize the DisasOps.OUT fields
3910 with the TCG register to which we will write. Used in combination with
3911 the "wout" generators, in some cases we need a new temporary, and in
3912 some cases we can write to a TCG global. */
3913
3914 static void prep_new(DisasContext *s, DisasFields *f, DisasOps *o)
3915 {
3916 o->out = tcg_temp_new_i64();
3917 }
3918 #define SPEC_prep_new 0
3919
3920 static void prep_new_P(DisasContext *s, DisasFields *f, DisasOps *o)
3921 {
3922 o->out = tcg_temp_new_i64();
3923 o->out2 = tcg_temp_new_i64();
3924 }
3925 #define SPEC_prep_new_P 0
3926
3927 static void prep_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3928 {
3929 o->out = regs[get_field(f, r1)];
3930 o->g_out = true;
3931 }
3932 #define SPEC_prep_r1 0
3933
3934 static void prep_r1_P(DisasContext *s, DisasFields *f, DisasOps *o)
3935 {
3936 int r1 = get_field(f, r1);
3937 o->out = regs[r1];
3938 o->out2 = regs[r1 + 1];
3939 o->g_out = o->g_out2 = true;
3940 }
3941 #define SPEC_prep_r1_P SPEC_r1_even
3942
3943 static void prep_f1(DisasContext *s, DisasFields *f, DisasOps *o)
3944 {
3945 o->out = fregs[get_field(f, r1)];
3946 o->g_out = true;
3947 }
3948 #define SPEC_prep_f1 0
3949
3950 static void prep_x1(DisasContext *s, DisasFields *f, DisasOps *o)
3951 {
3952 int r1 = get_field(f, r1);
3953 o->out = fregs[r1];
3954 o->out2 = fregs[r1 + 2];
3955 o->g_out = o->g_out2 = true;
3956 }
3957 #define SPEC_prep_x1 SPEC_r1_f128
3958
3959 /* ====================================================================== */
3960 /* The "Write OUTput" generators. These generally perform some non-trivial
3961 copy of data to TCG globals, or to main memory. The trivial cases are
3962 generally handled by having a "prep" generator install the TCG global
3963 as the destination of the operation. */
3964
3965 static void wout_r1(DisasContext *s, DisasFields *f, DisasOps *o)
3966 {
3967 store_reg(get_field(f, r1), o->out);
3968 }
3969 #define SPEC_wout_r1 0
3970
3971 static void wout_r1_8(DisasContext *s, DisasFields *f, DisasOps *o)
3972 {
3973 int r1 = get_field(f, r1);
3974 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8);
3975 }
3976 #define SPEC_wout_r1_8 0
3977
3978 static void wout_r1_16(DisasContext *s, DisasFields *f, DisasOps *o)
3979 {
3980 int r1 = get_field(f, r1);
3981 tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 16);
3982 }
3983 #define SPEC_wout_r1_16 0
3984
3985 static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o)
3986 {
3987 store_reg32_i64(get_field(f, r1), o->out);
3988 }
3989 #define SPEC_wout_r1_32 0
3990
3991 static void wout_r1_P32(DisasContext *s, DisasFields *f, DisasOps *o)
3992 {
3993 int r1 = get_field(f, r1);
3994 store_reg32_i64(r1, o->out);
3995 store_reg32_i64(r1 + 1, o->out2);
3996 }
3997 #define SPEC_wout_r1_P32 SPEC_r1_even
3998
3999 static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
4000 {
4001 int r1 = get_field(f, r1);
4002 store_reg32_i64(r1 + 1, o->out);
4003 tcg_gen_shri_i64(o->out, o->out, 32);
4004 store_reg32_i64(r1, o->out);
4005 }
4006 #define SPEC_wout_r1_D32 SPEC_r1_even
4007
4008 static void wout_e1(DisasContext *s, DisasFields *f, DisasOps *o)
4009 {
4010 store_freg32_i64(get_field(f, r1), o->out);
4011 }
4012 #define SPEC_wout_e1 0
4013
4014 static void wout_f1(DisasContext *s, DisasFields *f, DisasOps *o)
4015 {
4016 store_freg(get_field(f, r1), o->out);
4017 }
4018 #define SPEC_wout_f1 0
4019
4020 static void wout_x1(DisasContext *s, DisasFields *f, DisasOps *o)
4021 {
4022 int f1 = get_field(s->fields, r1);
4023 store_freg(f1, o->out);
4024 store_freg(f1 + 2, o->out2);
4025 }
4026 #define SPEC_wout_x1 SPEC_r1_f128
4027
4028 static void wout_cond_r1r2_32(DisasContext *s, DisasFields *f, DisasOps *o)
4029 {
4030 if (get_field(f, r1) != get_field(f, r2)) {
4031 store_reg32_i64(get_field(f, r1), o->out);
4032 }
4033 }
4034 #define SPEC_wout_cond_r1r2_32 0
4035
4036 static void wout_cond_e1e2(DisasContext *s, DisasFields *f, DisasOps *o)
4037 {
4038 if (get_field(f, r1) != get_field(f, r2)) {
4039 store_freg32_i64(get_field(f, r1), o->out);
4040 }
4041 }
4042 #define SPEC_wout_cond_e1e2 0
4043
4044 static void wout_m1_8(DisasContext *s, DisasFields *f, DisasOps *o)
4045 {
4046 tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s));
4047 }
4048 #define SPEC_wout_m1_8 0
4049
4050 static void wout_m1_16(DisasContext *s, DisasFields *f, DisasOps *o)
4051 {
4052 tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s));
4053 }
4054 #define SPEC_wout_m1_16 0
4055
4056 static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o)
4057 {
4058 tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
4059 }
4060 #define SPEC_wout_m1_32 0
4061
4062 static void wout_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
4063 {
4064 tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
4065 }
4066 #define SPEC_wout_m1_64 0
4067
4068 static void wout_m2_32(DisasContext *s, DisasFields *f, DisasOps *o)
4069 {
4070 tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s));
4071 }
4072 #define SPEC_wout_m2_32 0
4073
4074 static void wout_m2_32_r1_atomic(DisasContext *s, DisasFields *f, DisasOps *o)
4075 {
4076 /* XXX release reservation */
4077 tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
4078 store_reg32_i64(get_field(f, r1), o->in2);
4079 }
4080 #define SPEC_wout_m2_32_r1_atomic 0
4081
4082 static void wout_m2_64_r1_atomic(DisasContext *s, DisasFields *f, DisasOps *o)
4083 {
4084 /* XXX release reservation */
4085 tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
4086 store_reg(get_field(f, r1), o->in2);
4087 }
4088 #define SPEC_wout_m2_64_r1_atomic 0
4089
4090 /* ====================================================================== */
4091 /* The "INput 1" generators. These load the first operand to an insn. */
4092
4093 static void in1_r1(DisasContext *s, DisasFields *f, DisasOps *o)
4094 {
4095 o->in1 = load_reg(get_field(f, r1));
4096 }
4097 #define SPEC_in1_r1 0
4098
4099 static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
4100 {
4101 o->in1 = regs[get_field(f, r1)];
4102 o->g_in1 = true;
4103 }
4104 #define SPEC_in1_r1_o 0
4105
4106 static void in1_r1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
4107 {
4108 o->in1 = tcg_temp_new_i64();
4109 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r1)]);
4110 }
4111 #define SPEC_in1_r1_32s 0
4112
4113 static void in1_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4114 {
4115 o->in1 = tcg_temp_new_i64();
4116 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r1)]);
4117 }
4118 #define SPEC_in1_r1_32u 0
4119
4120 static void in1_r1_sr32(DisasContext *s, DisasFields *f, DisasOps *o)
4121 {
4122 o->in1 = tcg_temp_new_i64();
4123 tcg_gen_shri_i64(o->in1, regs[get_field(f, r1)], 32);
4124 }
4125 #define SPEC_in1_r1_sr32 0
4126
4127 static void in1_r1p1(DisasContext *s, DisasFields *f, DisasOps *o)
4128 {
4129 o->in1 = load_reg(get_field(f, r1) + 1);
4130 }
4131 #define SPEC_in1_r1p1 SPEC_r1_even
4132
4133 static void in1_r1p1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
4134 {
4135 o->in1 = tcg_temp_new_i64();
4136 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r1) + 1]);
4137 }
4138 #define SPEC_in1_r1p1_32s SPEC_r1_even
4139
4140 static void in1_r1p1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4141 {
4142 o->in1 = tcg_temp_new_i64();
4143 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r1) + 1]);
4144 }
4145 #define SPEC_in1_r1p1_32u SPEC_r1_even
4146
4147 static void in1_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
4148 {
4149 int r1 = get_field(f, r1);
4150 o->in1 = tcg_temp_new_i64();
4151 tcg_gen_concat32_i64(o->in1, regs[r1 + 1], regs[r1]);
4152 }
4153 #define SPEC_in1_r1_D32 SPEC_r1_even
4154
4155 static void in1_r2(DisasContext *s, DisasFields *f, DisasOps *o)
4156 {
4157 o->in1 = load_reg(get_field(f, r2));
4158 }
4159 #define SPEC_in1_r2 0
4160
4161 static void in1_r3(DisasContext *s, DisasFields *f, DisasOps *o)
4162 {
4163 o->in1 = load_reg(get_field(f, r3));
4164 }
4165 #define SPEC_in1_r3 0
4166
4167 static void in1_r3_o(DisasContext *s, DisasFields *f, DisasOps *o)
4168 {
4169 o->in1 = regs[get_field(f, r3)];
4170 o->g_in1 = true;
4171 }
4172 #define SPEC_in1_r3_o 0
4173
4174 static void in1_r3_32s(DisasContext *s, DisasFields *f, DisasOps *o)
4175 {
4176 o->in1 = tcg_temp_new_i64();
4177 tcg_gen_ext32s_i64(o->in1, regs[get_field(f, r3)]);
4178 }
4179 #define SPEC_in1_r3_32s 0
4180
4181 static void in1_r3_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4182 {
4183 o->in1 = tcg_temp_new_i64();
4184 tcg_gen_ext32u_i64(o->in1, regs[get_field(f, r3)]);
4185 }
4186 #define SPEC_in1_r3_32u 0
4187
4188 static void in1_r3_D32(DisasContext *s, DisasFields *f, DisasOps *o)
4189 {
4190 int r3 = get_field(f, r3);
4191 o->in1 = tcg_temp_new_i64();
4192 tcg_gen_concat32_i64(o->in1, regs[r3 + 1], regs[r3]);
4193 }
4194 #define SPEC_in1_r3_D32 SPEC_r3_even
4195
4196 static void in1_e1(DisasContext *s, DisasFields *f, DisasOps *o)
4197 {
4198 o->in1 = load_freg32_i64(get_field(f, r1));
4199 }
4200 #define SPEC_in1_e1 0
4201
4202 static void in1_f1_o(DisasContext *s, DisasFields *f, DisasOps *o)
4203 {
4204 o->in1 = fregs[get_field(f, r1)];
4205 o->g_in1 = true;
4206 }
4207 #define SPEC_in1_f1_o 0
4208
4209 static void in1_x1_o(DisasContext *s, DisasFields *f, DisasOps *o)
4210 {
4211 int r1 = get_field(f, r1);
4212 o->out = fregs[r1];
4213 o->out2 = fregs[r1 + 2];
4214 o->g_out = o->g_out2 = true;
4215 }
4216 #define SPEC_in1_x1_o SPEC_r1_f128
4217
4218 static void in1_f3_o(DisasContext *s, DisasFields *f, DisasOps *o)
4219 {
4220 o->in1 = fregs[get_field(f, r3)];
4221 o->g_in1 = true;
4222 }
4223 #define SPEC_in1_f3_o 0
4224
4225 static void in1_la1(DisasContext *s, DisasFields *f, DisasOps *o)
4226 {
4227 o->addr1 = get_address(s, 0, get_field(f, b1), get_field(f, d1));
4228 }
4229 #define SPEC_in1_la1 0
4230
4231 static void in1_la2(DisasContext *s, DisasFields *f, DisasOps *o)
4232 {
4233 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
4234 o->addr1 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
4235 }
4236 #define SPEC_in1_la2 0
4237
4238 static void in1_m1_8u(DisasContext *s, DisasFields *f, DisasOps *o)
4239 {
4240 in1_la1(s, f, o);
4241 o->in1 = tcg_temp_new_i64();
4242 tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s));
4243 }
4244 #define SPEC_in1_m1_8u 0
4245
4246 static void in1_m1_16s(DisasContext *s, DisasFields *f, DisasOps *o)
4247 {
4248 in1_la1(s, f, o);
4249 o->in1 = tcg_temp_new_i64();
4250 tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s));
4251 }
4252 #define SPEC_in1_m1_16s 0
4253
4254 static void in1_m1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
4255 {
4256 in1_la1(s, f, o);
4257 o->in1 = tcg_temp_new_i64();
4258 tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s));
4259 }
4260 #define SPEC_in1_m1_16u 0
4261
4262 static void in1_m1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
4263 {
4264 in1_la1(s, f, o);
4265 o->in1 = tcg_temp_new_i64();
4266 tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s));
4267 }
4268 #define SPEC_in1_m1_32s 0
4269
4270 static void in1_m1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4271 {
4272 in1_la1(s, f, o);
4273 o->in1 = tcg_temp_new_i64();
4274 tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s));
4275 }
4276 #define SPEC_in1_m1_32u 0
4277
4278 static void in1_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
4279 {
4280 in1_la1(s, f, o);
4281 o->in1 = tcg_temp_new_i64();
4282 tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s));
4283 }
4284 #define SPEC_in1_m1_64 0
4285
4286 /* ====================================================================== */
4287 /* The "INput 2" generators. These load the second operand to an insn. */
4288
4289 static void in2_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
4290 {
4291 o->in2 = regs[get_field(f, r1)];
4292 o->g_in2 = true;
4293 }
4294 #define SPEC_in2_r1_o 0
4295
4296 static void in2_r1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
4297 {
4298 o->in2 = tcg_temp_new_i64();
4299 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r1)]);
4300 }
4301 #define SPEC_in2_r1_16u 0
4302
4303 static void in2_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4304 {
4305 o->in2 = tcg_temp_new_i64();
4306 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r1)]);
4307 }
4308 #define SPEC_in2_r1_32u 0
4309
4310 static void in2_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o)
4311 {
4312 int r1 = get_field(f, r1);
4313 o->in2 = tcg_temp_new_i64();
4314 tcg_gen_concat32_i64(o->in2, regs[r1 + 1], regs[r1]);
4315 }
4316 #define SPEC_in2_r1_D32 SPEC_r1_even
4317
4318 static void in2_r2(DisasContext *s, DisasFields *f, DisasOps *o)
4319 {
4320 o->in2 = load_reg(get_field(f, r2));
4321 }
4322 #define SPEC_in2_r2 0
4323
4324 static void in2_r2_o(DisasContext *s, DisasFields *f, DisasOps *o)
4325 {
4326 o->in2 = regs[get_field(f, r2)];
4327 o->g_in2 = true;
4328 }
4329 #define SPEC_in2_r2_o 0
4330
4331 static void in2_r2_nz(DisasContext *s, DisasFields *f, DisasOps *o)
4332 {
4333 int r2 = get_field(f, r2);
4334 if (r2 != 0) {
4335 o->in2 = load_reg(r2);
4336 }
4337 }
4338 #define SPEC_in2_r2_nz 0
4339
4340 static void in2_r2_8s(DisasContext *s, DisasFields *f, DisasOps *o)
4341 {
4342 o->in2 = tcg_temp_new_i64();
4343 tcg_gen_ext8s_i64(o->in2, regs[get_field(f, r2)]);
4344 }
4345 #define SPEC_in2_r2_8s 0
4346
4347 static void in2_r2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
4348 {
4349 o->in2 = tcg_temp_new_i64();
4350 tcg_gen_ext8u_i64(o->in2, regs[get_field(f, r2)]);
4351 }
4352 #define SPEC_in2_r2_8u 0
4353
4354 static void in2_r2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
4355 {
4356 o->in2 = tcg_temp_new_i64();
4357 tcg_gen_ext16s_i64(o->in2, regs[get_field(f, r2)]);
4358 }
4359 #define SPEC_in2_r2_16s 0
4360
4361 static void in2_r2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
4362 {
4363 o->in2 = tcg_temp_new_i64();
4364 tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r2)]);
4365 }
4366 #define SPEC_in2_r2_16u 0
4367
4368 static void in2_r3(DisasContext *s, DisasFields *f, DisasOps *o)
4369 {
4370 o->in2 = load_reg(get_field(f, r3));
4371 }
4372 #define SPEC_in2_r3 0
4373
4374 static void in2_r2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
4375 {
4376 o->in2 = tcg_temp_new_i64();
4377 tcg_gen_ext32s_i64(o->in2, regs[get_field(f, r2)]);
4378 }
4379 #define SPEC_in2_r2_32s 0
4380
4381 static void in2_r2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4382 {
4383 o->in2 = tcg_temp_new_i64();
4384 tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r2)]);
4385 }
4386 #define SPEC_in2_r2_32u 0
4387
4388 static void in2_e2(DisasContext *s, DisasFields *f, DisasOps *o)
4389 {
4390 o->in2 = load_freg32_i64(get_field(f, r2));
4391 }
4392 #define SPEC_in2_e2 0
4393
4394 static void in2_f2_o(DisasContext *s, DisasFields *f, DisasOps *o)
4395 {
4396 o->in2 = fregs[get_field(f, r2)];
4397 o->g_in2 = true;
4398 }
4399 #define SPEC_in2_f2_o 0
4400
4401 static void in2_x2_o(DisasContext *s, DisasFields *f, DisasOps *o)
4402 {
4403 int r2 = get_field(f, r2);
4404 o->in1 = fregs[r2];
4405 o->in2 = fregs[r2 + 2];
4406 o->g_in1 = o->g_in2 = true;
4407 }
4408 #define SPEC_in2_x2_o SPEC_r2_f128
4409
4410 static void in2_ra2(DisasContext *s, DisasFields *f, DisasOps *o)
4411 {
4412 o->in2 = get_address(s, 0, get_field(f, r2), 0);
4413 }
4414 #define SPEC_in2_ra2 0
4415
4416 static void in2_a2(DisasContext *s, DisasFields *f, DisasOps *o)
4417 {
4418 int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
4419 o->in2 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
4420 }
4421 #define SPEC_in2_a2 0
4422
4423 static void in2_ri2(DisasContext *s, DisasFields *f, DisasOps *o)
4424 {
4425 o->in2 = tcg_const_i64(s->pc + (int64_t)get_field(f, i2) * 2);
4426 }
4427 #define SPEC_in2_ri2 0
4428
4429 static void in2_sh32(DisasContext *s, DisasFields *f, DisasOps *o)
4430 {
4431 help_l2_shift(s, f, o, 31);
4432 }
4433 #define SPEC_in2_sh32 0
4434
4435 static void in2_sh64(DisasContext *s, DisasFields *f, DisasOps *o)
4436 {
4437 help_l2_shift(s, f, o, 63);
4438 }
4439 #define SPEC_in2_sh64 0
4440
4441 static void in2_m2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
4442 {
4443 in2_a2(s, f, o);
4444 tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s));
4445 }
4446 #define SPEC_in2_m2_8u 0
4447
4448 static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
4449 {
4450 in2_a2(s, f, o);
4451 tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
4452 }
4453 #define SPEC_in2_m2_16s 0
4454
4455 static void in2_m2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
4456 {
4457 in2_a2(s, f, o);
4458 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
4459 }
4460 #define SPEC_in2_m2_16u 0
4461
4462 static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
4463 {
4464 in2_a2(s, f, o);
4465 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
4466 }
4467 #define SPEC_in2_m2_32s 0
4468
4469 static void in2_m2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4470 {
4471 in2_a2(s, f, o);
4472 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
4473 }
4474 #define SPEC_in2_m2_32u 0
4475
4476 static void in2_m2_64(DisasContext *s, DisasFields *f, DisasOps *o)
4477 {
4478 in2_a2(s, f, o);
4479 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
4480 }
4481 #define SPEC_in2_m2_64 0
4482
4483 static void in2_mri2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
4484 {
4485 in2_ri2(s, f, o);
4486 tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
4487 }
4488 #define SPEC_in2_mri2_16u 0
4489
4490 static void in2_mri2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
4491 {
4492 in2_ri2(s, f, o);
4493 tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
4494 }
4495 #define SPEC_in2_mri2_32s 0
4496
4497 static void in2_mri2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4498 {
4499 in2_ri2(s, f, o);
4500 tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
4501 }
4502 #define SPEC_in2_mri2_32u 0
4503
4504 static void in2_mri2_64(DisasContext *s, DisasFields *f, DisasOps *o)
4505 {
4506 in2_ri2(s, f, o);
4507 tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
4508 }
4509 #define SPEC_in2_mri2_64 0
4510
4511 static void in2_m2_32s_atomic(DisasContext *s, DisasFields *f, DisasOps *o)
4512 {
4513 /* XXX should reserve the address */
4514 in1_la2(s, f, o);
4515 o->in2 = tcg_temp_new_i64();
4516 tcg_gen_qemu_ld32s(o->in2, o->addr1, get_mem_index(s));
4517 }
4518 #define SPEC_in2_m2_32s_atomic 0
4519
4520 static void in2_m2_64_atomic(DisasContext *s, DisasFields *f, DisasOps *o)
4521 {
4522 /* XXX should reserve the address */
4523 in1_la2(s, f, o);
4524 o->in2 = tcg_temp_new_i64();
4525 tcg_gen_qemu_ld64(o->in2, o->addr1, get_mem_index(s));
4526 }
4527 #define SPEC_in2_m2_64_atomic 0
4528
4529 static void in2_i2(DisasContext *s, DisasFields *f, DisasOps *o)
4530 {
4531 o->in2 = tcg_const_i64(get_field(f, i2));
4532 }
4533 #define SPEC_in2_i2 0
4534
4535 static void in2_i2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
4536 {
4537 o->in2 = tcg_const_i64((uint8_t)get_field(f, i2));
4538 }
4539 #define SPEC_in2_i2_8u 0
4540
4541 static void in2_i2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
4542 {
4543 o->in2 = tcg_const_i64((uint16_t)get_field(f, i2));
4544 }
4545 #define SPEC_in2_i2_16u 0
4546
4547 static void in2_i2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
4548 {
4549 o->in2 = tcg_const_i64((uint32_t)get_field(f, i2));
4550 }
4551 #define SPEC_in2_i2_32u 0
4552
4553 static void in2_i2_16u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
4554 {
4555 uint64_t i2 = (uint16_t)get_field(f, i2);
4556 o->in2 = tcg_const_i64(i2 << s->insn->data);
4557 }
4558 #define SPEC_in2_i2_16u_shl 0
4559
4560 static void in2_i2_32u_shl(DisasContext *s, DisasFields *f, DisasOps *o)
4561 {
4562 uint64_t i2 = (uint32_t)get_field(f, i2);
4563 o->in2 = tcg_const_i64(i2 << s->insn->data);
4564 }
4565 #define SPEC_in2_i2_32u_shl 0
4566
4567 /* ====================================================================== */
4568
4569 /* Find opc within the table of insns. This is formulated as a switch
4570 statement so that (1) we get compile-time notice of cut-paste errors
4571 for duplicated opcodes, and (2) the compiler generates the binary
4572 search tree, rather than us having to post-process the table. */
4573
4574 #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
4575 D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0)
4576
4577 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) insn_ ## NM,
4578
4579 enum DisasInsnEnum {
4580 #include "insn-data.def"
4581 };
4582
4583 #undef D
4584 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) { \
4585 .opc = OPC, \
4586 .fmt = FMT_##FT, \
4587 .fac = FAC_##FC, \
4588 .spec = SPEC_in1_##I1 | SPEC_in2_##I2 | SPEC_prep_##P | SPEC_wout_##W, \
4589 .name = #NM, \
4590 .help_in1 = in1_##I1, \
4591 .help_in2 = in2_##I2, \
4592 .help_prep = prep_##P, \
4593 .help_wout = wout_##W, \
4594 .help_cout = cout_##CC, \
4595 .help_op = op_##OP, \
4596 .data = D \
4597 },
4598
4599 /* Allow 0 to be used for NULL in the table below. */
4600 #define in1_0 NULL
4601 #define in2_0 NULL
4602 #define prep_0 NULL
4603 #define wout_0 NULL
4604 #define cout_0 NULL
4605 #define op_0 NULL
4606
4607 #define SPEC_in1_0 0
4608 #define SPEC_in2_0 0
4609 #define SPEC_prep_0 0
4610 #define SPEC_wout_0 0
4611
4612 static const DisasInsn insn_info[] = {
4613 #include "insn-data.def"
4614 };
4615
4616 #undef D
4617 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
4618 case OPC: return &insn_info[insn_ ## NM];
4619
4620 static const DisasInsn *lookup_opc(uint16_t opc)
4621 {
4622 switch (opc) {
4623 #include "insn-data.def"
4624 default:
4625 return NULL;
4626 }
4627 }
4628
4629 #undef D
4630 #undef C
4631
4632 /* Extract a field from the insn. The INSN should be left-aligned in
4633 the uint64_t so that we can more easily utilize the big-bit-endian
4634 definitions we extract from the Principals of Operation. */
4635
4636 static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn)
4637 {
4638 uint32_t r, m;
4639
4640 if (f->size == 0) {
4641 return;
4642 }
4643
4644 /* Zero extract the field from the insn. */
4645 r = (insn << f->beg) >> (64 - f->size);
4646
4647 /* Sign-extend, or un-swap the field as necessary. */
4648 switch (f->type) {
4649 case 0: /* unsigned */
4650 break;
4651 case 1: /* signed */
4652 assert(f->size <= 32);
4653 m = 1u << (f->size - 1);
4654 r = (r ^ m) - m;
4655 break;
4656 case 2: /* dl+dh split, signed 20 bit. */
4657 r = ((int8_t)r << 12) | (r >> 8);
4658 break;
4659 default:
4660 abort();
4661 }
4662
4663 /* Validate that the "compressed" encoding we selected above is valid.
4664 I.e. we havn't make two different original fields overlap. */
4665 assert(((o->presentC >> f->indexC) & 1) == 0);
4666 o->presentC |= 1 << f->indexC;
4667 o->presentO |= 1 << f->indexO;
4668
4669 o->c[f->indexC] = r;
4670 }
4671
4672 /* Lookup the insn at the current PC, extracting the operands into O and
4673 returning the info struct for the insn. Returns NULL for invalid insn. */
4674
4675 static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
4676 DisasFields *f)
4677 {
4678 uint64_t insn, pc = s->pc;
4679 int op, op2, ilen;
4680 const DisasInsn *info;
4681
4682 insn = ld_code2(env, pc);
4683 op = (insn >> 8) & 0xff;
4684 ilen = get_ilen(op);
4685 s->next_pc = s->pc + ilen;
4686
4687 switch (ilen) {
4688 case 2:
4689 insn = insn << 48;
4690 break;
4691 case 4:
4692 insn = ld_code4(env, pc) << 32;
4693 break;
4694 case 6:
4695 insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
4696 break;
4697 default:
4698 abort();
4699 }
4700
4701 /* We can't actually determine the insn format until we've looked up
4702 the full insn opcode. Which we can't do without locating the
4703 secondary opcode. Assume by default that OP2 is at bit 40; for
4704 those smaller insns that don't actually have a secondary opcode
4705 this will correctly result in OP2 = 0. */
4706 switch (op) {
4707 case 0x01: /* E */
4708 case 0x80: /* S */
4709 case 0x82: /* S */
4710 case 0x93: /* S */
4711 case 0xb2: /* S, RRF, RRE */
4712 case 0xb3: /* RRE, RRD, RRF */
4713 case 0xb9: /* RRE, RRF */
4714 case 0xe5: /* SSE, SIL */
4715 op2 = (insn << 8) >> 56;
4716 break;
4717 case 0xa5: /* RI */
4718 case 0xa7: /* RI */
4719 case 0xc0: /* RIL */
4720 case 0xc2: /* RIL */
4721 case 0xc4: /* RIL */
4722 case 0xc6: /* RIL */
4723 case 0xc8: /* SSF */
4724 case 0xcc: /* RIL */
4725 op2 = (insn << 12) >> 60;
4726 break;
4727 case 0xd0 ... 0xdf: /* SS */
4728 case 0xe1: /* SS */
4729 case 0xe2: /* SS */
4730 case 0xe8: /* SS */
4731 case 0xe9: /* SS */
4732 case 0xea: /* SS */
4733 case 0xee ... 0xf3: /* SS */
4734 case 0xf8 ... 0xfd: /* SS */
4735 op2 = 0;
4736 break;
4737 default:
4738 op2 = (insn << 40) >> 56;
4739 break;
4740 }
4741
4742 memset(f, 0, sizeof(*f));
4743 f->op = op;
4744 f->op2 = op2;
4745
4746 /* Lookup the instruction. */
4747 info = lookup_opc(op << 8 | op2);
4748
4749 /* If we found it, extract the operands. */
4750 if (info != NULL) {
4751 DisasFormat fmt = info->fmt;
4752 int i;
4753
4754 for (i = 0; i < NUM_C_FIELD; ++i) {
4755 extract_field(f, &format_info[fmt].op[i], insn);
4756 }
4757 }
4758 return info;
4759 }
4760
4761 static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
4762 {
4763 const DisasInsn *insn;
4764 ExitStatus ret = NO_EXIT;
4765 DisasFields f;
4766 DisasOps o;
4767
4768 /* Search for the insn in the table. */
4769 insn = extract_insn(env, s, &f);
4770
4771 /* Not found means unimplemented/illegal opcode. */
4772 if (insn == NULL) {
4773 qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%02x%02x\n",
4774 f.op, f.op2);
4775 gen_illegal_opcode(s);
4776 return EXIT_NORETURN;
4777 }
4778
4779 /* Check for insn specification exceptions. */
4780 if (insn->spec) {
4781 int spec = insn->spec, excp = 0, r;
4782
4783 if (spec & SPEC_r1_even) {
4784 r = get_field(&f, r1);
4785 if (r & 1) {
4786 excp = PGM_SPECIFICATION;
4787 }
4788 }
4789 if (spec & SPEC_r2_even) {
4790 r = get_field(&f, r2);
4791 if (r & 1) {
4792 excp = PGM_SPECIFICATION;
4793 }
4794 }
4795 if (spec & SPEC_r3_even) {
4796 r = get_field(&f, r3);
4797 if (r & 1) {
4798 excp = PGM_SPECIFICATION;
4799 }
4800 }
4801 if (spec & SPEC_r1_f128) {
4802 r = get_field(&f, r1);
4803 if (r > 13) {
4804 excp = PGM_SPECIFICATION;
4805 }
4806 }
4807 if (spec & SPEC_r2_f128) {
4808 r = get_field(&f, r2);
4809 if (r > 13) {
4810 excp = PGM_SPECIFICATION;
4811 }
4812 }
4813 if (excp) {
4814 gen_program_exception(s, excp);
4815 return EXIT_NORETURN;
4816 }
4817 }
4818
4819 /* Set up the strutures we use to communicate with the helpers. */
4820 s->insn = insn;
4821 s->fields = &f;
4822 o.g_out = o.g_out2 = o.g_in1 = o.g_in2 = false;
4823 TCGV_UNUSED_I64(o.out);
4824 TCGV_UNUSED_I64(o.out2);
4825 TCGV_UNUSED_I64(o.in1);
4826 TCGV_UNUSED_I64(o.in2);
4827 TCGV_UNUSED_I64(o.addr1);
4828
4829 /* Implement the instruction. */
4830 if (insn->help_in1) {
4831 insn->help_in1(s, &f, &o);
4832 }
4833 if (insn->help_in2) {
4834 insn->help_in2(s, &f, &o);
4835 }
4836 if (insn->help_prep) {
4837 insn->help_prep(s, &f, &o);
4838 }
4839 if (insn->help_op) {
4840 ret = insn->help_op(s, &o);
4841 }
4842 if (insn->help_wout) {
4843 insn->help_wout(s, &f, &o);
4844 }
4845 if (insn->help_cout) {
4846 insn->help_cout(s, &o);
4847 }
4848
4849 /* Free any temporaries created by the helpers. */
4850 if (!TCGV_IS_UNUSED_I64(o.out) && !o.g_out) {
4851 tcg_temp_free_i64(o.out);
4852 }
4853 if (!TCGV_IS_UNUSED_I64(o.out2) && !o.g_out2) {
4854 tcg_temp_free_i64(o.out2);
4855 }
4856 if (!TCGV_IS_UNUSED_I64(o.in1) && !o.g_in1) {
4857 tcg_temp_free_i64(o.in1);
4858 }
4859 if (!TCGV_IS_UNUSED_I64(o.in2) && !o.g_in2) {
4860 tcg_temp_free_i64(o.in2);
4861 }
4862 if (!TCGV_IS_UNUSED_I64(o.addr1)) {
4863 tcg_temp_free_i64(o.addr1);
4864 }
4865
4866 /* Advance to the next instruction. */
4867 s->pc = s->next_pc;
4868 return ret;
4869 }
4870
4871 static inline void gen_intermediate_code_internal(S390CPU *cpu,
4872 TranslationBlock *tb,
4873 bool search_pc)
4874 {
4875 CPUState *cs = CPU(cpu);
4876 CPUS390XState *env = &cpu->env;
4877 DisasContext dc;
4878 target_ulong pc_start;
4879 uint64_t next_page_start;
4880 int j, lj = -1;
4881 int num_insns, max_insns;
4882 CPUBreakpoint *bp;
4883 ExitStatus status;
4884 bool do_debug;
4885
4886 pc_start = tb->pc;
4887
4888 /* 31-bit mode */
4889 if (!(tb->flags & FLAG_MASK_64)) {
4890 pc_start &= 0x7fffffff;
4891 }
4892
4893 dc.tb = tb;
4894 dc.pc = pc_start;
4895 dc.cc_op = CC_OP_DYNAMIC;
4896 do_debug = dc.singlestep_enabled = cs->singlestep_enabled;
4897
4898 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4899
4900 num_insns = 0;
4901 max_insns = tb->cflags & CF_COUNT_MASK;
4902 if (max_insns == 0) {
4903 max_insns = CF_COUNT_MASK;
4904 }
4905
4906 gen_tb_start(tb);
4907
4908 do {
4909 if (search_pc) {
4910 j = tcg_op_buf_count();
4911 if (lj < j) {
4912 lj++;
4913 while (lj < j) {
4914 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4915 }
4916 }
4917 tcg_ctx.gen_opc_pc[lj] = dc.pc;
4918 gen_opc_cc_op[lj] = dc.cc_op;
4919 tcg_ctx.gen_opc_instr_start[lj] = 1;
4920 tcg_ctx.gen_opc_icount[lj] = num_insns;
4921 }
4922 if (++num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
4923 gen_io_start();
4924 }
4925
4926 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4927 tcg_gen_debug_insn_start(dc.pc);
4928 }
4929
4930 status = NO_EXIT;
4931 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
4932 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
4933 if (bp->pc == dc.pc) {
4934 status = EXIT_PC_STALE;
4935 do_debug = true;
4936 break;
4937 }
4938 }
4939 }
4940 if (status == NO_EXIT) {
4941 status = translate_one(env, &dc);
4942 }
4943
4944 /* If we reach a page boundary, are single stepping,
4945 or exhaust instruction count, stop generation. */
4946 if (status == NO_EXIT
4947 && (dc.pc >= next_page_start
4948 || tcg_op_buf_full()
4949 || num_insns >= max_insns
4950 || singlestep
4951 || cs->singlestep_enabled)) {
4952 status = EXIT_PC_STALE;
4953 }
4954 } while (status == NO_EXIT);
4955
4956 if (tb->cflags & CF_LAST_IO) {
4957 gen_io_end();
4958 }
4959
4960 switch (status) {
4961 case EXIT_GOTO_TB:
4962 case EXIT_NORETURN:
4963 break;
4964 case EXIT_PC_STALE:
4965 update_psw_addr(&dc);
4966 /* FALLTHRU */
4967 case EXIT_PC_UPDATED:
4968 /* Next TB starts off with CC_OP_DYNAMIC, so make sure the
4969 cc op type is in env */
4970 update_cc_op(&dc);
4971 /* Exit the TB, either by raising a debug exception or by return. */
4972 if (do_debug) {
4973 gen_exception(EXCP_DEBUG);
4974 } else {
4975 tcg_gen_exit_tb(0);
4976 }
4977 break;
4978 default:
4979 abort();
4980 }
4981
4982 gen_tb_end(tb, num_insns);
4983
4984 if (search_pc) {
4985 j = tcg_op_buf_count();
4986 lj++;
4987 while (lj <= j) {
4988 tcg_ctx.gen_opc_instr_start[lj++] = 0;
4989 }
4990 } else {
4991 tb->size = dc.pc - pc_start;
4992 tb->icount = num_insns;
4993 }
4994
4995 #if defined(S390X_DEBUG_DISAS)
4996 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
4997 qemu_log("IN: %s\n", lookup_symbol(pc_start));
4998 log_target_disas(env, pc_start, dc.pc - pc_start, 1);
4999 qemu_log("\n");
5000 }
5001 #endif
5002 }
5003
5004 void gen_intermediate_code (CPUS390XState *env, struct TranslationBlock *tb)
5005 {
5006 gen_intermediate_code_internal(s390_env_get_cpu(env), tb, false);
5007 }
5008
5009 void gen_intermediate_code_pc (CPUS390XState *env, struct TranslationBlock *tb)
5010 {
5011 gen_intermediate_code_internal(s390_env_get_cpu(env), tb, true);
5012 }
5013
5014 void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos)
5015 {
5016 int cc_op;
5017 env->psw.addr = tcg_ctx.gen_opc_pc[pc_pos];
5018 cc_op = gen_opc_cc_op[pc_pos];
5019 if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {
5020 env->cc_op = cc_op;
5021 }
5022 }
AR7 emulation for QEMU