apic: rename apic specific bitopts
[qemu/ar7.git] / target-i386 / arch_memory_mapping.c
blob844893f44d9da3e95c64ce166f13d99cb9a651c7
1 /*
2 * i386 memory mapping
4 * Copyright Fujitsu, Corp. 2011, 2012
6 * Authors:
7 * Wen Congyang <wency@cn.fujitsu.com>
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
14 #include "cpu.h"
15 #include "exec/cpu-all.h"
16 #include "sysemu/memory_mapping.h"
18 /* PAE Paging or IA-32e Paging */
19 static void walk_pte(MemoryMappingList *list, hwaddr pte_start_addr,
20 int32_t a20_mask, target_ulong start_line_addr)
22 hwaddr pte_addr, start_paddr;
23 uint64_t pte;
24 target_ulong start_vaddr;
25 int i;
27 for (i = 0; i < 512; i++) {
28 pte_addr = (pte_start_addr + i * 8) & a20_mask;
29 pte = ldq_phys(pte_addr);
30 if (!(pte & PG_PRESENT_MASK)) {
31 /* not present */
32 continue;
35 start_paddr = (pte & ~0xfff) & ~(0x1ULL << 63);
36 if (cpu_physical_memory_is_io(start_paddr)) {
37 /* I/O region */
38 continue;
41 start_vaddr = start_line_addr | ((i & 0x1fff) << 12);
42 memory_mapping_list_add_merge_sorted(list, start_paddr,
43 start_vaddr, 1 << 12);
47 /* 32-bit Paging */
48 static void walk_pte2(MemoryMappingList *list,
49 hwaddr pte_start_addr, int32_t a20_mask,
50 target_ulong start_line_addr)
52 hwaddr pte_addr, start_paddr;
53 uint32_t pte;
54 target_ulong start_vaddr;
55 int i;
57 for (i = 0; i < 1024; i++) {
58 pte_addr = (pte_start_addr + i * 4) & a20_mask;
59 pte = ldl_phys(pte_addr);
60 if (!(pte & PG_PRESENT_MASK)) {
61 /* not present */
62 continue;
65 start_paddr = pte & ~0xfff;
66 if (cpu_physical_memory_is_io(start_paddr)) {
67 /* I/O region */
68 continue;
71 start_vaddr = start_line_addr | ((i & 0x3ff) << 12);
72 memory_mapping_list_add_merge_sorted(list, start_paddr,
73 start_vaddr, 1 << 12);
77 /* PAE Paging or IA-32e Paging */
78 static void walk_pde(MemoryMappingList *list, hwaddr pde_start_addr,
79 int32_t a20_mask, target_ulong start_line_addr)
81 hwaddr pde_addr, pte_start_addr, start_paddr;
82 uint64_t pde;
83 target_ulong line_addr, start_vaddr;
84 int i;
86 for (i = 0; i < 512; i++) {
87 pde_addr = (pde_start_addr + i * 8) & a20_mask;
88 pde = ldq_phys(pde_addr);
89 if (!(pde & PG_PRESENT_MASK)) {
90 /* not present */
91 continue;
94 line_addr = start_line_addr | ((i & 0x1ff) << 21);
95 if (pde & PG_PSE_MASK) {
96 /* 2 MB page */
97 start_paddr = (pde & ~0x1fffff) & ~(0x1ULL << 63);
98 if (cpu_physical_memory_is_io(start_paddr)) {
99 /* I/O region */
100 continue;
102 start_vaddr = line_addr;
103 memory_mapping_list_add_merge_sorted(list, start_paddr,
104 start_vaddr, 1 << 21);
105 continue;
108 pte_start_addr = (pde & ~0xfff) & a20_mask;
109 walk_pte(list, pte_start_addr, a20_mask, line_addr);
113 /* 32-bit Paging */
114 static void walk_pde2(MemoryMappingList *list,
115 hwaddr pde_start_addr, int32_t a20_mask,
116 bool pse)
118 hwaddr pde_addr, pte_start_addr, start_paddr, high_paddr;
119 uint32_t pde;
120 target_ulong line_addr, start_vaddr;
121 int i;
123 for (i = 0; i < 1024; i++) {
124 pde_addr = (pde_start_addr + i * 4) & a20_mask;
125 pde = ldl_phys(pde_addr);
126 if (!(pde & PG_PRESENT_MASK)) {
127 /* not present */
128 continue;
131 line_addr = (((unsigned int)i & 0x3ff) << 22);
132 if ((pde & PG_PSE_MASK) && pse) {
134 * 4 MB page:
135 * bits 39:32 are bits 20:13 of the PDE
136 * bit3 31:22 are bits 31:22 of the PDE
138 high_paddr = ((hwaddr)(pde & 0x1fe000) << 19);
139 start_paddr = (pde & ~0x3fffff) | high_paddr;
140 if (cpu_physical_memory_is_io(start_paddr)) {
141 /* I/O region */
142 continue;
144 start_vaddr = line_addr;
145 memory_mapping_list_add_merge_sorted(list, start_paddr,
146 start_vaddr, 1 << 22);
147 continue;
150 pte_start_addr = (pde & ~0xfff) & a20_mask;
151 walk_pte2(list, pte_start_addr, a20_mask, line_addr);
155 /* PAE Paging */
156 static void walk_pdpe2(MemoryMappingList *list,
157 hwaddr pdpe_start_addr, int32_t a20_mask)
159 hwaddr pdpe_addr, pde_start_addr;
160 uint64_t pdpe;
161 target_ulong line_addr;
162 int i;
164 for (i = 0; i < 4; i++) {
165 pdpe_addr = (pdpe_start_addr + i * 8) & a20_mask;
166 pdpe = ldq_phys(pdpe_addr);
167 if (!(pdpe & PG_PRESENT_MASK)) {
168 /* not present */
169 continue;
172 line_addr = (((unsigned int)i & 0x3) << 30);
173 pde_start_addr = (pdpe & ~0xfff) & a20_mask;
174 walk_pde(list, pde_start_addr, a20_mask, line_addr);
178 #ifdef TARGET_X86_64
179 /* IA-32e Paging */
180 static void walk_pdpe(MemoryMappingList *list,
181 hwaddr pdpe_start_addr, int32_t a20_mask,
182 target_ulong start_line_addr)
184 hwaddr pdpe_addr, pde_start_addr, start_paddr;
185 uint64_t pdpe;
186 target_ulong line_addr, start_vaddr;
187 int i;
189 for (i = 0; i < 512; i++) {
190 pdpe_addr = (pdpe_start_addr + i * 8) & a20_mask;
191 pdpe = ldq_phys(pdpe_addr);
192 if (!(pdpe & PG_PRESENT_MASK)) {
193 /* not present */
194 continue;
197 line_addr = start_line_addr | ((i & 0x1ffULL) << 30);
198 if (pdpe & PG_PSE_MASK) {
199 /* 1 GB page */
200 start_paddr = (pdpe & ~0x3fffffff) & ~(0x1ULL << 63);
201 if (cpu_physical_memory_is_io(start_paddr)) {
202 /* I/O region */
203 continue;
205 start_vaddr = line_addr;
206 memory_mapping_list_add_merge_sorted(list, start_paddr,
207 start_vaddr, 1 << 30);
208 continue;
211 pde_start_addr = (pdpe & ~0xfff) & a20_mask;
212 walk_pde(list, pde_start_addr, a20_mask, line_addr);
216 /* IA-32e Paging */
217 static void walk_pml4e(MemoryMappingList *list,
218 hwaddr pml4e_start_addr, int32_t a20_mask)
220 hwaddr pml4e_addr, pdpe_start_addr;
221 uint64_t pml4e;
222 target_ulong line_addr;
223 int i;
225 for (i = 0; i < 512; i++) {
226 pml4e_addr = (pml4e_start_addr + i * 8) & a20_mask;
227 pml4e = ldq_phys(pml4e_addr);
228 if (!(pml4e & PG_PRESENT_MASK)) {
229 /* not present */
230 continue;
233 line_addr = ((i & 0x1ffULL) << 39) | (0xffffULL << 48);
234 pdpe_start_addr = (pml4e & ~0xfff) & a20_mask;
235 walk_pdpe(list, pdpe_start_addr, a20_mask, line_addr);
238 #endif
240 int cpu_get_memory_mapping(MemoryMappingList *list, CPUArchState *env)
242 if (!cpu_paging_enabled(env)) {
243 /* paging is disabled */
244 return 0;
247 if (env->cr[4] & CR4_PAE_MASK) {
248 #ifdef TARGET_X86_64
249 if (env->hflags & HF_LMA_MASK) {
250 hwaddr pml4e_addr;
252 pml4e_addr = (env->cr[3] & ~0xfff) & env->a20_mask;
253 walk_pml4e(list, pml4e_addr, env->a20_mask);
254 } else
255 #endif
257 hwaddr pdpe_addr;
259 pdpe_addr = (env->cr[3] & ~0x1f) & env->a20_mask;
260 walk_pdpe2(list, pdpe_addr, env->a20_mask);
262 } else {
263 hwaddr pde_addr;
264 bool pse;
266 pde_addr = (env->cr[3] & ~0xfff) & env->a20_mask;
267 pse = !!(env->cr[4] & CR4_PSE_MASK);
268 walk_pde2(list, pde_addr, env->a20_mask, pse);
271 return 0;
274 bool cpu_paging_enabled(CPUArchState *env)
276 return env->cr[0] & CR0_PG_MASK;