hw/timer/puv3_ost.c

   1 /*
   2  * OSTimer device simulation in PKUnity SoC
   3  *
   4  * Copyright (C) 2010-2012 Guan Xuetao
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation, or any later version.
   9  * See the COPYING file in the top-level directory.
  10  */
  11 #include "hw/sysbus.h"
  12 #include "hw/ptimer.h"
  13
  14 #undef DEBUG_PUV3
  15 #include "hw/unicore32/puv3.h"
  16
  17 /* puv3 ostimer implementation. */
  18 typedef struct {
  19     SysBusDevice busdev;
  20     MemoryRegion iomem;
  21     QEMUBH *bh;
  22     qemu_irq irq;
  23     ptimer_state *ptimer;
  24
  25     uint32_t reg_OSMR0;
  26     uint32_t reg_OSCR;
  27     uint32_t reg_OSSR;
  28     uint32_t reg_OIER;
  29 } PUV3OSTState;
  30
  31 static uint64_t puv3_ost_read(void *opaque, hwaddr offset,
  32         unsigned size)
  33 {
  34     PUV3OSTState *s = opaque;
  35     uint32_t ret = 0;
  36
  37     switch (offset) {
  38     case 0x10: /* Counter Register */
  39         ret = s->reg_OSMR0 - (uint32_t)ptimer_get_count(s->ptimer);
  40         break;
  41     case 0x14: /* Status Register */
  42         ret = s->reg_OSSR;
  43         break;
  44     case 0x1c: /* Interrupt Enable Register */
  45         ret = s->reg_OIER;
  46         break;
  47     default:
  48         DPRINTF("Bad offset %x\n", (int)offset);
  49     }
  50     DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  51     return ret;
  52 }
  53
  54 static void puv3_ost_write(void *opaque, hwaddr offset,
  55         uint64_t value, unsigned size)
  56 {
  57     PUV3OSTState *s = opaque;
  58
  59     DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
  60     switch (offset) {
  61     case 0x00: /* Match Register 0 */
  62         s->reg_OSMR0 = value;
  63         if (s->reg_OSMR0 > s->reg_OSCR) {
  64             ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR);
  65         } else {
  66             ptimer_set_count(s->ptimer, s->reg_OSMR0 +
  67                     (0xffffffff - s->reg_OSCR));
  68         }
  69         ptimer_run(s->ptimer, 2);
  70         break;
  71     case 0x14: /* Status Register */
  72         assert(value == 0);
  73         if (s->reg_OSSR) {
  74             s->reg_OSSR = value;
  75             qemu_irq_lower(s->irq);
  76         }
  77         break;
  78     case 0x1c: /* Interrupt Enable Register */
  79         s->reg_OIER = value;
  80         break;
  81     default:
  82         DPRINTF("Bad offset %x\n", (int)offset);
  83     }
  84 }
  85
  86 static const MemoryRegionOps puv3_ost_ops = {
  87     .read = puv3_ost_read,
  88     .write = puv3_ost_write,
  89     .impl = {
  90         .min_access_size = 4,
  91         .max_access_size = 4,
  92     },
  93     .endianness = DEVICE_NATIVE_ENDIAN,
  94 };
  95
  96 static void puv3_ost_tick(void *opaque)
  97 {
  98     PUV3OSTState *s = opaque;
  99
 100     DPRINTF("ost hit when ptimer counter from 0x%x to 0x%x!\n",
 101             s->reg_OSCR, s->reg_OSMR0);
 102
 103     s->reg_OSCR = s->reg_OSMR0;
 104     if (s->reg_OIER) {
 105         s->reg_OSSR = 1;
 106         qemu_irq_raise(s->irq);
 107     }
 108 }
 109
 110 static int puv3_ost_init(SysBusDevice *dev)
 111 {
 112     PUV3OSTState *s = FROM_SYSBUS(PUV3OSTState, dev);
 113
 114     s->reg_OIER = 0;
 115     s->reg_OSSR = 0;
 116     s->reg_OSMR0 = 0;
 117     s->reg_OSCR = 0;
 118
 119     sysbus_init_irq(dev, &s->irq);
 120
 121     s->bh = qemu_bh_new(puv3_ost_tick, s);
 122     s->ptimer = ptimer_init(s->bh);
 123     ptimer_set_freq(s->ptimer, 50 * 1000 * 1000);
 124
 125     memory_region_init_io(&s->iomem, &puv3_ost_ops, s, "puv3_ost",
 126             PUV3_REGS_OFFSET);
 127     sysbus_init_mmio(dev, &s->iomem);
 128
 129     return 0;
 130 }
 131
 132 static void puv3_ost_class_init(ObjectClass *klass, void *data)
 133 {
 134     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 135
 136     sdc->init = puv3_ost_init;
 137 }
 138
 139 static const TypeInfo puv3_ost_info = {
 140     .name = "puv3_ost",
 141     .parent = TYPE_SYS_BUS_DEVICE,
 142     .instance_size = sizeof(PUV3OSTState),
 143     .class_init = puv3_ost_class_init,
 144 };
 145
 146 static void puv3_ost_register_type(void)
 147 {
 148     type_register_static(&puv3_ost_info);
 149 }
 150
 151 type_init(puv3_ost_register_type)