target-s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * Contributions after 2012-10-29 are licensed under the terms of the
  17  * GNU GPL, version 2 or (at your option) any later version.
  18  *
  19  * You should have received a copy of the GNU (Lesser) General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22 #ifndef CPU_S390X_H
  23 #define CPU_S390X_H
  24
  25 #include "config.h"
  26 #include "qemu-common.h"
  27
  28 #define TARGET_LONG_BITS 64
  29
  30 #define ELF_MACHINE     EM_S390
  31 #define ELF_MACHINE_UNAME "S390X"
  32
  33 #define CPUArchState struct CPUS390XState
  34
  35 #include "exec/cpu-defs.h"
  36 #define TARGET_PAGE_BITS 12
  37
  38 #define TARGET_PHYS_ADDR_SPACE_BITS 64
  39 #define TARGET_VIRT_ADDR_SPACE_BITS 64
  40
  41 #include "exec/cpu-all.h"
  42
  43 #include "fpu/softfloat.h"
  44
  45 #define NB_MMU_MODES 3
  46
  47 #define MMU_MODE0_SUFFIX _primary
  48 #define MMU_MODE1_SUFFIX _secondary
  49 #define MMU_MODE2_SUFFIX _home
  50
  51 #define MMU_USER_IDX 1
  52
  53 #define MAX_EXT_QUEUE 16
  54 #define MAX_IO_QUEUE 16
  55 #define MAX_MCHK_QUEUE 16
  56
  57 #define PSW_MCHK_MASK 0x0004000000000000
  58 #define PSW_IO_MASK 0x0200000000000000
  59
  60 typedef struct PSW {
  61     uint64_t mask;
  62     uint64_t addr;
  63 } PSW;
  64
  65 typedef struct ExtQueue {
  66     uint32_t code;
  67     uint32_t param;
  68     uint32_t param64;
  69 } ExtQueue;
  70
  71 typedef struct IOIntQueue {
  72     uint16_t id;
  73     uint16_t nr;
  74     uint32_t parm;
  75     uint32_t word;
  76 } IOIntQueue;
  77
  78 typedef struct MchkQueue {
  79     uint16_t type;
  80 } MchkQueue;
  81
  82 typedef struct CPUS390XState {
  83     uint64_t regs[16];     /* GP registers */
  84     CPU_DoubleU fregs[16]; /* FP registers */
  85     uint32_t aregs[16];    /* access registers */
  86
  87     uint32_t fpc;          /* floating-point control register */
  88     uint32_t cc_op;
  89
  90     float_status fpu_status; /* passed to softfloat lib */
  91
  92     /* The low part of a 128-bit return, or remainder of a divide.  */
  93     uint64_t retxl;
  94
  95     PSW psw;
  96
  97     uint64_t cc_src;
  98     uint64_t cc_dst;
  99     uint64_t cc_vr;
 100
 101     uint64_t __excp_addr;
 102     uint64_t psa;
 103
 104     uint32_t int_pgm_code;
 105     uint32_t int_pgm_ilen;
 106
 107     uint32_t int_svc_code;
 108     uint32_t int_svc_ilen;
 109
 110     uint64_t cregs[16]; /* control registers */
 111
 112     ExtQueue ext_queue[MAX_EXT_QUEUE];
 113     IOIntQueue io_queue[MAX_IO_QUEUE][8];
 114     MchkQueue mchk_queue[MAX_MCHK_QUEUE];
 115
 116     int pending_int;
 117     int ext_index;
 118     int io_index[8];
 119     int mchk_index;
 120
 121     uint64_t ckc;
 122     uint64_t cputm;
 123     uint32_t todpr;
 124
 125     uint64_t pfault_token;
 126     uint64_t pfault_compare;
 127     uint64_t pfault_select;
 128
 129     uint64_t gbea;
 130     uint64_t pp;
 131
 132     CPU_COMMON
 133
 134     /* reset does memset(0) up to here */
 135
 136     uint32_t cpu_num;
 137     uint32_t machine_type;
 138
 139     uint8_t *storage_keys;
 140
 141     uint64_t tod_offset;
 142     uint64_t tod_basetime;
 143     QEMUTimer *tod_timer;
 144
 145     QEMUTimer *cpu_timer;
 146
 147     /*
 148      * The cpu state represents the logical state of a cpu. In contrast to other
 149      * architectures, there is a difference between a halt and a stop on s390.
 150      * If all cpus are either stopped (including check stop) or in the disabled
 151      * wait state, the vm can be shut down.
 152      */
 153 #define CPU_STATE_UNINITIALIZED        0x00
 154 #define CPU_STATE_STOPPED              0x01
 155 #define CPU_STATE_CHECK_STOP           0x02
 156 #define CPU_STATE_OPERATING            0x03
 157 #define CPU_STATE_LOAD                 0x04
 158     uint8_t cpu_state;
 159
 160 } CPUS390XState;
 161
 162 #include "cpu-qom.h"
 163 #include <sysemu/kvm.h>
 164
 165 /* distinguish between 24 bit and 31 bit addressing */
 166 #define HIGH_ORDER_BIT 0x80000000
 167
 168 /* Interrupt Codes */
 169 /* Program Interrupts */
 170 #define PGM_OPERATION                   0x0001
 171 #define PGM_PRIVILEGED                  0x0002
 172 #define PGM_EXECUTE                     0x0003
 173 #define PGM_PROTECTION                  0x0004
 174 #define PGM_ADDRESSING                  0x0005
 175 #define PGM_SPECIFICATION               0x0006
 176 #define PGM_DATA                        0x0007
 177 #define PGM_FIXPT_OVERFLOW              0x0008
 178 #define PGM_FIXPT_DIVIDE                0x0009
 179 #define PGM_DEC_OVERFLOW                0x000a
 180 #define PGM_DEC_DIVIDE                  0x000b
 181 #define PGM_HFP_EXP_OVERFLOW            0x000c
 182 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 183 #define PGM_HFP_SIGNIFICANCE            0x000e
 184 #define PGM_HFP_DIVIDE                  0x000f
 185 #define PGM_SEGMENT_TRANS               0x0010
 186 #define PGM_PAGE_TRANS                  0x0011
 187 #define PGM_TRANS_SPEC                  0x0012
 188 #define PGM_SPECIAL_OP                  0x0013
 189 #define PGM_OPERAND                     0x0015
 190 #define PGM_TRACE_TABLE                 0x0016
 191 #define PGM_SPACE_SWITCH                0x001c
 192 #define PGM_HFP_SQRT                    0x001d
 193 #define PGM_PC_TRANS_SPEC               0x001f
 194 #define PGM_AFX_TRANS                   0x0020
 195 #define PGM_ASX_TRANS                   0x0021
 196 #define PGM_LX_TRANS                    0x0022
 197 #define PGM_EX_TRANS                    0x0023
 198 #define PGM_PRIM_AUTH                   0x0024
 199 #define PGM_SEC_AUTH                    0x0025
 200 #define PGM_ALET_SPEC                   0x0028
 201 #define PGM_ALEN_SPEC                   0x0029
 202 #define PGM_ALE_SEQ                     0x002a
 203 #define PGM_ASTE_VALID                  0x002b
 204 #define PGM_ASTE_SEQ                    0x002c
 205 #define PGM_EXT_AUTH                    0x002d
 206 #define PGM_STACK_FULL                  0x0030
 207 #define PGM_STACK_EMPTY                 0x0031
 208 #define PGM_STACK_SPEC                  0x0032
 209 #define PGM_STACK_TYPE                  0x0033
 210 #define PGM_STACK_OP                    0x0034
 211 #define PGM_ASCE_TYPE                   0x0038
 212 #define PGM_REG_FIRST_TRANS             0x0039
 213 #define PGM_REG_SEC_TRANS               0x003a
 214 #define PGM_REG_THIRD_TRANS             0x003b
 215 #define PGM_MONITOR                     0x0040
 216 #define PGM_PER                         0x0080
 217 #define PGM_CRYPTO                      0x0119
 218
 219 /* External Interrupts */
 220 #define EXT_INTERRUPT_KEY               0x0040
 221 #define EXT_CLOCK_COMP                  0x1004
 222 #define EXT_CPU_TIMER                   0x1005
 223 #define EXT_MALFUNCTION                 0x1200
 224 #define EXT_EMERGENCY                   0x1201
 225 #define EXT_EXTERNAL_CALL               0x1202
 226 #define EXT_ETR                         0x1406
 227 #define EXT_SERVICE                     0x2401
 228 #define EXT_VIRTIO                      0x2603
 229
 230 /* PSW defines */
 231 #undef PSW_MASK_PER
 232 #undef PSW_MASK_DAT
 233 #undef PSW_MASK_IO
 234 #undef PSW_MASK_EXT
 235 #undef PSW_MASK_KEY
 236 #undef PSW_SHIFT_KEY
 237 #undef PSW_MASK_MCHECK
 238 #undef PSW_MASK_WAIT
 239 #undef PSW_MASK_PSTATE
 240 #undef PSW_MASK_ASC
 241 #undef PSW_MASK_CC
 242 #undef PSW_MASK_PM
 243 #undef PSW_MASK_64
 244 #undef PSW_MASK_32
 245 #undef PSW_MASK_ESA_ADDR
 246
 247 #define PSW_MASK_PER            0x4000000000000000ULL
 248 #define PSW_MASK_DAT            0x0400000000000000ULL
 249 #define PSW_MASK_IO             0x0200000000000000ULL
 250 #define PSW_MASK_EXT            0x0100000000000000ULL
 251 #define PSW_MASK_KEY            0x00F0000000000000ULL
 252 #define PSW_SHIFT_KEY           56
 253 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 254 #define PSW_MASK_WAIT           0x0002000000000000ULL
 255 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 256 #define PSW_MASK_ASC            0x0000C00000000000ULL
 257 #define PSW_MASK_CC             0x0000300000000000ULL
 258 #define PSW_MASK_PM             0x00000F0000000000ULL
 259 #define PSW_MASK_64             0x0000000100000000ULL
 260 #define PSW_MASK_32             0x0000000080000000ULL
 261 #define PSW_MASK_ESA_ADDR       0x000000007fffffffULL
 262
 263 #undef PSW_ASC_PRIMARY
 264 #undef PSW_ASC_ACCREG
 265 #undef PSW_ASC_SECONDARY
 266 #undef PSW_ASC_HOME
 267
 268 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 269 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 270 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 271 #define PSW_ASC_HOME            0x0000C00000000000ULL
 272
 273 /* tb flags */
 274
 275 #define FLAG_MASK_PER           (PSW_MASK_PER    >> 32)
 276 #define FLAG_MASK_DAT           (PSW_MASK_DAT    >> 32)
 277 #define FLAG_MASK_IO            (PSW_MASK_IO     >> 32)
 278 #define FLAG_MASK_EXT           (PSW_MASK_EXT    >> 32)
 279 #define FLAG_MASK_KEY           (PSW_MASK_KEY    >> 32)
 280 #define FLAG_MASK_MCHECK        (PSW_MASK_MCHECK >> 32)
 281 #define FLAG_MASK_WAIT          (PSW_MASK_WAIT   >> 32)
 282 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> 32)
 283 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> 32)
 284 #define FLAG_MASK_CC            (PSW_MASK_CC     >> 32)
 285 #define FLAG_MASK_PM            (PSW_MASK_PM     >> 32)
 286 #define FLAG_MASK_64            (PSW_MASK_64     >> 32)
 287 #define FLAG_MASK_32            0x00001000
 288
 289 /* Control register 0 bits */
 290 #define CR0_EDAT                0x0000000000800000ULL
 291
 292 static inline int cpu_mmu_index (CPUS390XState *env)
 293 {
 294     if (env->psw.mask & PSW_MASK_PSTATE) {
 295         return 1;
 296     }
 297
 298     return 0;
 299 }
 300
 301 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 302                                         target_ulong *cs_base, int *flags)
 303 {
 304     *pc = env->psw.addr;
 305     *cs_base = 0;
 306     *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
 307              ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
 308 }
 309
 310 /* While the PoO talks about ILC (a number between 1-3) what is actually
 311    stored in LowCore is shifted left one bit (an even between 2-6).  As
 312    this is the actual length of the insn and therefore more useful, that
 313    is what we want to pass around and manipulate.  To make sure that we
 314    have applied this distinction universally, rename the "ILC" to "ILEN".  */
 315 static inline int get_ilen(uint8_t opc)
 316 {
 317     switch (opc >> 6) {
 318     case 0:
 319         return 2;
 320     case 1:
 321     case 2:
 322         return 4;
 323     default:
 324         return 6;
 325     }
 326 }
 327
 328 #ifndef CONFIG_USER_ONLY
 329 /* In several cases of runtime exceptions, we havn't recorded the true
 330    instruction length.  Use these codes when raising exceptions in order
 331    to re-compute the length by examining the insn in memory.  */
 332 #define ILEN_LATER       0x20
 333 #define ILEN_LATER_INC   0x21
 334 #endif
 335
 336 S390CPU *cpu_s390x_init(const char *cpu_model);
 337 void s390x_translate_init(void);
 338 int cpu_s390x_exec(CPUS390XState *s);
 339
 340 /* you can call this signal handler from your SIGBUS and SIGSEGV
 341    signal handlers to inform the virtual CPU of exceptions. non zero
 342    is returned if the signal was handled by the virtual CPU.  */
 343 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
 344                            void *puc);
 345 int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 346                               int mmu_idx);
 347
 348 #include "ioinst.h"
 349
 350 #ifndef CONFIG_USER_ONLY
 351 void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
 352                                    int is_write);
 353 void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
 354                                     int is_write);
 355 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
 356 {
 357     hwaddr addr = 0;
 358     uint8_t reg;
 359
 360     reg = ipb >> 28;
 361     if (reg > 0) {
 362         addr = env->regs[reg];
 363     }
 364     addr += (ipb >> 16) & 0xfff;
 365
 366     return addr;
 367 }
 368
 369 /* Base/displacement are at the same locations. */
 370 #define decode_basedisp_rs decode_basedisp_s
 371
 372 /* helper functions for run_on_cpu() */
 373 static inline void s390_do_cpu_reset(void *arg)
 374 {
 375     CPUState *cs = arg;
 376     S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
 377
 378     scc->cpu_reset(cs);
 379 }
 380 static inline void s390_do_cpu_full_reset(void *arg)
 381 {
 382     CPUState *cs = arg;
 383
 384     cpu_reset(cs);
 385 }
 386
 387 void s390x_tod_timer(void *opaque);
 388 void s390x_cpu_timer(void *opaque);
 389
 390 int s390_virtio_hypercall(CPUS390XState *env);
 391 void s390_virtio_irq(int config_change, uint64_t token);
 392
 393 #ifdef CONFIG_KVM
 394 void kvm_s390_virtio_irq(int config_change, uint64_t token);
 395 void kvm_s390_service_interrupt(uint32_t parm);
 396 void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
 397 void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
 398 int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
 399 #else
 400 static inline void kvm_s390_virtio_irq(int config_change, uint64_t token)
 401 {
 402 }
 403 static inline void kvm_s390_service_interrupt(uint32_t parm)
 404 {
 405 }
 406 #endif
 407 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 408 unsigned int s390_cpu_halt(S390CPU *cpu);
 409 void s390_cpu_unhalt(S390CPU *cpu);
 410 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
 411
 412 /* service interrupts are floating therefore we must not pass an cpustate */
 413 void s390_sclp_extint(uint32_t parm);
 414
 415 /* from s390-virtio-bus */
 416 extern const hwaddr virtio_size;
 417
 418 #else
 419 static inline unsigned int s390_cpu_halt(S390CPU *cpu)
 420 {
 421     return 0;
 422 }
 423
 424 static inline void s390_cpu_unhalt(S390CPU *cpu)
 425 {
 426 }
 427
 428 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
 429 {
 430     return 0;
 431 }
 432 #endif
 433 void cpu_lock(void);
 434 void cpu_unlock(void);
 435
 436 typedef struct SubchDev SubchDev;
 437
 438 #ifndef CONFIG_USER_ONLY
 439 extern void io_subsystem_reset(void);
 440 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
 441                          uint16_t schid);
 442 bool css_subch_visible(SubchDev *sch);
 443 void css_conditional_io_interrupt(SubchDev *sch);
 444 int css_do_stsch(SubchDev *sch, SCHIB *schib);
 445 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
 446 int css_do_msch(SubchDev *sch, SCHIB *schib);
 447 int css_do_xsch(SubchDev *sch);
 448 int css_do_csch(SubchDev *sch);
 449 int css_do_hsch(SubchDev *sch);
 450 int css_do_ssch(SubchDev *sch, ORB *orb);
 451 int css_do_tsch(SubchDev *sch, IRB *irb);
 452 int css_do_stcrw(CRW *crw);
 453 int css_do_tpi(IOIntCode *int_code, int lowcore);
 454 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
 455                          int rfmt, void *buf);
 456 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
 457 int css_enable_mcsse(void);
 458 int css_enable_mss(void);
 459 int css_do_rsch(SubchDev *sch);
 460 int css_do_rchp(uint8_t cssid, uint8_t chpid);
 461 bool css_present(uint8_t cssid);
 462 #endif
 463
 464 #define cpu_init(model) (&cpu_s390x_init(model)->env)
 465 #define cpu_exec cpu_s390x_exec
 466 #define cpu_gen_code cpu_s390x_gen_code
 467 #define cpu_signal_handler cpu_s390x_signal_handler
 468
 469 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 470 #define cpu_list s390_cpu_list
 471
 472 #include "exec/exec-all.h"
 473
 474 #define EXCP_EXT 1 /* external interrupt */
 475 #define EXCP_SVC 2 /* supervisor call (syscall) */
 476 #define EXCP_PGM 3 /* program interruption */
 477 #define EXCP_IO  7 /* I/O interrupt */
 478 #define EXCP_MCHK 8 /* machine check */
 479
 480 #define INTERRUPT_EXT        (1 << 0)
 481 #define INTERRUPT_TOD        (1 << 1)
 482 #define INTERRUPT_CPUTIMER   (1 << 2)
 483 #define INTERRUPT_IO         (1 << 3)
 484 #define INTERRUPT_MCHK       (1 << 4)
 485
 486 /* Program Status Word.  */
 487 #define S390_PSWM_REGNUM 0
 488 #define S390_PSWA_REGNUM 1
 489 /* General Purpose Registers.  */
 490 #define S390_R0_REGNUM 2
 491 #define S390_R1_REGNUM 3
 492 #define S390_R2_REGNUM 4
 493 #define S390_R3_REGNUM 5
 494 #define S390_R4_REGNUM 6
 495 #define S390_R5_REGNUM 7
 496 #define S390_R6_REGNUM 8
 497 #define S390_R7_REGNUM 9
 498 #define S390_R8_REGNUM 10
 499 #define S390_R9_REGNUM 11
 500 #define S390_R10_REGNUM 12
 501 #define S390_R11_REGNUM 13
 502 #define S390_R12_REGNUM 14
 503 #define S390_R13_REGNUM 15
 504 #define S390_R14_REGNUM 16
 505 #define S390_R15_REGNUM 17
 506 /* Total Core Registers. */
 507 #define S390_NUM_CORE_REGS 18
 508
 509 /* CC optimization */
 510
 511 enum cc_op {
 512     CC_OP_CONST0 = 0,           /* CC is 0 */
 513     CC_OP_CONST1,               /* CC is 1 */
 514     CC_OP_CONST2,               /* CC is 2 */
 515     CC_OP_CONST3,               /* CC is 3 */
 516
 517     CC_OP_DYNAMIC,              /* CC calculation defined by env->cc_op */
 518     CC_OP_STATIC,               /* CC value is env->cc_op */
 519
 520     CC_OP_NZ,                   /* env->cc_dst != 0 */
 521     CC_OP_LTGT_32,              /* signed less/greater than (32bit) */
 522     CC_OP_LTGT_64,              /* signed less/greater than (64bit) */
 523     CC_OP_LTUGTU_32,            /* unsigned less/greater than (32bit) */
 524     CC_OP_LTUGTU_64,            /* unsigned less/greater than (64bit) */
 525     CC_OP_LTGT0_32,             /* signed less/greater than 0 (32bit) */
 526     CC_OP_LTGT0_64,             /* signed less/greater than 0 (64bit) */
 527
 528     CC_OP_ADD_64,               /* overflow on add (64bit) */
 529     CC_OP_ADDU_64,              /* overflow on unsigned add (64bit) */
 530     CC_OP_ADDC_64,              /* overflow on unsigned add-carry (64bit) */
 531     CC_OP_SUB_64,               /* overflow on subtraction (64bit) */
 532     CC_OP_SUBU_64,              /* overflow on unsigned subtraction (64bit) */
 533     CC_OP_SUBB_64,              /* overflow on unsigned sub-borrow (64bit) */
 534     CC_OP_ABS_64,               /* sign eval on abs (64bit) */
 535     CC_OP_NABS_64,              /* sign eval on nabs (64bit) */
 536
 537     CC_OP_ADD_32,               /* overflow on add (32bit) */
 538     CC_OP_ADDU_32,              /* overflow on unsigned add (32bit) */
 539     CC_OP_ADDC_32,              /* overflow on unsigned add-carry (32bit) */
 540     CC_OP_SUB_32,               /* overflow on subtraction (32bit) */
 541     CC_OP_SUBU_32,              /* overflow on unsigned subtraction (32bit) */
 542     CC_OP_SUBB_32,              /* overflow on unsigned sub-borrow (32bit) */
 543     CC_OP_ABS_32,               /* sign eval on abs (64bit) */
 544     CC_OP_NABS_32,              /* sign eval on nabs (64bit) */
 545
 546     CC_OP_COMP_32,              /* complement */
 547     CC_OP_COMP_64,              /* complement */
 548
 549     CC_OP_TM_32,                /* test under mask (32bit) */
 550     CC_OP_TM_64,                /* test under mask (64bit) */
 551
 552     CC_OP_NZ_F32,               /* FP dst != 0 (32bit) */
 553     CC_OP_NZ_F64,               /* FP dst != 0 (64bit) */
 554     CC_OP_NZ_F128,              /* FP dst != 0 (128bit) */
 555
 556     CC_OP_ICM,                  /* insert characters under mask */
 557     CC_OP_SLA_32,               /* Calculate shift left signed (32bit) */
 558     CC_OP_SLA_64,               /* Calculate shift left signed (64bit) */
 559     CC_OP_FLOGR,                /* find leftmost one */
 560     CC_OP_MAX
 561 };
 562
 563 static const char *cc_names[] = {
 564     [CC_OP_CONST0]    = "CC_OP_CONST0",
 565     [CC_OP_CONST1]    = "CC_OP_CONST1",
 566     [CC_OP_CONST2]    = "CC_OP_CONST2",
 567     [CC_OP_CONST3]    = "CC_OP_CONST3",
 568     [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
 569     [CC_OP_STATIC]    = "CC_OP_STATIC",
 570     [CC_OP_NZ]        = "CC_OP_NZ",
 571     [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
 572     [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
 573     [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
 574     [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
 575     [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 576     [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 577     [CC_OP_ADD_64]    = "CC_OP_ADD_64",
 578     [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
 579     [CC_OP_ADDC_64]   = "CC_OP_ADDC_64",
 580     [CC_OP_SUB_64]    = "CC_OP_SUB_64",
 581     [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
 582     [CC_OP_SUBB_64]   = "CC_OP_SUBB_64",
 583     [CC_OP_ABS_64]    = "CC_OP_ABS_64",
 584     [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 585     [CC_OP_ADD_32]    = "CC_OP_ADD_32",
 586     [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
 587     [CC_OP_ADDC_32]   = "CC_OP_ADDC_32",
 588     [CC_OP_SUB_32]    = "CC_OP_SUB_32",
 589     [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
 590     [CC_OP_SUBB_32]   = "CC_OP_SUBB_32",
 591     [CC_OP_ABS_32]    = "CC_OP_ABS_32",
 592     [CC_OP_NABS_32]   = "CC_OP_NABS_32",
 593     [CC_OP_COMP_32]   = "CC_OP_COMP_32",
 594     [CC_OP_COMP_64]   = "CC_OP_COMP_64",
 595     [CC_OP_TM_32]     = "CC_OP_TM_32",
 596     [CC_OP_TM_64]     = "CC_OP_TM_64",
 597     [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
 598     [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
 599     [CC_OP_NZ_F128]   = "CC_OP_NZ_F128",
 600     [CC_OP_ICM]       = "CC_OP_ICM",
 601     [CC_OP_SLA_32]    = "CC_OP_SLA_32",
 602     [CC_OP_SLA_64]    = "CC_OP_SLA_64",
 603     [CC_OP_FLOGR]     = "CC_OP_FLOGR",
 604 };
 605
 606 static inline const char *cc_name(int cc_op)
 607 {
 608     return cc_names[cc_op];
 609 }
 610
 611 static inline void setcc(S390CPU *cpu, uint64_t cc)
 612 {
 613     CPUS390XState *env = &cpu->env;
 614
 615     env->psw.mask &= ~(3ull << 44);
 616     env->psw.mask |= (cc & 3) << 44;
 617 }
 618
 619 typedef struct LowCore
 620 {
 621     /* prefix area: defined by architecture */
 622     uint32_t        ccw1[2];                  /* 0x000 */
 623     uint32_t        ccw2[4];                  /* 0x008 */
 624     uint8_t         pad1[0x80-0x18];          /* 0x018 */
 625     uint32_t        ext_params;               /* 0x080 */
 626     uint16_t        cpu_addr;                 /* 0x084 */
 627     uint16_t        ext_int_code;             /* 0x086 */
 628     uint16_t        svc_ilen;                 /* 0x088 */
 629     uint16_t        svc_code;                 /* 0x08a */
 630     uint16_t        pgm_ilen;                 /* 0x08c */
 631     uint16_t        pgm_code;                 /* 0x08e */
 632     uint32_t        data_exc_code;            /* 0x090 */
 633     uint16_t        mon_class_num;            /* 0x094 */
 634     uint16_t        per_perc_atmid;           /* 0x096 */
 635     uint64_t        per_address;              /* 0x098 */
 636     uint8_t         exc_access_id;            /* 0x0a0 */
 637     uint8_t         per_access_id;            /* 0x0a1 */
 638     uint8_t         op_access_id;             /* 0x0a2 */
 639     uint8_t         ar_access_id;             /* 0x0a3 */
 640     uint8_t         pad2[0xA8-0xA4];          /* 0x0a4 */
 641     uint64_t        trans_exc_code;           /* 0x0a8 */
 642     uint64_t        monitor_code;             /* 0x0b0 */
 643     uint16_t        subchannel_id;            /* 0x0b8 */
 644     uint16_t        subchannel_nr;            /* 0x0ba */
 645     uint32_t        io_int_parm;              /* 0x0bc */
 646     uint32_t        io_int_word;              /* 0x0c0 */
 647     uint8_t         pad3[0xc8-0xc4];          /* 0x0c4 */
 648     uint32_t        stfl_fac_list;            /* 0x0c8 */
 649     uint8_t         pad4[0xe8-0xcc];          /* 0x0cc */
 650     uint32_t        mcck_interruption_code[2]; /* 0x0e8 */
 651     uint8_t         pad5[0xf4-0xf0];          /* 0x0f0 */
 652     uint32_t        external_damage_code;     /* 0x0f4 */
 653     uint64_t        failing_storage_address;  /* 0x0f8 */
 654     uint8_t         pad6[0x120-0x100];        /* 0x100 */
 655     PSW             restart_old_psw;          /* 0x120 */
 656     PSW             external_old_psw;         /* 0x130 */
 657     PSW             svc_old_psw;              /* 0x140 */
 658     PSW             program_old_psw;          /* 0x150 */
 659     PSW             mcck_old_psw;             /* 0x160 */
 660     PSW             io_old_psw;               /* 0x170 */
 661     uint8_t         pad7[0x1a0-0x180];        /* 0x180 */
 662     PSW             restart_psw;              /* 0x1a0 */
 663     PSW             external_new_psw;         /* 0x1b0 */
 664     PSW             svc_new_psw;              /* 0x1c0 */
 665     PSW             program_new_psw;          /* 0x1d0 */
 666     PSW             mcck_new_psw;             /* 0x1e0 */
 667     PSW             io_new_psw;               /* 0x1f0 */
 668     PSW             return_psw;               /* 0x200 */
 669     uint8_t         irb[64];                  /* 0x210 */
 670     uint64_t        sync_enter_timer;         /* 0x250 */
 671     uint64_t        async_enter_timer;        /* 0x258 */
 672     uint64_t        exit_timer;               /* 0x260 */
 673     uint64_t        last_update_timer;        /* 0x268 */
 674     uint64_t        user_timer;               /* 0x270 */
 675     uint64_t        system_timer;             /* 0x278 */
 676     uint64_t        last_update_clock;        /* 0x280 */
 677     uint64_t        steal_clock;              /* 0x288 */
 678     PSW             return_mcck_psw;          /* 0x290 */
 679     uint8_t         pad8[0xc00-0x2a0];        /* 0x2a0 */
 680     /* System info area */
 681     uint64_t        save_area[16];            /* 0xc00 */
 682     uint8_t         pad9[0xd40-0xc80];        /* 0xc80 */
 683     uint64_t        kernel_stack;             /* 0xd40 */
 684     uint64_t        thread_info;              /* 0xd48 */
 685     uint64_t        async_stack;              /* 0xd50 */
 686     uint64_t        kernel_asce;              /* 0xd58 */
 687     uint64_t        user_asce;                /* 0xd60 */
 688     uint64_t        panic_stack;              /* 0xd68 */
 689     uint64_t        user_exec_asce;           /* 0xd70 */
 690     uint8_t         pad10[0xdc0-0xd78];       /* 0xd78 */
 691
 692     /* SMP info area: defined by DJB */
 693     uint64_t        clock_comparator;         /* 0xdc0 */
 694     uint64_t        ext_call_fast;            /* 0xdc8 */
 695     uint64_t        percpu_offset;            /* 0xdd0 */
 696     uint64_t        current_task;             /* 0xdd8 */
 697     uint32_t        softirq_pending;          /* 0xde0 */
 698     uint32_t        pad_0x0de4;               /* 0xde4 */
 699     uint64_t        int_clock;                /* 0xde8 */
 700     uint8_t         pad12[0xe00-0xdf0];       /* 0xdf0 */
 701
 702     /* 0xe00 is used as indicator for dump tools */
 703     /* whether the kernel died with panic() or not */
 704     uint32_t        panic_magic;              /* 0xe00 */
 705
 706     uint8_t         pad13[0x11b8-0xe04];      /* 0xe04 */
 707
 708     /* 64 bit extparam used for pfault, diag 250 etc  */
 709     uint64_t        ext_params2;               /* 0x11B8 */
 710
 711     uint8_t         pad14[0x1200-0x11C0];      /* 0x11C0 */
 712
 713     /* System info area */
 714
 715     uint64_t        floating_pt_save_area[16]; /* 0x1200 */
 716     uint64_t        gpregs_save_area[16];      /* 0x1280 */
 717     uint32_t        st_status_fixed_logout[4]; /* 0x1300 */
 718     uint8_t         pad15[0x1318-0x1310];      /* 0x1310 */
 719     uint32_t        prefixreg_save_area;       /* 0x1318 */
 720     uint32_t        fpt_creg_save_area;        /* 0x131c */
 721     uint8_t         pad16[0x1324-0x1320];      /* 0x1320 */
 722     uint32_t        tod_progreg_save_area;     /* 0x1324 */
 723     uint32_t        cpu_timer_save_area[2];    /* 0x1328 */
 724     uint32_t        clock_comp_save_area[2];   /* 0x1330 */
 725     uint8_t         pad17[0x1340-0x1338];      /* 0x1338 */
 726     uint32_t        access_regs_save_area[16]; /* 0x1340 */
 727     uint64_t        cregs_save_area[16];       /* 0x1380 */
 728
 729     /* align to the top of the prefix area */
 730
 731     uint8_t         pad18[0x2000-0x1400];      /* 0x1400 */
 732 } QEMU_PACKED LowCore;
 733
 734 /* STSI */
 735 #define STSI_LEVEL_MASK         0x00000000f0000000ULL
 736 #define STSI_LEVEL_CURRENT      0x0000000000000000ULL
 737 #define STSI_LEVEL_1            0x0000000010000000ULL
 738 #define STSI_LEVEL_2            0x0000000020000000ULL
 739 #define STSI_LEVEL_3            0x0000000030000000ULL
 740 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 741 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 742 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 743 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 744
 745 /* Basic Machine Configuration */
 746 struct sysib_111 {
 747     uint32_t res1[8];
 748     uint8_t  manuf[16];
 749     uint8_t  type[4];
 750     uint8_t  res2[12];
 751     uint8_t  model[16];
 752     uint8_t  sequence[16];
 753     uint8_t  plant[4];
 754     uint8_t  res3[156];
 755 };
 756
 757 /* Basic Machine CPU */
 758 struct sysib_121 {
 759     uint32_t res1[80];
 760     uint8_t  sequence[16];
 761     uint8_t  plant[4];
 762     uint8_t  res2[2];
 763     uint16_t cpu_addr;
 764     uint8_t  res3[152];
 765 };
 766
 767 /* Basic Machine CPUs */
 768 struct sysib_122 {
 769     uint8_t res1[32];
 770     uint32_t capability;
 771     uint16_t total_cpus;
 772     uint16_t active_cpus;
 773     uint16_t standby_cpus;
 774     uint16_t reserved_cpus;
 775     uint16_t adjustments[2026];
 776 };
 777
 778 /* LPAR CPU */
 779 struct sysib_221 {
 780     uint32_t res1[80];
 781     uint8_t  sequence[16];
 782     uint8_t  plant[4];
 783     uint16_t cpu_id;
 784     uint16_t cpu_addr;
 785     uint8_t  res3[152];
 786 };
 787
 788 /* LPAR CPUs */
 789 struct sysib_222 {
 790     uint32_t res1[32];
 791     uint16_t lpar_num;
 792     uint8_t  res2;
 793     uint8_t  lcpuc;
 794     uint16_t total_cpus;
 795     uint16_t conf_cpus;
 796     uint16_t standby_cpus;
 797     uint16_t reserved_cpus;
 798     uint8_t  name[8];
 799     uint32_t caf;
 800     uint8_t  res3[16];
 801     uint16_t dedicated_cpus;
 802     uint16_t shared_cpus;
 803     uint8_t  res4[180];
 804 };
 805
 806 /* VM CPUs */
 807 struct sysib_322 {
 808     uint8_t  res1[31];
 809     uint8_t  count;
 810     struct {
 811         uint8_t  res2[4];
 812         uint16_t total_cpus;
 813         uint16_t conf_cpus;
 814         uint16_t standby_cpus;
 815         uint16_t reserved_cpus;
 816         uint8_t  name[8];
 817         uint32_t caf;
 818         uint8_t  cpi[16];
 819         uint8_t  res3[24];
 820     } vm[8];
 821     uint8_t res4[3552];
 822 };
 823
 824 /* MMU defines */
 825 #define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
 826 #define _ASCE_SUBSPACE          0x200     /* subspace group control           */
 827 #define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
 828 #define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
 829 #define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
 830 #define _ASCE_REAL_SPACE        0x20      /* real space control               */
 831 #define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
 832 #define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
 833 #define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
 834 #define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
 835 #define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
 836 #define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
 837
 838 #define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
 839 #define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
 840 #define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
 841 #define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
 842 #define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
 843 #define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
 844 #define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
 845
 846 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
 847 #define _SEGMENT_ENTRY_FC       0x400     /* format control                   */
 848 #define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
 849 #define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
 850
 851 #define _PAGE_RO        0x200            /* HW read-only bit  */
 852 #define _PAGE_INVALID   0x400            /* HW invalid bit    */
 853
 854 #define SK_C                    (0x1 << 1)
 855 #define SK_R                    (0x1 << 2)
 856 #define SK_F                    (0x1 << 3)
 857 #define SK_ACC_MASK             (0xf << 4)
 858
 859 #define SIGP_SENSE             0x01
 860 #define SIGP_EXTERNAL_CALL     0x02
 861 #define SIGP_EMERGENCY         0x03
 862 #define SIGP_START             0x04
 863 #define SIGP_STOP              0x05
 864 #define SIGP_RESTART           0x06
 865 #define SIGP_STOP_STORE_STATUS 0x09
 866 #define SIGP_INITIAL_CPU_RESET 0x0b
 867 #define SIGP_CPU_RESET         0x0c
 868 #define SIGP_SET_PREFIX        0x0d
 869 #define SIGP_STORE_STATUS_ADDR 0x0e
 870 #define SIGP_SET_ARCH          0x12
 871
 872 /* cpu status bits */
 873 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
 874 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
 875 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
 876 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
 877 #define SIGP_STAT_STOPPED           0x00000040UL
 878 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
 879 #define SIGP_STAT_CHECK_STOP        0x00000010UL
 880 #define SIGP_STAT_INOPERATIVE       0x00000004UL
 881 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
 882 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
 883
 884 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
 885 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 886                   target_ulong *raddr, int *flags);
 887 int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
 888 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
 889                  uint64_t vr);
 890
 891 /* The value of the TOD clock for 1.1.1970. */
 892 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
 893
 894 /* Converts ns to s390's clock format */
 895 static inline uint64_t time2tod(uint64_t ns) {
 896     return (ns << 9) / 125;
 897 }
 898
 899 static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
 900                                   uint64_t param64)
 901 {
 902     CPUS390XState *env = &cpu->env;
 903
 904     if (env->ext_index == MAX_EXT_QUEUE - 1) {
 905         /* ugh - can't queue anymore. Let's drop. */
 906         return;
 907     }
 908
 909     env->ext_index++;
 910     assert(env->ext_index < MAX_EXT_QUEUE);
 911
 912     env->ext_queue[env->ext_index].code = code;
 913     env->ext_queue[env->ext_index].param = param;
 914     env->ext_queue[env->ext_index].param64 = param64;
 915
 916     env->pending_int |= INTERRUPT_EXT;
 917     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
 918 }
 919
 920 static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
 921                                  uint16_t subchannel_number,
 922                                  uint32_t io_int_parm, uint32_t io_int_word)
 923 {
 924     CPUS390XState *env = &cpu->env;
 925     int isc = IO_INT_WORD_ISC(io_int_word);
 926
 927     if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
 928         /* ugh - can't queue anymore. Let's drop. */
 929         return;
 930     }
 931
 932     env->io_index[isc]++;
 933     assert(env->io_index[isc] < MAX_IO_QUEUE);
 934
 935     env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
 936     env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
 937     env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
 938     env->io_queue[env->io_index[isc]][isc].word = io_int_word;
 939
 940     env->pending_int |= INTERRUPT_IO;
 941     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
 942 }
 943
 944 static inline void cpu_inject_crw_mchk(S390CPU *cpu)
 945 {
 946     CPUS390XState *env = &cpu->env;
 947
 948     if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
 949         /* ugh - can't queue anymore. Let's drop. */
 950         return;
 951     }
 952
 953     env->mchk_index++;
 954     assert(env->mchk_index < MAX_MCHK_QUEUE);
 955
 956     env->mchk_queue[env->mchk_index].type = 1;
 957
 958     env->pending_int |= INTERRUPT_MCHK;
 959     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
 960 }
 961
 962 /* from s390-virtio-ccw */
 963 #define MEM_SECTION_SIZE             0x10000000UL
 964 #define MAX_AVAIL_SLOTS              32
 965
 966 /* fpu_helper.c */
 967 uint32_t set_cc_nz_f32(float32 v);
 968 uint32_t set_cc_nz_f64(float64 v);
 969 uint32_t set_cc_nz_f128(float128 v);
 970
 971 /* misc_helper.c */
 972 #ifndef CONFIG_USER_ONLY
 973 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
 974 #endif
 975 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
 976 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
 977                                      uintptr_t retaddr);
 978
 979 #ifdef CONFIG_KVM
 980 void kvm_s390_io_interrupt(uint16_t subchannel_id,
 981                            uint16_t subchannel_nr, uint32_t io_int_parm,
 982                            uint32_t io_int_word);
 983 void kvm_s390_crw_mchk(void);
 984 void kvm_s390_enable_css_support(S390CPU *cpu);
 985 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
 986                                     int vq, bool assign);
 987 int kvm_s390_cpu_restart(S390CPU *cpu);
 988 int kvm_s390_get_memslot_count(KVMState *s);
 989 void kvm_s390_clear_cmma_callback(void *opaque);
 990 int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
 991 void kvm_s390_reset_vcpu(S390CPU *cpu);
 992 #else
 993 static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
 994                                         uint16_t subchannel_nr,
 995                                         uint32_t io_int_parm,
 996                                         uint32_t io_int_word)
 997 {
 998 }
 999 static inline void kvm_s390_crw_mchk(void)
1000 {
1001 }
1002 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1003 {
1004 }
1005 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1006                                                   uint32_t sch, int vq,
1007                                                   bool assign)
1008 {
1009     return -ENOSYS;
1010 }
1011 static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1012 {
1013     return -ENOSYS;
1014 }
1015 static inline void kvm_s390_clear_cmma_callback(void *opaque)
1016 {
1017 }
1018 static inline int kvm_s390_get_memslot_count(KVMState *s)
1019 {
1020   return MAX_AVAIL_SLOTS;
1021 }
1022 static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1023 {
1024     return -ENOSYS;
1025 }
1026 static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1027 {
1028 }
1029 #endif
1030
1031 static inline void cmma_reset(S390CPU *cpu)
1032 {
1033     if (kvm_enabled()) {
1034         CPUState *cs = CPU(cpu);
1035         kvm_s390_clear_cmma_callback(cs->kvm_state);
1036     }
1037 }
1038
1039 static inline int s390_cpu_restart(S390CPU *cpu)
1040 {
1041     if (kvm_enabled()) {
1042         return kvm_s390_cpu_restart(cpu);
1043     }
1044     return -ENOSYS;
1045 }
1046
1047 static inline int s390_get_memslot_count(KVMState *s)
1048 {
1049     if (kvm_enabled()) {
1050         return kvm_s390_get_memslot_count(s);
1051     } else {
1052         return MAX_AVAIL_SLOTS;
1053     }
1054 }
1055
1056 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1057                        uint32_t io_int_parm, uint32_t io_int_word);
1058 void s390_crw_mchk(void);
1059
1060 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1061                                               uint32_t sch_id, int vq,
1062                                               bool assign)
1063 {
1064     if (kvm_enabled()) {
1065         return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1066     } else {
1067         return -ENOSYS;
1068     }
1069 }
1070
1071 #endif