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arm: virt: Add an abstract ARM virt machine type
[qemu/ar7.git] / target-tilegx / translate.c
blob03918ebd5d4a5a4b2fe961a7aa8f7ef7e014a40b
1 /*
2 * QEMU TILE-Gx CPU
3 *
4 * Copyright (c) 2015 Chen Gang
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "qemu/log.h"
24 #include "exec/log.h"
25 #include "disas/disas.h"
26 #include "tcg-op.h"
27 #include "exec/cpu_ldst.h"
28 #include "linux-user/syscall_defs.h"
29
30 #include "opcode_tilegx.h"
31 #include "spr_def_64.h"
32
33 #define FMT64X "%016" PRIx64
34
35 static TCGv_env cpu_env;
36 static TCGv cpu_pc;
37 static TCGv cpu_regs[TILEGX_R_COUNT];
38
39 static const char * const reg_names[64] = {
40 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
41 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
42 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
43 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
44 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
45 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
46 "r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr",
47 "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn2", "zero"
48 };
49
50 /* Modified registers are cached in temporaries until the end of the bundle. */
51 typedef struct {
52 unsigned reg;
53 TCGv val;
54 } DisasContextTemp;
55
56 #define MAX_WRITEBACK 4
57
58 /* This is the state at translation time. */
59 typedef struct {
60 uint64_t pc; /* Current pc */
61
62 TCGv zero; /* For zero register */
63
64 DisasContextTemp wb[MAX_WRITEBACK];
65 int num_wb;
66 int mmuidx;
67 bool exit_tb;
68 TileExcp atomic_excp;
69
70 struct {
71 TCGCond cond; /* branch condition */
72 TCGv dest; /* branch destination */
73 TCGv val1; /* value to be compared against zero, for cond */
74 } jmp; /* Jump object, only once in each TB block */
75 } DisasContext;
76
77 #include "exec/gen-icount.h"
78
79 /* Differentiate the various pipe encodings. */
80 #define TY_X0 0
81 #define TY_X1 1
82 #define TY_Y0 2
83 #define TY_Y1 3
84
85 /* Remerge the base opcode and extension fields for switching.
86 The X opcode fields are 3 bits; Y0/Y1 opcode fields are 4 bits;
87 Y2 opcode field is 2 bits. */
88 #define OE(OP, EXT, XY) (TY_##XY + OP * 4 + EXT * 64)
89
90 /* Similar, but for Y2 only. */
91 #define OEY2(OP, MODE) (OP + MODE * 4)
92
93 /* Similar, but make sure opcode names match up. */
94 #define OE_RR_X0(E) OE(RRR_0_OPCODE_X0, E##_UNARY_OPCODE_X0, X0)
95 #define OE_RR_X1(E) OE(RRR_0_OPCODE_X1, E##_UNARY_OPCODE_X1, X1)
96 #define OE_RR_Y0(E) OE(RRR_1_OPCODE_Y0, E##_UNARY_OPCODE_Y0, Y0)
97 #define OE_RR_Y1(E) OE(RRR_1_OPCODE_Y1, E##_UNARY_OPCODE_Y1, Y1)
98 #define OE_RRR(E,N,XY) OE(RRR_##N##_OPCODE_##XY, E##_RRR_##N##_OPCODE_##XY, XY)
99 #define OE_IM(E,XY) OE(IMM8_OPCODE_##XY, E##_IMM8_OPCODE_##XY, XY)
100 #define OE_SH(E,XY) OE(SHIFT_OPCODE_##XY, E##_SHIFT_OPCODE_##XY, XY)
101
102 #define V1_IMM(X) (((X) & 0xff) * 0x0101010101010101ull)
103 #define V2_IMM(X) (((X) & 0xffff) * 0x0001000100010001ull)
104
105
106 static void gen_exception(DisasContext *dc, TileExcp num)
107 {
108 TCGv_i32 tmp;
109
110 tcg_gen_movi_tl(cpu_pc, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
111
112 tmp = tcg_const_i32(num);
113 gen_helper_exception(cpu_env, tmp);
114 tcg_temp_free_i32(tmp);
115 dc->exit_tb = true;
116 }
117
118 static bool check_gr(DisasContext *dc, uint8_t reg)
119 {
120 if (likely(reg < TILEGX_R_COUNT)) {
121 return true;
122 }
123
124 switch (reg) {
125 case TILEGX_R_SN:
126 case TILEGX_R_ZERO:
127 break;
128 case TILEGX_R_IDN0:
129 case TILEGX_R_IDN1:
130 gen_exception(dc, TILEGX_EXCP_REG_IDN_ACCESS);
131 break;
132 case TILEGX_R_UDN0:
133 case TILEGX_R_UDN1:
134 case TILEGX_R_UDN2:
135 case TILEGX_R_UDN3:
136 gen_exception(dc, TILEGX_EXCP_REG_UDN_ACCESS);
137 break;
138 default:
139 g_assert_not_reached();
140 }
141 return false;
142 }
143
144 static TCGv load_zero(DisasContext *dc)
145 {
146 if (TCGV_IS_UNUSED_I64(dc->zero)) {
147 dc->zero = tcg_const_i64(0);
148 }
149 return dc->zero;
150 }
151
152 static TCGv load_gr(DisasContext *dc, unsigned reg)
153 {
154 if (check_gr(dc, reg)) {
155 return cpu_regs[reg];
156 }
157 return load_zero(dc);
158 }
159
160 static TCGv dest_gr(DisasContext *dc, unsigned reg)
161 {
162 int n;
163
164 /* Skip the result, mark the exception if necessary, and continue */
165 check_gr(dc, reg);
166
167 n = dc->num_wb++;
168 dc->wb[n].reg = reg;
169 return dc->wb[n].val = tcg_temp_new_i64();
170 }
171
172 static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv tsrcb,
173 void (*operate)(TCGv, TCGv, TCGv))
174 {
175 TCGv t0 = tcg_temp_new();
176
177 tcg_gen_ext32s_tl(tdest, tsrca);
178 tcg_gen_ext32s_tl(t0, tsrcb);
179 operate(tdest, tdest, t0);
180
181 tcg_gen_movi_tl(t0, 0x7fffffff);
182 tcg_gen_movcond_tl(TCG_COND_GT, tdest, tdest, t0, t0, tdest);
183 tcg_gen_movi_tl(t0, -0x80000000LL);
184 tcg_gen_movcond_tl(TCG_COND_LT, tdest, tdest, t0, t0, tdest);
185
186 tcg_temp_free(t0);
187 }
188
189 static void gen_atomic_excp(DisasContext *dc, unsigned dest, TCGv tdest,
190 TCGv tsrca, TCGv tsrcb, TileExcp excp)
191 {
192 #ifdef CONFIG_USER_ONLY
193 TCGv_i32 t;
194
195 tcg_gen_st_tl(tsrca, cpu_env, offsetof(CPUTLGState, atomic_srca));
196 tcg_gen_st_tl(tsrcb, cpu_env, offsetof(CPUTLGState, atomic_srcb));
197 t = tcg_const_i32(dest);
198 tcg_gen_st_i32(t, cpu_env, offsetof(CPUTLGState, atomic_dstr));
199 tcg_temp_free_i32(t);
200
201 /* We're going to write the real result in the exception. But in
202 the meantime we've already created a writeback register, and
203 we don't want that to remain uninitialized. */
204 tcg_gen_movi_tl(tdest, 0);
205
206 /* Note that we need to delay issuing the exception that implements
207 the atomic operation until after writing back the results of the
208 instruction occupying the X0 pipe. */
209 dc->atomic_excp = excp;
210 #else
211 gen_exception(dc, TILEGX_EXCP_OPCODE_UNIMPLEMENTED);
212 #endif
213 }
214
215 /* Shift the 128-bit value TSRCA:TSRCD right by the number of bytes
216 specified by the bottom 3 bits of TSRCB, and set TDEST to the
217 low 64 bits of the resulting value. */
218 static void gen_dblalign(TCGv tdest, TCGv tsrcd, TCGv tsrca, TCGv tsrcb)
219 {
220 TCGv t0 = tcg_temp_new();
221
222 tcg_gen_andi_tl(t0, tsrcb, 7);
223 tcg_gen_shli_tl(t0, t0, 3);
224 tcg_gen_shr_tl(tdest, tsrcd, t0);
225
226 /* We want to do "t0 = tsrca << (64 - t0)". Two's complement
227 arithmetic on a 6-bit field tells us that 64 - t0 is equal
228 to (t0 ^ 63) + 1. So we can do the shift in two parts,
229 neither of which will be an invalid shift by 64. */
230 tcg_gen_xori_tl(t0, t0, 63);
231 tcg_gen_shl_tl(t0, tsrca, t0);
232 tcg_gen_shli_tl(t0, t0, 1);
233 tcg_gen_or_tl(tdest, tdest, t0);
234
235 tcg_temp_free(t0);
236 }
237
238 /* Similarly, except that the 128-bit value is TSRCA:TSRCB, and the
239 right shift is an immediate. */
240 static void gen_dblaligni(TCGv tdest, TCGv tsrca, TCGv tsrcb, int shr)
241 {
242 TCGv t0 = tcg_temp_new();
243
244 tcg_gen_shri_tl(t0, tsrcb, shr);
245 tcg_gen_shli_tl(tdest, tsrca, 64 - shr);
246 tcg_gen_or_tl(tdest, tdest, t0);
247
248 tcg_temp_free(t0);
249 }
250
251 typedef enum {
252 LU, LS, HU, HS
253 } MulHalf;
254
255 static void gen_ext_half(TCGv d, TCGv s, MulHalf h)
256 {
257 switch (h) {
258 case LU:
259 tcg_gen_ext32u_tl(d, s);
260 break;
261 case LS:
262 tcg_gen_ext32s_tl(d, s);
263 break;
264 case HU:
265 tcg_gen_shri_tl(d, s, 32);
266 break;
267 case HS:
268 tcg_gen_sari_tl(d, s, 32);
269 break;
270 }
271 }
272
273 static void gen_mul_half(TCGv tdest, TCGv tsrca, TCGv tsrcb,
274 MulHalf ha, MulHalf hb)
275 {
276 TCGv t = tcg_temp_new();
277 gen_ext_half(t, tsrca, ha);
278 gen_ext_half(tdest, tsrcb, hb);
279 tcg_gen_mul_tl(tdest, tdest, t);
280 tcg_temp_free(t);
281 }
282
283 static void gen_cmul2(TCGv tdest, TCGv tsrca, TCGv tsrcb, int sh, int rd)
284 {
285 TCGv_i32 tsh = tcg_const_i32(sh);
286 TCGv_i32 trd = tcg_const_i32(rd);
287 gen_helper_cmul2(tdest, tsrca, tsrcb, tsh, trd);
288 tcg_temp_free_i32(tsh);
289 tcg_temp_free_i32(trd);
290 }
291
292 static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca,
293 unsigned srcb, TCGMemOp memop, const char *name)
294 {
295 if (dest) {
296 return TILEGX_EXCP_OPCODE_UNKNOWN;
297 }
298
299 tcg_gen_qemu_st_tl(load_gr(dc, srcb), load_gr(dc, srca),
300 dc->mmuidx, memop);
301
302 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", name,
303 reg_names[srca], reg_names[srcb]);
304 return TILEGX_EXCP_NONE;
305 }
306
307 static TileExcp gen_st_add_opcode(DisasContext *dc, unsigned srca, unsigned srcb,
308 int imm, TCGMemOp memop, const char *name)
309 {
310 TCGv tsrca = load_gr(dc, srca);
311 TCGv tsrcb = load_gr(dc, srcb);
312
313 tcg_gen_qemu_st_tl(tsrcb, tsrca, dc->mmuidx, memop);
314 tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
315
316 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", name,
317 reg_names[srca], reg_names[srcb], imm);
318 return TILEGX_EXCP_NONE;
319 }
320
321 /* Equality comparison with zero can be done quickly and efficiently. */
322 static void gen_v1cmpeq0(TCGv v)
323 {
324 TCGv m = tcg_const_tl(V1_IMM(0x7f));
325 TCGv c = tcg_temp_new();
326
327 /* ~(((v & m) + m) | m | v). Sets the msb for each byte == 0. */
328 tcg_gen_and_tl(c, v, m);
329 tcg_gen_add_tl(c, c, m);
330 tcg_gen_or_tl(c, c, m);
331 tcg_gen_nor_tl(c, c, v);
332 tcg_temp_free(m);
333
334 /* Shift the msb down to form the lsb boolean result. */
335 tcg_gen_shri_tl(v, c, 7);
336 tcg_temp_free(c);
337 }
338
339 static void gen_v1cmpne0(TCGv v)
340 {
341 TCGv m = tcg_const_tl(V1_IMM(0x7f));
342 TCGv c = tcg_temp_new();
343
344 /* (((v & m) + m) | v) & ~m. Sets the msb for each byte != 0. */
345 tcg_gen_and_tl(c, v, m);
346 tcg_gen_add_tl(c, c, m);
347 tcg_gen_or_tl(c, c, v);
348 tcg_gen_andc_tl(c, c, m);
349 tcg_temp_free(m);
350
351 /* Shift the msb down to form the lsb boolean result. */
352 tcg_gen_shri_tl(v, c, 7);
353 tcg_temp_free(c);
354 }
355
356 /* Vector addition can be performed via arithmetic plus masking. It is
357 efficient this way only for 4 or more elements. */
358 static void gen_v12add(TCGv tdest, TCGv tsrca, TCGv tsrcb, uint64_t sign)
359 {
360 TCGv tmask = tcg_const_tl(~sign);
361 TCGv t0 = tcg_temp_new();
362 TCGv t1 = tcg_temp_new();
363
364 /* ((a & ~sign) + (b & ~sign)) ^ ((a ^ b) & sign). */
365 tcg_gen_and_tl(t0, tsrca, tmask);
366 tcg_gen_and_tl(t1, tsrcb, tmask);
367 tcg_gen_add_tl(tdest, t0, t1);
368 tcg_gen_xor_tl(t0, tsrca, tsrcb);
369 tcg_gen_andc_tl(t0, t0, tmask);
370 tcg_gen_xor_tl(tdest, tdest, t0);
371
372 tcg_temp_free(t1);
373 tcg_temp_free(t0);
374 tcg_temp_free(tmask);
375 }
376
377 /* Similarly for vector subtraction. */
378 static void gen_v12sub(TCGv tdest, TCGv tsrca, TCGv tsrcb, uint64_t sign)
379 {
380 TCGv tsign = tcg_const_tl(sign);
381 TCGv t0 = tcg_temp_new();
382 TCGv t1 = tcg_temp_new();
383
384 /* ((a | sign) - (b & ~sign)) ^ ((a ^ ~b) & sign). */
385 tcg_gen_or_tl(t0, tsrca, tsign);
386 tcg_gen_andc_tl(t1, tsrcb, tsign);
387 tcg_gen_sub_tl(tdest, t0, t1);
388 tcg_gen_eqv_tl(t0, tsrca, tsrcb);
389 tcg_gen_and_tl(t0, t0, tsign);
390 tcg_gen_xor_tl(tdest, tdest, t0);
391
392 tcg_temp_free(t1);
393 tcg_temp_free(t0);
394 tcg_temp_free(tsign);
395 }
396
397 static void gen_v4sh(TCGv d64, TCGv a64, TCGv b64,
398 void (*generate)(TCGv_i32, TCGv_i32, TCGv_i32))
399 {
400 TCGv_i32 al = tcg_temp_new_i32();
401 TCGv_i32 ah = tcg_temp_new_i32();
402 TCGv_i32 bl = tcg_temp_new_i32();
403
404 tcg_gen_extr_i64_i32(al, ah, a64);
405 tcg_gen_extrl_i64_i32(bl, b64);
406 tcg_gen_andi_i32(bl, bl, 31);
407 generate(al, al, bl);
408 generate(ah, ah, bl);
409 tcg_gen_concat_i32_i64(d64, al, ah);
410
411 tcg_temp_free_i32(al);
412 tcg_temp_free_i32(ah);
413 tcg_temp_free_i32(bl);
414 }
415
416 static void gen_v4op(TCGv d64, TCGv a64, TCGv b64,
417 void (*generate)(TCGv_i32, TCGv_i32, TCGv_i32))
418 {
419 TCGv_i32 al = tcg_temp_new_i32();
420 TCGv_i32 ah = tcg_temp_new_i32();
421 TCGv_i32 bl = tcg_temp_new_i32();
422 TCGv_i32 bh = tcg_temp_new_i32();
423
424 tcg_gen_extr_i64_i32(al, ah, a64);
425 tcg_gen_extr_i64_i32(bl, bh, b64);
426 generate(al, al, bl);
427 generate(ah, ah, bh);
428 tcg_gen_concat_i32_i64(d64, al, ah);
429
430 tcg_temp_free_i32(al);
431 tcg_temp_free_i32(ah);
432 tcg_temp_free_i32(bl);
433 tcg_temp_free_i32(bh);
434 }
435
436 static TileExcp gen_signal(DisasContext *dc, int signo, int sigcode,
437 const char *mnemonic)
438 {
439 TCGv_i32 t0 = tcg_const_i32(signo);
440 TCGv_i32 t1 = tcg_const_i32(sigcode);
441
442 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUTLGState, signo));
443 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUTLGState, sigcode));
444
445 tcg_temp_free_i32(t1);
446 tcg_temp_free_i32(t0);
447
448 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
449 return TILEGX_EXCP_SIGNAL;
450 }
451
452 static bool parse_from_addli(uint64_t bundle, int *signo, int *sigcode)
453 {
454 int imm;
455
456 if ((get_Opcode_X0(bundle) != ADDLI_OPCODE_X0)
457 || (get_Dest_X0(bundle) != TILEGX_R_ZERO)
458 || (get_SrcA_X0(bundle) != TILEGX_R_ZERO)) {
459 return false;
460 }
461
462 imm = get_Imm16_X0(bundle);
463 *signo = imm & 0x3f;
464 *sigcode = (imm >> 6) & 0xf;
465
466 /* ??? The linux kernel validates both signo and the sigcode vs the
467 known max for each signal. Don't bother here. */
468 return true;
469 }
470
471 static TileExcp gen_specill(DisasContext *dc, unsigned dest, unsigned srca,
472 uint64_t bundle)
473 {
474 const char *mnemonic;
475 int signo;
476 int sigcode;
477
478 if (dest == 0x1c && srca == 0x25) {
479 signo = TARGET_SIGTRAP;
480 sigcode = TARGET_TRAP_BRKPT;
481 mnemonic = "bpt";
482 } else if (dest == 0x1d && srca == 0x25
483 && parse_from_addli(bundle, &signo, &sigcode)) {
484 mnemonic = "raise";
485 } else {
486 signo = TARGET_SIGILL;
487 sigcode = TARGET_ILL_ILLOPC;
488 mnemonic = "ill";
489 }
490
491 return gen_signal(dc, signo, sigcode, mnemonic);
492 }
493
494 static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
495 unsigned dest, unsigned srca, uint64_t bundle)
496 {
497 TCGv tdest, tsrca;
498 const char *mnemonic;
499 TCGMemOp memop;
500 TileExcp ret = TILEGX_EXCP_NONE;
501 bool prefetch_nofault = false;
502
503 /* Eliminate instructions with no output before doing anything else. */
504 switch (opext) {
505 case OE_RR_Y0(NOP):
506 case OE_RR_Y1(NOP):
507 case OE_RR_X0(NOP):
508 case OE_RR_X1(NOP):
509 mnemonic = "nop";
510 goto done0;
511 case OE_RR_Y0(FNOP):
512 case OE_RR_Y1(FNOP):
513 case OE_RR_X0(FNOP):
514 case OE_RR_X1(FNOP):
515 mnemonic = "fnop";
516 goto done0;
517 case OE_RR_X1(DRAIN):
518 mnemonic = "drain";
519 goto done0;
520 case OE_RR_X1(FLUSHWB):
521 mnemonic = "flushwb";
522 goto done0;
523 case OE_RR_X1(ILL):
524 return gen_specill(dc, dest, srca, bundle);
525 case OE_RR_Y1(ILL):
526 return gen_signal(dc, TARGET_SIGILL, TARGET_ILL_ILLOPC, "ill");
527 case OE_RR_X1(MF):
528 mnemonic = "mf";
529 goto done0;
530 case OE_RR_X1(NAP):
531 /* ??? This should yield, especially in system mode. */
532 mnemonic = "nap";
533 goto done0;
534 case OE_RR_X1(IRET):
535 gen_helper_ext01_ics(cpu_env);
536 dc->jmp.cond = TCG_COND_ALWAYS;
537 dc->jmp.dest = tcg_temp_new();
538 tcg_gen_ld_tl(dc->jmp.dest, cpu_env,
539 offsetof(CPUTLGState, spregs[TILEGX_SPR_EX_CONTEXT_0_0]));
540 tcg_gen_andi_tl(dc->jmp.dest, dc->jmp.dest, ~7);
541 mnemonic = "iret";
542 goto done0;
543 case OE_RR_X1(SWINT0):
544 case OE_RR_X1(SWINT2):
545 case OE_RR_X1(SWINT3):
546 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
547 case OE_RR_X1(SWINT1):
548 ret = TILEGX_EXCP_SYSCALL;
549 mnemonic = "swint1";
550 done0:
551 if (srca || dest) {
552 return TILEGX_EXCP_OPCODE_UNKNOWN;
553 }
554 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
555 return ret;
556
557 case OE_RR_X1(DTLBPR):
558 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
559 case OE_RR_X1(FINV):
560 mnemonic = "finv";
561 goto done1;
562 case OE_RR_X1(FLUSH):
563 mnemonic = "flush";
564 goto done1;
565 case OE_RR_X1(ICOH):
566 mnemonic = "icoh";
567 goto done1;
568 case OE_RR_X1(INV):
569 mnemonic = "inv";
570 goto done1;
571 case OE_RR_X1(WH64):
572 mnemonic = "wh64";
573 goto done1;
574 case OE_RR_X1(JRP):
575 case OE_RR_Y1(JRP):
576 mnemonic = "jrp";
577 goto do_jr;
578 case OE_RR_X1(JR):
579 case OE_RR_Y1(JR):
580 mnemonic = "jr";
581 goto do_jr;
582 case OE_RR_X1(JALRP):
583 case OE_RR_Y1(JALRP):
584 mnemonic = "jalrp";
585 goto do_jalr;
586 case OE_RR_X1(JALR):
587 case OE_RR_Y1(JALR):
588 mnemonic = "jalr";
589 do_jalr:
590 tcg_gen_movi_tl(dest_gr(dc, TILEGX_R_LR),
591 dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
592 do_jr:
593 dc->jmp.cond = TCG_COND_ALWAYS;
594 dc->jmp.dest = tcg_temp_new();
595 tcg_gen_andi_tl(dc->jmp.dest, load_gr(dc, srca), ~7);
596 done1:
597 if (dest) {
598 return TILEGX_EXCP_OPCODE_UNKNOWN;
599 }
600 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s", mnemonic, reg_names[srca]);
601 return ret;
602 }
603
604 tdest = dest_gr(dc, dest);
605 tsrca = load_gr(dc, srca);
606
607 switch (opext) {
608 case OE_RR_X0(CNTLZ):
609 case OE_RR_Y0(CNTLZ):
610 gen_helper_cntlz(tdest, tsrca);
611 mnemonic = "cntlz";
612 break;
613 case OE_RR_X0(CNTTZ):
614 case OE_RR_Y0(CNTTZ):
615 gen_helper_cnttz(tdest, tsrca);
616 mnemonic = "cnttz";
617 break;
618 case OE_RR_X0(FSINGLE_PACK1):
619 case OE_RR_Y0(FSINGLE_PACK1):
620 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
621 case OE_RR_X1(LD1S):
622 memop = MO_SB;
623 mnemonic = "ld1s"; /* prefetch_l1_fault */
624 goto do_load;
625 case OE_RR_X1(LD1U):
626 memop = MO_UB;
627 mnemonic = "ld1u"; /* prefetch, prefetch_l1 */
628 prefetch_nofault = (dest == TILEGX_R_ZERO);
629 goto do_load;
630 case OE_RR_X1(LD2S):
631 memop = MO_TESW;
632 mnemonic = "ld2s"; /* prefetch_l2_fault */
633 goto do_load;
634 case OE_RR_X1(LD2U):
635 memop = MO_TEUW;
636 mnemonic = "ld2u"; /* prefetch_l2 */
637 prefetch_nofault = (dest == TILEGX_R_ZERO);
638 goto do_load;
639 case OE_RR_X1(LD4S):
640 memop = MO_TESL;
641 mnemonic = "ld4s"; /* prefetch_l3_fault */
642 goto do_load;
643 case OE_RR_X1(LD4U):
644 memop = MO_TEUL;
645 mnemonic = "ld4u"; /* prefetch_l3 */
646 prefetch_nofault = (dest == TILEGX_R_ZERO);
647 goto do_load;
648 case OE_RR_X1(LDNT1S):
649 memop = MO_SB;
650 mnemonic = "ldnt1s";
651 goto do_load;
652 case OE_RR_X1(LDNT1U):
653 memop = MO_UB;
654 mnemonic = "ldnt1u";
655 goto do_load;
656 case OE_RR_X1(LDNT2S):
657 memop = MO_TESW;
658 mnemonic = "ldnt2s";
659 goto do_load;
660 case OE_RR_X1(LDNT2U):
661 memop = MO_TEUW;
662 mnemonic = "ldnt2u";
663 goto do_load;
664 case OE_RR_X1(LDNT4S):
665 memop = MO_TESL;
666 mnemonic = "ldnt4s";
667 goto do_load;
668 case OE_RR_X1(LDNT4U):
669 memop = MO_TEUL;
670 mnemonic = "ldnt4u";
671 goto do_load;
672 case OE_RR_X1(LDNT):
673 memop = MO_TEQ;
674 mnemonic = "ldnt";
675 goto do_load;
676 case OE_RR_X1(LD):
677 memop = MO_TEQ;
678 mnemonic = "ld";
679 do_load:
680 if (!prefetch_nofault) {
681 tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
682 }
683 break;
684 case OE_RR_X1(LDNA):
685 tcg_gen_andi_tl(tdest, tsrca, ~7);
686 tcg_gen_qemu_ld_tl(tdest, tdest, dc->mmuidx, MO_TEQ);
687 mnemonic = "ldna";
688 break;
689 case OE_RR_X1(LNK):
690 case OE_RR_Y1(LNK):
691 if (srca) {
692 return TILEGX_EXCP_OPCODE_UNKNOWN;
693 }
694 tcg_gen_movi_tl(tdest, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
695 mnemonic = "lnk";
696 break;
697 case OE_RR_X0(PCNT):
698 case OE_RR_Y0(PCNT):
699 gen_helper_pcnt(tdest, tsrca);
700 mnemonic = "pcnt";
701 break;
702 case OE_RR_X0(REVBITS):
703 case OE_RR_Y0(REVBITS):
704 gen_helper_revbits(tdest, tsrca);
705 mnemonic = "revbits";
706 break;
707 case OE_RR_X0(REVBYTES):
708 case OE_RR_Y0(REVBYTES):
709 tcg_gen_bswap64_tl(tdest, tsrca);
710 mnemonic = "revbytes";
711 break;
712 case OE_RR_X0(TBLIDXB0):
713 case OE_RR_Y0(TBLIDXB0):
714 tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tsrca, 2, 8);
715 mnemonic = "tblidxb0";
716 break;
717 case OE_RR_X0(TBLIDXB1):
718 case OE_RR_Y0(TBLIDXB1):
719 tcg_gen_shri_tl(tdest, tsrca, 8);
720 tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tdest, 2, 8);
721 mnemonic = "tblidxb1";
722 break;
723 case OE_RR_X0(TBLIDXB2):
724 case OE_RR_Y0(TBLIDXB2):
725 tcg_gen_shri_tl(tdest, tsrca, 16);
726 tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tdest, 2, 8);
727 mnemonic = "tblidxb2";
728 break;
729 case OE_RR_X0(TBLIDXB3):
730 case OE_RR_Y0(TBLIDXB3):
731 tcg_gen_shri_tl(tdest, tsrca, 24);
732 tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tdest, 2, 8);
733 mnemonic = "tblidxb3";
734 break;
735 default:
736 return TILEGX_EXCP_OPCODE_UNKNOWN;
737 }
738
739 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
740 reg_names[dest], reg_names[srca]);
741 return ret;
742 }
743
744 static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
745 unsigned dest, unsigned srca, unsigned srcb)
746 {
747 TCGv tdest = dest_gr(dc, dest);
748 TCGv tsrca = load_gr(dc, srca);
749 TCGv tsrcb = load_gr(dc, srcb);
750 TCGv t0;
751 const char *mnemonic;
752
753 switch (opext) {
754 case OE_RRR(ADDXSC, 0, X0):
755 case OE_RRR(ADDXSC, 0, X1):
756 gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_add_tl);
757 mnemonic = "addxsc";
758 break;
759 case OE_RRR(ADDX, 0, X0):
760 case OE_RRR(ADDX, 0, X1):
761 case OE_RRR(ADDX, 0, Y0):
762 case OE_RRR(ADDX, 0, Y1):
763 tcg_gen_add_tl(tdest, tsrca, tsrcb);
764 tcg_gen_ext32s_tl(tdest, tdest);
765 mnemonic = "addx";
766 break;
767 case OE_RRR(ADD, 0, X0):
768 case OE_RRR(ADD, 0, X1):
769 case OE_RRR(ADD, 0, Y0):
770 case OE_RRR(ADD, 0, Y1):
771 tcg_gen_add_tl(tdest, tsrca, tsrcb);
772 mnemonic = "add";
773 break;
774 case OE_RRR(AND, 0, X0):
775 case OE_RRR(AND, 0, X1):
776 case OE_RRR(AND, 5, Y0):
777 case OE_RRR(AND, 5, Y1):
778 tcg_gen_and_tl(tdest, tsrca, tsrcb);
779 mnemonic = "and";
780 break;
781 case OE_RRR(CMOVEQZ, 0, X0):
782 case OE_RRR(CMOVEQZ, 4, Y0):
783 tcg_gen_movcond_tl(TCG_COND_EQ, tdest, tsrca, load_zero(dc),
784 tsrcb, load_gr(dc, dest));
785 mnemonic = "cmoveqz";
786 break;
787 case OE_RRR(CMOVNEZ, 0, X0):
788 case OE_RRR(CMOVNEZ, 4, Y0):
789 tcg_gen_movcond_tl(TCG_COND_NE, tdest, tsrca, load_zero(dc),
790 tsrcb, load_gr(dc, dest));
791 mnemonic = "cmovnez";
792 break;
793 case OE_RRR(CMPEQ, 0, X0):
794 case OE_RRR(CMPEQ, 0, X1):
795 case OE_RRR(CMPEQ, 3, Y0):
796 case OE_RRR(CMPEQ, 3, Y1):
797 tcg_gen_setcond_tl(TCG_COND_EQ, tdest, tsrca, tsrcb);
798 mnemonic = "cmpeq";
799 break;
800 case OE_RRR(CMPEXCH4, 0, X1):
801 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
802 TILEGX_EXCP_OPCODE_CMPEXCH4);
803 mnemonic = "cmpexch4";
804 break;
805 case OE_RRR(CMPEXCH, 0, X1):
806 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
807 TILEGX_EXCP_OPCODE_CMPEXCH);
808 mnemonic = "cmpexch";
809 break;
810 case OE_RRR(CMPLES, 0, X0):
811 case OE_RRR(CMPLES, 0, X1):
812 case OE_RRR(CMPLES, 2, Y0):
813 case OE_RRR(CMPLES, 2, Y1):
814 tcg_gen_setcond_tl(TCG_COND_LE, tdest, tsrca, tsrcb);
815 mnemonic = "cmples";
816 break;
817 case OE_RRR(CMPLEU, 0, X0):
818 case OE_RRR(CMPLEU, 0, X1):
819 case OE_RRR(CMPLEU, 2, Y0):
820 case OE_RRR(CMPLEU, 2, Y1):
821 tcg_gen_setcond_tl(TCG_COND_LEU, tdest, tsrca, tsrcb);
822 mnemonic = "cmpleu";
823 break;
824 case OE_RRR(CMPLTS, 0, X0):
825 case OE_RRR(CMPLTS, 0, X1):
826 case OE_RRR(CMPLTS, 2, Y0):
827 case OE_RRR(CMPLTS, 2, Y1):
828 tcg_gen_setcond_tl(TCG_COND_LT, tdest, tsrca, tsrcb);
829 mnemonic = "cmplts";
830 break;
831 case OE_RRR(CMPLTU, 0, X0):
832 case OE_RRR(CMPLTU, 0, X1):
833 case OE_RRR(CMPLTU, 2, Y0):
834 case OE_RRR(CMPLTU, 2, Y1):
835 tcg_gen_setcond_tl(TCG_COND_LTU, tdest, tsrca, tsrcb);
836 mnemonic = "cmpltu";
837 break;
838 case OE_RRR(CMPNE, 0, X0):
839 case OE_RRR(CMPNE, 0, X1):
840 case OE_RRR(CMPNE, 3, Y0):
841 case OE_RRR(CMPNE, 3, Y1):
842 tcg_gen_setcond_tl(TCG_COND_NE, tdest, tsrca, tsrcb);
843 mnemonic = "cmpne";
844 break;
845 case OE_RRR(CMULAF, 0, X0):
846 gen_helper_cmulaf(tdest, load_gr(dc, dest), tsrca, tsrcb);
847 mnemonic = "cmulaf";
848 break;
849 case OE_RRR(CMULA, 0, X0):
850 gen_helper_cmula(tdest, load_gr(dc, dest), tsrca, tsrcb);
851 mnemonic = "cmula";
852 break;
853 case OE_RRR(CMULFR, 0, X0):
854 gen_cmul2(tdest, tsrca, tsrcb, 15, 1 << 14);
855 mnemonic = "cmulfr";
856 break;
857 case OE_RRR(CMULF, 0, X0):
858 gen_cmul2(tdest, tsrca, tsrcb, 15, 0);
859 mnemonic = "cmulf";
860 break;
861 case OE_RRR(CMULHR, 0, X0):
862 gen_cmul2(tdest, tsrca, tsrcb, 16, 1 << 15);
863 mnemonic = "cmulhr";
864 break;
865 case OE_RRR(CMULH, 0, X0):
866 gen_cmul2(tdest, tsrca, tsrcb, 16, 0);
867 mnemonic = "cmulh";
868 break;
869 case OE_RRR(CMUL, 0, X0):
870 gen_helper_cmula(tdest, load_zero(dc), tsrca, tsrcb);
871 mnemonic = "cmul";
872 break;
873 case OE_RRR(CRC32_32, 0, X0):
874 gen_helper_crc32_32(tdest, tsrca, tsrcb);
875 mnemonic = "crc32_32";
876 break;
877 case OE_RRR(CRC32_8, 0, X0):
878 gen_helper_crc32_8(tdest, tsrca, tsrcb);
879 mnemonic = "crc32_8";
880 break;
881 case OE_RRR(DBLALIGN2, 0, X0):
882 case OE_RRR(DBLALIGN2, 0, X1):
883 gen_dblaligni(tdest, tsrca, tsrcb, 16);
884 mnemonic = "dblalign2";
885 break;
886 case OE_RRR(DBLALIGN4, 0, X0):
887 case OE_RRR(DBLALIGN4, 0, X1):
888 gen_dblaligni(tdest, tsrca, tsrcb, 32);
889 mnemonic = "dblalign4";
890 break;
891 case OE_RRR(DBLALIGN6, 0, X0):
892 case OE_RRR(DBLALIGN6, 0, X1):
893 gen_dblaligni(tdest, tsrca, tsrcb, 48);
894 mnemonic = "dblalign6";
895 break;
896 case OE_RRR(DBLALIGN, 0, X0):
897 gen_dblalign(tdest, load_gr(dc, dest), tsrca, tsrcb);
898 mnemonic = "dblalign";
899 break;
900 case OE_RRR(EXCH4, 0, X1):
901 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
902 TILEGX_EXCP_OPCODE_EXCH4);
903 mnemonic = "exch4";
904 break;
905 case OE_RRR(EXCH, 0, X1):
906 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
907 TILEGX_EXCP_OPCODE_EXCH);
908 mnemonic = "exch";
909 break;
910 case OE_RRR(FDOUBLE_ADDSUB, 0, X0):
911 case OE_RRR(FDOUBLE_ADD_FLAGS, 0, X0):
912 case OE_RRR(FDOUBLE_MUL_FLAGS, 0, X0):
913 case OE_RRR(FDOUBLE_PACK1, 0, X0):
914 case OE_RRR(FDOUBLE_PACK2, 0, X0):
915 case OE_RRR(FDOUBLE_SUB_FLAGS, 0, X0):
916 case OE_RRR(FDOUBLE_UNPACK_MAX, 0, X0):
917 case OE_RRR(FDOUBLE_UNPACK_MIN, 0, X0):
918 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
919 case OE_RRR(FETCHADD4, 0, X1):
920 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
921 TILEGX_EXCP_OPCODE_FETCHADD4);
922 mnemonic = "fetchadd4";
923 break;
924 case OE_RRR(FETCHADDGEZ4, 0, X1):
925 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
926 TILEGX_EXCP_OPCODE_FETCHADDGEZ4);
927 mnemonic = "fetchaddgez4";
928 break;
929 case OE_RRR(FETCHADDGEZ, 0, X1):
930 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
931 TILEGX_EXCP_OPCODE_FETCHADDGEZ);
932 mnemonic = "fetchaddgez";
933 break;
934 case OE_RRR(FETCHADD, 0, X1):
935 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
936 TILEGX_EXCP_OPCODE_FETCHADD);
937 mnemonic = "fetchadd";
938 break;
939 case OE_RRR(FETCHAND4, 0, X1):
940 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
941 TILEGX_EXCP_OPCODE_FETCHAND4);
942 mnemonic = "fetchand4";
943 break;
944 case OE_RRR(FETCHAND, 0, X1):
945 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
946 TILEGX_EXCP_OPCODE_FETCHAND);
947 mnemonic = "fetchand";
948 break;
949 case OE_RRR(FETCHOR4, 0, X1):
950 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
951 TILEGX_EXCP_OPCODE_FETCHOR4);
952 mnemonic = "fetchor4";
953 break;
954 case OE_RRR(FETCHOR, 0, X1):
955 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
956 TILEGX_EXCP_OPCODE_FETCHOR);
957 mnemonic = "fetchor";
958 break;
959 case OE_RRR(FSINGLE_ADD1, 0, X0):
960 case OE_RRR(FSINGLE_ADDSUB2, 0, X0):
961 case OE_RRR(FSINGLE_MUL1, 0, X0):
962 case OE_RRR(FSINGLE_MUL2, 0, X0):
963 case OE_RRR(FSINGLE_PACK2, 0, X0):
964 case OE_RRR(FSINGLE_SUB1, 0, X0):
965 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
966 case OE_RRR(MNZ, 0, X0):
967 case OE_RRR(MNZ, 0, X1):
968 case OE_RRR(MNZ, 4, Y0):
969 case OE_RRR(MNZ, 4, Y1):
970 t0 = load_zero(dc);
971 tcg_gen_movcond_tl(TCG_COND_NE, tdest, tsrca, t0, tsrcb, t0);
972 mnemonic = "mnz";
973 break;
974 case OE_RRR(MULAX, 0, X0):
975 case OE_RRR(MULAX, 3, Y0):
976 tcg_gen_mul_tl(tdest, tsrca, tsrcb);
977 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
978 tcg_gen_ext32s_tl(tdest, tdest);
979 mnemonic = "mulax";
980 break;
981 case OE_RRR(MULA_HS_HS, 0, X0):
982 case OE_RRR(MULA_HS_HS, 9, Y0):
983 gen_mul_half(tdest, tsrca, tsrcb, HS, HS);
984 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
985 mnemonic = "mula_hs_hs";
986 break;
987 case OE_RRR(MULA_HS_HU, 0, X0):
988 gen_mul_half(tdest, tsrca, tsrcb, HS, HU);
989 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
990 mnemonic = "mula_hs_hu";
991 break;
992 case OE_RRR(MULA_HS_LS, 0, X0):
993 gen_mul_half(tdest, tsrca, tsrcb, HS, LS);
994 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
995 mnemonic = "mula_hs_ls";
996 break;
997 case OE_RRR(MULA_HS_LU, 0, X0):
998 gen_mul_half(tdest, tsrca, tsrcb, HS, LU);
999 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
1000 mnemonic = "mula_hs_lu";
1001 break;
1002 case OE_RRR(MULA_HU_HU, 0, X0):
1003 case OE_RRR(MULA_HU_HU, 9, Y0):
1004 gen_mul_half(tdest, tsrca, tsrcb, HU, HU);
1005 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
1006 mnemonic = "mula_hu_hu";
1007 break;
1008 case OE_RRR(MULA_HU_LS, 0, X0):
1009 gen_mul_half(tdest, tsrca, tsrcb, HU, LS);
1010 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
1011 mnemonic = "mula_hu_ls";
1012 break;
1013 case OE_RRR(MULA_HU_LU, 0, X0):
1014 gen_mul_half(tdest, tsrca, tsrcb, HU, LU);
1015 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
1016 mnemonic = "mula_hu_lu";
1017 break;
1018 case OE_RRR(MULA_LS_LS, 0, X0):
1019 case OE_RRR(MULA_LS_LS, 9, Y0):
1020 gen_mul_half(tdest, tsrca, tsrcb, LS, LS);
1021 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
1022 mnemonic = "mula_ls_ls";
1023 break;
1024 case OE_RRR(MULA_LS_LU, 0, X0):
1025 gen_mul_half(tdest, tsrca, tsrcb, LS, LU);
1026 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
1027 mnemonic = "mula_ls_lu";
1028 break;
1029 case OE_RRR(MULA_LU_LU, 0, X0):
1030 case OE_RRR(MULA_LU_LU, 9, Y0):
1031 gen_mul_half(tdest, tsrca, tsrcb, LU, LU);
1032 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
1033 mnemonic = "mula_lu_lu";
1034 break;
1035 case OE_RRR(MULX, 0, X0):
1036 case OE_RRR(MULX, 3, Y0):
1037 tcg_gen_mul_tl(tdest, tsrca, tsrcb);
1038 tcg_gen_ext32s_tl(tdest, tdest);
1039 mnemonic = "mulx";
1040 break;
1041 case OE_RRR(MUL_HS_HS, 0, X0):
1042 case OE_RRR(MUL_HS_HS, 8, Y0):
1043 gen_mul_half(tdest, tsrca, tsrcb, HS, HS);
1044 mnemonic = "mul_hs_hs";
1045 break;
1046 case OE_RRR(MUL_HS_HU, 0, X0):
1047 gen_mul_half(tdest, tsrca, tsrcb, HS, HU);
1048 mnemonic = "mul_hs_hu";
1049 break;
1050 case OE_RRR(MUL_HS_LS, 0, X0):
1051 gen_mul_half(tdest, tsrca, tsrcb, HS, LS);
1052 mnemonic = "mul_hs_ls";
1053 break;
1054 case OE_RRR(MUL_HS_LU, 0, X0):
1055 gen_mul_half(tdest, tsrca, tsrcb, HS, LU);
1056 mnemonic = "mul_hs_lu";
1057 break;
1058 case OE_RRR(MUL_HU_HU, 0, X0):
1059 case OE_RRR(MUL_HU_HU, 8, Y0):
1060 gen_mul_half(tdest, tsrca, tsrcb, HU, HU);
1061 mnemonic = "mul_hu_hu";
1062 break;
1063 case OE_RRR(MUL_HU_LS, 0, X0):
1064 gen_mul_half(tdest, tsrca, tsrcb, HU, LS);
1065 mnemonic = "mul_hu_ls";
1066 break;
1067 case OE_RRR(MUL_HU_LU, 0, X0):
1068 gen_mul_half(tdest, tsrca, tsrcb, HU, LU);
1069 mnemonic = "mul_hu_lu";
1070 break;
1071 case OE_RRR(MUL_LS_LS, 0, X0):
1072 case OE_RRR(MUL_LS_LS, 8, Y0):
1073 gen_mul_half(tdest, tsrca, tsrcb, LS, LS);
1074 mnemonic = "mul_ls_ls";
1075 break;
1076 case OE_RRR(MUL_LS_LU, 0, X0):
1077 gen_mul_half(tdest, tsrca, tsrcb, LS, LU);
1078 mnemonic = "mul_ls_lu";
1079 break;
1080 case OE_RRR(MUL_LU_LU, 0, X0):
1081 case OE_RRR(MUL_LU_LU, 8, Y0):
1082 gen_mul_half(tdest, tsrca, tsrcb, LU, LU);
1083 mnemonic = "mul_lu_lu";
1084 break;
1085 case OE_RRR(MZ, 0, X0):
1086 case OE_RRR(MZ, 0, X1):
1087 case OE_RRR(MZ, 4, Y0):
1088 case OE_RRR(MZ, 4, Y1):
1089 t0 = load_zero(dc);
1090 tcg_gen_movcond_tl(TCG_COND_EQ, tdest, tsrca, t0, tsrcb, t0);
1091 mnemonic = "mz";
1092 break;
1093 case OE_RRR(NOR, 0, X0):
1094 case OE_RRR(NOR, 0, X1):
1095 case OE_RRR(NOR, 5, Y0):
1096 case OE_RRR(NOR, 5, Y1):
1097 tcg_gen_nor_tl(tdest, tsrca, tsrcb);
1098 mnemonic = "nor";
1099 break;
1100 case OE_RRR(OR, 0, X0):
1101 case OE_RRR(OR, 0, X1):
1102 case OE_RRR(OR, 5, Y0):
1103 case OE_RRR(OR, 5, Y1):
1104 tcg_gen_or_tl(tdest, tsrca, tsrcb);
1105 mnemonic = "or";
1106 break;
1107 case OE_RRR(ROTL, 0, X0):
1108 case OE_RRR(ROTL, 0, X1):
1109 case OE_RRR(ROTL, 6, Y0):
1110 case OE_RRR(ROTL, 6, Y1):
1111 tcg_gen_andi_tl(tdest, tsrcb, 63);
1112 tcg_gen_rotl_tl(tdest, tsrca, tdest);
1113 mnemonic = "rotl";
1114 break;
1115 case OE_RRR(SHL1ADDX, 0, X0):
1116 case OE_RRR(SHL1ADDX, 0, X1):
1117 case OE_RRR(SHL1ADDX, 7, Y0):
1118 case OE_RRR(SHL1ADDX, 7, Y1):
1119 tcg_gen_shli_tl(tdest, tsrca, 1);
1120 tcg_gen_add_tl(tdest, tdest, tsrcb);
1121 tcg_gen_ext32s_tl(tdest, tdest);
1122 mnemonic = "shl1addx";
1123 break;
1124 case OE_RRR(SHL1ADD, 0, X0):
1125 case OE_RRR(SHL1ADD, 0, X1):
1126 case OE_RRR(SHL1ADD, 1, Y0):
1127 case OE_RRR(SHL1ADD, 1, Y1):
1128 tcg_gen_shli_tl(tdest, tsrca, 1);
1129 tcg_gen_add_tl(tdest, tdest, tsrcb);
1130 mnemonic = "shl1add";
1131 break;
1132 case OE_RRR(SHL2ADDX, 0, X0):
1133 case OE_RRR(SHL2ADDX, 0, X1):
1134 case OE_RRR(SHL2ADDX, 7, Y0):
1135 case OE_RRR(SHL2ADDX, 7, Y1):
1136 tcg_gen_shli_tl(tdest, tsrca, 2);
1137 tcg_gen_add_tl(tdest, tdest, tsrcb);
1138 tcg_gen_ext32s_tl(tdest, tdest);
1139 mnemonic = "shl2addx";
1140 break;
1141 case OE_RRR(SHL2ADD, 0, X0):
1142 case OE_RRR(SHL2ADD, 0, X1):
1143 case OE_RRR(SHL2ADD, 1, Y0):
1144 case OE_RRR(SHL2ADD, 1, Y1):
1145 tcg_gen_shli_tl(tdest, tsrca, 2);
1146 tcg_gen_add_tl(tdest, tdest, tsrcb);
1147 mnemonic = "shl2add";
1148 break;
1149 case OE_RRR(SHL3ADDX, 0, X0):
1150 case OE_RRR(SHL3ADDX, 0, X1):
1151 case OE_RRR(SHL3ADDX, 7, Y0):
1152 case OE_RRR(SHL3ADDX, 7, Y1):
1153 tcg_gen_shli_tl(tdest, tsrca, 3);
1154 tcg_gen_add_tl(tdest, tdest, tsrcb);
1155 tcg_gen_ext32s_tl(tdest, tdest);
1156 mnemonic = "shl3addx";
1157 break;
1158 case OE_RRR(SHL3ADD, 0, X0):
1159 case OE_RRR(SHL3ADD, 0, X1):
1160 case OE_RRR(SHL3ADD, 1, Y0):
1161 case OE_RRR(SHL3ADD, 1, Y1):
1162 tcg_gen_shli_tl(tdest, tsrca, 3);
1163 tcg_gen_add_tl(tdest, tdest, tsrcb);
1164 mnemonic = "shl3add";
1165 break;
1166 case OE_RRR(SHLX, 0, X0):
1167 case OE_RRR(SHLX, 0, X1):
1168 tcg_gen_andi_tl(tdest, tsrcb, 31);
1169 tcg_gen_shl_tl(tdest, tsrca, tdest);
1170 tcg_gen_ext32s_tl(tdest, tdest);
1171 mnemonic = "shlx";
1172 break;
1173 case OE_RRR(SHL, 0, X0):
1174 case OE_RRR(SHL, 0, X1):
1175 case OE_RRR(SHL, 6, Y0):
1176 case OE_RRR(SHL, 6, Y1):
1177 tcg_gen_andi_tl(tdest, tsrcb, 63);
1178 tcg_gen_shl_tl(tdest, tsrca, tdest);
1179 mnemonic = "shl";
1180 break;
1181 case OE_RRR(SHRS, 0, X0):
1182 case OE_RRR(SHRS, 0, X1):
1183 case OE_RRR(SHRS, 6, Y0):
1184 case OE_RRR(SHRS, 6, Y1):
1185 tcg_gen_andi_tl(tdest, tsrcb, 63);
1186 tcg_gen_sar_tl(tdest, tsrca, tdest);
1187 mnemonic = "shrs";
1188 break;
1189 case OE_RRR(SHRUX, 0, X0):
1190 case OE_RRR(SHRUX, 0, X1):
1191 t0 = tcg_temp_new();
1192 tcg_gen_andi_tl(t0, tsrcb, 31);
1193 tcg_gen_ext32u_tl(tdest, tsrca);
1194 tcg_gen_shr_tl(tdest, tdest, t0);
1195 tcg_gen_ext32s_tl(tdest, tdest);
1196 tcg_temp_free(t0);
1197 mnemonic = "shrux";
1198 break;
1199 case OE_RRR(SHRU, 0, X0):
1200 case OE_RRR(SHRU, 0, X1):
1201 case OE_RRR(SHRU, 6, Y0):
1202 case OE_RRR(SHRU, 6, Y1):
1203 tcg_gen_andi_tl(tdest, tsrcb, 63);
1204 tcg_gen_shr_tl(tdest, tsrca, tdest);
1205 mnemonic = "shru";
1206 break;
1207 case OE_RRR(SHUFFLEBYTES, 0, X0):
1208 gen_helper_shufflebytes(tdest, load_gr(dc, dest), tsrca, tsrca);
1209 mnemonic = "shufflebytes";
1210 break;
1211 case OE_RRR(SUBXSC, 0, X0):
1212 case OE_RRR(SUBXSC, 0, X1):
1213 gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_sub_tl);
1214 mnemonic = "subxsc";
1215 break;
1216 case OE_RRR(SUBX, 0, X0):
1217 case OE_RRR(SUBX, 0, X1):
1218 case OE_RRR(SUBX, 0, Y0):
1219 case OE_RRR(SUBX, 0, Y1):
1220 tcg_gen_sub_tl(tdest, tsrca, tsrcb);
1221 tcg_gen_ext32s_tl(tdest, tdest);
1222 mnemonic = "subx";
1223 break;
1224 case OE_RRR(SUB, 0, X0):
1225 case OE_RRR(SUB, 0, X1):
1226 case OE_RRR(SUB, 0, Y0):
1227 case OE_RRR(SUB, 0, Y1):
1228 tcg_gen_sub_tl(tdest, tsrca, tsrcb);
1229 mnemonic = "sub";
1230 break;
1231 case OE_RRR(V1ADDUC, 0, X0):
1232 case OE_RRR(V1ADDUC, 0, X1):
1233 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1234 case OE_RRR(V1ADD, 0, X0):
1235 case OE_RRR(V1ADD, 0, X1):
1236 gen_v12add(tdest, tsrca, tsrcb, V1_IMM(0x80));
1237 mnemonic = "v1add";
1238 break;
1239 case OE_RRR(V1ADIFFU, 0, X0):
1240 case OE_RRR(V1AVGU, 0, X0):
1241 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1242 case OE_RRR(V1CMPEQ, 0, X0):
1243 case OE_RRR(V1CMPEQ, 0, X1):
1244 tcg_gen_xor_tl(tdest, tsrca, tsrcb);
1245 gen_v1cmpeq0(tdest);
1246 mnemonic = "v1cmpeq";
1247 break;
1248 case OE_RRR(V1CMPLES, 0, X0):
1249 case OE_RRR(V1CMPLES, 0, X1):
1250 case OE_RRR(V1CMPLEU, 0, X0):
1251 case OE_RRR(V1CMPLEU, 0, X1):
1252 case OE_RRR(V1CMPLTS, 0, X0):
1253 case OE_RRR(V1CMPLTS, 0, X1):
1254 case OE_RRR(V1CMPLTU, 0, X0):
1255 case OE_RRR(V1CMPLTU, 0, X1):
1256 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1257 case OE_RRR(V1CMPNE, 0, X0):
1258 case OE_RRR(V1CMPNE, 0, X1):
1259 tcg_gen_xor_tl(tdest, tsrca, tsrcb);
1260 gen_v1cmpne0(tdest);
1261 mnemonic = "v1cmpne";
1262 break;
1263 case OE_RRR(V1DDOTPUA, 0, X0):
1264 case OE_RRR(V1DDOTPUSA, 0, X0):
1265 case OE_RRR(V1DDOTPUS, 0, X0):
1266 case OE_RRR(V1DDOTPU, 0, X0):
1267 case OE_RRR(V1DOTPA, 0, X0):
1268 case OE_RRR(V1DOTPUA, 0, X0):
1269 case OE_RRR(V1DOTPUSA, 0, X0):
1270 case OE_RRR(V1DOTPUS, 0, X0):
1271 case OE_RRR(V1DOTPU, 0, X0):
1272 case OE_RRR(V1DOTP, 0, X0):
1273 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1274 case OE_RRR(V1INT_H, 0, X0):
1275 case OE_RRR(V1INT_H, 0, X1):
1276 gen_helper_v1int_h(tdest, tsrca, tsrcb);
1277 mnemonic = "v1int_h";
1278 break;
1279 case OE_RRR(V1INT_L, 0, X0):
1280 case OE_RRR(V1INT_L, 0, X1):
1281 gen_helper_v1int_l(tdest, tsrca, tsrcb);
1282 mnemonic = "v1int_l";
1283 break;
1284 case OE_RRR(V1MAXU, 0, X0):
1285 case OE_RRR(V1MAXU, 0, X1):
1286 case OE_RRR(V1MINU, 0, X0):
1287 case OE_RRR(V1MINU, 0, X1):
1288 case OE_RRR(V1MNZ, 0, X0):
1289 case OE_RRR(V1MNZ, 0, X1):
1290 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1291 case OE_RRR(V1MULTU, 0, X0):
1292 gen_helper_v1multu(tdest, tsrca, tsrcb);
1293 mnemonic = "v1multu";
1294 break;
1295 case OE_RRR(V1MULUS, 0, X0):
1296 case OE_RRR(V1MULU, 0, X0):
1297 case OE_RRR(V1MZ, 0, X0):
1298 case OE_RRR(V1MZ, 0, X1):
1299 case OE_RRR(V1SADAU, 0, X0):
1300 case OE_RRR(V1SADU, 0, X0):
1301 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1302 case OE_RRR(V1SHL, 0, X0):
1303 case OE_RRR(V1SHL, 0, X1):
1304 gen_helper_v1shl(tdest, tsrca, tsrcb);
1305 mnemonic = "v1shl";
1306 break;
1307 case OE_RRR(V1SHRS, 0, X0):
1308 case OE_RRR(V1SHRS, 0, X1):
1309 gen_helper_v1shrs(tdest, tsrca, tsrcb);
1310 mnemonic = "v1shrs";
1311 break;
1312 case OE_RRR(V1SHRU, 0, X0):
1313 case OE_RRR(V1SHRU, 0, X1):
1314 gen_helper_v1shru(tdest, tsrca, tsrcb);
1315 mnemonic = "v1shru";
1316 break;
1317 case OE_RRR(V1SUBUC, 0, X0):
1318 case OE_RRR(V1SUBUC, 0, X1):
1319 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1320 case OE_RRR(V1SUB, 0, X0):
1321 case OE_RRR(V1SUB, 0, X1):
1322 gen_v12sub(tdest, tsrca, tsrcb, V1_IMM(0x80));
1323 mnemonic = "v1sub";
1324 break;
1325 case OE_RRR(V2ADDSC, 0, X0):
1326 case OE_RRR(V2ADDSC, 0, X1):
1327 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1328 case OE_RRR(V2ADD, 0, X0):
1329 case OE_RRR(V2ADD, 0, X1):
1330 gen_v12add(tdest, tsrca, tsrcb, V2_IMM(0x8000));
1331 mnemonic = "v2add";
1332 break;
1333 case OE_RRR(V2ADIFFS, 0, X0):
1334 case OE_RRR(V2AVGS, 0, X0):
1335 case OE_RRR(V2CMPEQ, 0, X0):
1336 case OE_RRR(V2CMPEQ, 0, X1):
1337 case OE_RRR(V2CMPLES, 0, X0):
1338 case OE_RRR(V2CMPLES, 0, X1):
1339 case OE_RRR(V2CMPLEU, 0, X0):
1340 case OE_RRR(V2CMPLEU, 0, X1):
1341 case OE_RRR(V2CMPLTS, 0, X0):
1342 case OE_RRR(V2CMPLTS, 0, X1):
1343 case OE_RRR(V2CMPLTU, 0, X0):
1344 case OE_RRR(V2CMPLTU, 0, X1):
1345 case OE_RRR(V2CMPNE, 0, X0):
1346 case OE_RRR(V2CMPNE, 0, X1):
1347 case OE_RRR(V2DOTPA, 0, X0):
1348 case OE_RRR(V2DOTP, 0, X0):
1349 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1350 case OE_RRR(V2INT_H, 0, X0):
1351 case OE_RRR(V2INT_H, 0, X1):
1352 gen_helper_v2int_h(tdest, tsrca, tsrcb);
1353 mnemonic = "v2int_h";
1354 break;
1355 case OE_RRR(V2INT_L, 0, X0):
1356 case OE_RRR(V2INT_L, 0, X1):
1357 gen_helper_v2int_l(tdest, tsrca, tsrcb);
1358 mnemonic = "v2int_l";
1359 break;
1360 case OE_RRR(V2MAXS, 0, X0):
1361 case OE_RRR(V2MAXS, 0, X1):
1362 case OE_RRR(V2MINS, 0, X0):
1363 case OE_RRR(V2MINS, 0, X1):
1364 case OE_RRR(V2MNZ, 0, X0):
1365 case OE_RRR(V2MNZ, 0, X1):
1366 case OE_RRR(V2MULFSC, 0, X0):
1367 case OE_RRR(V2MULS, 0, X0):
1368 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1369 case OE_RRR(V2MULTS, 0, X0):
1370 gen_helper_v2mults(tdest, tsrca, tsrcb);
1371 mnemonic = "v2mults";
1372 break;
1373 case OE_RRR(V2MZ, 0, X0):
1374 case OE_RRR(V2MZ, 0, X1):
1375 case OE_RRR(V2PACKH, 0, X0):
1376 case OE_RRR(V2PACKH, 0, X1):
1377 case OE_RRR(V2PACKL, 0, X0):
1378 case OE_RRR(V2PACKL, 0, X1):
1379 case OE_RRR(V2PACKUC, 0, X0):
1380 case OE_RRR(V2PACKUC, 0, X1):
1381 case OE_RRR(V2SADAS, 0, X0):
1382 case OE_RRR(V2SADAU, 0, X0):
1383 case OE_RRR(V2SADS, 0, X0):
1384 case OE_RRR(V2SADU, 0, X0):
1385 case OE_RRR(V2SHLSC, 0, X0):
1386 case OE_RRR(V2SHLSC, 0, X1):
1387 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1388 case OE_RRR(V2SHL, 0, X0):
1389 case OE_RRR(V2SHL, 0, X1):
1390 gen_helper_v2shl(tdest, tsrca, tsrcb);
1391 mnemonic = "v2shl";
1392 break;
1393 case OE_RRR(V2SHRS, 0, X0):
1394 case OE_RRR(V2SHRS, 0, X1):
1395 gen_helper_v2shrs(tdest, tsrca, tsrcb);
1396 mnemonic = "v2shrs";
1397 break;
1398 case OE_RRR(V2SHRU, 0, X0):
1399 case OE_RRR(V2SHRU, 0, X1):
1400 gen_helper_v2shru(tdest, tsrca, tsrcb);
1401 mnemonic = "v2shru";
1402 break;
1403 case OE_RRR(V2SUBSC, 0, X0):
1404 case OE_RRR(V2SUBSC, 0, X1):
1405 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1406 case OE_RRR(V2SUB, 0, X0):
1407 case OE_RRR(V2SUB, 0, X1):
1408 gen_v12sub(tdest, tsrca, tsrcb, V2_IMM(0x8000));
1409 mnemonic = "v2sub";
1410 break;
1411 case OE_RRR(V4ADDSC, 0, X0):
1412 case OE_RRR(V4ADDSC, 0, X1):
1413 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1414 case OE_RRR(V4ADD, 0, X0):
1415 case OE_RRR(V4ADD, 0, X1):
1416 gen_v4op(tdest, tsrca, tsrcb, tcg_gen_add_i32);
1417 mnemonic = "v4add";
1418 break;
1419 case OE_RRR(V4INT_H, 0, X0):
1420 case OE_RRR(V4INT_H, 0, X1):
1421 tcg_gen_shri_tl(tdest, tsrcb, 32);
1422 tcg_gen_deposit_tl(tdest, tsrca, tdest, 0, 32);
1423 mnemonic = "v4int_h";
1424 break;
1425 case OE_RRR(V4INT_L, 0, X0):
1426 case OE_RRR(V4INT_L, 0, X1):
1427 tcg_gen_deposit_tl(tdest, tsrcb, tsrca, 32, 32);
1428 mnemonic = "v4int_l";
1429 break;
1430 case OE_RRR(V4PACKSC, 0, X0):
1431 case OE_RRR(V4PACKSC, 0, X1):
1432 case OE_RRR(V4SHLSC, 0, X0):
1433 case OE_RRR(V4SHLSC, 0, X1):
1434 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1435 case OE_RRR(V4SHL, 0, X0):
1436 case OE_RRR(V4SHL, 0, X1):
1437 gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_shl_i32);
1438 mnemonic = "v4shl";
1439 break;
1440 case OE_RRR(V4SHRS, 0, X0):
1441 case OE_RRR(V4SHRS, 0, X1):
1442 gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_sar_i32);
1443 mnemonic = "v4shrs";
1444 break;
1445 case OE_RRR(V4SHRU, 0, X0):
1446 case OE_RRR(V4SHRU, 0, X1):
1447 gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_shr_i32);
1448 mnemonic = "v4shru";
1449 break;
1450 case OE_RRR(V4SUBSC, 0, X0):
1451 case OE_RRR(V4SUBSC, 0, X1):
1452 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1453 case OE_RRR(V4SUB, 0, X0):
1454 case OE_RRR(V4SUB, 0, X1):
1455 gen_v4op(tdest, tsrca, tsrcb, tcg_gen_sub_i32);
1456 mnemonic = "v2sub";
1457 break;
1458 case OE_RRR(XOR, 0, X0):
1459 case OE_RRR(XOR, 0, X1):
1460 case OE_RRR(XOR, 5, Y0):
1461 case OE_RRR(XOR, 5, Y1):
1462 tcg_gen_xor_tl(tdest, tsrca, tsrcb);
1463 mnemonic = "xor";
1464 break;
1465 default:
1466 return TILEGX_EXCP_OPCODE_UNKNOWN;
1467 }
1468
1469 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %s", mnemonic,
1470 reg_names[dest], reg_names[srca], reg_names[srcb]);
1471 return TILEGX_EXCP_NONE;
1472 }
1473
1474 static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
1475 unsigned dest, unsigned srca, int imm)
1476 {
1477 TCGv tdest = dest_gr(dc, dest);
1478 TCGv tsrca = load_gr(dc, srca);
1479 bool prefetch_nofault = false;
1480 const char *mnemonic;
1481 TCGMemOp memop;
1482 int i2, i3;
1483 TCGv t0;
1484
1485 switch (opext) {
1486 case OE(ADDI_OPCODE_Y0, 0, Y0):
1487 case OE(ADDI_OPCODE_Y1, 0, Y1):
1488 case OE_IM(ADDI, X0):
1489 case OE_IM(ADDI, X1):
1490 tcg_gen_addi_tl(tdest, tsrca, imm);
1491 mnemonic = "addi";
1492 break;
1493 case OE(ADDXI_OPCODE_Y0, 0, Y0):
1494 case OE(ADDXI_OPCODE_Y1, 0, Y1):
1495 case OE_IM(ADDXI, X0):
1496 case OE_IM(ADDXI, X1):
1497 tcg_gen_addi_tl(tdest, tsrca, imm);
1498 tcg_gen_ext32s_tl(tdest, tdest);
1499 mnemonic = "addxi";
1500 break;
1501 case OE(ANDI_OPCODE_Y0, 0, Y0):
1502 case OE(ANDI_OPCODE_Y1, 0, Y1):
1503 case OE_IM(ANDI, X0):
1504 case OE_IM(ANDI, X1):
1505 tcg_gen_andi_tl(tdest, tsrca, imm);
1506 mnemonic = "andi";
1507 break;
1508 case OE(CMPEQI_OPCODE_Y0, 0, Y0):
1509 case OE(CMPEQI_OPCODE_Y1, 0, Y1):
1510 case OE_IM(CMPEQI, X0):
1511 case OE_IM(CMPEQI, X1):
1512 tcg_gen_setcondi_tl(TCG_COND_EQ, tdest, tsrca, imm);
1513 mnemonic = "cmpeqi";
1514 break;
1515 case OE(CMPLTSI_OPCODE_Y0, 0, Y0):
1516 case OE(CMPLTSI_OPCODE_Y1, 0, Y1):
1517 case OE_IM(CMPLTSI, X0):
1518 case OE_IM(CMPLTSI, X1):
1519 tcg_gen_setcondi_tl(TCG_COND_LT, tdest, tsrca, imm);
1520 mnemonic = "cmpltsi";
1521 break;
1522 case OE_IM(CMPLTUI, X0):
1523 case OE_IM(CMPLTUI, X1):
1524 tcg_gen_setcondi_tl(TCG_COND_LTU, tdest, tsrca, imm);
1525 mnemonic = "cmpltui";
1526 break;
1527 case OE_IM(LD1S_ADD, X1):
1528 memop = MO_SB;
1529 mnemonic = "ld1s_add"; /* prefetch_add_l1_fault */
1530 goto do_load_add;
1531 case OE_IM(LD1U_ADD, X1):
1532 memop = MO_UB;
1533 mnemonic = "ld1u_add"; /* prefetch_add_l1 */
1534 prefetch_nofault = (dest == TILEGX_R_ZERO);
1535 goto do_load_add;
1536 case OE_IM(LD2S_ADD, X1):
1537 memop = MO_TESW;
1538 mnemonic = "ld2s_add"; /* prefetch_add_l2_fault */
1539 goto do_load_add;
1540 case OE_IM(LD2U_ADD, X1):
1541 memop = MO_TEUW;
1542 mnemonic = "ld2u_add"; /* prefetch_add_l2 */
1543 prefetch_nofault = (dest == TILEGX_R_ZERO);
1544 goto do_load_add;
1545 case OE_IM(LD4S_ADD, X1):
1546 memop = MO_TESL;
1547 mnemonic = "ld4s_add"; /* prefetch_add_l3_fault */
1548 goto do_load_add;
1549 case OE_IM(LD4U_ADD, X1):
1550 memop = MO_TEUL;
1551 mnemonic = "ld4u_add"; /* prefetch_add_l3 */
1552 prefetch_nofault = (dest == TILEGX_R_ZERO);
1553 goto do_load_add;
1554 case OE_IM(LDNT1S_ADD, X1):
1555 memop = MO_SB;
1556 mnemonic = "ldnt1s_add";
1557 goto do_load_add;
1558 case OE_IM(LDNT1U_ADD, X1):
1559 memop = MO_UB;
1560 mnemonic = "ldnt1u_add";
1561 goto do_load_add;
1562 case OE_IM(LDNT2S_ADD, X1):
1563 memop = MO_TESW;
1564 mnemonic = "ldnt2s_add";
1565 goto do_load_add;
1566 case OE_IM(LDNT2U_ADD, X1):
1567 memop = MO_TEUW;
1568 mnemonic = "ldnt2u_add";
1569 goto do_load_add;
1570 case OE_IM(LDNT4S_ADD, X1):
1571 memop = MO_TESL;
1572 mnemonic = "ldnt4s_add";
1573 goto do_load_add;
1574 case OE_IM(LDNT4U_ADD, X1):
1575 memop = MO_TEUL;
1576 mnemonic = "ldnt4u_add";
1577 goto do_load_add;
1578 case OE_IM(LDNT_ADD, X1):
1579 memop = MO_TEQ;
1580 mnemonic = "ldnt_add";
1581 goto do_load_add;
1582 case OE_IM(LD_ADD, X1):
1583 memop = MO_TEQ;
1584 mnemonic = "ld_add";
1585 do_load_add:
1586 if (!prefetch_nofault) {
1587 tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
1588 }
1589 tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
1590 break;
1591 case OE_IM(LDNA_ADD, X1):
1592 tcg_gen_andi_tl(tdest, tsrca, ~7);
1593 tcg_gen_qemu_ld_tl(tdest, tdest, dc->mmuidx, MO_TEQ);
1594 tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
1595 mnemonic = "ldna_add";
1596 break;
1597 case OE_IM(ORI, X0):
1598 case OE_IM(ORI, X1):
1599 tcg_gen_ori_tl(tdest, tsrca, imm);
1600 mnemonic = "ori";
1601 break;
1602 case OE_IM(V1ADDI, X0):
1603 case OE_IM(V1ADDI, X1):
1604 t0 = tcg_const_tl(V1_IMM(imm));
1605 gen_v12add(tdest, tsrca, t0, V1_IMM(0x80));
1606 tcg_temp_free(t0);
1607 mnemonic = "v1addi";
1608 break;
1609 case OE_IM(V1CMPEQI, X0):
1610 case OE_IM(V1CMPEQI, X1):
1611 tcg_gen_xori_tl(tdest, tsrca, V1_IMM(imm));
1612 gen_v1cmpeq0(tdest);
1613 mnemonic = "v1cmpeqi";
1614 break;
1615 case OE_IM(V1CMPLTSI, X0):
1616 case OE_IM(V1CMPLTSI, X1):
1617 case OE_IM(V1CMPLTUI, X0):
1618 case OE_IM(V1CMPLTUI, X1):
1619 case OE_IM(V1MAXUI, X0):
1620 case OE_IM(V1MAXUI, X1):
1621 case OE_IM(V1MINUI, X0):
1622 case OE_IM(V1MINUI, X1):
1623 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1624 case OE_IM(V2ADDI, X0):
1625 case OE_IM(V2ADDI, X1):
1626 t0 = tcg_const_tl(V2_IMM(imm));
1627 gen_v12add(tdest, tsrca, t0, V2_IMM(0x8000));
1628 tcg_temp_free(t0);
1629 mnemonic = "v2addi";
1630 break;
1631 case OE_IM(V2CMPEQI, X0):
1632 case OE_IM(V2CMPEQI, X1):
1633 case OE_IM(V2CMPLTSI, X0):
1634 case OE_IM(V2CMPLTSI, X1):
1635 case OE_IM(V2CMPLTUI, X0):
1636 case OE_IM(V2CMPLTUI, X1):
1637 case OE_IM(V2MAXSI, X0):
1638 case OE_IM(V2MAXSI, X1):
1639 case OE_IM(V2MINSI, X0):
1640 case OE_IM(V2MINSI, X1):
1641 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1642 case OE_IM(XORI, X0):
1643 case OE_IM(XORI, X1):
1644 tcg_gen_xori_tl(tdest, tsrca, imm);
1645 mnemonic = "xori";
1646 break;
1647
1648 case OE_SH(ROTLI, X0):
1649 case OE_SH(ROTLI, X1):
1650 case OE_SH(ROTLI, Y0):
1651 case OE_SH(ROTLI, Y1):
1652 tcg_gen_rotli_tl(tdest, tsrca, imm);
1653 mnemonic = "rotli";
1654 break;
1655 case OE_SH(SHLI, X0):
1656 case OE_SH(SHLI, X1):
1657 case OE_SH(SHLI, Y0):
1658 case OE_SH(SHLI, Y1):
1659 tcg_gen_shli_tl(tdest, tsrca, imm);
1660 mnemonic = "shli";
1661 break;
1662 case OE_SH(SHLXI, X0):
1663 case OE_SH(SHLXI, X1):
1664 tcg_gen_shli_tl(tdest, tsrca, imm & 31);
1665 tcg_gen_ext32s_tl(tdest, tdest);
1666 mnemonic = "shlxi";
1667 break;
1668 case OE_SH(SHRSI, X0):
1669 case OE_SH(SHRSI, X1):
1670 case OE_SH(SHRSI, Y0):
1671 case OE_SH(SHRSI, Y1):
1672 tcg_gen_sari_tl(tdest, tsrca, imm);
1673 mnemonic = "shrsi";
1674 break;
1675 case OE_SH(SHRUI, X0):
1676 case OE_SH(SHRUI, X1):
1677 case OE_SH(SHRUI, Y0):
1678 case OE_SH(SHRUI, Y1):
1679 tcg_gen_shri_tl(tdest, tsrca, imm);
1680 mnemonic = "shrui";
1681 break;
1682 case OE_SH(SHRUXI, X0):
1683 case OE_SH(SHRUXI, X1):
1684 if ((imm & 31) == 0) {
1685 tcg_gen_ext32s_tl(tdest, tsrca);
1686 } else {
1687 tcg_gen_ext32u_tl(tdest, tsrca);
1688 tcg_gen_shri_tl(tdest, tdest, imm & 31);
1689 }
1690 mnemonic = "shlxi";
1691 break;
1692 case OE_SH(V1SHLI, X0):
1693 case OE_SH(V1SHLI, X1):
1694 i2 = imm & 7;
1695 i3 = 0xff >> i2;
1696 tcg_gen_andi_tl(tdest, tsrca, V1_IMM(i3));
1697 tcg_gen_shli_tl(tdest, tdest, i2);
1698 mnemonic = "v1shli";
1699 break;
1700 case OE_SH(V1SHRSI, X0):
1701 case OE_SH(V1SHRSI, X1):
1702 t0 = tcg_const_tl(imm & 7);
1703 gen_helper_v1shrs(tdest, tsrca, t0);
1704 tcg_temp_free(t0);
1705 mnemonic = "v1shrsi";
1706 break;
1707 case OE_SH(V1SHRUI, X0):
1708 case OE_SH(V1SHRUI, X1):
1709 i2 = imm & 7;
1710 i3 = (0xff << i2) & 0xff;
1711 tcg_gen_andi_tl(tdest, tsrca, V1_IMM(i3));
1712 tcg_gen_shri_tl(tdest, tdest, i2);
1713 mnemonic = "v1shrui";
1714 break;
1715 case OE_SH(V2SHLI, X0):
1716 case OE_SH(V2SHLI, X1):
1717 i2 = imm & 15;
1718 i3 = 0xffff >> i2;
1719 tcg_gen_andi_tl(tdest, tsrca, V2_IMM(i3));
1720 tcg_gen_shli_tl(tdest, tdest, i2);
1721 mnemonic = "v2shli";
1722 break;
1723 case OE_SH(V2SHRSI, X0):
1724 case OE_SH(V2SHRSI, X1):
1725 t0 = tcg_const_tl(imm & 15);
1726 gen_helper_v2shrs(tdest, tsrca, t0);
1727 tcg_temp_free(t0);
1728 mnemonic = "v2shrsi";
1729 break;
1730 case OE_SH(V2SHRUI, X0):
1731 case OE_SH(V2SHRUI, X1):
1732 i2 = imm & 15;
1733 i3 = (0xffff << i2) & 0xffff;
1734 tcg_gen_andi_tl(tdest, tsrca, V2_IMM(i3));
1735 tcg_gen_shri_tl(tdest, tdest, i2);
1736 mnemonic = "v2shrui";
1737 break;
1738
1739 case OE(ADDLI_OPCODE_X0, 0, X0):
1740 case OE(ADDLI_OPCODE_X1, 0, X1):
1741 tcg_gen_addi_tl(tdest, tsrca, imm);
1742 mnemonic = "addli";
1743 break;
1744 case OE(ADDXLI_OPCODE_X0, 0, X0):
1745 case OE(ADDXLI_OPCODE_X1, 0, X1):
1746 tcg_gen_addi_tl(tdest, tsrca, imm);
1747 tcg_gen_ext32s_tl(tdest, tdest);
1748 mnemonic = "addxli";
1749 break;
1750 case OE(SHL16INSLI_OPCODE_X0, 0, X0):
1751 case OE(SHL16INSLI_OPCODE_X1, 0, X1):
1752 tcg_gen_shli_tl(tdest, tsrca, 16);
1753 tcg_gen_ori_tl(tdest, tdest, imm & 0xffff);
1754 mnemonic = "shl16insli";
1755 break;
1756
1757 default:
1758 return TILEGX_EXCP_OPCODE_UNKNOWN;
1759 }
1760
1761 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", mnemonic,
1762 reg_names[dest], reg_names[srca], imm);
1763 return TILEGX_EXCP_NONE;
1764 }
1765
1766 static TileExcp gen_bf_opcode_x0(DisasContext *dc, unsigned ext,
1767 unsigned dest, unsigned srca,
1768 unsigned bfs, unsigned bfe)
1769 {
1770 TCGv tdest = dest_gr(dc, dest);
1771 TCGv tsrca = load_gr(dc, srca);
1772 TCGv tsrcd;
1773 int len;
1774 const char *mnemonic;
1775
1776 /* The bitfield is either between E and S inclusive,
1777 or up from S and down from E inclusive. */
1778 if (bfs <= bfe) {
1779 len = bfe - bfs + 1;
1780 } else {
1781 len = (64 - bfs) + (bfe + 1);
1782 }
1783
1784 switch (ext) {
1785 case BFEXTU_BF_OPCODE_X0:
1786 if (bfs == 0 && bfe == 7) {
1787 tcg_gen_ext8u_tl(tdest, tsrca);
1788 } else if (bfs == 0 && bfe == 15) {
1789 tcg_gen_ext16u_tl(tdest, tsrca);
1790 } else if (bfs == 0 && bfe == 31) {
1791 tcg_gen_ext32u_tl(tdest, tsrca);
1792 } else {
1793 int rol = 63 - bfe;
1794 if (bfs <= bfe) {
1795 tcg_gen_shli_tl(tdest, tsrca, rol);
1796 } else {
1797 tcg_gen_rotli_tl(tdest, tsrca, rol);
1798 }
1799 tcg_gen_shri_tl(tdest, tdest, (bfs + rol) & 63);
1800 }
1801 mnemonic = "bfextu";
1802 break;
1803
1804 case BFEXTS_BF_OPCODE_X0:
1805 if (bfs == 0 && bfe == 7) {
1806 tcg_gen_ext8s_tl(tdest, tsrca);
1807 } else if (bfs == 0 && bfe == 15) {
1808 tcg_gen_ext16s_tl(tdest, tsrca);
1809 } else if (bfs == 0 && bfe == 31) {
1810 tcg_gen_ext32s_tl(tdest, tsrca);
1811 } else {
1812 int rol = 63 - bfe;
1813 if (bfs <= bfe) {
1814 tcg_gen_shli_tl(tdest, tsrca, rol);
1815 } else {
1816 tcg_gen_rotli_tl(tdest, tsrca, rol);
1817 }
1818 tcg_gen_sari_tl(tdest, tdest, (bfs + rol) & 63);
1819 }
1820 mnemonic = "bfexts";
1821 break;
1822
1823 case BFINS_BF_OPCODE_X0:
1824 tsrcd = load_gr(dc, dest);
1825 if (bfs <= bfe) {
1826 tcg_gen_deposit_tl(tdest, tsrcd, tsrca, bfs, len);
1827 } else {
1828 tcg_gen_rotri_tl(tdest, tsrcd, bfs);
1829 tcg_gen_deposit_tl(tdest, tdest, tsrca, 0, len);
1830 tcg_gen_rotli_tl(tdest, tdest, bfs);
1831 }
1832 mnemonic = "bfins";
1833 break;
1834
1835 case MM_BF_OPCODE_X0:
1836 tsrcd = load_gr(dc, dest);
1837 if (bfs == 0) {
1838 tcg_gen_deposit_tl(tdest, tsrca, tsrcd, 0, len);
1839 } else {
1840 uint64_t mask = len == 64 ? -1 : rol64((1ULL << len) - 1, bfs);
1841 TCGv tmp = tcg_const_tl(mask);
1842
1843 tcg_gen_and_tl(tdest, tsrcd, tmp);
1844 tcg_gen_andc_tl(tmp, tsrca, tmp);
1845 tcg_gen_or_tl(tdest, tdest, tmp);
1846 tcg_temp_free(tmp);
1847 }
1848 mnemonic = "mm";
1849 break;
1850
1851 default:
1852 return TILEGX_EXCP_OPCODE_UNKNOWN;
1853 }
1854
1855 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %u, %u", mnemonic,
1856 reg_names[dest], reg_names[srca], bfs, bfe);
1857 return TILEGX_EXCP_NONE;
1858 }
1859
1860 static TileExcp gen_branch_opcode_x1(DisasContext *dc, unsigned ext,
1861 unsigned srca, int off)
1862 {
1863 target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
1864 const char *mnemonic;
1865
1866 dc->jmp.dest = tcg_const_tl(tgt);
1867 dc->jmp.val1 = tcg_temp_new();
1868 tcg_gen_mov_tl(dc->jmp.val1, load_gr(dc, srca));
1869
1870 /* Note that the "predict taken" opcodes have bit 0 clear.
1871 Therefore, fold the two cases together by setting bit 0. */
1872 switch (ext | 1) {
1873 case BEQZ_BRANCH_OPCODE_X1:
1874 dc->jmp.cond = TCG_COND_EQ;
1875 mnemonic = "beqz";
1876 break;
1877 case BNEZ_BRANCH_OPCODE_X1:
1878 dc->jmp.cond = TCG_COND_NE;
1879 mnemonic = "bnez";
1880 break;
1881 case BGEZ_BRANCH_OPCODE_X1:
1882 dc->jmp.cond = TCG_COND_GE;
1883 mnemonic = "bgez";
1884 break;
1885 case BGTZ_BRANCH_OPCODE_X1:
1886 dc->jmp.cond = TCG_COND_GT;
1887 mnemonic = "bgtz";
1888 break;
1889 case BLEZ_BRANCH_OPCODE_X1:
1890 dc->jmp.cond = TCG_COND_LE;
1891 mnemonic = "blez";
1892 break;
1893 case BLTZ_BRANCH_OPCODE_X1:
1894 dc->jmp.cond = TCG_COND_LT;
1895 mnemonic = "bltz";
1896 break;
1897 case BLBC_BRANCH_OPCODE_X1:
1898 dc->jmp.cond = TCG_COND_EQ;
1899 tcg_gen_andi_tl(dc->jmp.val1, dc->jmp.val1, 1);
1900 mnemonic = "blbc";
1901 break;
1902 case BLBS_BRANCH_OPCODE_X1:
1903 dc->jmp.cond = TCG_COND_NE;
1904 tcg_gen_andi_tl(dc->jmp.val1, dc->jmp.val1, 1);
1905 mnemonic = "blbs";
1906 break;
1907 default:
1908 return TILEGX_EXCP_OPCODE_UNKNOWN;
1909 }
1910
1911 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1912 qemu_log("%s%s %s, " TARGET_FMT_lx " <%s>",
1913 mnemonic, ext & 1 ? "" : "t",
1914 reg_names[srca], tgt, lookup_symbol(tgt));
1915 }
1916 return TILEGX_EXCP_NONE;
1917 }
1918
1919 static TileExcp gen_jump_opcode_x1(DisasContext *dc, unsigned ext, int off)
1920 {
1921 target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
1922 const char *mnemonic = "j";
1923
1924 /* The extension field is 1 bit, therefore we only have JAL and J. */
1925 if (ext == JAL_JUMP_OPCODE_X1) {
1926 tcg_gen_movi_tl(dest_gr(dc, TILEGX_R_LR),
1927 dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
1928 mnemonic = "jal";
1929 }
1930 dc->jmp.cond = TCG_COND_ALWAYS;
1931 dc->jmp.dest = tcg_const_tl(tgt);
1932
1933 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1934 qemu_log("%s " TARGET_FMT_lx " <%s>",
1935 mnemonic, tgt, lookup_symbol(tgt));
1936 }
1937 return TILEGX_EXCP_NONE;
1938 }
1939
1940 typedef struct {
1941 const char *name;
1942 intptr_t offset;
1943 void (*get)(TCGv, TCGv_ptr);
1944 void (*put)(TCGv_ptr, TCGv);
1945 } TileSPR;
1946
1947 static const TileSPR *find_spr(unsigned spr)
1948 {
1949 /* Allow the compiler to construct the binary search tree. */
1950 #define D(N, O, G, P) \
1951 case SPR_##N: { static const TileSPR x = { #N, O, G, P }; return &x; }
1952
1953 switch (spr) {
1954 D(CMPEXCH_VALUE,
1955 offsetof(CPUTLGState, spregs[TILEGX_SPR_CMPEXCH]), 0, 0)
1956 D(INTERRUPT_CRITICAL_SECTION,
1957 offsetof(CPUTLGState, spregs[TILEGX_SPR_CRITICAL_SEC]), 0, 0)
1958 D(SIM_CONTROL,
1959 offsetof(CPUTLGState, spregs[TILEGX_SPR_SIM_CONTROL]), 0, 0)
1960 D(EX_CONTEXT_0_0,
1961 offsetof(CPUTLGState, spregs[TILEGX_SPR_EX_CONTEXT_0_0]), 0, 0)
1962 D(EX_CONTEXT_0_1,
1963 offsetof(CPUTLGState, spregs[TILEGX_SPR_EX_CONTEXT_0_1]), 0, 0)
1964 }
1965
1966 #undef D
1967
1968 qemu_log_mask(LOG_UNIMP, "UNIMP SPR %u\n", spr);
1969 return NULL;
1970 }
1971
1972 static TileExcp gen_mtspr_x1(DisasContext *dc, unsigned spr, unsigned srca)
1973 {
1974 const TileSPR *def = find_spr(spr);
1975 TCGv tsrca;
1976
1977 if (def == NULL) {
1978 qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr spr[%u], %s", spr, reg_names[srca]);
1979 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1980 }
1981
1982 tsrca = load_gr(dc, srca);
1983 if (def->put) {
1984 def->put(cpu_env, tsrca);
1985 } else {
1986 tcg_gen_st_tl(tsrca, cpu_env, def->offset);
1987 }
1988 qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, %s", def->name, reg_names[srca]);
1989 return TILEGX_EXCP_NONE;
1990 }
1991
1992 static TileExcp gen_mfspr_x1(DisasContext *dc, unsigned dest, unsigned spr)
1993 {
1994 const TileSPR *def = find_spr(spr);
1995 TCGv tdest;
1996
1997 if (def == NULL) {
1998 qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, spr[%u]", reg_names[dest], spr);
1999 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
2000 }
2001
2002 tdest = dest_gr(dc, dest);
2003 if (def->get) {
2004 def->get(tdest, cpu_env);
2005 } else {
2006 tcg_gen_ld_tl(tdest, cpu_env, def->offset);
2007 }
2008 qemu_log_mask(CPU_LOG_TB_IN_ASM, "mfspr %s, %s", reg_names[dest], def->name);
2009 return TILEGX_EXCP_NONE;
2010 }
2011
2012 static TileExcp decode_y0(DisasContext *dc, tilegx_bundle_bits bundle)
2013 {
2014 unsigned opc = get_Opcode_Y0(bundle);
2015 unsigned ext = get_RRROpcodeExtension_Y0(bundle);
2016 unsigned dest = get_Dest_Y0(bundle);
2017 unsigned srca = get_SrcA_Y0(bundle);
2018 unsigned srcb;
2019 int imm;
2020
2021 switch (opc) {
2022 case RRR_1_OPCODE_Y0:
2023 if (ext == UNARY_RRR_1_OPCODE_Y0) {
2024 ext = get_UnaryOpcodeExtension_Y0(bundle);
2025 return gen_rr_opcode(dc, OE(opc, ext, Y0), dest, srca, bundle);
2026 }
2027 /* fallthru */
2028 case RRR_0_OPCODE_Y0:
2029 case RRR_2_OPCODE_Y0:
2030 case RRR_3_OPCODE_Y0:
2031 case RRR_4_OPCODE_Y0:
2032 case RRR_5_OPCODE_Y0:
2033 case RRR_6_OPCODE_Y0:
2034 case RRR_7_OPCODE_Y0:
2035 case RRR_8_OPCODE_Y0:
2036 case RRR_9_OPCODE_Y0:
2037 srcb = get_SrcB_Y0(bundle);
2038 return gen_rrr_opcode(dc, OE(opc, ext, Y0), dest, srca, srcb);
2039
2040 case SHIFT_OPCODE_Y0:
2041 ext = get_ShiftOpcodeExtension_Y0(bundle);
2042 imm = get_ShAmt_Y0(bundle);
2043 return gen_rri_opcode(dc, OE(opc, ext, Y0), dest, srca, imm);
2044
2045 case ADDI_OPCODE_Y0:
2046 case ADDXI_OPCODE_Y0:
2047 case ANDI_OPCODE_Y0:
2048 case CMPEQI_OPCODE_Y0:
2049 case CMPLTSI_OPCODE_Y0:
2050 imm = (int8_t)get_Imm8_Y0(bundle);
2051 return gen_rri_opcode(dc, OE(opc, 0, Y0), dest, srca, imm);
2052
2053 default:
2054 return TILEGX_EXCP_OPCODE_UNKNOWN;
2055 }
2056 }
2057
2058 static TileExcp decode_y1(DisasContext *dc, tilegx_bundle_bits bundle)
2059 {
2060 unsigned opc = get_Opcode_Y1(bundle);
2061 unsigned ext = get_RRROpcodeExtension_Y1(bundle);
2062 unsigned dest = get_Dest_Y1(bundle);
2063 unsigned srca = get_SrcA_Y1(bundle);
2064 unsigned srcb;
2065 int imm;
2066
2067 switch (get_Opcode_Y1(bundle)) {
2068 case RRR_1_OPCODE_Y1:
2069 if (ext == UNARY_RRR_1_OPCODE_Y0) {
2070 ext = get_UnaryOpcodeExtension_Y1(bundle);
2071 return gen_rr_opcode(dc, OE(opc, ext, Y1), dest, srca, bundle);
2072 }
2073 /* fallthru */
2074 case RRR_0_OPCODE_Y1:
2075 case RRR_2_OPCODE_Y1:
2076 case RRR_3_OPCODE_Y1:
2077 case RRR_4_OPCODE_Y1:
2078 case RRR_5_OPCODE_Y1:
2079 case RRR_6_OPCODE_Y1:
2080 case RRR_7_OPCODE_Y1:
2081 srcb = get_SrcB_Y1(bundle);
2082 return gen_rrr_opcode(dc, OE(opc, ext, Y1), dest, srca, srcb);
2083
2084 case SHIFT_OPCODE_Y1:
2085 ext = get_ShiftOpcodeExtension_Y1(bundle);
2086 imm = get_ShAmt_Y1(bundle);
2087 return gen_rri_opcode(dc, OE(opc, ext, Y1), dest, srca, imm);
2088
2089 case ADDI_OPCODE_Y1:
2090 case ADDXI_OPCODE_Y1:
2091 case ANDI_OPCODE_Y1:
2092 case CMPEQI_OPCODE_Y1:
2093 case CMPLTSI_OPCODE_Y1:
2094 imm = (int8_t)get_Imm8_Y1(bundle);
2095 return gen_rri_opcode(dc, OE(opc, 0, Y1), dest, srca, imm);
2096
2097 default:
2098 return TILEGX_EXCP_OPCODE_UNKNOWN;
2099 }
2100 }
2101
2102 static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
2103 {
2104 unsigned mode = get_Mode(bundle);
2105 unsigned opc = get_Opcode_Y2(bundle);
2106 unsigned srca = get_SrcA_Y2(bundle);
2107 unsigned srcbdest = get_SrcBDest_Y2(bundle);
2108 const char *mnemonic;
2109 TCGMemOp memop;
2110 bool prefetch_nofault = false;
2111
2112 switch (OEY2(opc, mode)) {
2113 case OEY2(LD1S_OPCODE_Y2, MODE_OPCODE_YA2):
2114 memop = MO_SB;
2115 mnemonic = "ld1s"; /* prefetch_l1_fault */
2116 goto do_load;
2117 case OEY2(LD1U_OPCODE_Y2, MODE_OPCODE_YA2):
2118 memop = MO_UB;
2119 mnemonic = "ld1u"; /* prefetch, prefetch_l1 */
2120 prefetch_nofault = (srcbdest == TILEGX_R_ZERO);
2121 goto do_load;
2122 case OEY2(LD2S_OPCODE_Y2, MODE_OPCODE_YA2):
2123 memop = MO_TESW;
2124 mnemonic = "ld2s"; /* prefetch_l2_fault */
2125 goto do_load;
2126 case OEY2(LD2U_OPCODE_Y2, MODE_OPCODE_YA2):
2127 memop = MO_TEUW;
2128 mnemonic = "ld2u"; /* prefetch_l2 */
2129 prefetch_nofault = (srcbdest == TILEGX_R_ZERO);
2130 goto do_load;
2131 case OEY2(LD4S_OPCODE_Y2, MODE_OPCODE_YB2):
2132 memop = MO_TESL;
2133 mnemonic = "ld4s"; /* prefetch_l3_fault */
2134 goto do_load;
2135 case OEY2(LD4U_OPCODE_Y2, MODE_OPCODE_YB2):
2136 memop = MO_TEUL;
2137 mnemonic = "ld4u"; /* prefetch_l3 */
2138 prefetch_nofault = (srcbdest == TILEGX_R_ZERO);
2139 goto do_load;
2140 case OEY2(LD_OPCODE_Y2, MODE_OPCODE_YB2):
2141 memop = MO_TEQ;
2142 mnemonic = "ld";
2143 do_load:
2144 if (!prefetch_nofault) {
2145 tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca),
2146 dc->mmuidx, memop);
2147 }
2148 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
2149 reg_names[srcbdest], reg_names[srca]);
2150 return TILEGX_EXCP_NONE;
2151
2152 case OEY2(ST1_OPCODE_Y2, MODE_OPCODE_YC2):
2153 return gen_st_opcode(dc, 0, srca, srcbdest, MO_UB, "st1");
2154 case OEY2(ST2_OPCODE_Y2, MODE_OPCODE_YC2):
2155 return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEUW, "st2");
2156 case OEY2(ST4_OPCODE_Y2, MODE_OPCODE_YC2):
2157 return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEUL, "st4");
2158 case OEY2(ST_OPCODE_Y2, MODE_OPCODE_YC2):
2159 return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEQ, "st");
2160
2161 default:
2162 return TILEGX_EXCP_OPCODE_UNKNOWN;
2163 }
2164 }
2165
2166 static TileExcp decode_x0(DisasContext *dc, tilegx_bundle_bits bundle)
2167 {
2168 unsigned opc = get_Opcode_X0(bundle);
2169 unsigned dest = get_Dest_X0(bundle);
2170 unsigned srca = get_SrcA_X0(bundle);
2171 unsigned ext, srcb, bfs, bfe;
2172 int imm;
2173
2174 switch (opc) {
2175 case RRR_0_OPCODE_X0:
2176 ext = get_RRROpcodeExtension_X0(bundle);
2177 if (ext == UNARY_RRR_0_OPCODE_X0) {
2178 ext = get_UnaryOpcodeExtension_X0(bundle);
2179 return gen_rr_opcode(dc, OE(opc, ext, X0), dest, srca, bundle);
2180 }
2181 srcb = get_SrcB_X0(bundle);
2182 return gen_rrr_opcode(dc, OE(opc, ext, X0), dest, srca, srcb);
2183
2184 case SHIFT_OPCODE_X0:
2185 ext = get_ShiftOpcodeExtension_X0(bundle);
2186 imm = get_ShAmt_X0(bundle);
2187 return gen_rri_opcode(dc, OE(opc, ext, X0), dest, srca, imm);
2188
2189 case IMM8_OPCODE_X0:
2190 ext = get_Imm8OpcodeExtension_X0(bundle);
2191 imm = (int8_t)get_Imm8_X0(bundle);
2192 return gen_rri_opcode(dc, OE(opc, ext, X0), dest, srca, imm);
2193
2194 case BF_OPCODE_X0:
2195 ext = get_BFOpcodeExtension_X0(bundle);
2196 bfs = get_BFStart_X0(bundle);
2197 bfe = get_BFEnd_X0(bundle);
2198 return gen_bf_opcode_x0(dc, ext, dest, srca, bfs, bfe);
2199
2200 case ADDLI_OPCODE_X0:
2201 case SHL16INSLI_OPCODE_X0:
2202 case ADDXLI_OPCODE_X0:
2203 imm = (int16_t)get_Imm16_X0(bundle);
2204 return gen_rri_opcode(dc, OE(opc, 0, X0), dest, srca, imm);
2205
2206 default:
2207 return TILEGX_EXCP_OPCODE_UNKNOWN;
2208 }
2209 }
2210
2211 static TileExcp decode_x1(DisasContext *dc, tilegx_bundle_bits bundle)
2212 {
2213 unsigned opc = get_Opcode_X1(bundle);
2214 unsigned dest = get_Dest_X1(bundle);
2215 unsigned srca = get_SrcA_X1(bundle);
2216 unsigned ext, srcb;
2217 int imm;
2218
2219 switch (opc) {
2220 case RRR_0_OPCODE_X1:
2221 ext = get_RRROpcodeExtension_X1(bundle);
2222 srcb = get_SrcB_X1(bundle);
2223 switch (ext) {
2224 case UNARY_RRR_0_OPCODE_X1:
2225 ext = get_UnaryOpcodeExtension_X1(bundle);
2226 return gen_rr_opcode(dc, OE(opc, ext, X1), dest, srca, bundle);
2227 case ST1_RRR_0_OPCODE_X1:
2228 return gen_st_opcode(dc, dest, srca, srcb, MO_UB, "st1");
2229 case ST2_RRR_0_OPCODE_X1:
2230 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUW, "st2");
2231 case ST4_RRR_0_OPCODE_X1:
2232 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUL, "st4");
2233 case STNT1_RRR_0_OPCODE_X1:
2234 return gen_st_opcode(dc, dest, srca, srcb, MO_UB, "stnt1");
2235 case STNT2_RRR_0_OPCODE_X1:
2236 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUW, "stnt2");
2237 case STNT4_RRR_0_OPCODE_X1:
2238 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUL, "stnt4");
2239 case STNT_RRR_0_OPCODE_X1:
2240 return gen_st_opcode(dc, dest, srca, srcb, MO_TEQ, "stnt");
2241 case ST_RRR_0_OPCODE_X1:
2242 return gen_st_opcode(dc, dest, srca, srcb, MO_TEQ, "st");
2243 }
2244 return gen_rrr_opcode(dc, OE(opc, ext, X1), dest, srca, srcb);
2245
2246 case SHIFT_OPCODE_X1:
2247 ext = get_ShiftOpcodeExtension_X1(bundle);
2248 imm = get_ShAmt_X1(bundle);
2249 return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm);
2250
2251 case IMM8_OPCODE_X1:
2252 ext = get_Imm8OpcodeExtension_X1(bundle);
2253 imm = (int8_t)get_Dest_Imm8_X1(bundle);
2254 srcb = get_SrcB_X1(bundle);
2255 switch (ext) {
2256 case ST1_ADD_IMM8_OPCODE_X1:
2257 return gen_st_add_opcode(dc, srca, srcb, imm, MO_UB, "st1_add");
2258 case ST2_ADD_IMM8_OPCODE_X1:
2259 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUW, "st2_add");
2260 case ST4_ADD_IMM8_OPCODE_X1:
2261 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUL, "st4_add");
2262 case STNT1_ADD_IMM8_OPCODE_X1:
2263 return gen_st_add_opcode(dc, srca, srcb, imm, MO_UB, "stnt1_add");
2264 case STNT2_ADD_IMM8_OPCODE_X1:
2265 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUW, "stnt2_add");
2266 case STNT4_ADD_IMM8_OPCODE_X1:
2267 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUL, "stnt4_add");
2268 case STNT_ADD_IMM8_OPCODE_X1:
2269 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEQ, "stnt_add");
2270 case ST_ADD_IMM8_OPCODE_X1:
2271 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEQ, "st_add");
2272 case MFSPR_IMM8_OPCODE_X1:
2273 return gen_mfspr_x1(dc, dest, get_MF_Imm14_X1(bundle));
2274 case MTSPR_IMM8_OPCODE_X1:
2275 return gen_mtspr_x1(dc, get_MT_Imm14_X1(bundle), srca);
2276 }
2277 imm = (int8_t)get_Imm8_X1(bundle);
2278 return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm);
2279
2280 case BRANCH_OPCODE_X1:
2281 ext = get_BrType_X1(bundle);
2282 imm = sextract32(get_BrOff_X1(bundle), 0, 17);
2283 return gen_branch_opcode_x1(dc, ext, srca, imm);
2284
2285 case JUMP_OPCODE_X1:
2286 ext = get_JumpOpcodeExtension_X1(bundle);
2287 imm = sextract32(get_JumpOff_X1(bundle), 0, 27);
2288 return gen_jump_opcode_x1(dc, ext, imm);
2289
2290 case ADDLI_OPCODE_X1:
2291 case SHL16INSLI_OPCODE_X1:
2292 case ADDXLI_OPCODE_X1:
2293 imm = (int16_t)get_Imm16_X1(bundle);
2294 return gen_rri_opcode(dc, OE(opc, 0, X1), dest, srca, imm);
2295
2296 default:
2297 return TILEGX_EXCP_OPCODE_UNKNOWN;
2298 }
2299 }
2300
2301 static void notice_excp(DisasContext *dc, uint64_t bundle,
2302 const char *type, TileExcp excp)
2303 {
2304 if (likely(excp == TILEGX_EXCP_NONE)) {
2305 return;
2306 }
2307 gen_exception(dc, excp);
2308 switch (excp) {
2309 case TILEGX_EXCP_OPCODE_UNIMPLEMENTED:
2310 qemu_log_mask(LOG_UNIMP, "UNIMP %s, [" FMT64X "]\n", type, bundle);
2311 break;
2312 case TILEGX_EXCP_OPCODE_UNKNOWN:
2313 qemu_log_mask(LOG_UNIMP, "UNKNOWN %s, [" FMT64X "]\n", type, bundle);
2314 break;
2315 default:
2316 break;
2317 }
2318 }
2319
2320 static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
2321 {
2322 int i;
2323
2324 for (i = 0; i < ARRAY_SIZE(dc->wb); i++) {
2325 DisasContextTemp *wb = &dc->wb[i];
2326 wb->reg = TILEGX_R_NOREG;
2327 TCGV_UNUSED_I64(wb->val);
2328 }
2329 dc->num_wb = 0;
2330
2331 qemu_log_mask(CPU_LOG_TB_IN_ASM, " %" PRIx64 ": { ", dc->pc);
2332 if (get_Mode(bundle)) {
2333 notice_excp(dc, bundle, "y0", decode_y0(dc, bundle));
2334 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
2335 notice_excp(dc, bundle, "y1", decode_y1(dc, bundle));
2336 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
2337 notice_excp(dc, bundle, "y2", decode_y2(dc, bundle));
2338 } else {
2339 notice_excp(dc, bundle, "x0", decode_x0(dc, bundle));
2340 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
2341 notice_excp(dc, bundle, "x1", decode_x1(dc, bundle));
2342 }
2343 qemu_log_mask(CPU_LOG_TB_IN_ASM, " }\n");
2344
2345 for (i = dc->num_wb - 1; i >= 0; --i) {
2346 DisasContextTemp *wb = &dc->wb[i];
2347 if (wb->reg < TILEGX_R_COUNT) {
2348 tcg_gen_mov_i64(cpu_regs[wb->reg], wb->val);
2349 }
2350 tcg_temp_free_i64(wb->val);
2351 }
2352
2353 if (dc->jmp.cond != TCG_COND_NEVER) {
2354 if (dc->jmp.cond == TCG_COND_ALWAYS) {
2355 tcg_gen_mov_i64(cpu_pc, dc->jmp.dest);
2356 } else {
2357 TCGv next = tcg_const_i64(dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
2358 tcg_gen_movcond_i64(dc->jmp.cond, cpu_pc,
2359 dc->jmp.val1, load_zero(dc),
2360 dc->jmp.dest, next);
2361 tcg_temp_free_i64(dc->jmp.val1);
2362 tcg_temp_free_i64(next);
2363 }
2364 tcg_temp_free_i64(dc->jmp.dest);
2365 tcg_gen_exit_tb(0);
2366 dc->exit_tb = true;
2367 } else if (dc->atomic_excp != TILEGX_EXCP_NONE) {
2368 gen_exception(dc, dc->atomic_excp);
2369 }
2370 }
2371
2372 void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb)
2373 {
2374 TileGXCPU *cpu = tilegx_env_get_cpu(env);
2375 DisasContext ctx;
2376 DisasContext *dc = &ctx;
2377 CPUState *cs = CPU(cpu);
2378 uint64_t pc_start = tb->pc;
2379 uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2380 int num_insns = 0;
2381 int max_insns = tb->cflags & CF_COUNT_MASK;
2382
2383 dc->pc = pc_start;
2384 dc->mmuidx = 0;
2385 dc->exit_tb = false;
2386 dc->atomic_excp = TILEGX_EXCP_NONE;
2387 dc->jmp.cond = TCG_COND_NEVER;
2388 TCGV_UNUSED_I64(dc->jmp.dest);
2389 TCGV_UNUSED_I64(dc->jmp.val1);
2390 TCGV_UNUSED_I64(dc->zero);
2391
2392 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
2393 qemu_log("IN: %s\n", lookup_symbol(pc_start));
2394 }
2395 if (!max_insns) {
2396 max_insns = CF_COUNT_MASK;
2397 }
2398 if (cs->singlestep_enabled || singlestep) {
2399 max_insns = 1;
2400 }
2401 if (max_insns > TCG_MAX_INSNS) {
2402 max_insns = TCG_MAX_INSNS;
2403 }
2404 gen_tb_start(tb);
2405
2406 while (1) {
2407 tcg_gen_insn_start(dc->pc);
2408 num_insns++;
2409
2410 translate_one_bundle(dc, cpu_ldq_data(env, dc->pc));
2411
2412 if (dc->exit_tb) {
2413 /* PC updated and EXIT_TB/GOTO_TB/exception emitted. */
2414 break;
2415 }
2416 dc->pc += TILEGX_BUNDLE_SIZE_IN_BYTES;
2417 if (num_insns >= max_insns
2418 || dc->pc >= next_page_start
2419 || tcg_op_buf_full()) {
2420 /* Ending the TB due to TB size or page boundary. Set PC. */
2421 tcg_gen_movi_tl(cpu_pc, dc->pc);
2422 tcg_gen_exit_tb(0);
2423 break;
2424 }
2425 }
2426
2427 gen_tb_end(tb, num_insns);
2428 tb->size = dc->pc - pc_start;
2429 tb->icount = num_insns;
2430
2431 qemu_log_mask(CPU_LOG_TB_IN_ASM, "\n");
2432 }
2433
2434 void restore_state_to_opc(CPUTLGState *env, TranslationBlock *tb,
2435 target_ulong *data)
2436 {
2437 env->pc = data[0];
2438 }
2439
2440 void tilegx_tcg_init(void)
2441 {
2442 int i;
2443
2444 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
2445 cpu_pc = tcg_global_mem_new_i64(cpu_env, offsetof(CPUTLGState, pc), "pc");
2446 for (i = 0; i < TILEGX_R_COUNT; i++) {
2447 cpu_regs[i] = tcg_global_mem_new_i64(cpu_env,
2448 offsetof(CPUTLGState, regs[i]),
2449 reg_names[i]);
2450 }
2451 }
AR7 emulation for QEMU