2 * QEMU RISC-V CPU -- internal functions and types
4 * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #ifndef RISCV_CPU_INTERNALS_H
20 #define RISCV_CPU_INTERNALS_H
22 #include "hw/registerfields.h"
24 /* share data between vector helpers and decode code */
25 FIELD(VDATA
, VM
, 0, 1)
26 FIELD(VDATA
, LMUL
, 1, 3)
27 FIELD(VDATA
, VTA
, 4, 1)
28 FIELD(VDATA
, VTA_ALL_1S
, 5, 1)
29 FIELD(VDATA
, VMA
, 6, 1)
30 FIELD(VDATA
, NF
, 7, 4)
31 FIELD(VDATA
, WD
, 7, 1)
33 /* float point classify helpers */
34 target_ulong
fclass_h(uint64_t frs1
);
35 target_ulong
fclass_s(uint64_t frs1
);
36 target_ulong
fclass_d(uint64_t frs1
);
38 #ifndef CONFIG_USER_ONLY
39 extern const VMStateDescription vmstate_riscv_cpu
;
43 RISCV_FRM_RNE
= 0, /* Round to Nearest, ties to Even */
44 RISCV_FRM_RTZ
= 1, /* Round towards Zero */
45 RISCV_FRM_RDN
= 2, /* Round Down */
46 RISCV_FRM_RUP
= 3, /* Round Up */
47 RISCV_FRM_RMM
= 4, /* Round to Nearest, ties to Max Magnitude */
48 RISCV_FRM_DYN
= 7, /* Dynamic rounding mode */
49 RISCV_FRM_ROD
= 8, /* Round to Odd */
52 static inline uint64_t nanbox_s(CPURISCVState
*env
, float32 f
)
54 /* the value is sign-extended instead of NaN-boxing for zfinx */
55 if (RISCV_CPU(env_cpu(env
))->cfg
.ext_zfinx
) {
58 return f
| MAKE_64BIT_MASK(32, 32);
62 static inline float32
check_nanbox_s(CPURISCVState
*env
, uint64_t f
)
64 /* Disable NaN-boxing check when enable zfinx */
65 if (RISCV_CPU(env_cpu(env
))->cfg
.ext_zfinx
) {
69 uint64_t mask
= MAKE_64BIT_MASK(32, 32);
71 if (likely((f
& mask
) == mask
)) {
74 return 0x7fc00000u
; /* default qnan */
78 static inline uint64_t nanbox_h(CPURISCVState
*env
, float16 f
)
80 /* the value is sign-extended instead of NaN-boxing for zfinx */
81 if (RISCV_CPU(env_cpu(env
))->cfg
.ext_zfinx
) {
84 return f
| MAKE_64BIT_MASK(16, 48);
88 static inline float16
check_nanbox_h(CPURISCVState
*env
, uint64_t f
)
90 /* Disable nanbox check when enable zfinx */
91 if (RISCV_CPU(env_cpu(env
))->cfg
.ext_zfinx
) {
95 uint64_t mask
= MAKE_64BIT_MASK(16, 48);
97 if (likely((f
& mask
) == mask
)) {
100 return 0x7E00u
; /* default qnan */