1 /* Support for generating ACPI tables and passing them to Guests
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
7 * Author: Michael S. Tsirkin <mst@redhat.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/osdep.h"
24 #include "acpi-build.h"
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
31 #include "hw/i386/pc.h"
32 #include "target-i386/cpu.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/nvram/fw_cfg.h"
37 #include "hw/acpi/bios-linker-loader.h"
38 #include "hw/loader.h"
39 #include "hw/isa/isa.h"
40 #include "hw/block/fdc.h"
41 #include "hw/acpi/memory_hotplug.h"
42 #include "sysemu/tpm.h"
43 #include "hw/acpi/tpm.h"
44 #include "sysemu/tpm_backend.h"
45 #include "hw/timer/mc146818rtc_regs.h"
47 /* Supported chipsets: */
48 #include "hw/acpi/piix4.h"
49 #include "hw/acpi/pcihp.h"
50 #include "hw/i386/ich9.h"
51 #include "hw/pci/pci_bus.h"
52 #include "hw/pci-host/q35.h"
53 #include "hw/i386/intel_iommu.h"
54 #include "hw/timer/hpet.h"
56 #include "hw/acpi/aml-build.h"
58 #include "qapi/qmp/qint.h"
59 #include "qom/qom-qobject.h"
61 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
62 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
63 * a little bit, there should be plenty of free space since the DSDT
64 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
66 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
67 #define ACPI_BUILD_ALIGN_SIZE 0x1000
69 #define ACPI_BUILD_TABLE_SIZE 0x20000
71 /* #define DEBUG_ACPI_BUILD */
72 #ifdef DEBUG_ACPI_BUILD
73 #define ACPI_BUILD_DPRINTF(fmt, ...) \
74 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
76 #define ACPI_BUILD_DPRINTF(fmt, ...)
79 typedef struct AcpiMcfgInfo
{
84 typedef struct AcpiPmInfo
{
90 uint8_t acpi_enable_cmd
;
91 uint8_t acpi_disable_cmd
;
93 uint32_t gpe0_blk_len
;
95 uint16_t cpu_hp_io_base
;
96 uint16_t cpu_hp_io_len
;
97 uint16_t mem_hp_io_base
;
98 uint16_t mem_hp_io_len
;
99 uint16_t pcihp_io_base
;
100 uint16_t pcihp_io_len
;
103 typedef struct AcpiMiscInfo
{
106 TPMVersion tpm_version
;
107 const unsigned char *dsdt_code
;
109 uint16_t pvpanic_port
;
110 uint16_t applesmc_io_base
;
113 typedef struct AcpiBuildPciBusHotplugState
{
114 GArray
*device_table
;
115 GArray
*notify_table
;
116 struct AcpiBuildPciBusHotplugState
*parent
;
117 bool pcihp_bridge_en
;
118 } AcpiBuildPciBusHotplugState
;
120 static void acpi_get_pm_info(AcpiPmInfo
*pm
)
122 Object
*piix
= piix4_pm_find();
123 Object
*lpc
= ich9_lpc_find();
127 pm
->cpu_hp_io_base
= 0;
128 pm
->pcihp_io_base
= 0;
129 pm
->pcihp_io_len
= 0;
132 pm
->cpu_hp_io_base
= PIIX4_CPU_HOTPLUG_IO_BASE
;
134 object_property_get_int(obj
, ACPI_PCIHP_IO_BASE_PROP
, NULL
);
136 object_property_get_int(obj
, ACPI_PCIHP_IO_LEN_PROP
, NULL
);
140 pm
->cpu_hp_io_base
= ICH9_CPU_HOTPLUG_IO_BASE
;
144 pm
->cpu_hp_io_len
= ACPI_GPE_PROC_LEN
;
145 pm
->mem_hp_io_base
= ACPI_MEMORY_HOTPLUG_BASE
;
146 pm
->mem_hp_io_len
= ACPI_MEMORY_HOTPLUG_IO_LEN
;
148 /* Fill in optional s3/s4 related properties */
149 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S3_DISABLED
, NULL
);
151 pm
->s3_disabled
= qint_get_int(qobject_to_qint(o
));
153 pm
->s3_disabled
= false;
156 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_DISABLED
, NULL
);
158 pm
->s4_disabled
= qint_get_int(qobject_to_qint(o
));
160 pm
->s4_disabled
= false;
163 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_VAL
, NULL
);
165 pm
->s4_val
= qint_get_int(qobject_to_qint(o
));
171 /* Fill in mandatory properties */
172 pm
->sci_int
= object_property_get_int(obj
, ACPI_PM_PROP_SCI_INT
, NULL
);
174 pm
->acpi_enable_cmd
= object_property_get_int(obj
,
175 ACPI_PM_PROP_ACPI_ENABLE_CMD
,
177 pm
->acpi_disable_cmd
= object_property_get_int(obj
,
178 ACPI_PM_PROP_ACPI_DISABLE_CMD
,
180 pm
->io_base
= object_property_get_int(obj
, ACPI_PM_PROP_PM_IO_BASE
,
182 pm
->gpe0_blk
= object_property_get_int(obj
, ACPI_PM_PROP_GPE0_BLK
,
184 pm
->gpe0_blk_len
= object_property_get_int(obj
, ACPI_PM_PROP_GPE0_BLK_LEN
,
186 pm
->pcihp_bridge_en
=
187 object_property_get_bool(obj
, "acpi-pci-hotplug-with-bridge-support",
191 static void acpi_get_misc_info(AcpiMiscInfo
*info
)
193 Object
*piix
= piix4_pm_find();
194 Object
*lpc
= ich9_lpc_find();
195 assert(!!piix
!= !!lpc
);
198 info
->is_piix4
= true;
201 info
->is_piix4
= false;
204 info
->has_hpet
= hpet_find();
205 info
->tpm_version
= tpm_get_version();
206 info
->pvpanic_port
= pvpanic_port();
207 info
->applesmc_io_base
= applesmc_port();
211 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
212 * On i386 arch we only have two pci hosts, so we can look only for them.
214 static Object
*acpi_get_i386_pci_host(void)
218 host
= OBJECT_CHECK(PCIHostState
,
219 object_resolve_path("/machine/i440fx", NULL
),
220 TYPE_PCI_HOST_BRIDGE
);
222 host
= OBJECT_CHECK(PCIHostState
,
223 object_resolve_path("/machine/q35", NULL
),
224 TYPE_PCI_HOST_BRIDGE
);
230 static void acpi_get_pci_info(PcPciInfo
*info
)
235 pci_host
= acpi_get_i386_pci_host();
238 info
->w32
.begin
= object_property_get_int(pci_host
,
239 PCI_HOST_PROP_PCI_HOLE_START
,
241 info
->w32
.end
= object_property_get_int(pci_host
,
242 PCI_HOST_PROP_PCI_HOLE_END
,
244 info
->w64
.begin
= object_property_get_int(pci_host
,
245 PCI_HOST_PROP_PCI_HOLE64_START
,
247 info
->w64
.end
= object_property_get_int(pci_host
,
248 PCI_HOST_PROP_PCI_HOLE64_END
,
252 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
254 static void acpi_align_size(GArray
*blob
, unsigned align
)
256 /* Align size to multiple of given size. This reduces the chance
257 * we need to change size in the future (breaking cross version migration).
259 g_array_set_size(blob
, ROUND_UP(acpi_data_len(blob
), align
));
264 build_facs(GArray
*table_data
, GArray
*linker
)
266 AcpiFacsDescriptorRev1
*facs
= acpi_data_push(table_data
, sizeof *facs
);
267 memcpy(&facs
->signature
, "FACS", 4);
268 facs
->length
= cpu_to_le32(sizeof(*facs
));
271 /* Load chipset information in FADT */
272 static void fadt_setup(AcpiFadtDescriptorRev1
*fadt
, AcpiPmInfo
*pm
)
276 fadt
->sci_int
= cpu_to_le16(pm
->sci_int
);
277 fadt
->smi_cmd
= cpu_to_le32(ACPI_PORT_SMI_CMD
);
278 fadt
->acpi_enable
= pm
->acpi_enable_cmd
;
279 fadt
->acpi_disable
= pm
->acpi_disable_cmd
;
280 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
281 fadt
->pm1a_evt_blk
= cpu_to_le32(pm
->io_base
);
282 fadt
->pm1a_cnt_blk
= cpu_to_le32(pm
->io_base
+ 0x04);
283 fadt
->pm_tmr_blk
= cpu_to_le32(pm
->io_base
+ 0x08);
284 fadt
->gpe0_blk
= cpu_to_le32(pm
->gpe0_blk
);
285 /* EVT, CNT, TMR length matches hw/acpi/core.c */
286 fadt
->pm1_evt_len
= 4;
287 fadt
->pm1_cnt_len
= 2;
288 fadt
->pm_tmr_len
= 4;
289 fadt
->gpe0_blk_len
= pm
->gpe0_blk_len
;
290 fadt
->plvl2_lat
= cpu_to_le16(0xfff); /* C2 state not supported */
291 fadt
->plvl3_lat
= cpu_to_le16(0xfff); /* C3 state not supported */
292 fadt
->flags
= cpu_to_le32((1 << ACPI_FADT_F_WBINVD
) |
293 (1 << ACPI_FADT_F_PROC_C1
) |
294 (1 << ACPI_FADT_F_SLP_BUTTON
) |
295 (1 << ACPI_FADT_F_RTC_S4
));
296 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK
);
297 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
298 * For more than 8 CPUs, "Clustered Logical" mode has to be used
301 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL
);
303 fadt
->century
= RTC_CENTURY
;
309 build_fadt(GArray
*table_data
, GArray
*linker
, AcpiPmInfo
*pm
,
310 unsigned facs
, unsigned dsdt
,
311 const char *oem_id
, const char *oem_table_id
)
313 AcpiFadtDescriptorRev1
*fadt
= acpi_data_push(table_data
, sizeof(*fadt
));
315 fadt
->firmware_ctrl
= cpu_to_le32(facs
);
316 /* FACS address to be filled by Guest linker */
317 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_TABLE_FILE
,
318 ACPI_BUILD_TABLE_FILE
,
319 table_data
, &fadt
->firmware_ctrl
,
320 sizeof fadt
->firmware_ctrl
);
322 fadt
->dsdt
= cpu_to_le32(dsdt
);
323 /* DSDT address to be filled by Guest linker */
324 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_TABLE_FILE
,
325 ACPI_BUILD_TABLE_FILE
,
326 table_data
, &fadt
->dsdt
,
329 fadt_setup(fadt
, pm
);
331 build_header(linker
, table_data
,
332 (void *)fadt
, "FACP", sizeof(*fadt
), 1, oem_id
, oem_table_id
);
336 build_madt(GArray
*table_data
, GArray
*linker
, PCMachineState
*pcms
)
338 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
339 CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(MACHINE(pcms
));
340 int madt_start
= table_data
->len
;
342 AcpiMultipleApicTable
*madt
;
343 AcpiMadtIoApic
*io_apic
;
344 AcpiMadtIntsrcovr
*intsrcovr
;
345 AcpiMadtLocalNmi
*local_nmi
;
348 madt
= acpi_data_push(table_data
, sizeof *madt
);
349 madt
->local_apic_address
= cpu_to_le32(APIC_DEFAULT_ADDRESS
);
350 madt
->flags
= cpu_to_le32(1);
352 for (i
= 0; i
< apic_ids
->len
; i
++) {
353 AcpiMadtProcessorApic
*apic
= acpi_data_push(table_data
, sizeof *apic
);
354 int apic_id
= apic_ids
->cpus
[i
].arch_id
;
356 apic
->type
= ACPI_APIC_PROCESSOR
;
357 apic
->length
= sizeof(*apic
);
358 apic
->processor_id
= apic_id
;
359 apic
->local_apic_id
= apic_id
;
360 if (apic_ids
->cpus
[i
].cpu
!= NULL
) {
361 apic
->flags
= cpu_to_le32(1);
363 /* ACPI spec says that LAPIC entry for non present
364 * CPU may be omitted from MADT or it must be marked
365 * as disabled. However omitting non present CPU from
366 * MADT breaks hotplug on linux. So possible CPUs
367 * should be put in MADT but kept disabled.
369 apic
->flags
= cpu_to_le32(0);
374 io_apic
= acpi_data_push(table_data
, sizeof *io_apic
);
375 io_apic
->type
= ACPI_APIC_IO
;
376 io_apic
->length
= sizeof(*io_apic
);
377 #define ACPI_BUILD_IOAPIC_ID 0x0
378 io_apic
->io_apic_id
= ACPI_BUILD_IOAPIC_ID
;
379 io_apic
->address
= cpu_to_le32(IO_APIC_DEFAULT_ADDRESS
);
380 io_apic
->interrupt
= cpu_to_le32(0);
382 if (pcms
->apic_xrupt_override
) {
383 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
384 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
385 intsrcovr
->length
= sizeof(*intsrcovr
);
386 intsrcovr
->source
= 0;
387 intsrcovr
->gsi
= cpu_to_le32(2);
388 intsrcovr
->flags
= cpu_to_le16(0); /* conforms to bus specifications */
390 for (i
= 1; i
< 16; i
++) {
391 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
392 if (!(ACPI_BUILD_PCI_IRQS
& (1 << i
))) {
393 /* No need for a INT source override structure. */
396 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
397 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
398 intsrcovr
->length
= sizeof(*intsrcovr
);
399 intsrcovr
->source
= i
;
400 intsrcovr
->gsi
= cpu_to_le32(i
);
401 intsrcovr
->flags
= cpu_to_le16(0xd); /* active high, level triggered */
404 local_nmi
= acpi_data_push(table_data
, sizeof *local_nmi
);
405 local_nmi
->type
= ACPI_APIC_LOCAL_NMI
;
406 local_nmi
->length
= sizeof(*local_nmi
);
407 local_nmi
->processor_id
= 0xff; /* all processors */
408 local_nmi
->flags
= cpu_to_le16(0);
409 local_nmi
->lint
= 1; /* ACPI_LINT1 */
411 build_header(linker
, table_data
,
412 (void *)(table_data
->data
+ madt_start
), "APIC",
413 table_data
->len
- madt_start
, 1, NULL
, NULL
);
416 /* Assign BSEL property to all buses. In the future, this can be changed
417 * to only assign to buses that support hotplug.
419 static void *acpi_set_bsel(PCIBus
*bus
, void *opaque
)
421 unsigned *bsel_alloc
= opaque
;
424 if (qbus_is_hotpluggable(BUS(bus
))) {
425 bus_bsel
= g_malloc(sizeof *bus_bsel
);
427 *bus_bsel
= (*bsel_alloc
)++;
428 object_property_add_uint32_ptr(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
,
435 static void acpi_set_pci_info(void)
437 PCIBus
*bus
= find_i440fx(); /* TODO: Q35 support */
438 unsigned bsel_alloc
= 0;
441 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
442 pci_for_each_bus_depth_first(bus
, acpi_set_bsel
, NULL
, &bsel_alloc
);
446 static void build_append_pcihp_notify_entry(Aml
*method
, int slot
)
449 int32_t devfn
= PCI_DEVFN(slot
, 0);
451 if_ctx
= aml_if(aml_and(aml_arg(0), aml_int(0x1U
<< slot
), NULL
));
452 aml_append(if_ctx
, aml_notify(aml_name("S%.02X", devfn
), aml_arg(1)));
453 aml_append(method
, if_ctx
);
456 static void build_append_pci_bus_devices(Aml
*parent_scope
, PCIBus
*bus
,
457 bool pcihp_bridge_en
)
459 Aml
*dev
, *notify_method
, *method
;
464 bsel
= object_property_get_qobject(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
, NULL
);
466 int64_t bsel_val
= qint_get_int(qobject_to_qint(bsel
));
468 aml_append(parent_scope
, aml_name_decl("BSEL", aml_int(bsel_val
)));
469 notify_method
= aml_method("DVNT", 2, AML_NOTSERIALIZED
);
472 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); i
+= PCI_FUNC_MAX
) {
475 PCIDevice
*pdev
= bus
->devices
[i
];
476 int slot
= PCI_SLOT(i
);
477 bool hotplug_enabled_dev
;
481 if (bsel
) { /* add hotplug slots for non present devices */
482 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
483 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
484 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
485 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
487 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
489 aml_append(dev
, method
);
490 aml_append(parent_scope
, dev
);
492 build_append_pcihp_notify_entry(notify_method
, slot
);
497 pc
= PCI_DEVICE_GET_CLASS(pdev
);
498 dc
= DEVICE_GET_CLASS(pdev
);
500 /* When hotplug for bridges is enabled, bridges are
501 * described in ACPI separately (see build_pci_bus_end).
502 * In this case they aren't themselves hot-pluggable.
503 * Hotplugged bridges *are* hot-pluggable.
505 bridge_in_acpi
= pc
->is_bridge
&& pcihp_bridge_en
&&
506 !DEVICE(pdev
)->hotplugged
;
508 hotplug_enabled_dev
= bsel
&& dc
->hotpluggable
&& !bridge_in_acpi
;
510 if (pc
->class_id
== PCI_CLASS_BRIDGE_ISA
) {
514 /* start to compose PCI slot descriptor */
515 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
516 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
518 if (pc
->class_id
== PCI_CLASS_DISPLAY_VGA
) {
519 /* add VGA specific AML methods */
522 if (object_dynamic_cast(OBJECT(pdev
), "qxl-vga")) {
528 method
= aml_method("_S1D", 0, AML_NOTSERIALIZED
);
529 aml_append(method
, aml_return(aml_int(0)));
530 aml_append(dev
, method
);
532 method
= aml_method("_S2D", 0, AML_NOTSERIALIZED
);
533 aml_append(method
, aml_return(aml_int(0)));
534 aml_append(dev
, method
);
536 method
= aml_method("_S3D", 0, AML_NOTSERIALIZED
);
537 aml_append(method
, aml_return(aml_int(s3d
)));
538 aml_append(dev
, method
);
539 } else if (hotplug_enabled_dev
) {
540 /* add _SUN/_EJ0 to make slot hotpluggable */
541 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
543 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
545 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
547 aml_append(dev
, method
);
550 build_append_pcihp_notify_entry(notify_method
, slot
);
552 } else if (bridge_in_acpi
) {
554 * device is coldplugged bridge,
555 * add child device descriptions into its scope
557 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
559 build_append_pci_bus_devices(dev
, sec_bus
, pcihp_bridge_en
);
561 /* slot descriptor has been composed, add it into parent context */
562 aml_append(parent_scope
, dev
);
566 aml_append(parent_scope
, notify_method
);
569 /* Append PCNT method to notify about events on local and child buses.
570 * Add unconditionally for root since DSDT expects it.
572 method
= aml_method("PCNT", 0, AML_NOTSERIALIZED
);
574 /* If bus supports hotplug select it and notify about local events */
576 int64_t bsel_val
= qint_get_int(qobject_to_qint(bsel
));
577 aml_append(method
, aml_store(aml_int(bsel_val
), aml_name("BNUM")));
579 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
582 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
586 /* Notify about child bus events in any case */
587 if (pcihp_bridge_en
) {
588 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
589 int32_t devfn
= sec
->parent_dev
->devfn
;
591 aml_append(method
, aml_name("^S%.02X.PCNT", devfn
));
594 aml_append(parent_scope
, method
);
595 qobject_decref(bsel
);
600 * @link_name: link name for PCI route entry
602 * build AML package containing a PCI route entry for @link_name
604 static Aml
*build_prt_entry(const char *link_name
)
606 Aml
*a_zero
= aml_int(0);
607 Aml
*pkg
= aml_package(4);
608 aml_append(pkg
, a_zero
);
609 aml_append(pkg
, a_zero
);
610 aml_append(pkg
, aml_name("%s", link_name
));
611 aml_append(pkg
, a_zero
);
616 * initialize_route - Initialize the interrupt routing rule
617 * through a specific LINK:
618 * if (lnk_idx == idx)
619 * route using link 'link_name'
621 static Aml
*initialize_route(Aml
*route
, const char *link_name
,
622 Aml
*lnk_idx
, int idx
)
624 Aml
*if_ctx
= aml_if(aml_equal(lnk_idx
, aml_int(idx
)));
625 Aml
*pkg
= build_prt_entry(link_name
);
627 aml_append(if_ctx
, aml_store(pkg
, route
));
633 * build_prt - Define interrupt rounting rules
635 * Returns an array of 128 routes, one for each device,
636 * based on device location.
637 * The main goal is to equaly distribute the interrupts
638 * over the 4 existing ACPI links (works only for i440fx).
639 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
642 static Aml
*build_prt(bool is_pci0_prt
)
644 Aml
*method
, *while_ctx
, *pin
, *res
;
646 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
649 aml_append(method
, aml_store(aml_package(128), res
));
650 aml_append(method
, aml_store(aml_int(0), pin
));
652 /* while (pin < 128) */
653 while_ctx
= aml_while(aml_lless(pin
, aml_int(128)));
655 Aml
*slot
= aml_local(2);
656 Aml
*lnk_idx
= aml_local(3);
657 Aml
*route
= aml_local(4);
659 /* slot = pin >> 2 */
660 aml_append(while_ctx
,
661 aml_store(aml_shiftright(pin
, aml_int(2), NULL
), slot
));
662 /* lnk_idx = (slot + pin) & 3 */
663 aml_append(while_ctx
,
664 aml_store(aml_and(aml_add(pin
, slot
, NULL
), aml_int(3), NULL
),
667 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
668 aml_append(while_ctx
, initialize_route(route
, "LNKD", lnk_idx
, 0));
670 Aml
*if_device_1
, *if_pin_4
, *else_pin_4
;
672 /* device 1 is the power-management device, needs SCI */
673 if_device_1
= aml_if(aml_equal(lnk_idx
, aml_int(1)));
675 if_pin_4
= aml_if(aml_equal(pin
, aml_int(4)));
678 aml_store(build_prt_entry("LNKS"), route
));
680 aml_append(if_device_1
, if_pin_4
);
681 else_pin_4
= aml_else();
683 aml_append(else_pin_4
,
684 aml_store(build_prt_entry("LNKA"), route
));
686 aml_append(if_device_1
, else_pin_4
);
688 aml_append(while_ctx
, if_device_1
);
690 aml_append(while_ctx
, initialize_route(route
, "LNKA", lnk_idx
, 1));
692 aml_append(while_ctx
, initialize_route(route
, "LNKB", lnk_idx
, 2));
693 aml_append(while_ctx
, initialize_route(route
, "LNKC", lnk_idx
, 3));
695 /* route[0] = 0x[slot]FFFF */
696 aml_append(while_ctx
,
697 aml_store(aml_or(aml_shiftleft(slot
, aml_int(16)), aml_int(0xFFFF),
699 aml_index(route
, aml_int(0))));
700 /* route[1] = pin & 3 */
701 aml_append(while_ctx
,
702 aml_store(aml_and(pin
, aml_int(3), NULL
),
703 aml_index(route
, aml_int(1))));
704 /* res[pin] = route */
705 aml_append(while_ctx
, aml_store(route
, aml_index(res
, pin
)));
707 aml_append(while_ctx
, aml_increment(pin
));
709 aml_append(method
, while_ctx
);
711 aml_append(method
, aml_return(res
));
716 typedef struct CrsRangeEntry
{
721 static void crs_range_insert(GPtrArray
*ranges
, uint64_t base
, uint64_t limit
)
723 CrsRangeEntry
*entry
;
725 entry
= g_malloc(sizeof(*entry
));
727 entry
->limit
= limit
;
729 g_ptr_array_add(ranges
, entry
);
732 static void crs_range_free(gpointer data
)
734 CrsRangeEntry
*entry
= (CrsRangeEntry
*)data
;
738 static gint
crs_range_compare(gconstpointer a
, gconstpointer b
)
740 CrsRangeEntry
*entry_a
= *(CrsRangeEntry
**)a
;
741 CrsRangeEntry
*entry_b
= *(CrsRangeEntry
**)b
;
743 return (int64_t)entry_a
->base
- (int64_t)entry_b
->base
;
747 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
748 * interval, computes the 'free' ranges from the same interval.
749 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
750 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
752 static void crs_replace_with_free_ranges(GPtrArray
*ranges
,
753 uint64_t start
, uint64_t end
)
755 GPtrArray
*free_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
756 uint64_t free_base
= start
;
759 g_ptr_array_sort(ranges
, crs_range_compare
);
760 for (i
= 0; i
< ranges
->len
; i
++) {
761 CrsRangeEntry
*used
= g_ptr_array_index(ranges
, i
);
763 if (free_base
< used
->base
) {
764 crs_range_insert(free_ranges
, free_base
, used
->base
- 1);
767 free_base
= used
->limit
+ 1;
770 if (free_base
< end
) {
771 crs_range_insert(free_ranges
, free_base
, end
);
774 g_ptr_array_set_size(ranges
, 0);
775 for (i
= 0; i
< free_ranges
->len
; i
++) {
776 g_ptr_array_add(ranges
, g_ptr_array_index(free_ranges
, i
));
779 g_ptr_array_free(free_ranges
, false);
783 * crs_range_merge - merges adjacent ranges in the given array.
784 * Array elements are deleted and replaced with the merged ranges.
786 static void crs_range_merge(GPtrArray
*range
)
788 GPtrArray
*tmp
= g_ptr_array_new_with_free_func(crs_range_free
);
789 CrsRangeEntry
*entry
;
790 uint64_t range_base
, range_limit
;
797 g_ptr_array_sort(range
, crs_range_compare
);
799 entry
= g_ptr_array_index(range
, 0);
800 range_base
= entry
->base
;
801 range_limit
= entry
->limit
;
802 for (i
= 1; i
< range
->len
; i
++) {
803 entry
= g_ptr_array_index(range
, i
);
804 if (entry
->base
- 1 == range_limit
) {
805 range_limit
= entry
->limit
;
807 crs_range_insert(tmp
, range_base
, range_limit
);
808 range_base
= entry
->base
;
809 range_limit
= entry
->limit
;
812 crs_range_insert(tmp
, range_base
, range_limit
);
814 g_ptr_array_set_size(range
, 0);
815 for (i
= 0; i
< tmp
->len
; i
++) {
816 entry
= g_ptr_array_index(tmp
, i
);
817 crs_range_insert(range
, entry
->base
, entry
->limit
);
819 g_ptr_array_free(tmp
, true);
822 static Aml
*build_crs(PCIHostState
*host
,
823 GPtrArray
*io_ranges
, GPtrArray
*mem_ranges
)
825 Aml
*crs
= aml_resource_template();
826 GPtrArray
*host_io_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
827 GPtrArray
*host_mem_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
828 CrsRangeEntry
*entry
;
829 uint8_t max_bus
= pci_bus_num(host
->bus
);
834 for (devfn
= 0; devfn
< ARRAY_SIZE(host
->bus
->devices
); devfn
++) {
835 uint64_t range_base
, range_limit
;
836 PCIDevice
*dev
= host
->bus
->devices
[devfn
];
842 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
843 PCIIORegion
*r
= &dev
->io_regions
[i
];
845 range_base
= r
->addr
;
846 range_limit
= r
->addr
+ r
->size
- 1;
849 * Work-around for old bioses
850 * that do not support multiple root buses
852 if (!range_base
|| range_base
> range_limit
) {
856 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
857 crs_range_insert(host_io_ranges
, range_base
, range_limit
);
858 } else { /* "memory" */
859 crs_range_insert(host_mem_ranges
, range_base
, range_limit
);
863 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
864 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
865 uint8_t subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
866 if (subordinate
> max_bus
) {
867 max_bus
= subordinate
;
870 range_base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
871 range_limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
874 * Work-around for old bioses
875 * that do not support multiple root buses
877 if (range_base
&& range_base
<= range_limit
) {
878 crs_range_insert(host_io_ranges
, range_base
, range_limit
);
882 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
884 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
887 * Work-around for old bioses
888 * that do not support multiple root buses
890 if (range_base
&& range_base
<= range_limit
) {
891 crs_range_insert(host_mem_ranges
, range_base
, range_limit
);
895 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
897 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
900 * Work-around for old bioses
901 * that do not support multiple root buses
903 if (range_base
&& range_base
<= range_limit
) {
904 crs_range_insert(host_mem_ranges
, range_base
, range_limit
);
909 crs_range_merge(host_io_ranges
);
910 for (i
= 0; i
< host_io_ranges
->len
; i
++) {
911 entry
= g_ptr_array_index(host_io_ranges
, i
);
913 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
914 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
915 0, entry
->base
, entry
->limit
, 0,
916 entry
->limit
- entry
->base
+ 1));
917 crs_range_insert(io_ranges
, entry
->base
, entry
->limit
);
919 g_ptr_array_free(host_io_ranges
, true);
921 crs_range_merge(host_mem_ranges
);
922 for (i
= 0; i
< host_mem_ranges
->len
; i
++) {
923 entry
= g_ptr_array_index(host_mem_ranges
, i
);
925 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
926 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
928 0, entry
->base
, entry
->limit
, 0,
929 entry
->limit
- entry
->base
+ 1));
930 crs_range_insert(mem_ranges
, entry
->base
, entry
->limit
);
932 g_ptr_array_free(host_mem_ranges
, true);
935 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
937 pci_bus_num(host
->bus
),
940 max_bus
- pci_bus_num(host
->bus
) + 1));
945 static void build_processor_devices(Aml
*sb_scope
, MachineState
*machine
,
955 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
956 CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(machine
);
957 PCMachineState
*pcms
= PC_MACHINE(machine
);
959 /* The current AML generator can cover the APIC ID range [0..255],
960 * inclusive, for VCPU hotplug. */
961 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT
> 256);
962 g_assert(pcms
->apic_id_limit
<= ACPI_CPU_HOTPLUG_ID_LIMIT
);
964 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
965 dev
= aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE
));
966 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
968 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
970 /* device present, functioning, decoding, not shown in UI */
971 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
972 crs
= aml_resource_template();
974 aml_io(AML_DECODE16
, pm
->cpu_hp_io_base
, pm
->cpu_hp_io_base
, 1,
977 aml_append(dev
, aml_name_decl("_CRS", crs
));
978 aml_append(sb_scope
, dev
);
979 /* declare CPU hotplug MMIO region and PRS field to access it */
980 aml_append(sb_scope
, aml_operation_region(
981 "PRST", AML_SYSTEM_IO
, aml_int(pm
->cpu_hp_io_base
), pm
->cpu_hp_io_len
));
982 field
= aml_field("PRST", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
983 aml_append(field
, aml_named_field("PRS", 256));
984 aml_append(sb_scope
, field
);
986 /* build Processor object for each processor */
987 for (i
= 0; i
< apic_ids
->len
; i
++) {
988 int apic_id
= apic_ids
->cpus
[i
].arch_id
;
990 assert(apic_id
< ACPI_CPU_HOTPLUG_ID_LIMIT
);
992 dev
= aml_processor(apic_id
, 0, 0, "CP%.02X", apic_id
);
994 method
= aml_method("_MAT", 0, AML_NOTSERIALIZED
);
996 aml_return(aml_call1(CPU_MAT_METHOD
, aml_int(apic_id
))));
997 aml_append(dev
, method
);
999 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1001 aml_return(aml_call1(CPU_STATUS_METHOD
, aml_int(apic_id
))));
1002 aml_append(dev
, method
);
1004 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
1006 aml_return(aml_call2(CPU_EJECT_METHOD
, aml_int(apic_id
),
1009 aml_append(dev
, method
);
1011 aml_append(sb_scope
, dev
);
1015 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
1017 /* Arg0 = Processor ID = APIC ID */
1018 method
= aml_method(AML_NOTIFY_METHOD
, 2, AML_NOTSERIALIZED
);
1019 for (i
= 0; i
< apic_ids
->len
; i
++) {
1020 int apic_id
= apic_ids
->cpus
[i
].arch_id
;
1022 ifctx
= aml_if(aml_equal(aml_arg(0), aml_int(apic_id
)));
1024 aml_notify(aml_name("CP%.02X", apic_id
), aml_arg(1))
1026 aml_append(method
, ifctx
);
1028 aml_append(sb_scope
, method
);
1030 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1032 * Note: The ability to create variable-sized packages was first
1033 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1034 * ith up to 255 elements. Windows guests up to win2k8 fail when
1035 * VarPackageOp is used.
1037 pkg
= pcms
->apic_id_limit
<= 255 ? aml_package(pcms
->apic_id_limit
) :
1038 aml_varpackage(pcms
->apic_id_limit
);
1040 for (i
= 0, apic_idx
= 0; i
< apic_ids
->len
; i
++) {
1041 int apic_id
= apic_ids
->cpus
[i
].arch_id
;
1043 for (; apic_idx
< apic_id
; apic_idx
++) {
1044 aml_append(pkg
, aml_int(0));
1046 aml_append(pkg
, aml_int(apic_ids
->cpus
[i
].cpu
? 1 : 0));
1047 apic_idx
= apic_id
+ 1;
1049 aml_append(sb_scope
, aml_name_decl(CPU_ON_BITMAP
, pkg
));
1053 static void build_memory_devices(Aml
*sb_scope
, int nr_mem
,
1054 uint16_t io_base
, uint16_t io_len
)
1064 /* build memory devices */
1065 assert(nr_mem
<= ACPI_MAX_RAM_SLOTS
);
1066 scope
= aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE
);
1068 aml_name_decl(MEMORY_SLOTS_NUMBER
, aml_int(nr_mem
))
1071 crs
= aml_resource_template();
1073 aml_io(AML_DECODE16
, io_base
, io_base
, 0, io_len
)
1075 aml_append(scope
, aml_name_decl("_CRS", crs
));
1077 aml_append(scope
, aml_operation_region(
1078 MEMORY_HOTPLUG_IO_REGION
, AML_SYSTEM_IO
,
1079 aml_int(io_base
), io_len
)
1082 field
= aml_field(MEMORY_HOTPLUG_IO_REGION
, AML_DWORD_ACC
,
1083 AML_NOLOCK
, AML_PRESERVE
);
1084 aml_append(field
, /* read only */
1085 aml_named_field(MEMORY_SLOT_ADDR_LOW
, 32));
1086 aml_append(field
, /* read only */
1087 aml_named_field(MEMORY_SLOT_ADDR_HIGH
, 32));
1088 aml_append(field
, /* read only */
1089 aml_named_field(MEMORY_SLOT_SIZE_LOW
, 32));
1090 aml_append(field
, /* read only */
1091 aml_named_field(MEMORY_SLOT_SIZE_HIGH
, 32));
1092 aml_append(field
, /* read only */
1093 aml_named_field(MEMORY_SLOT_PROXIMITY
, 32));
1094 aml_append(scope
, field
);
1096 field
= aml_field(MEMORY_HOTPLUG_IO_REGION
, AML_BYTE_ACC
,
1097 AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1098 aml_append(field
, aml_reserved_field(160 /* bits, Offset(20) */));
1099 aml_append(field
, /* 1 if enabled, read only */
1100 aml_named_field(MEMORY_SLOT_ENABLED
, 1));
1102 /*(read) 1 if has a insert event. (write) 1 to clear event */
1103 aml_named_field(MEMORY_SLOT_INSERT_EVENT
, 1));
1105 /* (read) 1 if has a remove event. (write) 1 to clear event */
1106 aml_named_field(MEMORY_SLOT_REMOVE_EVENT
, 1));
1108 /* initiates device eject, write only */
1109 aml_named_field(MEMORY_SLOT_EJECT
, 1));
1110 aml_append(scope
, field
);
1112 field
= aml_field(MEMORY_HOTPLUG_IO_REGION
, AML_DWORD_ACC
,
1113 AML_NOLOCK
, AML_PRESERVE
);
1114 aml_append(field
, /* DIMM selector, write only */
1115 aml_named_field(MEMORY_SLOT_SLECTOR
, 32));
1116 aml_append(field
, /* _OST event code, write only */
1117 aml_named_field(MEMORY_SLOT_OST_EVENT
, 32));
1118 aml_append(field
, /* _OST status code, write only */
1119 aml_named_field(MEMORY_SLOT_OST_STATUS
, 32));
1120 aml_append(scope
, field
);
1121 aml_append(sb_scope
, scope
);
1123 for (i
= 0; i
< nr_mem
; i
++) {
1124 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
1127 dev
= aml_device("MP%02X", i
);
1128 aml_append(dev
, aml_name_decl("_UID", aml_string("0x%02X", i
)));
1129 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1131 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1132 s
= BASEPATH MEMORY_SLOT_CRS_METHOD
;
1133 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1134 aml_append(dev
, method
);
1136 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1137 s
= BASEPATH MEMORY_SLOT_STATUS_METHOD
;
1138 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1139 aml_append(dev
, method
);
1141 method
= aml_method("_PXM", 0, AML_NOTSERIALIZED
);
1142 s
= BASEPATH MEMORY_SLOT_PROXIMITY_METHOD
;
1143 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1144 aml_append(dev
, method
);
1146 method
= aml_method("_OST", 3, AML_NOTSERIALIZED
);
1147 s
= BASEPATH MEMORY_SLOT_OST_METHOD
;
1149 aml_append(method
, aml_return(aml_call4(
1150 s
, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1152 aml_append(dev
, method
);
1154 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
1155 s
= BASEPATH MEMORY_SLOT_EJECT_METHOD
;
1156 aml_append(method
, aml_return(aml_call2(
1157 s
, aml_name("_UID"), aml_arg(0))));
1158 aml_append(dev
, method
);
1160 aml_append(sb_scope
, dev
);
1163 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1164 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1166 method
= aml_method(MEMORY_SLOT_NOTIFY_METHOD
, 2, AML_NOTSERIALIZED
);
1167 for (i
= 0; i
< nr_mem
; i
++) {
1168 ifctx
= aml_if(aml_equal(aml_arg(0), aml_int(i
)));
1170 aml_notify(aml_name("MP%.02X", i
), aml_arg(1))
1172 aml_append(method
, ifctx
);
1174 aml_append(sb_scope
, method
);
1177 static void build_hpet_aml(Aml
*table
)
1183 Aml
*scope
= aml_scope("_SB");
1184 Aml
*dev
= aml_device("HPET");
1185 Aml
*zero
= aml_int(0);
1186 Aml
*id
= aml_local(0);
1187 Aml
*period
= aml_local(1);
1189 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1190 aml_append(dev
, aml_name_decl("_UID", zero
));
1193 aml_operation_region("HPTM", AML_SYSTEM_MEMORY
, aml_int(HPET_BASE
),
1195 field
= aml_field("HPTM", AML_DWORD_ACC
, AML_LOCK
, AML_PRESERVE
);
1196 aml_append(field
, aml_named_field("VEND", 32));
1197 aml_append(field
, aml_named_field("PRD", 32));
1198 aml_append(dev
, field
);
1200 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1201 aml_append(method
, aml_store(aml_name("VEND"), id
));
1202 aml_append(method
, aml_store(aml_name("PRD"), period
));
1203 aml_append(method
, aml_shiftright(id
, aml_int(16), id
));
1204 if_ctx
= aml_if(aml_lor(aml_equal(id
, zero
),
1205 aml_equal(id
, aml_int(0xffff))));
1207 aml_append(if_ctx
, aml_return(zero
));
1209 aml_append(method
, if_ctx
);
1211 if_ctx
= aml_if(aml_lor(aml_equal(period
, zero
),
1212 aml_lgreater(period
, aml_int(100000000))));
1214 aml_append(if_ctx
, aml_return(zero
));
1216 aml_append(method
, if_ctx
);
1218 aml_append(method
, aml_return(aml_int(0x0F)));
1219 aml_append(dev
, method
);
1221 crs
= aml_resource_template();
1222 aml_append(crs
, aml_memory32_fixed(HPET_BASE
, HPET_LEN
, AML_READ_ONLY
));
1223 aml_append(dev
, aml_name_decl("_CRS", crs
));
1225 aml_append(scope
, dev
);
1226 aml_append(table
, scope
);
1229 static Aml
*build_fdinfo_aml(int idx
, FloppyDriveType type
)
1232 uint8_t maxc
, maxh
, maxs
;
1234 isa_fdc_get_drive_max_chs(type
, &maxc
, &maxh
, &maxs
);
1236 dev
= aml_device("FLP%c", 'A' + idx
);
1238 aml_append(dev
, aml_name_decl("_ADR", aml_int(idx
)));
1240 fdi
= aml_package(16);
1241 aml_append(fdi
, aml_int(idx
)); /* Drive Number */
1243 aml_int(cmos_get_fd_drive_type(type
))); /* Device Type */
1245 * the values below are the limits of the drive, and are thus independent
1246 * of the inserted media
1248 aml_append(fdi
, aml_int(maxc
)); /* Maximum Cylinder Number */
1249 aml_append(fdi
, aml_int(maxs
)); /* Maximum Sector Number */
1250 aml_append(fdi
, aml_int(maxh
)); /* Maximum Head Number */
1252 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1253 * the drive type, so shall we
1255 aml_append(fdi
, aml_int(0xAF)); /* disk_specify_1 */
1256 aml_append(fdi
, aml_int(0x02)); /* disk_specify_2 */
1257 aml_append(fdi
, aml_int(0x25)); /* disk_motor_wait */
1258 aml_append(fdi
, aml_int(0x02)); /* disk_sector_siz */
1259 aml_append(fdi
, aml_int(0x12)); /* disk_eot */
1260 aml_append(fdi
, aml_int(0x1B)); /* disk_rw_gap */
1261 aml_append(fdi
, aml_int(0xFF)); /* disk_dtl */
1262 aml_append(fdi
, aml_int(0x6C)); /* disk_formt_gap */
1263 aml_append(fdi
, aml_int(0xF6)); /* disk_fill */
1264 aml_append(fdi
, aml_int(0x0F)); /* disk_head_sttl */
1265 aml_append(fdi
, aml_int(0x08)); /* disk_motor_strt */
1267 aml_append(dev
, aml_name_decl("_FDI", fdi
));
1271 static Aml
*build_fdc_device_aml(ISADevice
*fdc
)
1277 #define ACPI_FDE_MAX_FD 4
1278 uint32_t fde_buf
[5] = {
1279 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1280 cpu_to_le32(2) /* tape presence (2 == never present) */
1283 dev
= aml_device("FDC0");
1284 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1286 crs
= aml_resource_template();
1287 aml_append(crs
, aml_io(AML_DECODE16
, 0x03F2, 0x03F2, 0x00, 0x04));
1288 aml_append(crs
, aml_io(AML_DECODE16
, 0x03F7, 0x03F7, 0x00, 0x01));
1289 aml_append(crs
, aml_irq_no_flags(6));
1291 aml_dma(AML_COMPATIBILITY
, AML_NOTBUSMASTER
, AML_TRANSFER8
, 2));
1292 aml_append(dev
, aml_name_decl("_CRS", crs
));
1294 for (i
= 0; i
< MIN(MAX_FD
, ACPI_FDE_MAX_FD
); i
++) {
1295 FloppyDriveType type
= isa_fdc_get_drive_type(fdc
, i
);
1297 if (type
< FLOPPY_DRIVE_TYPE_NONE
) {
1298 fde_buf
[i
] = cpu_to_le32(1); /* drive present */
1299 aml_append(dev
, build_fdinfo_aml(i
, type
));
1302 aml_append(dev
, aml_name_decl("_FDE",
1303 aml_buffer(sizeof(fde_buf
), (uint8_t *)fde_buf
)));
1308 static Aml
*build_rtc_device_aml(void)
1313 dev
= aml_device("RTC");
1314 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1315 crs
= aml_resource_template();
1316 aml_append(crs
, aml_io(AML_DECODE16
, 0x0070, 0x0070, 0x10, 0x02));
1317 aml_append(crs
, aml_irq_no_flags(8));
1318 aml_append(crs
, aml_io(AML_DECODE16
, 0x0072, 0x0072, 0x02, 0x06));
1319 aml_append(dev
, aml_name_decl("_CRS", crs
));
1324 static Aml
*build_kbd_device_aml(void)
1330 dev
= aml_device("KBD");
1331 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1333 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1334 aml_append(method
, aml_return(aml_int(0x0f)));
1335 aml_append(dev
, method
);
1337 crs
= aml_resource_template();
1338 aml_append(crs
, aml_io(AML_DECODE16
, 0x0060, 0x0060, 0x01, 0x01));
1339 aml_append(crs
, aml_io(AML_DECODE16
, 0x0064, 0x0064, 0x01, 0x01));
1340 aml_append(crs
, aml_irq_no_flags(1));
1341 aml_append(dev
, aml_name_decl("_CRS", crs
));
1346 static Aml
*build_mouse_device_aml(void)
1352 dev
= aml_device("MOU");
1353 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1355 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1356 aml_append(method
, aml_return(aml_int(0x0f)));
1357 aml_append(dev
, method
);
1359 crs
= aml_resource_template();
1360 aml_append(crs
, aml_irq_no_flags(12));
1361 aml_append(dev
, aml_name_decl("_CRS", crs
));
1366 static Aml
*build_lpt_device_aml(void)
1373 Aml
*zero
= aml_int(0);
1374 Aml
*is_present
= aml_local(0);
1376 dev
= aml_device("LPT");
1377 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1379 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1380 aml_append(method
, aml_store(aml_name("LPEN"), is_present
));
1381 if_ctx
= aml_if(aml_equal(is_present
, zero
));
1383 aml_append(if_ctx
, aml_return(aml_int(0x00)));
1385 aml_append(method
, if_ctx
);
1386 else_ctx
= aml_else();
1388 aml_append(else_ctx
, aml_return(aml_int(0x0f)));
1390 aml_append(method
, else_ctx
);
1391 aml_append(dev
, method
);
1393 crs
= aml_resource_template();
1394 aml_append(crs
, aml_io(AML_DECODE16
, 0x0378, 0x0378, 0x08, 0x08));
1395 aml_append(crs
, aml_irq_no_flags(7));
1396 aml_append(dev
, aml_name_decl("_CRS", crs
));
1401 static Aml
*build_com_device_aml(uint8_t uid
)
1408 Aml
*zero
= aml_int(0);
1409 Aml
*is_present
= aml_local(0);
1410 const char *enabled_field
= "CAEN";
1412 uint16_t io_port
= 0x03F8;
1414 assert(uid
== 1 || uid
== 2);
1416 enabled_field
= "CBEN";
1421 dev
= aml_device("COM%d", uid
);
1422 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1423 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1425 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1426 aml_append(method
, aml_store(aml_name("%s", enabled_field
), is_present
));
1427 if_ctx
= aml_if(aml_equal(is_present
, zero
));
1429 aml_append(if_ctx
, aml_return(aml_int(0x00)));
1431 aml_append(method
, if_ctx
);
1432 else_ctx
= aml_else();
1434 aml_append(else_ctx
, aml_return(aml_int(0x0f)));
1436 aml_append(method
, else_ctx
);
1437 aml_append(dev
, method
);
1439 crs
= aml_resource_template();
1440 aml_append(crs
, aml_io(AML_DECODE16
, io_port
, io_port
, 0x00, 0x08));
1441 aml_append(crs
, aml_irq_no_flags(irq
));
1442 aml_append(dev
, aml_name_decl("_CRS", crs
));
1447 static void build_isa_devices_aml(Aml
*table
)
1449 ISADevice
*fdc
= pc_find_fdc0();
1451 Aml
*scope
= aml_scope("_SB.PCI0.ISA");
1453 aml_append(scope
, build_rtc_device_aml());
1454 aml_append(scope
, build_kbd_device_aml());
1455 aml_append(scope
, build_mouse_device_aml());
1457 aml_append(scope
, build_fdc_device_aml(fdc
));
1459 aml_append(scope
, build_lpt_device_aml());
1460 aml_append(scope
, build_com_device_aml(1));
1461 aml_append(scope
, build_com_device_aml(2));
1463 aml_append(table
, scope
);
1466 static void build_dbg_aml(Aml
*table
)
1471 Aml
*scope
= aml_scope("\\");
1472 Aml
*buf
= aml_local(0);
1473 Aml
*len
= aml_local(1);
1474 Aml
*idx
= aml_local(2);
1477 aml_operation_region("DBG", AML_SYSTEM_IO
, aml_int(0x0402), 0x01));
1478 field
= aml_field("DBG", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1479 aml_append(field
, aml_named_field("DBGB", 8));
1480 aml_append(scope
, field
);
1482 method
= aml_method("DBUG", 1, AML_NOTSERIALIZED
);
1484 aml_append(method
, aml_to_hexstring(aml_arg(0), buf
));
1485 aml_append(method
, aml_to_buffer(buf
, buf
));
1486 aml_append(method
, aml_subtract(aml_sizeof(buf
), aml_int(1), len
));
1487 aml_append(method
, aml_store(aml_int(0), idx
));
1489 while_ctx
= aml_while(aml_lless(idx
, len
));
1490 aml_append(while_ctx
,
1491 aml_store(aml_derefof(aml_index(buf
, idx
)), aml_name("DBGB")));
1492 aml_append(while_ctx
, aml_increment(idx
));
1493 aml_append(method
, while_ctx
);
1495 aml_append(method
, aml_store(aml_int(0x0A), aml_name("DBGB")));
1496 aml_append(scope
, method
);
1498 aml_append(table
, scope
);
1501 static Aml
*build_link_dev(const char *name
, uint8_t uid
, Aml
*reg
)
1506 uint32_t irqs
[] = {5, 10, 11};
1508 dev
= aml_device("%s", name
);
1509 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1510 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1512 crs
= aml_resource_template();
1513 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1514 AML_SHARED
, irqs
, ARRAY_SIZE(irqs
)));
1515 aml_append(dev
, aml_name_decl("_PRS", crs
));
1517 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1518 aml_append(method
, aml_return(aml_call1("IQST", reg
)));
1519 aml_append(dev
, method
);
1521 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1522 aml_append(method
, aml_or(reg
, aml_int(0x80), reg
));
1523 aml_append(dev
, method
);
1525 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1526 aml_append(method
, aml_return(aml_call1("IQCR", reg
)));
1527 aml_append(dev
, method
);
1529 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1530 aml_append(method
, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1531 aml_append(method
, aml_store(aml_name("PRRI"), reg
));
1532 aml_append(dev
, method
);
1537 static Aml
*build_gsi_link_dev(const char *name
, uint8_t uid
, uint8_t gsi
)
1544 dev
= aml_device("%s", name
);
1545 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1546 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1548 crs
= aml_resource_template();
1550 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1551 AML_SHARED
, &irqs
, 1));
1552 aml_append(dev
, aml_name_decl("_PRS", crs
));
1554 aml_append(dev
, aml_name_decl("_CRS", crs
));
1557 * _DIS can be no-op because the interrupt cannot be disabled.
1559 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1560 aml_append(dev
, method
);
1562 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1563 aml_append(dev
, method
);
1568 /* _CRS method - get current settings */
1569 static Aml
*build_iqcr_method(bool is_piix4
)
1573 Aml
*method
= aml_method("IQCR", 1, AML_SERIALIZED
);
1574 Aml
*crs
= aml_resource_template();
1577 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1578 AML_ACTIVE_HIGH
, AML_SHARED
, &irqs
, 1));
1579 aml_append(method
, aml_name_decl("PRR0", crs
));
1582 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1585 if_ctx
= aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1586 aml_append(if_ctx
, aml_store(aml_arg(0), aml_name("PRRI")));
1587 aml_append(method
, if_ctx
);
1590 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL
),
1594 aml_append(method
, aml_return(aml_name("PRR0")));
1598 /* _STA method - get status */
1599 static Aml
*build_irq_status_method(void)
1602 Aml
*method
= aml_method("IQST", 1, AML_NOTSERIALIZED
);
1604 if_ctx
= aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL
));
1605 aml_append(if_ctx
, aml_return(aml_int(0x09)));
1606 aml_append(method
, if_ctx
);
1607 aml_append(method
, aml_return(aml_int(0x0B)));
1611 static void build_piix4_pci0_int(Aml
*table
)
1618 Aml
*sb_scope
= aml_scope("_SB");
1619 Aml
*pci0_scope
= aml_scope("PCI0");
1621 aml_append(pci0_scope
, build_prt(true));
1622 aml_append(sb_scope
, pci0_scope
);
1624 field
= aml_field("PCI0.ISA.P40C", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1625 aml_append(field
, aml_named_field("PRQ0", 8));
1626 aml_append(field
, aml_named_field("PRQ1", 8));
1627 aml_append(field
, aml_named_field("PRQ2", 8));
1628 aml_append(field
, aml_named_field("PRQ3", 8));
1629 aml_append(sb_scope
, field
);
1631 aml_append(sb_scope
, build_irq_status_method());
1632 aml_append(sb_scope
, build_iqcr_method(true));
1634 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1635 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1636 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1637 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1639 dev
= aml_device("LNKS");
1641 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1642 aml_append(dev
, aml_name_decl("_UID", aml_int(4)));
1644 crs
= aml_resource_template();
1646 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1647 AML_ACTIVE_HIGH
, AML_SHARED
,
1649 aml_append(dev
, aml_name_decl("_PRS", crs
));
1651 /* The SCI cannot be disabled and is always attached to GSI 9,
1652 * so these are no-ops. We only need this link to override the
1653 * polarity to active high and match the content of the MADT.
1655 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1656 aml_append(method
, aml_return(aml_int(0x0b)));
1657 aml_append(dev
, method
);
1659 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1660 aml_append(dev
, method
);
1662 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1663 aml_append(method
, aml_return(aml_name("_PRS")));
1664 aml_append(dev
, method
);
1666 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1667 aml_append(dev
, method
);
1669 aml_append(sb_scope
, dev
);
1671 aml_append(table
, sb_scope
);
1674 static void append_q35_prt_entry(Aml
*ctx
, uint32_t nr
, const char *name
)
1679 char base
= name
[3] < 'E' ? 'A' : 'E';
1680 char *s
= g_strdup(name
);
1681 Aml
*a_nr
= aml_int((nr
<< 16) | 0xffff);
1683 assert(strlen(s
) == 4);
1685 head
= name
[3] - base
;
1686 for (i
= 0; i
< 4; i
++) {
1690 s
[3] = base
+ head
+ i
;
1691 pkg
= aml_package(4);
1692 aml_append(pkg
, a_nr
);
1693 aml_append(pkg
, aml_int(i
));
1694 aml_append(pkg
, aml_name("%s", s
));
1695 aml_append(pkg
, aml_int(0));
1696 aml_append(ctx
, pkg
);
1701 static Aml
*build_q35_routing_table(const char *str
)
1705 char *name
= g_strdup_printf("%s ", str
);
1707 pkg
= aml_package(128);
1708 for (i
= 0; i
< 0x18; i
++) {
1709 name
[3] = 'E' + (i
& 0x3);
1710 append_q35_prt_entry(pkg
, i
, name
);
1714 append_q35_prt_entry(pkg
, 0x18, name
);
1716 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1717 for (i
= 0x0019; i
< 0x1e; i
++) {
1719 append_q35_prt_entry(pkg
, i
, name
);
1722 /* PCIe->PCI bridge. use PIRQ[E-H] */
1724 append_q35_prt_entry(pkg
, 0x1e, name
);
1726 append_q35_prt_entry(pkg
, 0x1f, name
);
1732 static void build_q35_pci0_int(Aml
*table
)
1736 Aml
*sb_scope
= aml_scope("_SB");
1737 Aml
*pci0_scope
= aml_scope("PCI0");
1739 /* Zero => PIC mode, One => APIC Mode */
1740 aml_append(table
, aml_name_decl("PICF", aml_int(0)));
1741 method
= aml_method("_PIC", 1, AML_NOTSERIALIZED
);
1743 aml_append(method
, aml_store(aml_arg(0), aml_name("PICF")));
1745 aml_append(table
, method
);
1747 aml_append(pci0_scope
,
1748 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1749 aml_append(pci0_scope
,
1750 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1752 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
1757 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1759 /* Note: we provide the same info as the PCI routing
1760 table of the Bochs BIOS */
1761 if_ctx
= aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1762 aml_append(if_ctx
, aml_return(aml_name("PRTP")));
1763 aml_append(method
, if_ctx
);
1764 else_ctx
= aml_else();
1765 aml_append(else_ctx
, aml_return(aml_name("PRTA")));
1766 aml_append(method
, else_ctx
);
1768 aml_append(pci0_scope
, method
);
1769 aml_append(sb_scope
, pci0_scope
);
1771 field
= aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1772 aml_append(field
, aml_named_field("PRQA", 8));
1773 aml_append(field
, aml_named_field("PRQB", 8));
1774 aml_append(field
, aml_named_field("PRQC", 8));
1775 aml_append(field
, aml_named_field("PRQD", 8));
1776 aml_append(field
, aml_reserved_field(0x20));
1777 aml_append(field
, aml_named_field("PRQE", 8));
1778 aml_append(field
, aml_named_field("PRQF", 8));
1779 aml_append(field
, aml_named_field("PRQG", 8));
1780 aml_append(field
, aml_named_field("PRQH", 8));
1781 aml_append(sb_scope
, field
);
1783 aml_append(sb_scope
, build_irq_status_method());
1784 aml_append(sb_scope
, build_iqcr_method(false));
1786 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQA")));
1787 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQB")));
1788 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQC")));
1789 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQD")));
1790 aml_append(sb_scope
, build_link_dev("LNKE", 4, aml_name("PRQE")));
1791 aml_append(sb_scope
, build_link_dev("LNKF", 5, aml_name("PRQF")));
1792 aml_append(sb_scope
, build_link_dev("LNKG", 6, aml_name("PRQG")));
1793 aml_append(sb_scope
, build_link_dev("LNKH", 7, aml_name("PRQH")));
1796 * TODO: UID probably shouldn't be the same for GSIx devices
1797 * but that's how it was in original ASL so keep it for now
1799 aml_append(sb_scope
, build_gsi_link_dev("GSIA", 0, 0x10));
1800 aml_append(sb_scope
, build_gsi_link_dev("GSIB", 0, 0x11));
1801 aml_append(sb_scope
, build_gsi_link_dev("GSIC", 0, 0x12));
1802 aml_append(sb_scope
, build_gsi_link_dev("GSID", 0, 0x13));
1803 aml_append(sb_scope
, build_gsi_link_dev("GSIE", 0, 0x14));
1804 aml_append(sb_scope
, build_gsi_link_dev("GSIF", 0, 0x15));
1805 aml_append(sb_scope
, build_gsi_link_dev("GSIG", 0, 0x16));
1806 aml_append(sb_scope
, build_gsi_link_dev("GSIH", 0, 0x17));
1808 aml_append(table
, sb_scope
);
1811 static void build_q35_isa_bridge(Aml
*table
)
1817 scope
= aml_scope("_SB.PCI0");
1818 dev
= aml_device("ISA");
1819 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x001F0000)));
1821 /* ICH9 PCI to ISA irq remapping */
1822 aml_append(dev
, aml_operation_region("PIRQ", AML_PCI_CONFIG
,
1823 aml_int(0x60), 0x0C));
1825 aml_append(dev
, aml_operation_region("LPCD", AML_PCI_CONFIG
,
1826 aml_int(0x80), 0x02));
1827 field
= aml_field("LPCD", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1828 aml_append(field
, aml_named_field("COMA", 3));
1829 aml_append(field
, aml_reserved_field(1));
1830 aml_append(field
, aml_named_field("COMB", 3));
1831 aml_append(field
, aml_reserved_field(1));
1832 aml_append(field
, aml_named_field("LPTD", 2));
1833 aml_append(dev
, field
);
1835 aml_append(dev
, aml_operation_region("LPCE", AML_PCI_CONFIG
,
1836 aml_int(0x82), 0x02));
1838 field
= aml_field("LPCE", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1839 aml_append(field
, aml_named_field("CAEN", 1));
1840 aml_append(field
, aml_named_field("CBEN", 1));
1841 aml_append(field
, aml_named_field("LPEN", 1));
1842 aml_append(dev
, field
);
1844 aml_append(scope
, dev
);
1845 aml_append(table
, scope
);
1848 static void build_piix4_pm(Aml
*table
)
1853 scope
= aml_scope("_SB.PCI0");
1854 dev
= aml_device("PX13");
1855 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010003)));
1857 aml_append(dev
, aml_operation_region("P13C", AML_PCI_CONFIG
,
1858 aml_int(0x00), 0xff));
1859 aml_append(scope
, dev
);
1860 aml_append(table
, scope
);
1863 static void build_piix4_isa_bridge(Aml
*table
)
1869 scope
= aml_scope("_SB.PCI0");
1870 dev
= aml_device("ISA");
1871 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010000)));
1873 /* PIIX PCI to ISA irq remapping */
1874 aml_append(dev
, aml_operation_region("P40C", AML_PCI_CONFIG
,
1875 aml_int(0x60), 0x04));
1877 field
= aml_field("^PX13.P13C", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1878 /* Offset(0x5f),, 7, */
1879 aml_append(field
, aml_reserved_field(0x2f8));
1880 aml_append(field
, aml_reserved_field(7));
1881 aml_append(field
, aml_named_field("LPEN", 1));
1882 /* Offset(0x67),, 3, */
1883 aml_append(field
, aml_reserved_field(0x38));
1884 aml_append(field
, aml_reserved_field(3));
1885 aml_append(field
, aml_named_field("CAEN", 1));
1886 aml_append(field
, aml_reserved_field(3));
1887 aml_append(field
, aml_named_field("CBEN", 1));
1888 aml_append(dev
, field
);
1890 aml_append(scope
, dev
);
1891 aml_append(table
, scope
);
1894 static void build_piix4_pci_hotplug(Aml
*table
)
1900 scope
= aml_scope("_SB.PCI0");
1903 aml_operation_region("PCST", AML_SYSTEM_IO
, aml_int(0xae00), 0x08));
1904 field
= aml_field("PCST", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1905 aml_append(field
, aml_named_field("PCIU", 32));
1906 aml_append(field
, aml_named_field("PCID", 32));
1907 aml_append(scope
, field
);
1910 aml_operation_region("SEJ", AML_SYSTEM_IO
, aml_int(0xae08), 0x04));
1911 field
= aml_field("SEJ", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1912 aml_append(field
, aml_named_field("B0EJ", 32));
1913 aml_append(scope
, field
);
1916 aml_operation_region("BNMR", AML_SYSTEM_IO
, aml_int(0xae10), 0x04));
1917 field
= aml_field("BNMR", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1918 aml_append(field
, aml_named_field("BNUM", 32));
1919 aml_append(scope
, field
);
1921 aml_append(scope
, aml_mutex("BLCK", 0));
1923 method
= aml_method("PCEJ", 2, AML_NOTSERIALIZED
);
1924 aml_append(method
, aml_acquire(aml_name("BLCK"), 0xFFFF));
1925 aml_append(method
, aml_store(aml_arg(0), aml_name("BNUM")));
1927 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1928 aml_append(method
, aml_release(aml_name("BLCK")));
1929 aml_append(method
, aml_return(aml_int(0)));
1930 aml_append(scope
, method
);
1932 aml_append(table
, scope
);
1935 static Aml
*build_q35_osc_method(void)
1941 Aml
*a_cwd1
= aml_name("CDW1");
1942 Aml
*a_ctrl
= aml_name("CTRL");
1944 method
= aml_method("_OSC", 4, AML_NOTSERIALIZED
);
1945 aml_append(method
, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1947 if_ctx
= aml_if(aml_equal(
1948 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1949 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1950 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1952 aml_append(if_ctx
, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1953 aml_append(if_ctx
, aml_store(aml_name("CDW3"), a_ctrl
));
1956 * Always allow native PME, AER (no dependencies)
1957 * Never allow SHPC (no SHPC controller in this system)
1959 aml_append(if_ctx
, aml_and(a_ctrl
, aml_int(0x1D), a_ctrl
));
1961 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1962 /* Unknown revision */
1963 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x08), a_cwd1
));
1964 aml_append(if_ctx
, if_ctx2
);
1966 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl
)));
1967 /* Capabilities bits were masked */
1968 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x10), a_cwd1
));
1969 aml_append(if_ctx
, if_ctx2
);
1971 /* Update DWORD3 in the buffer */
1972 aml_append(if_ctx
, aml_store(a_ctrl
, aml_name("CDW3")));
1973 aml_append(method
, if_ctx
);
1975 else_ctx
= aml_else();
1976 /* Unrecognized UUID */
1977 aml_append(else_ctx
, aml_or(a_cwd1
, aml_int(4), a_cwd1
));
1978 aml_append(method
, else_ctx
);
1980 aml_append(method
, aml_return(aml_arg(3)));
1985 build_dsdt(GArray
*table_data
, GArray
*linker
,
1986 AcpiPmInfo
*pm
, AcpiMiscInfo
*misc
,
1987 PcPciInfo
*pci
, MachineState
*machine
)
1989 CrsRangeEntry
*entry
;
1990 Aml
*dsdt
, *sb_scope
, *scope
, *dev
, *method
, *field
, *pkg
, *crs
;
1991 GPtrArray
*mem_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
1992 GPtrArray
*io_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
1993 PCMachineState
*pcms
= PC_MACHINE(machine
);
1994 uint32_t nr_mem
= machine
->ram_slots
;
1995 int root_bus_limit
= 0xFF;
1999 dsdt
= init_aml_allocator();
2001 /* Reserve space for header */
2002 acpi_data_push(dsdt
->buf
, sizeof(AcpiTableHeader
));
2004 build_dbg_aml(dsdt
);
2005 if (misc
->is_piix4
) {
2006 sb_scope
= aml_scope("_SB");
2007 dev
= aml_device("PCI0");
2008 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
2009 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
2010 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
2011 aml_append(sb_scope
, dev
);
2012 aml_append(dsdt
, sb_scope
);
2014 build_hpet_aml(dsdt
);
2015 build_piix4_pm(dsdt
);
2016 build_piix4_isa_bridge(dsdt
);
2017 build_isa_devices_aml(dsdt
);
2018 build_piix4_pci_hotplug(dsdt
);
2019 build_piix4_pci0_int(dsdt
);
2021 sb_scope
= aml_scope("_SB");
2022 aml_append(sb_scope
,
2023 aml_operation_region("PCST", AML_SYSTEM_IO
, aml_int(0xae00), 0x0c));
2024 aml_append(sb_scope
,
2025 aml_operation_region("PCSB", AML_SYSTEM_IO
, aml_int(0xae0c), 0x01));
2026 field
= aml_field("PCSB", AML_ANY_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
2027 aml_append(field
, aml_named_field("PCIB", 8));
2028 aml_append(sb_scope
, field
);
2029 aml_append(dsdt
, sb_scope
);
2031 sb_scope
= aml_scope("_SB");
2032 dev
= aml_device("PCI0");
2033 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
2034 aml_append(dev
, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
2035 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
2036 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
2037 aml_append(dev
, aml_name_decl("SUPP", aml_int(0)));
2038 aml_append(dev
, aml_name_decl("CTRL", aml_int(0)));
2039 aml_append(dev
, build_q35_osc_method());
2040 aml_append(sb_scope
, dev
);
2041 aml_append(dsdt
, sb_scope
);
2043 build_hpet_aml(dsdt
);
2044 build_q35_isa_bridge(dsdt
);
2045 build_isa_devices_aml(dsdt
);
2046 build_q35_pci0_int(dsdt
);
2049 build_cpu_hotplug_aml(dsdt
);
2050 build_memory_hotplug_aml(dsdt
, nr_mem
, pm
->mem_hp_io_base
,
2053 scope
= aml_scope("_GPE");
2055 aml_append(scope
, aml_name_decl("_HID", aml_string("ACPI0006")));
2057 aml_append(scope
, aml_method("_L00", 0, AML_NOTSERIALIZED
));
2059 if (misc
->is_piix4
) {
2060 method
= aml_method("_E01", 0, AML_NOTSERIALIZED
);
2062 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
2063 aml_append(method
, aml_call0("\\_SB.PCI0.PCNT"));
2064 aml_append(method
, aml_release(aml_name("\\_SB.PCI0.BLCK")));
2065 aml_append(scope
, method
);
2067 aml_append(scope
, aml_method("_L01", 0, AML_NOTSERIALIZED
));
2070 method
= aml_method("_E02", 0, AML_NOTSERIALIZED
);
2071 aml_append(method
, aml_call0("\\_SB." CPU_SCAN_METHOD
));
2072 aml_append(scope
, method
);
2074 method
= aml_method("_E03", 0, AML_NOTSERIALIZED
);
2075 aml_append(method
, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH
));
2076 aml_append(scope
, method
);
2078 aml_append(scope
, aml_method("_L04", 0, AML_NOTSERIALIZED
));
2079 aml_append(scope
, aml_method("_L05", 0, AML_NOTSERIALIZED
));
2080 aml_append(scope
, aml_method("_L06", 0, AML_NOTSERIALIZED
));
2081 aml_append(scope
, aml_method("_L07", 0, AML_NOTSERIALIZED
));
2082 aml_append(scope
, aml_method("_L08", 0, AML_NOTSERIALIZED
));
2083 aml_append(scope
, aml_method("_L09", 0, AML_NOTSERIALIZED
));
2084 aml_append(scope
, aml_method("_L0A", 0, AML_NOTSERIALIZED
));
2085 aml_append(scope
, aml_method("_L0B", 0, AML_NOTSERIALIZED
));
2086 aml_append(scope
, aml_method("_L0C", 0, AML_NOTSERIALIZED
));
2087 aml_append(scope
, aml_method("_L0D", 0, AML_NOTSERIALIZED
));
2088 aml_append(scope
, aml_method("_L0E", 0, AML_NOTSERIALIZED
));
2089 aml_append(scope
, aml_method("_L0F", 0, AML_NOTSERIALIZED
));
2091 aml_append(dsdt
, scope
);
2093 bus
= PC_MACHINE(machine
)->bus
;
2095 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
2096 uint8_t bus_num
= pci_bus_num(bus
);
2097 uint8_t numa_node
= pci_bus_numa_node(bus
);
2099 /* look only for expander root buses */
2100 if (!pci_bus_is_root(bus
)) {
2104 if (bus_num
< root_bus_limit
) {
2105 root_bus_limit
= bus_num
- 1;
2108 scope
= aml_scope("\\_SB");
2109 dev
= aml_device("PC%.02X", bus_num
);
2110 aml_append(dev
, aml_name_decl("_UID", aml_int(bus_num
)));
2111 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
2112 aml_append(dev
, aml_name_decl("_BBN", aml_int(bus_num
)));
2114 if (numa_node
!= NUMA_NODE_UNASSIGNED
) {
2115 aml_append(dev
, aml_name_decl("_PXM", aml_int(numa_node
)));
2118 aml_append(dev
, build_prt(false));
2119 crs
= build_crs(PCI_HOST_BRIDGE(BUS(bus
)->parent
),
2120 io_ranges
, mem_ranges
);
2121 aml_append(dev
, aml_name_decl("_CRS", crs
));
2122 aml_append(scope
, dev
);
2123 aml_append(dsdt
, scope
);
2127 scope
= aml_scope("\\_SB.PCI0");
2128 /* build PCI0._CRS */
2129 crs
= aml_resource_template();
2131 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
2132 0x0000, 0x0, root_bus_limit
,
2133 0x0000, root_bus_limit
+ 1));
2134 aml_append(crs
, aml_io(AML_DECODE16
, 0x0CF8, 0x0CF8, 0x01, 0x08));
2137 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
2138 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
2139 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
2141 crs_replace_with_free_ranges(io_ranges
, 0x0D00, 0xFFFF);
2142 for (i
= 0; i
< io_ranges
->len
; i
++) {
2143 entry
= g_ptr_array_index(io_ranges
, i
);
2145 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
2146 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
2147 0x0000, entry
->base
, entry
->limit
,
2148 0x0000, entry
->limit
- entry
->base
+ 1));
2152 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
2153 AML_CACHEABLE
, AML_READ_WRITE
,
2154 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2156 crs_replace_with_free_ranges(mem_ranges
, pci
->w32
.begin
, pci
->w32
.end
- 1);
2157 for (i
= 0; i
< mem_ranges
->len
; i
++) {
2158 entry
= g_ptr_array_index(mem_ranges
, i
);
2160 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
2161 AML_NON_CACHEABLE
, AML_READ_WRITE
,
2162 0, entry
->base
, entry
->limit
,
2163 0, entry
->limit
- entry
->base
+ 1));
2166 if (pci
->w64
.begin
) {
2168 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
2169 AML_CACHEABLE
, AML_READ_WRITE
,
2170 0, pci
->w64
.begin
, pci
->w64
.end
- 1, 0,
2171 pci
->w64
.end
- pci
->w64
.begin
));
2173 aml_append(scope
, aml_name_decl("_CRS", crs
));
2175 /* reserve GPE0 block resources */
2176 dev
= aml_device("GPE0");
2177 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
2178 aml_append(dev
, aml_name_decl("_UID", aml_string("GPE0 resources")));
2179 /* device present, functioning, decoding, not shown in UI */
2180 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2181 crs
= aml_resource_template();
2183 aml_io(AML_DECODE16
, pm
->gpe0_blk
, pm
->gpe0_blk
, 1, pm
->gpe0_blk_len
)
2185 aml_append(dev
, aml_name_decl("_CRS", crs
));
2186 aml_append(scope
, dev
);
2188 g_ptr_array_free(io_ranges
, true);
2189 g_ptr_array_free(mem_ranges
, true);
2191 /* reserve PCIHP resources */
2192 if (pm
->pcihp_io_len
) {
2193 dev
= aml_device("PHPR");
2194 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
2196 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2197 /* device present, functioning, decoding, not shown in UI */
2198 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2199 crs
= aml_resource_template();
2201 aml_io(AML_DECODE16
, pm
->pcihp_io_base
, pm
->pcihp_io_base
, 1,
2204 aml_append(dev
, aml_name_decl("_CRS", crs
));
2205 aml_append(scope
, dev
);
2207 aml_append(dsdt
, scope
);
2209 /* create S3_ / S4_ / S5_ packages if necessary */
2210 scope
= aml_scope("\\");
2211 if (!pm
->s3_disabled
) {
2212 pkg
= aml_package(4);
2213 aml_append(pkg
, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2214 aml_append(pkg
, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2215 aml_append(pkg
, aml_int(0)); /* reserved */
2216 aml_append(pkg
, aml_int(0)); /* reserved */
2217 aml_append(scope
, aml_name_decl("_S3", pkg
));
2220 if (!pm
->s4_disabled
) {
2221 pkg
= aml_package(4);
2222 aml_append(pkg
, aml_int(pm
->s4_val
)); /* PM1a_CNT.SLP_TYP */
2223 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2224 aml_append(pkg
, aml_int(pm
->s4_val
));
2225 aml_append(pkg
, aml_int(0)); /* reserved */
2226 aml_append(pkg
, aml_int(0)); /* reserved */
2227 aml_append(scope
, aml_name_decl("_S4", pkg
));
2230 pkg
= aml_package(4);
2231 aml_append(pkg
, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2232 aml_append(pkg
, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2233 aml_append(pkg
, aml_int(0)); /* reserved */
2234 aml_append(pkg
, aml_int(0)); /* reserved */
2235 aml_append(scope
, aml_name_decl("_S5", pkg
));
2236 aml_append(dsdt
, scope
);
2238 /* create fw_cfg node, unconditionally */
2240 /* when using port i/o, the 8-bit data register *always* overlaps
2241 * with half of the 16-bit control register. Hence, the total size
2242 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2243 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2244 uint8_t io_size
= object_property_get_bool(OBJECT(pcms
->fw_cfg
),
2245 "dma_enabled", NULL
) ?
2246 ROUND_UP(FW_CFG_CTL_SIZE
, 4) + sizeof(dma_addr_t
) :
2249 scope
= aml_scope("\\_SB.PCI0");
2250 dev
= aml_device("FWCF");
2252 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0002")));
2254 /* device present, functioning, decoding, not shown in UI */
2255 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2257 crs
= aml_resource_template();
2259 aml_io(AML_DECODE16
, FW_CFG_IO_BASE
, FW_CFG_IO_BASE
, 0x01, io_size
)
2261 aml_append(dev
, aml_name_decl("_CRS", crs
));
2263 aml_append(scope
, dev
);
2264 aml_append(dsdt
, scope
);
2267 if (misc
->applesmc_io_base
) {
2268 scope
= aml_scope("\\_SB.PCI0.ISA");
2269 dev
= aml_device("SMC");
2271 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("APP0001")));
2272 /* device present, functioning, decoding, not shown in UI */
2273 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2275 crs
= aml_resource_template();
2277 aml_io(AML_DECODE16
, misc
->applesmc_io_base
, misc
->applesmc_io_base
,
2278 0x01, APPLESMC_MAX_DATA_LENGTH
)
2280 aml_append(crs
, aml_irq_no_flags(6));
2281 aml_append(dev
, aml_name_decl("_CRS", crs
));
2283 aml_append(scope
, dev
);
2284 aml_append(dsdt
, scope
);
2287 if (misc
->pvpanic_port
) {
2288 scope
= aml_scope("\\_SB.PCI0.ISA");
2290 dev
= aml_device("PEVT");
2291 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0001")));
2293 crs
= aml_resource_template();
2295 aml_io(AML_DECODE16
, misc
->pvpanic_port
, misc
->pvpanic_port
, 1, 1)
2297 aml_append(dev
, aml_name_decl("_CRS", crs
));
2299 aml_append(dev
, aml_operation_region("PEOR", AML_SYSTEM_IO
,
2300 aml_int(misc
->pvpanic_port
), 1));
2301 field
= aml_field("PEOR", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
2302 aml_append(field
, aml_named_field("PEPT", 8));
2303 aml_append(dev
, field
);
2305 /* device present, functioning, decoding, shown in UI */
2306 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
2308 method
= aml_method("RDPT", 0, AML_NOTSERIALIZED
);
2309 aml_append(method
, aml_store(aml_name("PEPT"), aml_local(0)));
2310 aml_append(method
, aml_return(aml_local(0)));
2311 aml_append(dev
, method
);
2313 method
= aml_method("WRPT", 1, AML_NOTSERIALIZED
);
2314 aml_append(method
, aml_store(aml_arg(0), aml_name("PEPT")));
2315 aml_append(dev
, method
);
2317 aml_append(scope
, dev
);
2318 aml_append(dsdt
, scope
);
2321 sb_scope
= aml_scope("\\_SB");
2323 build_processor_devices(sb_scope
, machine
, pm
);
2325 build_memory_devices(sb_scope
, nr_mem
, pm
->mem_hp_io_base
,
2332 pci_host
= acpi_get_i386_pci_host();
2334 bus
= PCI_HOST_BRIDGE(pci_host
)->bus
;
2338 Aml
*scope
= aml_scope("PCI0");
2339 /* Scan all PCI buses. Generate tables to support hotplug. */
2340 build_append_pci_bus_devices(scope
, bus
, pm
->pcihp_bridge_en
);
2342 if (misc
->tpm_version
!= TPM_VERSION_UNSPEC
) {
2343 dev
= aml_device("ISA.TPM");
2344 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2345 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
2346 crs
= aml_resource_template();
2347 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
2348 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
2349 aml_append(crs
, aml_irq_no_flags(TPM_TIS_IRQ
));
2350 aml_append(dev
, aml_name_decl("_CRS", crs
));
2351 aml_append(scope
, dev
);
2354 aml_append(sb_scope
, scope
);
2357 aml_append(dsdt
, sb_scope
);
2360 /* copy AML table into ACPI tables blob and patch header there */
2361 g_array_append_vals(table_data
, dsdt
->buf
->data
, dsdt
->buf
->len
);
2362 build_header(linker
, table_data
,
2363 (void *)(table_data
->data
+ table_data
->len
- dsdt
->buf
->len
),
2364 "DSDT", dsdt
->buf
->len
, 1, NULL
, NULL
);
2365 free_aml_allocator();
2369 build_hpet(GArray
*table_data
, GArray
*linker
)
2373 hpet
= acpi_data_push(table_data
, sizeof(*hpet
));
2374 /* Note timer_block_id value must be kept in sync with value advertised by
2377 hpet
->timer_block_id
= cpu_to_le32(0x8086a201);
2378 hpet
->addr
.address
= cpu_to_le64(HPET_BASE
);
2379 build_header(linker
, table_data
,
2380 (void *)hpet
, "HPET", sizeof(*hpet
), 1, NULL
, NULL
);
2384 build_tpm_tcpa(GArray
*table_data
, GArray
*linker
, GArray
*tcpalog
)
2386 Acpi20Tcpa
*tcpa
= acpi_data_push(table_data
, sizeof *tcpa
);
2387 uint64_t log_area_start_address
= acpi_data_len(tcpalog
);
2389 tcpa
->platform_class
= cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT
);
2390 tcpa
->log_area_minimum_length
= cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE
);
2391 tcpa
->log_area_start_address
= cpu_to_le64(log_area_start_address
);
2393 bios_linker_loader_alloc(linker
, ACPI_BUILD_TPMLOG_FILE
, 1,
2394 false /* high memory */);
2396 /* log area start address to be filled by Guest linker */
2397 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_TABLE_FILE
,
2398 ACPI_BUILD_TPMLOG_FILE
,
2399 table_data
, &tcpa
->log_area_start_address
,
2400 sizeof(tcpa
->log_area_start_address
));
2402 build_header(linker
, table_data
,
2403 (void *)tcpa
, "TCPA", sizeof(*tcpa
), 2, NULL
, NULL
);
2405 acpi_data_push(tcpalog
, TPM_LOG_AREA_MINIMUM_SIZE
);
2409 build_tpm2(GArray
*table_data
, GArray
*linker
)
2411 Acpi20TPM2
*tpm2_ptr
;
2413 tpm2_ptr
= acpi_data_push(table_data
, sizeof *tpm2_ptr
);
2415 tpm2_ptr
->platform_class
= cpu_to_le16(TPM2_ACPI_CLASS_CLIENT
);
2416 tpm2_ptr
->control_area_address
= cpu_to_le64(0);
2417 tpm2_ptr
->start_method
= cpu_to_le32(TPM2_START_METHOD_MMIO
);
2419 build_header(linker
, table_data
,
2420 (void *)tpm2_ptr
, "TPM2", sizeof(*tpm2_ptr
), 4, NULL
, NULL
);
2424 MEM_AFFINITY_NOFLAGS
= 0,
2425 MEM_AFFINITY_ENABLED
= (1 << 0),
2426 MEM_AFFINITY_HOTPLUGGABLE
= (1 << 1),
2427 MEM_AFFINITY_NON_VOLATILE
= (1 << 2),
2428 } MemoryAffinityFlags
;
2431 acpi_build_srat_memory(AcpiSratMemoryAffinity
*numamem
, uint64_t base
,
2432 uint64_t len
, int node
, MemoryAffinityFlags flags
)
2434 numamem
->type
= ACPI_SRAT_MEMORY
;
2435 numamem
->length
= sizeof(*numamem
);
2436 memset(numamem
->proximity
, 0, 4);
2437 numamem
->proximity
[0] = node
;
2438 numamem
->flags
= cpu_to_le32(flags
);
2439 numamem
->base_addr
= cpu_to_le64(base
);
2440 numamem
->range_length
= cpu_to_le64(len
);
2444 build_srat(GArray
*table_data
, GArray
*linker
, MachineState
*machine
)
2446 AcpiSystemResourceAffinityTable
*srat
;
2447 AcpiSratProcessorAffinity
*core
;
2448 AcpiSratMemoryAffinity
*numamem
;
2452 int srat_start
, numa_start
, slots
;
2453 uint64_t mem_len
, mem_base
, next_base
;
2454 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2455 CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(machine
);
2456 PCMachineState
*pcms
= PC_MACHINE(machine
);
2457 ram_addr_t hotplugabble_address_space_size
=
2458 object_property_get_int(OBJECT(pcms
), PC_MACHINE_MEMHP_REGION_SIZE
,
2461 srat_start
= table_data
->len
;
2463 srat
= acpi_data_push(table_data
, sizeof *srat
);
2464 srat
->reserved1
= cpu_to_le32(1);
2466 for (i
= 0; i
< apic_ids
->len
; i
++) {
2467 int apic_id
= apic_ids
->cpus
[i
].arch_id
;
2469 core
= acpi_data_push(table_data
, sizeof *core
);
2470 core
->type
= ACPI_SRAT_PROCESSOR
;
2471 core
->length
= sizeof(*core
);
2472 core
->local_apic_id
= apic_id
;
2473 curnode
= pcms
->node_cpu
[apic_id
];
2474 core
->proximity_lo
= curnode
;
2475 memset(core
->proximity_hi
, 0, 3);
2476 core
->local_sapic_eid
= 0;
2477 core
->flags
= cpu_to_le32(1);
2481 /* the memory map is a bit tricky, it contains at least one hole
2482 * from 640k-1M and possibly another one from 3.5G-4G.
2485 numa_start
= table_data
->len
;
2487 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2488 acpi_build_srat_memory(numamem
, 0, 640*1024, 0, MEM_AFFINITY_ENABLED
);
2489 next_base
= 1024 * 1024;
2490 for (i
= 1; i
< pcms
->numa_nodes
+ 1; ++i
) {
2491 mem_base
= next_base
;
2492 mem_len
= pcms
->node_mem
[i
- 1];
2494 mem_len
-= 1024 * 1024;
2496 next_base
= mem_base
+ mem_len
;
2498 /* Cut out the ACPI_PCI hole */
2499 if (mem_base
<= pcms
->below_4g_mem_size
&&
2500 next_base
> pcms
->below_4g_mem_size
) {
2501 mem_len
-= next_base
- pcms
->below_4g_mem_size
;
2503 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2504 acpi_build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2505 MEM_AFFINITY_ENABLED
);
2507 mem_base
= 1ULL << 32;
2508 mem_len
= next_base
- pcms
->below_4g_mem_size
;
2509 next_base
+= (1ULL << 32) - pcms
->below_4g_mem_size
;
2511 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2512 acpi_build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2513 MEM_AFFINITY_ENABLED
);
2515 slots
= (table_data
->len
- numa_start
) / sizeof *numamem
;
2516 for (; slots
< pcms
->numa_nodes
+ 2; slots
++) {
2517 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2518 acpi_build_srat_memory(numamem
, 0, 0, 0, MEM_AFFINITY_NOFLAGS
);
2522 * Entry is required for Windows to enable memory hotplug in OS.
2523 * Memory devices may override proximity set by this entry,
2524 * providing _PXM method if necessary.
2526 if (hotplugabble_address_space_size
) {
2527 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2528 acpi_build_srat_memory(numamem
, pcms
->hotplug_memory
.base
,
2529 hotplugabble_address_space_size
, 0,
2530 MEM_AFFINITY_HOTPLUGGABLE
|
2531 MEM_AFFINITY_ENABLED
);
2534 build_header(linker
, table_data
,
2535 (void *)(table_data
->data
+ srat_start
),
2537 table_data
->len
- srat_start
, 1, NULL
, NULL
);
2542 build_mcfg_q35(GArray
*table_data
, GArray
*linker
, AcpiMcfgInfo
*info
)
2544 AcpiTableMcfg
*mcfg
;
2546 int len
= sizeof(*mcfg
) + 1 * sizeof(mcfg
->allocation
[0]);
2548 mcfg
= acpi_data_push(table_data
, len
);
2549 mcfg
->allocation
[0].address
= cpu_to_le64(info
->mcfg_base
);
2550 /* Only a single allocation so no need to play with segments */
2551 mcfg
->allocation
[0].pci_segment
= cpu_to_le16(0);
2552 mcfg
->allocation
[0].start_bus_number
= 0;
2553 mcfg
->allocation
[0].end_bus_number
= PCIE_MMCFG_BUS(info
->mcfg_size
- 1);
2555 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2556 * To avoid table size changes (which create migration issues),
2557 * always create the table even if there are no allocations,
2558 * but set the signature to a reserved value in this case.
2559 * ACPI spec requires OSPMs to ignore such tables.
2561 if (info
->mcfg_base
== PCIE_BASE_ADDR_UNMAPPED
) {
2562 /* Reserved signature: ignored by OSPM */
2567 build_header(linker
, table_data
, (void *)mcfg
, sig
, len
, 1, NULL
, NULL
);
2571 build_dmar_q35(GArray
*table_data
, GArray
*linker
)
2573 int dmar_start
= table_data
->len
;
2575 AcpiTableDmar
*dmar
;
2576 AcpiDmarHardwareUnit
*drhd
;
2578 dmar
= acpi_data_push(table_data
, sizeof(*dmar
));
2579 dmar
->host_address_width
= VTD_HOST_ADDRESS_WIDTH
- 1;
2580 dmar
->flags
= 0; /* No intr_remap for now */
2582 /* DMAR Remapping Hardware Unit Definition structure */
2583 drhd
= acpi_data_push(table_data
, sizeof(*drhd
));
2584 drhd
->type
= cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT
);
2585 drhd
->length
= cpu_to_le16(sizeof(*drhd
)); /* No device scope now */
2586 drhd
->flags
= ACPI_DMAR_INCLUDE_PCI_ALL
;
2587 drhd
->pci_segment
= cpu_to_le16(0);
2588 drhd
->address
= cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR
);
2590 build_header(linker
, table_data
, (void *)(table_data
->data
+ dmar_start
),
2591 "DMAR", table_data
->len
- dmar_start
, 1, NULL
, NULL
);
2595 build_rsdp(GArray
*rsdp_table
, GArray
*linker
, unsigned rsdt
)
2597 AcpiRsdpDescriptor
*rsdp
= acpi_data_push(rsdp_table
, sizeof *rsdp
);
2599 bios_linker_loader_alloc(linker
, ACPI_BUILD_RSDP_FILE
, 16,
2600 true /* fseg memory */);
2602 memcpy(&rsdp
->signature
, "RSD PTR ", 8);
2603 memcpy(rsdp
->oem_id
, ACPI_BUILD_APPNAME6
, 6);
2604 rsdp
->rsdt_physical_address
= cpu_to_le32(rsdt
);
2605 /* Address to be filled by Guest linker */
2606 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_RSDP_FILE
,
2607 ACPI_BUILD_TABLE_FILE
,
2608 rsdp_table
, &rsdp
->rsdt_physical_address
,
2609 sizeof rsdp
->rsdt_physical_address
);
2611 /* Checksum to be filled by Guest linker */
2612 bios_linker_loader_add_checksum(linker
, ACPI_BUILD_RSDP_FILE
,
2613 rsdp_table
, rsdp
, sizeof *rsdp
,
2620 struct AcpiBuildState
{
2621 /* Copy of table in RAM (for patching). */
2622 MemoryRegion
*table_mr
;
2623 /* Is table patched? */
2626 MemoryRegion
*rsdp_mr
;
2627 MemoryRegion
*linker_mr
;
2630 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
)
2635 pci_host
= acpi_get_i386_pci_host();
2638 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_BASE
, NULL
);
2642 mcfg
->mcfg_base
= qint_get_int(qobject_to_qint(o
));
2645 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_SIZE
, NULL
);
2647 mcfg
->mcfg_size
= qint_get_int(qobject_to_qint(o
));
2652 static bool acpi_has_iommu(void)
2655 Object
*intel_iommu
;
2657 intel_iommu
= object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE
,
2659 return intel_iommu
&& !ambiguous
;
2663 void acpi_build(AcpiBuildTables
*tables
, MachineState
*machine
)
2665 PCMachineState
*pcms
= PC_MACHINE(machine
);
2666 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2667 GArray
*table_offsets
;
2668 unsigned facs
, dsdt
, rsdt
, fadt
;
2675 GArray
*tables_blob
= tables
->table_data
;
2676 AcpiSlicOem slic_oem
= { .id
= NULL
, .table_id
= NULL
};
2678 acpi_get_pm_info(&pm
);
2679 acpi_get_misc_info(&misc
);
2680 acpi_get_pci_info(&pci
);
2681 acpi_get_slic_oem(&slic_oem
);
2683 table_offsets
= g_array_new(false, true /* clear */,
2685 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2687 bios_linker_loader_alloc(tables
->linker
, ACPI_BUILD_TABLE_FILE
,
2688 64 /* Ensure FACS is aligned */,
2689 false /* high memory */);
2692 * FACS is pointed to by FADT.
2693 * We place it first since it's the only table that has alignment
2696 facs
= tables_blob
->len
;
2697 build_facs(tables_blob
, tables
->linker
);
2699 /* DSDT is pointed to by FADT */
2700 dsdt
= tables_blob
->len
;
2701 build_dsdt(tables_blob
, tables
->linker
, &pm
, &misc
, &pci
, machine
);
2703 /* Count the size of the DSDT and SSDT, we will need it for legacy
2704 * sizing of ACPI tables.
2706 aml_len
+= tables_blob
->len
- dsdt
;
2708 /* ACPI tables pointed to by RSDT */
2709 fadt
= tables_blob
->len
;
2710 acpi_add_table(table_offsets
, tables_blob
);
2711 build_fadt(tables_blob
, tables
->linker
, &pm
, facs
, dsdt
,
2712 slic_oem
.id
, slic_oem
.table_id
);
2713 aml_len
+= tables_blob
->len
- fadt
;
2715 acpi_add_table(table_offsets
, tables_blob
);
2716 build_madt(tables_blob
, tables
->linker
, pcms
);
2718 if (misc
.has_hpet
) {
2719 acpi_add_table(table_offsets
, tables_blob
);
2720 build_hpet(tables_blob
, tables
->linker
);
2722 if (misc
.tpm_version
!= TPM_VERSION_UNSPEC
) {
2723 acpi_add_table(table_offsets
, tables_blob
);
2724 build_tpm_tcpa(tables_blob
, tables
->linker
, tables
->tcpalog
);
2726 if (misc
.tpm_version
== TPM_VERSION_2_0
) {
2727 acpi_add_table(table_offsets
, tables_blob
);
2728 build_tpm2(tables_blob
, tables
->linker
);
2731 if (pcms
->numa_nodes
) {
2732 acpi_add_table(table_offsets
, tables_blob
);
2733 build_srat(tables_blob
, tables
->linker
, machine
);
2735 if (acpi_get_mcfg(&mcfg
)) {
2736 acpi_add_table(table_offsets
, tables_blob
);
2737 build_mcfg_q35(tables_blob
, tables
->linker
, &mcfg
);
2739 if (acpi_has_iommu()) {
2740 acpi_add_table(table_offsets
, tables_blob
);
2741 build_dmar_q35(tables_blob
, tables
->linker
);
2743 if (pcms
->acpi_nvdimm_state
.is_enabled
) {
2744 nvdimm_build_acpi(table_offsets
, tables_blob
, tables
->linker
);
2747 /* Add tables supplied by user (if any) */
2748 for (u
= acpi_table_first(); u
; u
= acpi_table_next(u
)) {
2749 unsigned len
= acpi_table_len(u
);
2751 acpi_add_table(table_offsets
, tables_blob
);
2752 g_array_append_vals(tables_blob
, u
, len
);
2755 /* RSDT is pointed to by RSDP */
2756 rsdt
= tables_blob
->len
;
2757 build_rsdt(tables_blob
, tables
->linker
, table_offsets
,
2758 slic_oem
.id
, slic_oem
.table_id
);
2760 /* RSDP is in FSEG memory, so allocate it separately */
2761 build_rsdp(tables
->rsdp
, tables
->linker
, rsdt
);
2763 /* We'll expose it all to Guest so we want to reduce
2764 * chance of size changes.
2766 * We used to align the tables to 4k, but of course this would
2767 * too simple to be enough. 4k turned out to be too small an
2768 * alignment very soon, and in fact it is almost impossible to
2769 * keep the table size stable for all (max_cpus, max_memory_slots)
2770 * combinations. So the table size is always 64k for pc-i440fx-2.1
2771 * and we give an error if the table grows beyond that limit.
2773 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2774 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2775 * than 2.0 and we can always pad the smaller tables with zeros. We can
2776 * then use the exact size of the 2.0 tables.
2778 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2780 if (pcmc
->legacy_acpi_table_size
) {
2781 /* Subtracting aml_len gives the size of fixed tables. Then add the
2782 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2784 int legacy_aml_len
=
2785 pcmc
->legacy_acpi_table_size
+
2786 ACPI_BUILD_LEGACY_CPU_AML_SIZE
* max_cpus
;
2787 int legacy_table_size
=
2788 ROUND_UP(tables_blob
->len
- aml_len
+ legacy_aml_len
,
2789 ACPI_BUILD_ALIGN_SIZE
);
2790 if (tables_blob
->len
> legacy_table_size
) {
2791 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2792 error_report("Warning: migration may not work.");
2794 g_array_set_size(tables_blob
, legacy_table_size
);
2796 /* Make sure we have a buffer in case we need to resize the tables. */
2797 if (tables_blob
->len
> ACPI_BUILD_TABLE_SIZE
/ 2) {
2798 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2799 error_report("Warning: ACPI tables are larger than 64k.");
2800 error_report("Warning: migration may not work.");
2801 error_report("Warning: please remove CPUs, NUMA nodes, "
2802 "memory slots or PCI bridges.");
2804 acpi_align_size(tables_blob
, ACPI_BUILD_TABLE_SIZE
);
2807 acpi_align_size(tables
->linker
, ACPI_BUILD_ALIGN_SIZE
);
2809 /* Cleanup memory that's no longer used. */
2810 g_array_free(table_offsets
, true);
2813 static void acpi_ram_update(MemoryRegion
*mr
, GArray
*data
)
2815 uint32_t size
= acpi_data_len(data
);
2817 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2818 memory_region_ram_resize(mr
, size
, &error_abort
);
2820 memcpy(memory_region_get_ram_ptr(mr
), data
->data
, size
);
2821 memory_region_set_dirty(mr
, 0, size
);
2824 static void acpi_build_update(void *build_opaque
)
2826 AcpiBuildState
*build_state
= build_opaque
;
2827 AcpiBuildTables tables
;
2829 /* No state to update or already patched? Nothing to do. */
2830 if (!build_state
|| build_state
->patched
) {
2833 build_state
->patched
= 1;
2835 acpi_build_tables_init(&tables
);
2837 acpi_build(&tables
, MACHINE(qdev_get_machine()));
2839 acpi_ram_update(build_state
->table_mr
, tables
.table_data
);
2841 if (build_state
->rsdp
) {
2842 memcpy(build_state
->rsdp
, tables
.rsdp
->data
, acpi_data_len(tables
.rsdp
));
2844 acpi_ram_update(build_state
->rsdp_mr
, tables
.rsdp
);
2847 acpi_ram_update(build_state
->linker_mr
, tables
.linker
);
2848 acpi_build_tables_cleanup(&tables
, true);
2851 static void acpi_build_reset(void *build_opaque
)
2853 AcpiBuildState
*build_state
= build_opaque
;
2854 build_state
->patched
= 0;
2857 static MemoryRegion
*acpi_add_rom_blob(AcpiBuildState
*build_state
,
2858 GArray
*blob
, const char *name
,
2861 return rom_add_blob(name
, blob
->data
, acpi_data_len(blob
), max_size
, -1,
2862 name
, acpi_build_update
, build_state
);
2865 static const VMStateDescription vmstate_acpi_build
= {
2866 .name
= "acpi_build",
2868 .minimum_version_id
= 1,
2869 .fields
= (VMStateField
[]) {
2870 VMSTATE_UINT8(patched
, AcpiBuildState
),
2871 VMSTATE_END_OF_LIST()
2875 void acpi_setup(void)
2877 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
2878 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2879 AcpiBuildTables tables
;
2880 AcpiBuildState
*build_state
;
2882 if (!pcms
->fw_cfg
) {
2883 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2887 if (!pcmc
->has_acpi_build
) {
2888 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2892 if (!acpi_enabled
) {
2893 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2897 build_state
= g_malloc0(sizeof *build_state
);
2899 acpi_set_pci_info();
2901 acpi_build_tables_init(&tables
);
2902 acpi_build(&tables
, MACHINE(pcms
));
2904 /* Now expose it all to Guest */
2905 build_state
->table_mr
= acpi_add_rom_blob(build_state
, tables
.table_data
,
2906 ACPI_BUILD_TABLE_FILE
,
2907 ACPI_BUILD_TABLE_MAX_SIZE
);
2908 assert(build_state
->table_mr
!= NULL
);
2910 build_state
->linker_mr
=
2911 acpi_add_rom_blob(build_state
, tables
.linker
, "etc/table-loader", 0);
2913 fw_cfg_add_file(pcms
->fw_cfg
, ACPI_BUILD_TPMLOG_FILE
,
2914 tables
.tcpalog
->data
, acpi_data_len(tables
.tcpalog
));
2916 if (!pcmc
->rsdp_in_ram
) {
2918 * Keep for compatibility with old machine types.
2919 * Though RSDP is small, its contents isn't immutable, so
2920 * we'll update it along with the rest of tables on guest access.
2922 uint32_t rsdp_size
= acpi_data_len(tables
.rsdp
);
2924 build_state
->rsdp
= g_memdup(tables
.rsdp
->data
, rsdp_size
);
2925 fw_cfg_add_file_callback(pcms
->fw_cfg
, ACPI_BUILD_RSDP_FILE
,
2926 acpi_build_update
, build_state
,
2927 build_state
->rsdp
, rsdp_size
);
2928 build_state
->rsdp_mr
= NULL
;
2930 build_state
->rsdp
= NULL
;
2931 build_state
->rsdp_mr
= acpi_add_rom_blob(build_state
, tables
.rsdp
,
2932 ACPI_BUILD_RSDP_FILE
, 0);
2935 qemu_register_reset(acpi_build_reset
, build_state
);
2936 acpi_build_reset(build_state
);
2937 vmstate_register(NULL
, 0, &vmstate_acpi_build
, build_state
);
2939 /* Cleanup tables but don't free the memory: we track it
2942 acpi_build_tables_cleanup(&tables
, false);