hw/arm/aspeed_soc.c

   1 /*
   2  * ASPEED SoC family
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  * Jeremy Kerr <jk@ozlabs.org>
   6  *
   7  * Copyright 2016 IBM Corp.
   8  *
   9  * This code is licensed under the GPL version 2 or later.  See
  10  * the COPYING file in the top-level directory.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qapi/error.h"
  15 #include "cpu.h"
  16 #include "exec/address-spaces.h"
  17 #include "hw/misc/unimp.h"
  18 #include "hw/arm/aspeed_soc.h"
  19 #include "hw/char/serial.h"
  20 #include "qemu/log.h"
  21 #include "qemu/module.h"
  22 #include "qemu/error-report.h"
  23 #include "hw/i2c/aspeed_i2c.h"
  24 #include "net/net.h"
  25
  26 #define ASPEED_SOC_IOMEM_SIZE       0x00200000
  27
  28 static const hwaddr aspeed_soc_ast2400_memmap[] = {
  29     [ASPEED_IOMEM]  = 0x1E600000,
  30     [ASPEED_FMC]    = 0x1E620000,
  31     [ASPEED_SPI1]   = 0x1E630000,
  32     [ASPEED_VIC]    = 0x1E6C0000,
  33     [ASPEED_SDMC]   = 0x1E6E0000,
  34     [ASPEED_SCU]    = 0x1E6E2000,
  35     [ASPEED_ADC]    = 0x1E6E9000,
  36     [ASPEED_SRAM]   = 0x1E720000,
  37     [ASPEED_GPIO]   = 0x1E780000,
  38     [ASPEED_RTC]    = 0x1E781000,
  39     [ASPEED_TIMER1] = 0x1E782000,
  40     [ASPEED_WDT]    = 0x1E785000,
  41     [ASPEED_PWM]    = 0x1E786000,
  42     [ASPEED_LPC]    = 0x1E789000,
  43     [ASPEED_IBT]    = 0x1E789140,
  44     [ASPEED_I2C]    = 0x1E78A000,
  45     [ASPEED_ETH1]   = 0x1E660000,
  46     [ASPEED_ETH2]   = 0x1E680000,
  47     [ASPEED_UART1]  = 0x1E783000,
  48     [ASPEED_UART5]  = 0x1E784000,
  49     [ASPEED_VUART]  = 0x1E787000,
  50     [ASPEED_SDRAM]  = 0x40000000,
  51 };
  52
  53 static const hwaddr aspeed_soc_ast2500_memmap[] = {
  54     [ASPEED_IOMEM]  = 0x1E600000,
  55     [ASPEED_FMC]    = 0x1E620000,
  56     [ASPEED_SPI1]   = 0x1E630000,
  57     [ASPEED_SPI2]   = 0x1E631000,
  58     [ASPEED_VIC]    = 0x1E6C0000,
  59     [ASPEED_SDMC]   = 0x1E6E0000,
  60     [ASPEED_SCU]    = 0x1E6E2000,
  61     [ASPEED_ADC]    = 0x1E6E9000,
  62     [ASPEED_SRAM]   = 0x1E720000,
  63     [ASPEED_GPIO]   = 0x1E780000,
  64     [ASPEED_RTC]    = 0x1E781000,
  65     [ASPEED_TIMER1] = 0x1E782000,
  66     [ASPEED_WDT]    = 0x1E785000,
  67     [ASPEED_PWM]    = 0x1E786000,
  68     [ASPEED_LPC]    = 0x1E789000,
  69     [ASPEED_IBT]    = 0x1E789140,
  70     [ASPEED_I2C]    = 0x1E78A000,
  71     [ASPEED_ETH1]   = 0x1E660000,
  72     [ASPEED_ETH2]   = 0x1E680000,
  73     [ASPEED_UART1]  = 0x1E783000,
  74     [ASPEED_UART5]  = 0x1E784000,
  75     [ASPEED_VUART]  = 0x1E787000,
  76     [ASPEED_SDRAM]  = 0x80000000,
  77 };
  78
  79 static const int aspeed_soc_ast2400_irqmap[] = {
  80     [ASPEED_UART1]  = 9,
  81     [ASPEED_UART2]  = 32,
  82     [ASPEED_UART3]  = 33,
  83     [ASPEED_UART4]  = 34,
  84     [ASPEED_UART5]  = 10,
  85     [ASPEED_VUART]  = 8,
  86     [ASPEED_FMC]    = 19,
  87     [ASPEED_SDMC]   = 0,
  88     [ASPEED_SCU]    = 21,
  89     [ASPEED_ADC]    = 31,
  90     [ASPEED_GPIO]   = 20,
  91     [ASPEED_RTC]    = 22,
  92     [ASPEED_TIMER1] = 16,
  93     [ASPEED_TIMER2] = 17,
  94     [ASPEED_TIMER3] = 18,
  95     [ASPEED_TIMER4] = 35,
  96     [ASPEED_TIMER5] = 36,
  97     [ASPEED_TIMER6] = 37,
  98     [ASPEED_TIMER7] = 38,
  99     [ASPEED_TIMER8] = 39,
 100     [ASPEED_WDT]    = 27,
 101     [ASPEED_PWM]    = 28,
 102     [ASPEED_LPC]    = 8,
 103     [ASPEED_IBT]    = 8, /* LPC */
 104     [ASPEED_I2C]    = 12,
 105     [ASPEED_ETH1]   = 2,
 106     [ASPEED_ETH2]   = 3,
 107 };
 108
 109 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
 110
 111 static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
 112 static const char *aspeed_soc_ast2500_typenames[] = {
 113     "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
 114
 115 static const AspeedSoCInfo aspeed_socs[] = {
 116     {
 117         .name         = "ast2400-a0",
 118         .cpu_type     = ARM_CPU_TYPE_NAME("arm926"),
 119         .silicon_rev  = AST2400_A0_SILICON_REV,
 120         .sram_size    = 0x8000,
 121         .spis_num     = 1,
 122         .fmc_typename = "aspeed.smc.fmc",
 123         .spi_typename = aspeed_soc_ast2400_typenames,
 124         .wdts_num     = 2,
 125         .irqmap       = aspeed_soc_ast2400_irqmap,
 126         .memmap       = aspeed_soc_ast2400_memmap,
 127         .num_cpus     = 1,
 128     }, {
 129         .name         = "ast2400-a1",
 130         .cpu_type     = ARM_CPU_TYPE_NAME("arm926"),
 131         .silicon_rev  = AST2400_A1_SILICON_REV,
 132         .sram_size    = 0x8000,
 133         .spis_num     = 1,
 134         .fmc_typename = "aspeed.smc.fmc",
 135         .spi_typename = aspeed_soc_ast2400_typenames,
 136         .wdts_num     = 2,
 137         .irqmap       = aspeed_soc_ast2400_irqmap,
 138         .memmap       = aspeed_soc_ast2400_memmap,
 139         .num_cpus     = 1,
 140     }, {
 141         .name         = "ast2400",
 142         .cpu_type     = ARM_CPU_TYPE_NAME("arm926"),
 143         .silicon_rev  = AST2400_A0_SILICON_REV,
 144         .sram_size    = 0x8000,
 145         .spis_num     = 1,
 146         .fmc_typename = "aspeed.smc.fmc",
 147         .spi_typename = aspeed_soc_ast2400_typenames,
 148         .wdts_num     = 2,
 149         .irqmap       = aspeed_soc_ast2400_irqmap,
 150         .memmap       = aspeed_soc_ast2400_memmap,
 151         .num_cpus     = 1,
 152     }, {
 153         .name         = "ast2500-a1",
 154         .cpu_type     = ARM_CPU_TYPE_NAME("arm1176"),
 155         .silicon_rev  = AST2500_A1_SILICON_REV,
 156         .sram_size    = 0x9000,
 157         .spis_num     = 2,
 158         .fmc_typename = "aspeed.smc.ast2500-fmc",
 159         .spi_typename = aspeed_soc_ast2500_typenames,
 160         .wdts_num     = 3,
 161         .irqmap       = aspeed_soc_ast2500_irqmap,
 162         .memmap       = aspeed_soc_ast2500_memmap,
 163         .num_cpus     = 1,
 164     },
 165 };
 166
 167 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
 168 {
 169     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 170
 171     return qdev_get_gpio_in(DEVICE(&s->vic), sc->info->irqmap[ctrl]);
 172 }
 173
 174 static void aspeed_soc_init(Object *obj)
 175 {
 176     AspeedSoCState *s = ASPEED_SOC(obj);
 177     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 178     int i;
 179
 180     for (i = 0; i < sc->info->num_cpus; i++) {
 181         object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
 182                                 sizeof(s->cpu[i]), sc->info->cpu_type,
 183                                 &error_abort, NULL);
 184     }
 185
 186     sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
 187                           TYPE_ASPEED_SCU);
 188     qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
 189                          sc->info->silicon_rev);
 190     object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
 191                               "hw-strap1", &error_abort);
 192     object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
 193                               "hw-strap2", &error_abort);
 194     object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
 195                               "hw-prot-key", &error_abort);
 196
 197     sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
 198                           TYPE_ASPEED_VIC);
 199
 200     sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
 201                           TYPE_ASPEED_RTC);
 202
 203     sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
 204                           sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
 205     object_property_add_const_link(OBJECT(&s->timerctrl), "scu",
 206                                    OBJECT(&s->scu), &error_abort);
 207
 208     sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
 209                           TYPE_ASPEED_I2C);
 210
 211     sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
 212                           sc->info->fmc_typename);
 213     object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
 214                               &error_abort);
 215
 216     for (i = 0; i < sc->info->spis_num; i++) {
 217         sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
 218                               sizeof(s->spi[i]), sc->info->spi_typename[i]);
 219     }
 220
 221     sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
 222                           TYPE_ASPEED_SDMC);
 223     qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
 224                          sc->info->silicon_rev);
 225     object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
 226                               "ram-size", &error_abort);
 227     object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
 228                               "max-ram-size", &error_abort);
 229
 230     for (i = 0; i < sc->info->wdts_num; i++) {
 231         sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
 232                               sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
 233         qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev",
 234                                     sc->info->silicon_rev);
 235     }
 236
 237     sysbus_init_child_obj(obj, "ftgmac100", OBJECT(&s->ftgmac100),
 238                           sizeof(s->ftgmac100), TYPE_FTGMAC100);
 239 }
 240
 241 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
 242 {
 243     int i;
 244     AspeedSoCState *s = ASPEED_SOC(dev);
 245     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 246     Error *err = NULL, *local_err = NULL;
 247
 248     /* IO space */
 249     create_unimplemented_device("aspeed_soc.io", sc->info->memmap[ASPEED_IOMEM],
 250                                 ASPEED_SOC_IOMEM_SIZE);
 251
 252     if (s->num_cpus > sc->info->num_cpus) {
 253         warn_report("%s: invalid number of CPUs %d, using default %d",
 254                     sc->info->name, s->num_cpus, sc->info->num_cpus);
 255         s->num_cpus = sc->info->num_cpus;
 256     }
 257
 258     /* CPU */
 259     for (i = 0; i < s->num_cpus; i++) {
 260         object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
 261         if (err) {
 262             error_propagate(errp, err);
 263             return;
 264         }
 265     }
 266
 267     /* SRAM */
 268     memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
 269                            sc->info->sram_size, &err);
 270     if (err) {
 271         error_propagate(errp, err);
 272         return;
 273     }
 274     memory_region_add_subregion(get_system_memory(),
 275                                 sc->info->memmap[ASPEED_SRAM], &s->sram);
 276
 277     /* SCU */
 278     object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
 279     if (err) {
 280         error_propagate(errp, err);
 281         return;
 282     }
 283     sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->info->memmap[ASPEED_SCU]);
 284
 285     /* VIC */
 286     object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
 287     if (err) {
 288         error_propagate(errp, err);
 289         return;
 290     }
 291     sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->info->memmap[ASPEED_VIC]);
 292     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
 293                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
 294     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
 295                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
 296
 297     /* RTC */
 298     object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
 299     if (err) {
 300         error_propagate(errp, err);
 301         return;
 302     }
 303     sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->info->memmap[ASPEED_RTC]);
 304     sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
 305                        aspeed_soc_get_irq(s, ASPEED_RTC));
 306
 307     /* Timer */
 308     object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
 309     if (err) {
 310         error_propagate(errp, err);
 311         return;
 312     }
 313     sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
 314                     sc->info->memmap[ASPEED_TIMER1]);
 315     for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
 316         qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
 317         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
 318     }
 319
 320     /* UART - attach an 8250 to the IO space as our UART5 */
 321     if (serial_hd(0)) {
 322         qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
 323         serial_mm_init(get_system_memory(), sc->info->memmap[ASPEED_UART5], 2,
 324                        uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
 325     }
 326
 327     /* I2C */
 328     object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
 329     if (err) {
 330         error_propagate(errp, err);
 331         return;
 332     }
 333     sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->info->memmap[ASPEED_I2C]);
 334     sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
 335                        aspeed_soc_get_irq(s, ASPEED_I2C));
 336
 337     /* FMC, The number of CS is set at the board level */
 338     object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
 339     if (err) {
 340         error_propagate(errp, err);
 341         return;
 342     }
 343     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->info->memmap[ASPEED_FMC]);
 344     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
 345                     s->fmc.ctrl->flash_window_base);
 346     sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
 347                        aspeed_soc_get_irq(s, ASPEED_FMC));
 348
 349     /* SPI */
 350     for (i = 0; i < sc->info->spis_num; i++) {
 351         object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
 352         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
 353                                  &local_err);
 354         error_propagate(&err, local_err);
 355         if (err) {
 356             error_propagate(errp, err);
 357             return;
 358         }
 359         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
 360                         sc->info->memmap[ASPEED_SPI1 + i]);
 361         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
 362                         s->spi[i].ctrl->flash_window_base);
 363     }
 364
 365     /* SDMC - SDRAM Memory Controller */
 366     object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
 367     if (err) {
 368         error_propagate(errp, err);
 369         return;
 370     }
 371     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->info->memmap[ASPEED_SDMC]);
 372
 373     /* Watch dog */
 374     for (i = 0; i < sc->info->wdts_num; i++) {
 375         object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
 376         if (err) {
 377             error_propagate(errp, err);
 378             return;
 379         }
 380         sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
 381                         sc->info->memmap[ASPEED_WDT] + i * 0x20);
 382     }
 383
 384     /* Net */
 385     qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]);
 386     object_property_set_bool(OBJECT(&s->ftgmac100), true, "aspeed", &err);
 387     object_property_set_bool(OBJECT(&s->ftgmac100), true, "realized",
 388                              &local_err);
 389     error_propagate(&err, local_err);
 390     if (err) {
 391         error_propagate(errp, err);
 392         return;
 393     }
 394     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0,
 395                     sc->info->memmap[ASPEED_ETH1]);
 396     sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0,
 397                        aspeed_soc_get_irq(s, ASPEED_ETH1));
 398 }
 399 static Property aspeed_soc_properties[] = {
 400     DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
 401     DEFINE_PROP_END_OF_LIST(),
 402 };
 403
 404 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 405 {
 406     DeviceClass *dc = DEVICE_CLASS(oc);
 407     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
 408
 409     sc->info = (AspeedSoCInfo *) data;
 410     dc->realize = aspeed_soc_realize;
 411     /* Reason: Uses serial_hds and nd_table in realize() directly */
 412     dc->user_creatable = false;
 413     dc->props = aspeed_soc_properties;
 414 }
 415
 416 static const TypeInfo aspeed_soc_type_info = {
 417     .name           = TYPE_ASPEED_SOC,
 418     .parent         = TYPE_DEVICE,
 419     .instance_init  = aspeed_soc_init,
 420     .instance_size  = sizeof(AspeedSoCState),
 421     .class_size     = sizeof(AspeedSoCClass),
 422     .abstract       = true,
 423 };
 424
 425 static void aspeed_soc_register_types(void)
 426 {
 427     int i;
 428
 429     type_register_static(&aspeed_soc_type_info);
 430     for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {
 431         TypeInfo ti = {
 432             .name       = aspeed_socs[i].name,
 433             .parent     = TYPE_ASPEED_SOC,
 434             .class_init = aspeed_soc_class_init,
 435             .class_data = (void *) &aspeed_socs[i],
 436         };
 437         type_register(&ti);
 438     }
 439 }
 440
 441 type_init(aspeed_soc_register_types)