hw/arm/aspeed.c

   1 /*
   2  * OpenPOWER Palmetto BMC
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "qapi/error.h"
  14 #include "cpu.h"
  15 #include "exec/address-spaces.h"
  16 #include "hw/arm/boot.h"
  17 #include "hw/arm/aspeed.h"
  18 #include "hw/arm/aspeed_soc.h"
  19 #include "hw/boards.h"
  20 #include "hw/i2c/smbus_eeprom.h"
  21 #include "hw/misc/pca9552.h"
  22 #include "hw/misc/tmp105.h"
  23 #include "qemu/log.h"
  24 #include "sysemu/block-backend.h"
  25 #include "sysemu/sysemu.h"
  26 #include "hw/loader.h"
  27 #include "qemu/error-report.h"
  28 #include "qemu/units.h"
  29
  30 static struct arm_boot_info aspeed_board_binfo = {
  31     .board_id = -1, /* device-tree-only board */
  32 };
  33
  34 struct AspeedBoardState {
  35     AspeedSoCState soc;
  36     MemoryRegion ram;
  37     MemoryRegion max_ram;
  38 };
  39
  40 /* Palmetto hardware value: 0x120CE416 */
  41 #define PALMETTO_BMC_HW_STRAP1 (                                        \
  42         SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) |               \
  43         SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
  44         SCU_AST2400_HW_STRAP_ACPI_DIS |                                 \
  45         SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) |       \
  46         SCU_HW_STRAP_VGA_CLASS_CODE |                                   \
  47         SCU_HW_STRAP_LPC_RESET_PIN |                                    \
  48         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) |                \
  49         SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
  50         SCU_HW_STRAP_SPI_WIDTH |                                        \
  51         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
  52         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
  53
  54 /* AST2500 evb hardware value: 0xF100C2E6 */
  55 #define AST2500_EVB_HW_STRAP1 ((                                        \
  56         AST2500_HW_STRAP1_DEFAULTS |                                    \
  57         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
  58         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
  59         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
  60         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
  61         SCU_HW_STRAP_MAC1_RGMII |                                       \
  62         SCU_HW_STRAP_MAC0_RGMII) &                                      \
  63         ~SCU_HW_STRAP_2ND_BOOT_WDT)
  64
  65 /* Romulus hardware value: 0xF10AD206 */
  66 #define ROMULUS_BMC_HW_STRAP1 (                                         \
  67         AST2500_HW_STRAP1_DEFAULTS |                                    \
  68         SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
  69         SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
  70         SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
  71         SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
  72         SCU_AST2500_HW_STRAP_ACPI_ENABLE |                              \
  73         SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
  74
  75 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
  76 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
  77
  78 /*
  79  * The max ram region is for firmwares that scan the address space
  80  * with load/store to guess how much RAM the SoC has.
  81  */
  82 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
  83 {
  84     return 0;
  85 }
  86
  87 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
  88                            unsigned size)
  89 {
  90     /* Discard writes */
  91 }
  92
  93 static const MemoryRegionOps max_ram_ops = {
  94     .read = max_ram_read,
  95     .write = max_ram_write,
  96     .endianness = DEVICE_NATIVE_ENDIAN,
  97 };
  98
  99 #define FIRMWARE_ADDR 0x0
 100
 101 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
 102                            Error **errp)
 103 {
 104     BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
 105     uint8_t *storage;
 106     int64_t size;
 107
 108     /* The block backend size should have already been 'validated' by
 109      * the creation of the m25p80 object.
 110      */
 111     size = blk_getlength(blk);
 112     if (size <= 0) {
 113         error_setg(errp, "failed to get flash size");
 114         return;
 115     }
 116
 117     if (rom_size > size) {
 118         rom_size = size;
 119     }
 120
 121     storage = g_new0(uint8_t, rom_size);
 122     if (blk_pread(blk, 0, storage, rom_size) < 0) {
 123         error_setg(errp, "failed to read the initial flash content");
 124         return;
 125     }
 126
 127     rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
 128     g_free(storage);
 129 }
 130
 131 static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
 132                                       Error **errp)
 133 {
 134     int i ;
 135
 136     for (i = 0; i < s->num_cs; ++i) {
 137         AspeedSMCFlash *fl = &s->flashes[i];
 138         DriveInfo *dinfo = drive_get_next(IF_MTD);
 139         qemu_irq cs_line;
 140
 141         fl->flash = ssi_create_slave_no_init(s->spi, flashtype);
 142         if (dinfo) {
 143             qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo),
 144                                 errp);
 145         }
 146         qdev_init_nofail(fl->flash);
 147
 148         cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0);
 149         sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
 150     }
 151 }
 152
 153 static void aspeed_board_init(MachineState *machine,
 154                               const AspeedBoardConfig *cfg)
 155 {
 156     AspeedBoardState *bmc;
 157     AspeedSoCClass *sc;
 158     DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
 159     ram_addr_t max_ram_size;
 160
 161     bmc = g_new0(AspeedBoardState, 1);
 162     object_initialize_child(OBJECT(machine), "soc", &bmc->soc,
 163                             (sizeof(bmc->soc)), cfg->soc_name, &error_abort,
 164                             NULL);
 165
 166     sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
 167
 168     object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size",
 169                              &error_abort);
 170     object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1",
 171                             &error_abort);
 172     object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs",
 173                             &error_abort);
 174     object_property_set_int(OBJECT(&bmc->soc), smp_cpus, "num-cpus",
 175                             &error_abort);
 176     if (machine->kernel_filename) {
 177         /*
 178          * When booting with a -kernel command line there is no u-boot
 179          * that runs to unlock the SCU. In this case set the default to
 180          * be unlocked as the kernel expects
 181          */
 182         object_property_set_int(OBJECT(&bmc->soc), ASPEED_SCU_PROT_KEY,
 183                                 "hw-prot-key", &error_abort);
 184     }
 185     object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
 186                              &error_abort);
 187
 188     /*
 189      * Allocate RAM after the memory controller has checked the size
 190      * was valid. If not, a default value is used.
 191      */
 192     ram_size = object_property_get_uint(OBJECT(&bmc->soc), "ram-size",
 193                                         &error_abort);
 194
 195     memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size);
 196     memory_region_add_subregion(get_system_memory(),
 197                                 sc->info->memmap[ASPEED_SDRAM], &bmc->ram);
 198     object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
 199                                    &error_abort);
 200
 201     max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
 202                                             &error_abort);
 203     memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
 204                           "max_ram", max_ram_size  - ram_size);
 205     memory_region_add_subregion(get_system_memory(),
 206                                 sc->info->memmap[ASPEED_SDRAM] + ram_size,
 207                                 &bmc->max_ram);
 208
 209     aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort);
 210     aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort);
 211
 212     /* Install first FMC flash content as a boot rom. */
 213     if (drive0) {
 214         AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
 215         MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
 216
 217         /*
 218          * create a ROM region using the default mapping window size of
 219          * the flash module. The window size is 64MB for the AST2400
 220          * SoC and 128MB for the AST2500 SoC, which is twice as big as
 221          * needed by the flash modules of the Aspeed machines.
 222          */
 223         memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
 224                                fl->size, &error_abort);
 225         memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
 226                                     boot_rom);
 227         write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
 228     }
 229
 230     aspeed_board_binfo.kernel_filename = machine->kernel_filename;
 231     aspeed_board_binfo.initrd_filename = machine->initrd_filename;
 232     aspeed_board_binfo.kernel_cmdline = machine->kernel_cmdline;
 233     aspeed_board_binfo.ram_size = ram_size;
 234     aspeed_board_binfo.loader_start = sc->info->memmap[ASPEED_SDRAM];
 235     aspeed_board_binfo.nb_cpus = bmc->soc.num_cpus;
 236
 237     if (cfg->i2c_init) {
 238         cfg->i2c_init(bmc);
 239     }
 240
 241     arm_load_kernel(ARM_CPU(first_cpu), &aspeed_board_binfo);
 242 }
 243
 244 static void palmetto_bmc_i2c_init(AspeedBoardState *bmc)
 245 {
 246     AspeedSoCState *soc = &bmc->soc;
 247     DeviceState *dev;
 248     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
 249
 250     /* The palmetto platform expects a ds3231 RTC but a ds1338 is
 251      * enough to provide basic RTC features. Alarms will be missing */
 252     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68);
 253
 254     smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), 0x50,
 255                           eeprom_buf);
 256
 257     /* add a TMP423 temperature sensor */
 258     dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2),
 259                            "tmp423", 0x4c);
 260     object_property_set_int(OBJECT(dev), 31000, "temperature0", &error_abort);
 261     object_property_set_int(OBJECT(dev), 28000, "temperature1", &error_abort);
 262     object_property_set_int(OBJECT(dev), 20000, "temperature2", &error_abort);
 263     object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort);
 264 }
 265
 266 static void ast2500_evb_i2c_init(AspeedBoardState *bmc)
 267 {
 268     AspeedSoCState *soc = &bmc->soc;
 269     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 270
 271     smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), 0x50,
 272                           eeprom_buf);
 273
 274     /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
 275     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7),
 276                      TYPE_TMP105, 0x4d);
 277
 278     /* The AST2500 EVB does not have an RTC. Let's pretend that one is
 279      * plugged on the I2C bus header */
 280     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
 281 }
 282
 283 static void romulus_bmc_i2c_init(AspeedBoardState *bmc)
 284 {
 285     AspeedSoCState *soc = &bmc->soc;
 286
 287     /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
 288      * good enough */
 289     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
 290 }
 291
 292 static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
 293 {
 294     AspeedSoCState *soc = &bmc->soc;
 295     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 296
 297     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), TYPE_PCA9552,
 298                      0x60);
 299
 300     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c);
 301     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c);
 302
 303     /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
 304     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), TYPE_TMP105,
 305                      0x4a);
 306
 307     /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
 308      * good enough */
 309     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
 310
 311     smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), 0x51,
 312                           eeprom_buf);
 313     i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), TYPE_PCA9552,
 314                      0x60);
 315 }
 316
 317 static void aspeed_machine_init(MachineState *machine)
 318 {
 319     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
 320
 321     aspeed_board_init(machine, amc->board);
 322 }
 323
 324 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
 325 {
 326     MachineClass *mc = MACHINE_CLASS(oc);
 327     AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
 328     const AspeedBoardConfig *board = data;
 329
 330     mc->desc = board->desc;
 331     mc->init = aspeed_machine_init;
 332     mc->max_cpus = ASPEED_CPUS_NUM;
 333     mc->no_sdcard = 1;
 334     mc->no_floppy = 1;
 335     mc->no_cdrom = 1;
 336     mc->no_parallel = 1;
 337     if (board->ram) {
 338         mc->default_ram_size = board->ram;
 339     }
 340     amc->board = board;
 341 }
 342
 343 static const TypeInfo aspeed_machine_type = {
 344     .name = TYPE_ASPEED_MACHINE,
 345     .parent = TYPE_MACHINE,
 346     .instance_size = sizeof(AspeedMachine),
 347     .class_size = sizeof(AspeedMachineClass),
 348     .abstract = true,
 349 };
 350
 351 static const AspeedBoardConfig aspeed_boards[] = {
 352     {
 353         .name      = MACHINE_TYPE_NAME("palmetto-bmc"),
 354         .desc      = "OpenPOWER Palmetto BMC (ARM926EJ-S)",
 355         .soc_name  = "ast2400-a1",
 356         .hw_strap1 = PALMETTO_BMC_HW_STRAP1,
 357         .fmc_model = "n25q256a",
 358         .spi_model = "mx25l25635e",
 359         .num_cs    = 1,
 360         .i2c_init  = palmetto_bmc_i2c_init,
 361         .ram       = 256 * MiB,
 362     }, {
 363         .name      = MACHINE_TYPE_NAME("ast2500-evb"),
 364         .desc      = "Aspeed AST2500 EVB (ARM1176)",
 365         .soc_name  = "ast2500-a1",
 366         .hw_strap1 = AST2500_EVB_HW_STRAP1,
 367         .fmc_model = "w25q256",
 368         .spi_model = "mx25l25635e",
 369         .num_cs    = 1,
 370         .i2c_init  = ast2500_evb_i2c_init,
 371         .ram       = 512 * MiB,
 372     }, {
 373         .name      = MACHINE_TYPE_NAME("romulus-bmc"),
 374         .desc      = "OpenPOWER Romulus BMC (ARM1176)",
 375         .soc_name  = "ast2500-a1",
 376         .hw_strap1 = ROMULUS_BMC_HW_STRAP1,
 377         .fmc_model = "n25q256a",
 378         .spi_model = "mx66l1g45g",
 379         .num_cs    = 2,
 380         .i2c_init  = romulus_bmc_i2c_init,
 381         .ram       = 512 * MiB,
 382     }, {
 383         .name      = MACHINE_TYPE_NAME("witherspoon-bmc"),
 384         .desc      = "OpenPOWER Witherspoon BMC (ARM1176)",
 385         .soc_name  = "ast2500-a1",
 386         .hw_strap1 = WITHERSPOON_BMC_HW_STRAP1,
 387         .fmc_model = "mx25l25635e",
 388         .spi_model = "mx66l1g45g",
 389         .num_cs    = 2,
 390         .i2c_init  = witherspoon_bmc_i2c_init,
 391         .ram       = 512 * MiB,
 392     },
 393 };
 394
 395 static void aspeed_machine_types(void)
 396 {
 397     int i;
 398
 399     type_register_static(&aspeed_machine_type);
 400     for (i = 0; i < ARRAY_SIZE(aspeed_boards); ++i) {
 401         TypeInfo ti = {
 402             .name       = aspeed_boards[i].name,
 403             .parent     = TYPE_ASPEED_MACHINE,
 404             .class_init = aspeed_machine_class_init,
 405             .class_data = (void *)&aspeed_boards[i],
 406         };
 407         type_register(&ti);
 408     }
 409 }
 410
 411 type_init(aspeed_machine_types)