4 #include "host-utils.h"
7 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
11 /* VFP data registers are always little-endian. */
12 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
14 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
17 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
18 /* Aliases for Q regs. */
21 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
22 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
26 switch (reg
- nregs
) {
27 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
28 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
29 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
34 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
38 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
40 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
43 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
46 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
47 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
51 switch (reg
- nregs
) {
52 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
53 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
54 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
59 static int dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
62 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
66 static const ARMCPRegInfo cp_reginfo
[] = {
67 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
68 * version" bits will read as a reserved value, which should cause
69 * Linux to not try to use the debug hardware.
71 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
72 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
73 /* MMU Domain access control / MPU write buffer control */
74 { .name
= "DACR", .cp
= 15,
75 .crn
= 3, .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
76 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c3
),
77 .resetvalue
= 0, .writefn
= dacr_write
},
81 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
82 /* Not all pre-v6 cores implemented this WFI, so this is slightly
85 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
86 .access
= PL1_W
, .type
= ARM_CP_WFI
},
90 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
91 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
92 * is UNPREDICTABLE; we choose to NOP as most implementations do).
94 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
95 .access
= PL1_W
, .type
= ARM_CP_WFI
},
99 static const ARMCPRegInfo v6_cp_reginfo
[] = {
100 /* prefetch by MVA in v6, NOP in v7 */
101 { .name
= "MVA_prefetch",
102 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
103 .access
= PL1_W
, .type
= ARM_CP_NOP
},
104 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
105 .access
= PL0_W
, .type
= ARM_CP_NOP
},
106 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
107 .access
= PL0_W
, .type
= ARM_CP_NOP
},
108 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
109 .access
= PL0_W
, .type
= ARM_CP_NOP
},
113 static int pmreg_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
116 /* Generic performance monitor register read function for where
117 * user access may be allowed by PMUSERENR.
119 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
122 *value
= CPREG_FIELD32(env
, ri
);
126 static int pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
129 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
132 /* only the DP, X, D and E bits are writable */
133 env
->cp15
.c9_pmcr
&= ~0x39;
134 env
->cp15
.c9_pmcr
|= (value
& 0x39);
138 static int pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
141 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
145 env
->cp15
.c9_pmcnten
|= value
;
149 static int pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
152 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
156 env
->cp15
.c9_pmcnten
&= ~value
;
160 static int pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
163 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
166 env
->cp15
.c9_pmovsr
&= ~value
;
170 static int pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
173 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
176 env
->cp15
.c9_pmxevtyper
= value
& 0xff;
180 static int pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
183 env
->cp15
.c9_pmuserenr
= value
& 1;
187 static int pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
190 /* We have no event counters so only the C bit can be changed */
192 env
->cp15
.c9_pminten
|= value
;
196 static int pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
200 env
->cp15
.c9_pminten
&= ~value
;
204 static const ARMCPRegInfo v7_cp_reginfo
[] = {
205 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
208 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
209 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
210 { .name
= "DBGDRAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
211 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
212 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
213 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
214 .access
= PL1_W
, .type
= ARM_CP_NOP
},
215 /* Performance monitors are implementation defined in v7,
216 * but with an ARM recommended set of registers, which we
217 * follow (although we don't actually implement any counters)
219 * Performance registers fall into three categories:
220 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
221 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
222 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
223 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
224 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
226 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
227 .access
= PL0_RW
, .resetvalue
= 0,
228 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
229 .readfn
= pmreg_read
, .writefn
= pmcntenset_write
},
230 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
231 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
232 .readfn
= pmreg_read
, .writefn
= pmcntenclr_write
},
233 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
234 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
235 .readfn
= pmreg_read
, .writefn
= pmovsr_write
},
236 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
239 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
240 .access
= PL0_W
, .type
= ARM_CP_NOP
},
241 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
242 * We choose to RAZ/WI. XXX should respect PMUSERENR.
244 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
245 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
246 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
247 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
248 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
249 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
251 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmxevtyper
),
252 .readfn
= pmreg_read
, .writefn
= pmxevtyper_write
},
253 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
254 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
255 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
256 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
257 .access
= PL0_R
| PL1_RW
,
258 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
260 .writefn
= pmuserenr_write
},
261 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
263 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
265 .writefn
= pmintenset_write
},
266 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
268 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
270 .writefn
= pmintenclr_write
},
274 static int teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
281 static int teehbr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
284 /* This is a helper function because the user access rights
285 * depend on the value of the TEECR.
287 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
290 *value
= env
->teehbr
;
294 static int teehbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
297 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
304 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
305 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
306 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
308 .writefn
= teecr_write
},
309 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
310 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
312 .readfn
= teehbr_read
, .writefn
= teehbr_write
},
316 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
317 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
319 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls1
),
321 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
322 .access
= PL0_R
|PL1_W
,
323 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls2
),
325 { .name
= "TPIDRPRW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 4,
327 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls3
),
332 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
333 /* Dummy implementation: RAZ/WI the whole crn=14 space */
334 { .name
= "GENERIC_TIMER", .cp
= 15, .crn
= 14,
335 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
336 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
340 /* Return basic MPU access permission bits. */
341 static uint32_t simple_mpu_ap_bits(uint32_t val
)
348 for (i
= 0; i
< 16; i
+= 2) {
349 ret
|= (val
>> i
) & mask
;
355 /* Pad basic MPU access permission bits to extended format. */
356 static uint32_t extended_mpu_ap_bits(uint32_t val
)
363 for (i
= 0; i
< 16; i
+= 2) {
364 ret
|= (val
& mask
) << i
;
370 static int pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
373 env
->cp15
.c5_data
= extended_mpu_ap_bits(value
);
377 static int pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
380 *value
= simple_mpu_ap_bits(env
->cp15
.c5_data
);
384 static int pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
387 env
->cp15
.c5_insn
= extended_mpu_ap_bits(value
);
391 static int pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
394 *value
= simple_mpu_ap_bits(env
->cp15
.c5_insn
);
398 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
399 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
401 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0,
402 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
403 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
405 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0,
406 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
407 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
409 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
410 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
412 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
413 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
415 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
416 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
418 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
422 static int vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
426 env
->cp15
.c2_control
= value
;
427 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> value
);
428 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> value
);
432 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
434 env
->cp15
.c2_base_mask
= 0xffffc000u
;
435 env
->cp15
.c2_control
= 0;
436 env
->cp15
.c2_mask
= 0;
439 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
440 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
442 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
443 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
445 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
446 { .name
= "TTBR0", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
448 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base0
), .resetvalue
= 0, },
449 { .name
= "TTBR1", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
451 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base0
), .resetvalue
= 0, },
452 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
453 .access
= PL1_RW
, .writefn
= vmsa_ttbcr_write
,
454 .resetfn
= vmsa_ttbcr_reset
,
455 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_control
) },
459 static const ARMCPRegInfo omap_cp_reginfo
[] = {
460 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
461 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
462 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
466 void register_cp_regs_for_features(ARMCPU
*cpu
)
468 /* Register all the coprocessor registers based on feature bits */
469 CPUARMState
*env
= &cpu
->env
;
470 if (arm_feature(env
, ARM_FEATURE_M
)) {
471 /* M profile has no coprocessor registers */
475 define_arm_cp_regs(cpu
, cp_reginfo
);
476 if (arm_feature(env
, ARM_FEATURE_V6
)) {
477 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
479 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
481 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
482 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
484 if (arm_feature(env
, ARM_FEATURE_V7
)) {
485 /* v7 performance monitor control register: same implementor
486 * field as main ID register, and we implement no event counters.
488 ARMCPRegInfo pmcr
= {
489 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
490 .access
= PL0_RW
, .resetvalue
= cpu
->midr
& 0xff000000,
491 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
492 .readfn
= pmreg_read
, .writefn
= pmcr_write
494 define_one_arm_cp_reg(cpu
, &pmcr
);
495 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
497 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
499 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
500 /* These are the MPU registers prior to PMSAv6. Any new
501 * PMSA core later than the ARM946 will require that we
502 * implement the PMSAv6 or PMSAv7 registers, which are
503 * completely different.
505 assert(!arm_feature(env
, ARM_FEATURE_V6
));
506 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
508 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
510 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
511 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
513 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
514 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
516 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
517 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
521 ARMCPU
*cpu_arm_init(const char *cpu_model
)
525 static int inited
= 0;
527 if (!object_class_by_name(cpu_model
)) {
530 cpu
= ARM_CPU(object_new(cpu_model
));
532 env
->cpu_model_str
= cpu_model
;
533 arm_cpu_realize(cpu
);
535 if (tcg_enabled() && !inited
) {
537 arm_translate_init();
541 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
542 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
543 51, "arm-neon.xml", 0);
544 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
545 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
546 35, "arm-vfp3.xml", 0);
547 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
548 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
549 19, "arm-vfp.xml", 0);
555 typedef struct ARMCPUListState
{
556 fprintf_function cpu_fprintf
;
560 /* Sort alphabetically by type name, except for "any". */
561 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
563 ObjectClass
*class_a
= (ObjectClass
*)a
;
564 ObjectClass
*class_b
= (ObjectClass
*)b
;
565 const char *name_a
, *name_b
;
567 name_a
= object_class_get_name(class_a
);
568 name_b
= object_class_get_name(class_b
);
569 if (strcmp(name_a
, "any") == 0) {
571 } else if (strcmp(name_b
, "any") == 0) {
574 return strcmp(name_a
, name_b
);
578 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
580 ObjectClass
*oc
= data
;
581 ARMCPUListState
*s
= user_data
;
583 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
584 object_class_get_name(oc
));
587 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
589 ARMCPUListState s
= {
591 .cpu_fprintf
= cpu_fprintf
,
595 list
= object_class_get_list(TYPE_ARM_CPU
, false);
596 list
= g_slist_sort(list
, arm_cpu_list_compare
);
597 (*cpu_fprintf
)(f
, "Available CPUs:\n");
598 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
602 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
603 const ARMCPRegInfo
*r
, void *opaque
)
605 /* Define implementations of coprocessor registers.
606 * We store these in a hashtable because typically
607 * there are less than 150 registers in a space which
608 * is 16*16*16*8*8 = 262144 in size.
609 * Wildcarding is supported for the crm, opc1 and opc2 fields.
610 * If a register is defined twice then the second definition is
611 * used, so this can be used to define some generic registers and
612 * then override them with implementation specific variations.
613 * At least one of the original and the second definition should
614 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
615 * against accidental use.
618 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
619 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
620 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
621 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
622 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
623 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
624 /* 64 bit registers have only CRm and Opc1 fields */
625 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
626 /* Check that the register definition has enough info to handle
627 * reads and writes if they are permitted.
629 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
630 if (r
->access
& PL3_R
) {
631 assert(r
->fieldoffset
|| r
->readfn
);
633 if (r
->access
& PL3_W
) {
634 assert(r
->fieldoffset
|| r
->writefn
);
637 /* Bad type field probably means missing sentinel at end of reg list */
638 assert(cptype_valid(r
->type
));
639 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
640 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
641 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
642 uint32_t *key
= g_new(uint32_t, 1);
643 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
644 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
645 *key
= ENCODE_CP_REG(r
->cp
, is64
, r
->crn
, crm
, opc1
, opc2
);
647 /* Make sure reginfo passed to helpers for wildcarded regs
648 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
653 /* Overriding of an existing definition must be explicitly
656 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
657 ARMCPRegInfo
*oldreg
;
658 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
659 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
660 fprintf(stderr
, "Register redefined: cp=%d %d bit "
661 "crn=%d crm=%d opc1=%d opc2=%d, "
662 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
663 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
664 oldreg
->name
, r2
->name
);
668 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
674 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
675 const ARMCPRegInfo
*regs
, void *opaque
)
677 /* Define a whole list of registers */
678 const ARMCPRegInfo
*r
;
679 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
680 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
684 const ARMCPRegInfo
*get_arm_cp_reginfo(ARMCPU
*cpu
, uint32_t encoded_cp
)
686 return g_hash_table_lookup(cpu
->cp_regs
, &encoded_cp
);
689 int arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
692 /* Helper coprocessor write function for write-ignore registers */
696 int arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t *value
)
698 /* Helper coprocessor write function for read-as-zero registers */
703 static int bad_mode_switch(CPUARMState
*env
, int mode
)
705 /* Return true if it is not valid for us to switch to
706 * this CPU mode (ie all the UNPREDICTABLE cases in
707 * the ARM ARM CPSRWriteByInstr pseudocode).
710 case ARM_CPU_MODE_USR
:
711 case ARM_CPU_MODE_SYS
:
712 case ARM_CPU_MODE_SVC
:
713 case ARM_CPU_MODE_ABT
:
714 case ARM_CPU_MODE_UND
:
715 case ARM_CPU_MODE_IRQ
:
716 case ARM_CPU_MODE_FIQ
:
723 uint32_t cpsr_read(CPUARMState
*env
)
727 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
728 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
729 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
730 | ((env
->condexec_bits
& 0xfc) << 8)
734 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
736 if (mask
& CPSR_NZCV
) {
737 env
->ZF
= (~val
) & CPSR_Z
;
739 env
->CF
= (val
>> 29) & 1;
740 env
->VF
= (val
<< 3) & 0x80000000;
743 env
->QF
= ((val
& CPSR_Q
) != 0);
745 env
->thumb
= ((val
& CPSR_T
) != 0);
746 if (mask
& CPSR_IT_0_1
) {
747 env
->condexec_bits
&= ~3;
748 env
->condexec_bits
|= (val
>> 25) & 3;
750 if (mask
& CPSR_IT_2_7
) {
751 env
->condexec_bits
&= 3;
752 env
->condexec_bits
|= (val
>> 8) & 0xfc;
754 if (mask
& CPSR_GE
) {
755 env
->GE
= (val
>> 16) & 0xf;
758 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
759 if (bad_mode_switch(env
, val
& CPSR_M
)) {
760 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
761 * We choose to ignore the attempt and leave the CPSR M field
766 switch_mode(env
, val
& CPSR_M
);
769 mask
&= ~CACHED_CPSR_BITS
;
770 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
773 /* Sign/zero extend */
774 uint32_t HELPER(sxtb16
)(uint32_t x
)
777 res
= (uint16_t)(int8_t)x
;
778 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
782 uint32_t HELPER(uxtb16
)(uint32_t x
)
785 res
= (uint16_t)(uint8_t)x
;
786 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
790 uint32_t HELPER(clz
)(uint32_t x
)
795 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
799 if (num
== INT_MIN
&& den
== -1)
804 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
811 uint32_t HELPER(rbit
)(uint32_t x
)
813 x
= ((x
& 0xff000000) >> 24)
814 | ((x
& 0x00ff0000) >> 8)
815 | ((x
& 0x0000ff00) << 8)
816 | ((x
& 0x000000ff) << 24);
817 x
= ((x
& 0xf0f0f0f0) >> 4)
818 | ((x
& 0x0f0f0f0f) << 4);
819 x
= ((x
& 0x88888888) >> 3)
820 | ((x
& 0x44444444) >> 1)
821 | ((x
& 0x22222222) << 1)
822 | ((x
& 0x11111111) << 3);
826 uint32_t HELPER(abs
)(uint32_t x
)
828 return ((int32_t)x
< 0) ? -x
: x
;
831 #if defined(CONFIG_USER_ONLY)
833 void do_interrupt (CPUARMState
*env
)
835 env
->exception_index
= -1;
838 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
, int rw
,
842 env
->exception_index
= EXCP_PREFETCH_ABORT
;
843 env
->cp15
.c6_insn
= address
;
845 env
->exception_index
= EXCP_DATA_ABORT
;
846 env
->cp15
.c6_data
= address
;
851 void HELPER(set_cp15
)(CPUARMState
*env
, uint32_t insn
, uint32_t val
)
853 cpu_abort(env
, "cp15 insn %08x\n", insn
);
856 uint32_t HELPER(get_cp15
)(CPUARMState
*env
, uint32_t insn
)
858 cpu_abort(env
, "cp15 insn %08x\n", insn
);
861 /* These should probably raise undefined insn exceptions. */
862 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
864 cpu_abort(env
, "v7m_mrs %d\n", reg
);
867 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
869 cpu_abort(env
, "v7m_mrs %d\n", reg
);
873 void switch_mode(CPUARMState
*env
, int mode
)
875 if (mode
!= ARM_CPU_MODE_USR
)
876 cpu_abort(env
, "Tried to switch out of user mode\n");
879 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
881 cpu_abort(env
, "banked r13 write\n");
884 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
886 cpu_abort(env
, "banked r13 read\n");
892 /* Map CPU modes onto saved register banks. */
893 static inline int bank_number(CPUARMState
*env
, int mode
)
896 case ARM_CPU_MODE_USR
:
897 case ARM_CPU_MODE_SYS
:
899 case ARM_CPU_MODE_SVC
:
901 case ARM_CPU_MODE_ABT
:
903 case ARM_CPU_MODE_UND
:
905 case ARM_CPU_MODE_IRQ
:
907 case ARM_CPU_MODE_FIQ
:
910 cpu_abort(env
, "Bad mode %x\n", mode
);
914 void switch_mode(CPUARMState
*env
, int mode
)
919 old_mode
= env
->uncached_cpsr
& CPSR_M
;
920 if (mode
== old_mode
)
923 if (old_mode
== ARM_CPU_MODE_FIQ
) {
924 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
925 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
926 } else if (mode
== ARM_CPU_MODE_FIQ
) {
927 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
928 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
931 i
= bank_number(env
, old_mode
);
932 env
->banked_r13
[i
] = env
->regs
[13];
933 env
->banked_r14
[i
] = env
->regs
[14];
934 env
->banked_spsr
[i
] = env
->spsr
;
936 i
= bank_number(env
, mode
);
937 env
->regs
[13] = env
->banked_r13
[i
];
938 env
->regs
[14] = env
->banked_r14
[i
];
939 env
->spsr
= env
->banked_spsr
[i
];
942 static void v7m_push(CPUARMState
*env
, uint32_t val
)
945 stl_phys(env
->regs
[13], val
);
948 static uint32_t v7m_pop(CPUARMState
*env
)
951 val
= ldl_phys(env
->regs
[13]);
956 /* Switch to V7M main or process stack pointer. */
957 static void switch_v7m_sp(CPUARMState
*env
, int process
)
960 if (env
->v7m
.current_sp
!= process
) {
961 tmp
= env
->v7m
.other_sp
;
962 env
->v7m
.other_sp
= env
->regs
[13];
964 env
->v7m
.current_sp
= process
;
968 static void do_v7m_exception_exit(CPUARMState
*env
)
973 type
= env
->regs
[15];
974 if (env
->v7m
.exception
!= 0)
975 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
977 /* Switch to the target stack. */
978 switch_v7m_sp(env
, (type
& 4) != 0);
980 env
->regs
[0] = v7m_pop(env
);
981 env
->regs
[1] = v7m_pop(env
);
982 env
->regs
[2] = v7m_pop(env
);
983 env
->regs
[3] = v7m_pop(env
);
984 env
->regs
[12] = v7m_pop(env
);
985 env
->regs
[14] = v7m_pop(env
);
986 env
->regs
[15] = v7m_pop(env
);
988 xpsr_write(env
, xpsr
, 0xfffffdff);
989 /* Undo stack alignment. */
992 /* ??? The exception return type specifies Thread/Handler mode. However
993 this is also implied by the xPSR value. Not sure what to do
994 if there is a mismatch. */
995 /* ??? Likewise for mismatches between the CONTROL register and the stack
999 static void do_interrupt_v7m(CPUARMState
*env
)
1001 uint32_t xpsr
= xpsr_read(env
);
1006 if (env
->v7m
.current_sp
)
1008 if (env
->v7m
.exception
== 0)
1011 /* For exceptions we just mark as pending on the NVIC, and let that
1013 /* TODO: Need to escalate if the current priority is higher than the
1014 one we're raising. */
1015 switch (env
->exception_index
) {
1017 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
1021 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
1023 case EXCP_PREFETCH_ABORT
:
1024 case EXCP_DATA_ABORT
:
1025 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
1028 if (semihosting_enabled
) {
1030 nr
= arm_lduw_code(env
->regs
[15], env
->bswap_code
) & 0xff;
1033 env
->regs
[0] = do_arm_semihosting(env
);
1037 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
1040 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
1042 case EXCP_EXCEPTION_EXIT
:
1043 do_v7m_exception_exit(env
);
1046 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
1047 return; /* Never happens. Keep compiler happy. */
1050 /* Align stack pointer. */
1051 /* ??? Should only do this if Configuration Control Register
1052 STACKALIGN bit is set. */
1053 if (env
->regs
[13] & 4) {
1057 /* Switch to the handler mode. */
1058 v7m_push(env
, xpsr
);
1059 v7m_push(env
, env
->regs
[15]);
1060 v7m_push(env
, env
->regs
[14]);
1061 v7m_push(env
, env
->regs
[12]);
1062 v7m_push(env
, env
->regs
[3]);
1063 v7m_push(env
, env
->regs
[2]);
1064 v7m_push(env
, env
->regs
[1]);
1065 v7m_push(env
, env
->regs
[0]);
1066 switch_v7m_sp(env
, 0);
1068 env
->condexec_bits
= 0;
1070 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
1071 env
->regs
[15] = addr
& 0xfffffffe;
1072 env
->thumb
= addr
& 1;
1075 /* Handle a CPU exception. */
1076 void do_interrupt(CPUARMState
*env
)
1084 do_interrupt_v7m(env
);
1087 /* TODO: Vectored interrupt controller. */
1088 switch (env
->exception_index
) {
1090 new_mode
= ARM_CPU_MODE_UND
;
1099 if (semihosting_enabled
) {
1100 /* Check for semihosting interrupt. */
1102 mask
= arm_lduw_code(env
->regs
[15] - 2, env
->bswap_code
) & 0xff;
1104 mask
= arm_ldl_code(env
->regs
[15] - 4, env
->bswap_code
)
1107 /* Only intercept calls from privileged modes, to provide some
1108 semblance of security. */
1109 if (((mask
== 0x123456 && !env
->thumb
)
1110 || (mask
== 0xab && env
->thumb
))
1111 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
1112 env
->regs
[0] = do_arm_semihosting(env
);
1116 new_mode
= ARM_CPU_MODE_SVC
;
1119 /* The PC already points to the next instruction. */
1123 /* See if this is a semihosting syscall. */
1124 if (env
->thumb
&& semihosting_enabled
) {
1125 mask
= arm_lduw_code(env
->regs
[15], env
->bswap_code
) & 0xff;
1127 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
1129 env
->regs
[0] = do_arm_semihosting(env
);
1133 env
->cp15
.c5_insn
= 2;
1134 /* Fall through to prefetch abort. */
1135 case EXCP_PREFETCH_ABORT
:
1136 new_mode
= ARM_CPU_MODE_ABT
;
1138 mask
= CPSR_A
| CPSR_I
;
1141 case EXCP_DATA_ABORT
:
1142 new_mode
= ARM_CPU_MODE_ABT
;
1144 mask
= CPSR_A
| CPSR_I
;
1148 new_mode
= ARM_CPU_MODE_IRQ
;
1150 /* Disable IRQ and imprecise data aborts. */
1151 mask
= CPSR_A
| CPSR_I
;
1155 new_mode
= ARM_CPU_MODE_FIQ
;
1157 /* Disable FIQ, IRQ and imprecise data aborts. */
1158 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
1162 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
1163 return; /* Never happens. Keep compiler happy. */
1166 if (env
->cp15
.c1_sys
& (1 << 13)) {
1169 switch_mode (env
, new_mode
);
1170 env
->spsr
= cpsr_read(env
);
1171 /* Clear IT bits. */
1172 env
->condexec_bits
= 0;
1173 /* Switch to the new mode, and to the correct instruction set. */
1174 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
1175 env
->uncached_cpsr
|= mask
;
1176 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1177 * and we should just guard the thumb mode on V4 */
1178 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
1179 env
->thumb
= (env
->cp15
.c1_sys
& (1 << 30)) != 0;
1181 env
->regs
[14] = env
->regs
[15] + offset
;
1182 env
->regs
[15] = addr
;
1183 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1186 /* Check section/page access permissions.
1187 Returns the page protection flags, or zero if the access is not
1189 static inline int check_ap(CPUARMState
*env
, int ap
, int domain_prot
,
1190 int access_type
, int is_user
)
1194 if (domain_prot
== 3) {
1195 return PAGE_READ
| PAGE_WRITE
;
1198 if (access_type
== 1)
1201 prot_ro
= PAGE_READ
;
1205 if (access_type
== 1)
1207 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
1209 return is_user
? 0 : PAGE_READ
;
1216 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
1221 return PAGE_READ
| PAGE_WRITE
;
1223 return PAGE_READ
| PAGE_WRITE
;
1224 case 4: /* Reserved. */
1227 return is_user
? 0 : prot_ro
;
1231 if (!arm_feature (env
, ARM_FEATURE_V6K
))
1239 static uint32_t get_level1_table_address(CPUARMState
*env
, uint32_t address
)
1243 if (address
& env
->cp15
.c2_mask
)
1244 table
= env
->cp15
.c2_base1
& 0xffffc000;
1246 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
1248 table
|= (address
>> 18) & 0x3ffc;
1252 static int get_phys_addr_v5(CPUARMState
*env
, uint32_t address
, int access_type
,
1253 int is_user
, uint32_t *phys_ptr
, int *prot
,
1254 target_ulong
*page_size
)
1265 /* Pagetable walk. */
1266 /* Lookup l1 descriptor. */
1267 table
= get_level1_table_address(env
, address
);
1268 desc
= ldl_phys(table
);
1270 domain
= (desc
>> 5) & 0x0f;
1271 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
1273 /* Section translation fault. */
1277 if (domain_prot
== 0 || domain_prot
== 2) {
1279 code
= 9; /* Section domain fault. */
1281 code
= 11; /* Page domain fault. */
1286 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1287 ap
= (desc
>> 10) & 3;
1289 *page_size
= 1024 * 1024;
1291 /* Lookup l2 entry. */
1293 /* Coarse pagetable. */
1294 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1296 /* Fine pagetable. */
1297 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
1299 desc
= ldl_phys(table
);
1301 case 0: /* Page translation fault. */
1304 case 1: /* 64k page. */
1305 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1306 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
1307 *page_size
= 0x10000;
1309 case 2: /* 4k page. */
1310 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1311 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
1312 *page_size
= 0x1000;
1314 case 3: /* 1k page. */
1316 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1317 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1319 /* Page translation fault. */
1324 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
1326 ap
= (desc
>> 4) & 3;
1330 /* Never happens, but compiler isn't smart enough to tell. */
1335 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
1337 /* Access permission fault. */
1341 *phys_ptr
= phys_addr
;
1344 return code
| (domain
<< 4);
1347 static int get_phys_addr_v6(CPUARMState
*env
, uint32_t address
, int access_type
,
1348 int is_user
, uint32_t *phys_ptr
, int *prot
,
1349 target_ulong
*page_size
)
1361 /* Pagetable walk. */
1362 /* Lookup l1 descriptor. */
1363 table
= get_level1_table_address(env
, address
);
1364 desc
= ldl_phys(table
);
1367 /* Section translation fault. */
1371 } else if (type
== 2 && (desc
& (1 << 18))) {
1375 /* Section or page. */
1376 domain
= (desc
>> 5) & 0x0f;
1378 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
1379 if (domain_prot
== 0 || domain_prot
== 2) {
1381 code
= 9; /* Section domain fault. */
1383 code
= 11; /* Page domain fault. */
1387 if (desc
& (1 << 18)) {
1389 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
1390 *page_size
= 0x1000000;
1393 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1394 *page_size
= 0x100000;
1396 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
1397 xn
= desc
& (1 << 4);
1400 /* Lookup l2 entry. */
1401 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1402 desc
= ldl_phys(table
);
1403 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
1405 case 0: /* Page translation fault. */
1408 case 1: /* 64k page. */
1409 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1410 xn
= desc
& (1 << 15);
1411 *page_size
= 0x10000;
1413 case 2: case 3: /* 4k page. */
1414 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1416 *page_size
= 0x1000;
1419 /* Never happens, but compiler isn't smart enough to tell. */
1424 if (domain_prot
== 3) {
1425 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1427 if (xn
&& access_type
== 2)
1430 /* The simplified model uses AP[0] as an access control bit. */
1431 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
1432 /* Access flag fault. */
1433 code
= (code
== 15) ? 6 : 3;
1436 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
1438 /* Access permission fault. */
1445 *phys_ptr
= phys_addr
;
1448 return code
| (domain
<< 4);
1451 static int get_phys_addr_mpu(CPUARMState
*env
, uint32_t address
, int access_type
,
1452 int is_user
, uint32_t *phys_ptr
, int *prot
)
1458 *phys_ptr
= address
;
1459 for (n
= 7; n
>= 0; n
--) {
1460 base
= env
->cp15
.c6_region
[n
];
1461 if ((base
& 1) == 0)
1463 mask
= 1 << ((base
>> 1) & 0x1f);
1464 /* Keep this shift separate from the above to avoid an
1465 (undefined) << 32. */
1466 mask
= (mask
<< 1) - 1;
1467 if (((base
^ address
) & ~mask
) == 0)
1473 if (access_type
== 2) {
1474 mask
= env
->cp15
.c5_insn
;
1476 mask
= env
->cp15
.c5_data
;
1478 mask
= (mask
>> (n
* 4)) & 0xf;
1485 *prot
= PAGE_READ
| PAGE_WRITE
;
1490 *prot
|= PAGE_WRITE
;
1493 *prot
= PAGE_READ
| PAGE_WRITE
;
1504 /* Bad permission. */
1511 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
1512 int access_type
, int is_user
,
1513 uint32_t *phys_ptr
, int *prot
,
1514 target_ulong
*page_size
)
1516 /* Fast Context Switch Extension. */
1517 if (address
< 0x02000000)
1518 address
+= env
->cp15
.c13_fcse
;
1520 if ((env
->cp15
.c1_sys
& 1) == 0) {
1521 /* MMU/MPU disabled. */
1522 *phys_ptr
= address
;
1523 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1524 *page_size
= TARGET_PAGE_SIZE
;
1526 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1527 *page_size
= TARGET_PAGE_SIZE
;
1528 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
1530 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
1531 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
1534 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
1539 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
,
1540 int access_type
, int mmu_idx
)
1543 target_ulong page_size
;
1547 is_user
= mmu_idx
== MMU_USER_IDX
;
1548 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
,
1551 /* Map a single [sub]page. */
1552 phys_addr
&= ~(uint32_t)0x3ff;
1553 address
&= ~(uint32_t)0x3ff;
1554 tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
, page_size
);
1558 if (access_type
== 2) {
1559 env
->cp15
.c5_insn
= ret
;
1560 env
->cp15
.c6_insn
= address
;
1561 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1563 env
->cp15
.c5_data
= ret
;
1564 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
1565 env
->cp15
.c5_data
|= (1 << 11);
1566 env
->cp15
.c6_data
= address
;
1567 env
->exception_index
= EXCP_DATA_ABORT
;
1572 target_phys_addr_t
cpu_get_phys_page_debug(CPUARMState
*env
, target_ulong addr
)
1575 target_ulong page_size
;
1579 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
, &page_size
);
1587 void HELPER(set_cp15
)(CPUARMState
*env
, uint32_t insn
, uint32_t val
)
1593 op1
= (insn
>> 21) & 7;
1594 op2
= (insn
>> 5) & 7;
1596 switch ((insn
>> 16) & 0xf) {
1599 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1601 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1603 if (arm_feature(env
, ARM_FEATURE_V7
)
1604 && op1
== 2 && crm
== 0 && op2
== 0) {
1605 env
->cp15
.c0_cssel
= val
& 0xf;
1609 case 1: /* System configuration. */
1610 if (arm_feature(env
, ARM_FEATURE_V7
)
1611 && op1
== 0 && crm
== 1 && op2
== 0) {
1612 env
->cp15
.c1_scr
= val
;
1615 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1619 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) || crm
== 0)
1620 env
->cp15
.c1_sys
= val
;
1621 /* ??? Lots of these bits are not implemented. */
1622 /* This may enable/disable the MMU, so do a TLB flush. */
1625 case 1: /* Auxiliary control register. */
1626 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1627 env
->cp15
.c1_xscaleauxcr
= val
;
1630 /* Not implemented. */
1633 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1635 if (env
->cp15
.c1_coproc
!= val
) {
1636 env
->cp15
.c1_coproc
= val
;
1637 /* ??? Is this safe when called from within a TB? */
1645 case 4: /* Reserved. */
1647 case 6: /* MMU Fault address / MPU base/size. */
1648 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1651 env
->cp15
.c6_region
[crm
] = val
;
1653 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1657 env
->cp15
.c6_data
= val
;
1659 case 1: /* ??? This is WFAR on armv6 */
1661 env
->cp15
.c6_insn
= val
;
1668 case 7: /* Cache control. */
1669 env
->cp15
.c15_i_max
= 0x000;
1670 env
->cp15
.c15_i_min
= 0xff0;
1674 /* No cache, so nothing to do except VA->PA translations. */
1675 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
1678 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1679 env
->cp15
.c7_par
= val
& 0xfffff6ff;
1681 env
->cp15
.c7_par
= val
& 0xfffff1ff;
1686 target_ulong page_size
;
1688 int ret
, is_user
= op2
& 2;
1689 int access_type
= op2
& 1;
1692 /* Other states are only available with TrustZone */
1695 ret
= get_phys_addr(env
, val
, access_type
, is_user
,
1696 &phys_addr
, &prot
, &page_size
);
1698 /* We do not set any attribute bits in the PAR */
1699 if (page_size
== (1 << 24)
1700 && arm_feature(env
, ARM_FEATURE_V7
)) {
1701 env
->cp15
.c7_par
= (phys_addr
& 0xff000000) | 1 << 1;
1703 env
->cp15
.c7_par
= phys_addr
& 0xfffff000;
1706 env
->cp15
.c7_par
= ((ret
& (10 << 1)) >> 5) |
1707 ((ret
& (12 << 1)) >> 6) |
1708 ((ret
& 0xf) << 1) | 1;
1715 case 8: /* MMU TLB control. */
1717 case 0: /* Invalidate all (TLBIALL) */
1720 case 1: /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
1721 tlb_flush_page(env
, val
& TARGET_PAGE_MASK
);
1723 case 2: /* Invalidate by ASID (TLBIASID) */
1724 tlb_flush(env
, val
== 0);
1726 case 3: /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
1727 tlb_flush_page(env
, val
& TARGET_PAGE_MASK
);
1734 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1736 if (arm_feature(env
, ARM_FEATURE_STRONGARM
))
1737 break; /* Ignore ReadBuffer access */
1739 case 0: /* Cache lockdown. */
1741 case 0: /* L1 cache. */
1744 env
->cp15
.c9_data
= val
;
1747 env
->cp15
.c9_insn
= val
;
1753 case 1: /* L2 cache. */
1754 /* Ignore writes to L2 lockdown/auxiliary registers. */
1760 case 1: /* TCM memory region registers. */
1761 /* Not implemented. */
1767 case 10: /* MMU TLB lockdown. */
1768 /* ??? TLB lockdown not implemented. */
1770 case 12: /* Reserved. */
1772 case 13: /* Process ID. */
1775 /* Unlike real hardware the qemu TLB uses virtual addresses,
1776 not modified virtual addresses, so this causes a TLB flush.
1778 if (env
->cp15
.c13_fcse
!= val
)
1780 env
->cp15
.c13_fcse
= val
;
1783 /* This changes the ASID, so do a TLB flush. */
1784 if (env
->cp15
.c13_context
!= val
1785 && !arm_feature(env
, ARM_FEATURE_MPU
))
1787 env
->cp15
.c13_context
= val
;
1793 case 15: /* Implementation specific. */
1794 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1795 if (op2
== 0 && crm
== 1) {
1796 if (env
->cp15
.c15_cpar
!= (val
& 0x3fff)) {
1797 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1799 env
->cp15
.c15_cpar
= val
& 0x3fff;
1805 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1809 case 1: /* Set TI925T configuration. */
1810 env
->cp15
.c15_ticonfig
= val
& 0xe7;
1811 env
->cp15
.c0_cpuid
= (val
& (1 << 5)) ? /* OS_TYPE bit */
1812 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1814 case 2: /* Set I_max. */
1815 env
->cp15
.c15_i_max
= val
;
1817 case 3: /* Set I_min. */
1818 env
->cp15
.c15_i_min
= val
;
1820 case 4: /* Set thread-ID. */
1821 env
->cp15
.c15_threadid
= val
& 0xffff;
1823 case 8: /* Wait-for-interrupt (deprecated). */
1824 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
1830 if (ARM_CPUID(env
) == ARM_CPUID_CORTEXA9
) {
1833 if ((op1
== 0) && (op2
== 0)) {
1834 env
->cp15
.c15_power_control
= val
;
1835 } else if ((op1
== 0) && (op2
== 1)) {
1836 env
->cp15
.c15_diagnostic
= val
;
1837 } else if ((op1
== 0) && (op2
== 2)) {
1838 env
->cp15
.c15_power_diagnostic
= val
;
1848 /* ??? For debugging only. Should raise illegal instruction exception. */
1849 cpu_abort(env
, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1850 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1853 uint32_t HELPER(get_cp15
)(CPUARMState
*env
, uint32_t insn
)
1859 op1
= (insn
>> 21) & 7;
1860 op2
= (insn
>> 5) & 7;
1862 switch ((insn
>> 16) & 0xf) {
1863 case 0: /* ID codes. */
1869 case 0: /* Device ID. */
1870 return env
->cp15
.c0_cpuid
;
1871 case 1: /* Cache Type. */
1872 return env
->cp15
.c0_cachetype
;
1873 case 2: /* TCM status. */
1875 case 3: /* TLB type register. */
1876 return 0; /* No lockable TLB entries. */
1878 /* The MPIDR was standardised in v7; prior to
1879 * this it was implemented only in the 11MPCore.
1880 * For all other pre-v7 cores it does not exist.
1882 if (arm_feature(env
, ARM_FEATURE_V7
) ||
1883 ARM_CPUID(env
) == ARM_CPUID_ARM11MPCORE
) {
1884 int mpidr
= env
->cpu_index
;
1885 /* We don't support setting cluster ID ([8..11])
1886 * so these bits always RAZ.
1888 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
1890 /* Cores which are uniprocessor (non-coherent)
1891 * but still implement the MP extensions set
1892 * bit 30. (For instance, A9UP.) However we do
1893 * not currently model any of those cores.
1898 /* otherwise fall through to the unimplemented-reg case */
1903 if (!arm_feature(env
, ARM_FEATURE_V6
))
1905 return env
->cp15
.c0_c1
[op2
];
1907 if (!arm_feature(env
, ARM_FEATURE_V6
))
1909 return env
->cp15
.c0_c2
[op2
];
1910 case 3: case 4: case 5: case 6: case 7:
1916 /* These registers aren't documented on arm11 cores. However
1917 Linux looks at them anyway. */
1918 if (!arm_feature(env
, ARM_FEATURE_V6
))
1922 if (!arm_feature(env
, ARM_FEATURE_V7
))
1927 return env
->cp15
.c0_ccsid
[env
->cp15
.c0_cssel
];
1929 return env
->cp15
.c0_clid
;
1935 if (op2
!= 0 || crm
!= 0)
1937 return env
->cp15
.c0_cssel
;
1941 case 1: /* System configuration. */
1942 if (arm_feature(env
, ARM_FEATURE_V7
)
1943 && op1
== 0 && crm
== 1 && op2
== 0) {
1944 return env
->cp15
.c1_scr
;
1946 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1949 case 0: /* Control register. */
1950 return env
->cp15
.c1_sys
;
1951 case 1: /* Auxiliary control register. */
1952 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1953 return env
->cp15
.c1_xscaleauxcr
;
1954 if (!arm_feature(env
, ARM_FEATURE_AUXCR
))
1956 switch (ARM_CPUID(env
)) {
1957 case ARM_CPUID_ARM1026
:
1959 case ARM_CPUID_ARM1136
:
1960 case ARM_CPUID_ARM1136_R2
:
1961 case ARM_CPUID_ARM1176
:
1963 case ARM_CPUID_ARM11MPCORE
:
1965 case ARM_CPUID_CORTEXA8
:
1967 case ARM_CPUID_CORTEXA9
:
1968 case ARM_CPUID_CORTEXA15
:
1973 case 2: /* Coprocessor access register. */
1974 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1976 return env
->cp15
.c1_coproc
;
1980 case 4: /* Reserved. */
1982 case 6: /* MMU Fault address. */
1983 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1986 return env
->cp15
.c6_region
[crm
];
1988 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1992 return env
->cp15
.c6_data
;
1994 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1995 /* Watchpoint Fault Adrress. */
1996 return 0; /* Not implemented. */
1998 /* Instruction Fault Adrress. */
1999 /* Arm9 doesn't have an IFAR, but implementing it anyway
2000 shouldn't do any harm. */
2001 return env
->cp15
.c6_insn
;
2004 if (arm_feature(env
, ARM_FEATURE_V6
)) {
2005 /* Instruction Fault Adrress. */
2006 return env
->cp15
.c6_insn
;
2014 case 7: /* Cache control. */
2015 if (crm
== 4 && op1
== 0 && op2
== 0) {
2016 return env
->cp15
.c7_par
;
2018 /* FIXME: Should only clear Z flag if destination is r15. */
2021 case 8: /* MMU TLB control. */
2025 case 0: /* Cache lockdown */
2027 case 0: /* L1 cache. */
2028 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
2033 return env
->cp15
.c9_data
;
2035 return env
->cp15
.c9_insn
;
2039 case 1: /* L2 cache */
2040 /* L2 Lockdown and Auxiliary control. */
2043 /* L2 cache lockdown (A8 only) */
2046 /* L2 cache auxiliary control (A8) or control (A15) */
2047 if (ARM_CPUID(env
) == ARM_CPUID_CORTEXA15
) {
2048 /* Linux wants the number of processors from here.
2049 * Might as well set the interrupt-controller bit too.
2051 return ((smp_cpus
- 1) << 24) | (1 << 23);
2055 /* L2 cache extended control (A15) */
2068 case 10: /* MMU TLB lockdown. */
2069 /* ??? TLB lockdown not implemented. */
2071 case 11: /* TCM DMA control. */
2072 case 12: /* Reserved. */
2074 case 13: /* Process ID. */
2077 return env
->cp15
.c13_fcse
;
2079 return env
->cp15
.c13_context
;
2083 case 15: /* Implementation specific. */
2084 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
2085 if (op2
== 0 && crm
== 1)
2086 return env
->cp15
.c15_cpar
;
2090 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
2094 case 1: /* Read TI925T configuration. */
2095 return env
->cp15
.c15_ticonfig
;
2096 case 2: /* Read I_max. */
2097 return env
->cp15
.c15_i_max
;
2098 case 3: /* Read I_min. */
2099 return env
->cp15
.c15_i_min
;
2100 case 4: /* Read thread-ID. */
2101 return env
->cp15
.c15_threadid
;
2102 case 8: /* TI925T_status */
2105 /* TODO: Peripheral port remap register:
2106 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
2107 * controller base address at $rn & ~0xfff and map size of
2108 * 0x200 << ($rn & 0xfff), when MMU is off. */
2111 if (ARM_CPUID(env
) == ARM_CPUID_CORTEXA9
) {
2114 if ((op1
== 4) && (op2
== 0)) {
2115 /* The config_base_address should hold the value of
2116 * the peripheral base. ARM should get this from a CPU
2117 * object property, but that support isn't available in
2118 * December 2011. Default to 0 for now and board models
2119 * that care can set it by a private hook */
2120 return env
->cp15
.c15_config_base_address
;
2121 } else if ((op1
== 0) && (op2
== 0)) {
2122 /* power_control should be set to maximum latency. Again,
2123 default to 0 and set by private hook */
2124 return env
->cp15
.c15_power_control
;
2125 } else if ((op1
== 0) && (op2
== 1)) {
2126 return env
->cp15
.c15_diagnostic
;
2127 } else if ((op1
== 0) && (op2
== 2)) {
2128 return env
->cp15
.c15_power_diagnostic
;
2131 case 1: /* NEON Busy */
2133 case 5: /* tlb lockdown */
2136 if ((op1
== 5) && (op2
== 2)) {
2148 /* ??? For debugging only. Should raise illegal instruction exception. */
2149 cpu_abort(env
, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
2150 (insn
>> 16) & 0xf, crm
, op1
, op2
);
2154 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
2156 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2157 env
->regs
[13] = val
;
2159 env
->banked_r13
[bank_number(env
, mode
)] = val
;
2163 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
2165 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2166 return env
->regs
[13];
2168 return env
->banked_r13
[bank_number(env
, mode
)];
2172 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
2176 return xpsr_read(env
) & 0xf8000000;
2178 return xpsr_read(env
) & 0xf80001ff;
2180 return xpsr_read(env
) & 0xff00fc00;
2182 return xpsr_read(env
) & 0xff00fdff;
2184 return xpsr_read(env
) & 0x000001ff;
2186 return xpsr_read(env
) & 0x0700fc00;
2188 return xpsr_read(env
) & 0x0700edff;
2190 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
2192 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
2193 case 16: /* PRIMASK */
2194 return (env
->uncached_cpsr
& CPSR_I
) != 0;
2195 case 17: /* BASEPRI */
2196 case 18: /* BASEPRI_MAX */
2197 return env
->v7m
.basepri
;
2198 case 19: /* FAULTMASK */
2199 return (env
->uncached_cpsr
& CPSR_F
) != 0;
2200 case 20: /* CONTROL */
2201 return env
->v7m
.control
;
2203 /* ??? For debugging only. */
2204 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
2209 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
2213 xpsr_write(env
, val
, 0xf8000000);
2216 xpsr_write(env
, val
, 0xf8000000);
2219 xpsr_write(env
, val
, 0xfe00fc00);
2222 xpsr_write(env
, val
, 0xfe00fc00);
2225 /* IPSR bits are readonly. */
2228 xpsr_write(env
, val
, 0x0600fc00);
2231 xpsr_write(env
, val
, 0x0600fc00);
2234 if (env
->v7m
.current_sp
)
2235 env
->v7m
.other_sp
= val
;
2237 env
->regs
[13] = val
;
2240 if (env
->v7m
.current_sp
)
2241 env
->regs
[13] = val
;
2243 env
->v7m
.other_sp
= val
;
2245 case 16: /* PRIMASK */
2247 env
->uncached_cpsr
|= CPSR_I
;
2249 env
->uncached_cpsr
&= ~CPSR_I
;
2251 case 17: /* BASEPRI */
2252 env
->v7m
.basepri
= val
& 0xff;
2254 case 18: /* BASEPRI_MAX */
2256 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
2257 env
->v7m
.basepri
= val
;
2259 case 19: /* FAULTMASK */
2261 env
->uncached_cpsr
|= CPSR_F
;
2263 env
->uncached_cpsr
&= ~CPSR_F
;
2265 case 20: /* CONTROL */
2266 env
->v7m
.control
= val
& 3;
2267 switch_v7m_sp(env
, (val
& 2) != 0);
2270 /* ??? For debugging only. */
2271 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
2278 /* Note that signed overflow is undefined in C. The following routines are
2279 careful to use unsigned types where modulo arithmetic is required.
2280 Failure to do so _will_ break on newer gcc. */
2282 /* Signed saturating arithmetic. */
2284 /* Perform 16-bit signed saturating addition. */
2285 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
2290 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
2299 /* Perform 8-bit signed saturating addition. */
2300 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
2305 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
2314 /* Perform 16-bit signed saturating subtraction. */
2315 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
2320 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
2329 /* Perform 8-bit signed saturating subtraction. */
2330 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
2335 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2344 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2345 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2346 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2347 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2350 #include "op_addsub.h"
2352 /* Unsigned saturating arithmetic. */
2353 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2362 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2370 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2379 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2387 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2388 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2389 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2390 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2393 #include "op_addsub.h"
2395 /* Signed modulo arithmetic. */
2396 #define SARITH16(a, b, n, op) do { \
2398 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
2399 RESULT(sum, n, 16); \
2401 ge |= 3 << (n * 2); \
2404 #define SARITH8(a, b, n, op) do { \
2406 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
2407 RESULT(sum, n, 8); \
2413 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2414 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2415 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2416 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2420 #include "op_addsub.h"
2422 /* Unsigned modulo arithmetic. */
2423 #define ADD16(a, b, n) do { \
2425 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2426 RESULT(sum, n, 16); \
2427 if ((sum >> 16) == 1) \
2428 ge |= 3 << (n * 2); \
2431 #define ADD8(a, b, n) do { \
2433 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2434 RESULT(sum, n, 8); \
2435 if ((sum >> 8) == 1) \
2439 #define SUB16(a, b, n) do { \
2441 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2442 RESULT(sum, n, 16); \
2443 if ((sum >> 16) == 0) \
2444 ge |= 3 << (n * 2); \
2447 #define SUB8(a, b, n) do { \
2449 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2450 RESULT(sum, n, 8); \
2451 if ((sum >> 8) == 0) \
2458 #include "op_addsub.h"
2460 /* Halved signed arithmetic. */
2461 #define ADD16(a, b, n) \
2462 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2463 #define SUB16(a, b, n) \
2464 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2465 #define ADD8(a, b, n) \
2466 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2467 #define SUB8(a, b, n) \
2468 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2471 #include "op_addsub.h"
2473 /* Halved unsigned arithmetic. */
2474 #define ADD16(a, b, n) \
2475 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2476 #define SUB16(a, b, n) \
2477 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2478 #define ADD8(a, b, n) \
2479 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2480 #define SUB8(a, b, n) \
2481 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2484 #include "op_addsub.h"
2486 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2494 /* Unsigned sum of absolute byte differences. */
2495 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2498 sum
= do_usad(a
, b
);
2499 sum
+= do_usad(a
>> 8, b
>> 8);
2500 sum
+= do_usad(a
>> 16, b
>>16);
2501 sum
+= do_usad(a
>> 24, b
>> 24);
2505 /* For ARMv6 SEL instruction. */
2506 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2519 return (a
& mask
) | (b
& ~mask
);
2522 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2524 return (val
>> 32) | (val
!= 0);
2527 /* VFP support. We follow the convention used for VFP instrunctions:
2528 Single precition routines have a "s" suffix, double precision a
2531 /* Convert host exception flags to vfp form. */
2532 static inline int vfp_exceptbits_from_host(int host_bits
)
2534 int target_bits
= 0;
2536 if (host_bits
& float_flag_invalid
)
2538 if (host_bits
& float_flag_divbyzero
)
2540 if (host_bits
& float_flag_overflow
)
2542 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
2544 if (host_bits
& float_flag_inexact
)
2545 target_bits
|= 0x10;
2546 if (host_bits
& float_flag_input_denormal
)
2547 target_bits
|= 0x80;
2551 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
2556 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2557 | (env
->vfp
.vec_len
<< 16)
2558 | (env
->vfp
.vec_stride
<< 20);
2559 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2560 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
2561 fpscr
|= vfp_exceptbits_from_host(i
);
2565 uint32_t vfp_get_fpscr(CPUARMState
*env
)
2567 return HELPER(vfp_get_fpscr
)(env
);
2570 /* Convert vfp exception flags to target form. */
2571 static inline int vfp_exceptbits_to_host(int target_bits
)
2575 if (target_bits
& 1)
2576 host_bits
|= float_flag_invalid
;
2577 if (target_bits
& 2)
2578 host_bits
|= float_flag_divbyzero
;
2579 if (target_bits
& 4)
2580 host_bits
|= float_flag_overflow
;
2581 if (target_bits
& 8)
2582 host_bits
|= float_flag_underflow
;
2583 if (target_bits
& 0x10)
2584 host_bits
|= float_flag_inexact
;
2585 if (target_bits
& 0x80)
2586 host_bits
|= float_flag_input_denormal
;
2590 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
2595 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2596 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2597 env
->vfp
.vec_len
= (val
>> 16) & 7;
2598 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2601 if (changed
& (3 << 22)) {
2602 i
= (val
>> 22) & 3;
2605 i
= float_round_nearest_even
;
2611 i
= float_round_down
;
2614 i
= float_round_to_zero
;
2617 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2619 if (changed
& (1 << 24)) {
2620 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2621 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2623 if (changed
& (1 << 25))
2624 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
2626 i
= vfp_exceptbits_to_host(val
);
2627 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
2628 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
2631 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
2633 HELPER(vfp_set_fpscr
)(env
, val
);
2636 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2638 #define VFP_BINOP(name) \
2639 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
2641 float_status *fpst = fpstp; \
2642 return float32_ ## name(a, b, fpst); \
2644 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
2646 float_status *fpst = fpstp; \
2647 return float64_ ## name(a, b, fpst); \
2655 float32
VFP_HELPER(neg
, s
)(float32 a
)
2657 return float32_chs(a
);
2660 float64
VFP_HELPER(neg
, d
)(float64 a
)
2662 return float64_chs(a
);
2665 float32
VFP_HELPER(abs
, s
)(float32 a
)
2667 return float32_abs(a
);
2670 float64
VFP_HELPER(abs
, d
)(float64 a
)
2672 return float64_abs(a
);
2675 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
2677 return float32_sqrt(a
, &env
->vfp
.fp_status
);
2680 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
2682 return float64_sqrt(a
, &env
->vfp
.fp_status
);
2685 /* XXX: check quiet/signaling case */
2686 #define DO_VFP_cmp(p, type) \
2687 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
2690 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2691 case 0: flags = 0x6; break; \
2692 case -1: flags = 0x8; break; \
2693 case 1: flags = 0x2; break; \
2694 default: case 2: flags = 0x3; break; \
2696 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2697 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2699 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
2702 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2703 case 0: flags = 0x6; break; \
2704 case -1: flags = 0x8; break; \
2705 case 1: flags = 0x2; break; \
2706 default: case 2: flags = 0x3; break; \
2708 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2709 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2711 DO_VFP_cmp(s
, float32
)
2712 DO_VFP_cmp(d
, float64
)
2715 /* Integer to float and float to integer conversions */
2717 #define CONV_ITOF(name, fsz, sign) \
2718 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2720 float_status *fpst = fpstp; \
2721 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
2724 #define CONV_FTOI(name, fsz, sign, round) \
2725 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2727 float_status *fpst = fpstp; \
2728 if (float##fsz##_is_any_nan(x)) { \
2729 float_raise(float_flag_invalid, fpst); \
2732 return float##fsz##_to_##sign##int32##round(x, fpst); \
2735 #define FLOAT_CONVS(name, p, fsz, sign) \
2736 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2737 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2738 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
2740 FLOAT_CONVS(si
, s
, 32, )
2741 FLOAT_CONVS(si
, d
, 64, )
2742 FLOAT_CONVS(ui
, s
, 32, u
)
2743 FLOAT_CONVS(ui
, d
, 64, u
)
2749 /* floating point conversion */
2750 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
2752 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
2753 /* ARM requires that S<->D conversion of any kind of NaN generates
2754 * a quiet NaN by forcing the most significant frac bit to 1.
2756 return float64_maybe_silence_nan(r
);
2759 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
2761 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
2762 /* ARM requires that S<->D conversion of any kind of NaN generates
2763 * a quiet NaN by forcing the most significant frac bit to 1.
2765 return float32_maybe_silence_nan(r
);
2768 /* VFP3 fixed point conversion. */
2769 #define VFP_CONV_FIX(name, p, fsz, itype, sign) \
2770 float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2773 float_status *fpst = fpstp; \
2775 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2776 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
2778 uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2781 float_status *fpst = fpstp; \
2783 if (float##fsz##_is_any_nan(x)) { \
2784 float_raise(float_flag_invalid, fpst); \
2787 tmp = float##fsz##_scalbn(x, shift, fpst); \
2788 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
2791 VFP_CONV_FIX(sh
, d
, 64, int16
, )
2792 VFP_CONV_FIX(sl
, d
, 64, int32
, )
2793 VFP_CONV_FIX(uh
, d
, 64, uint16
, u
)
2794 VFP_CONV_FIX(ul
, d
, 64, uint32
, u
)
2795 VFP_CONV_FIX(sh
, s
, 32, int16
, )
2796 VFP_CONV_FIX(sl
, s
, 32, int32
, )
2797 VFP_CONV_FIX(uh
, s
, 32, uint16
, u
)
2798 VFP_CONV_FIX(ul
, s
, 32, uint32
, u
)
2801 /* Half precision conversions. */
2802 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
2804 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2805 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
2807 return float32_maybe_silence_nan(r
);
2812 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
2814 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2815 float16 r
= float32_to_float16(a
, ieee
, s
);
2817 r
= float16_maybe_silence_nan(r
);
2819 return float16_val(r
);
2822 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
2824 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
2827 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
2829 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
2832 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
2834 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
2837 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
2839 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
2842 #define float32_two make_float32(0x40000000)
2843 #define float32_three make_float32(0x40400000)
2844 #define float32_one_point_five make_float32(0x3fc00000)
2846 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
2848 float_status
*s
= &env
->vfp
.standard_fp_status
;
2849 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2850 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2851 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
2852 float_raise(float_flag_input_denormal
, s
);
2856 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
2859 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
2861 float_status
*s
= &env
->vfp
.standard_fp_status
;
2863 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2864 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2865 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
2866 float_raise(float_flag_input_denormal
, s
);
2868 return float32_one_point_five
;
2870 product
= float32_mul(a
, b
, s
);
2871 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
2876 /* Constants 256 and 512 are used in some helpers; we avoid relying on
2877 * int->float conversions at run-time. */
2878 #define float64_256 make_float64(0x4070000000000000LL)
2879 #define float64_512 make_float64(0x4080000000000000LL)
2881 /* The algorithm that must be used to calculate the estimate
2882 * is specified by the ARM ARM.
2884 static float64
recip_estimate(float64 a
, CPUARMState
*env
)
2886 /* These calculations mustn't set any fp exception flags,
2887 * so we use a local copy of the fp_status.
2889 float_status dummy_status
= env
->vfp
.standard_fp_status
;
2890 float_status
*s
= &dummy_status
;
2891 /* q = (int)(a * 512.0) */
2892 float64 q
= float64_mul(float64_512
, a
, s
);
2893 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
2895 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2896 q
= int64_to_float64(q_int
, s
);
2897 q
= float64_add(q
, float64_half
, s
);
2898 q
= float64_div(q
, float64_512
, s
);
2899 q
= float64_div(float64_one
, q
, s
);
2901 /* s = (int)(256.0 * r + 0.5) */
2902 q
= float64_mul(q
, float64_256
, s
);
2903 q
= float64_add(q
, float64_half
, s
);
2904 q_int
= float64_to_int64_round_to_zero(q
, s
);
2906 /* return (double)s / 256.0 */
2907 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
2910 float32
HELPER(recpe_f32
)(float32 a
, CPUARMState
*env
)
2912 float_status
*s
= &env
->vfp
.standard_fp_status
;
2914 uint32_t val32
= float32_val(a
);
2917 int a_exp
= (val32
& 0x7f800000) >> 23;
2918 int sign
= val32
& 0x80000000;
2920 if (float32_is_any_nan(a
)) {
2921 if (float32_is_signaling_nan(a
)) {
2922 float_raise(float_flag_invalid
, s
);
2924 return float32_default_nan
;
2925 } else if (float32_is_infinity(a
)) {
2926 return float32_set_sign(float32_zero
, float32_is_neg(a
));
2927 } else if (float32_is_zero_or_denormal(a
)) {
2928 if (!float32_is_zero(a
)) {
2929 float_raise(float_flag_input_denormal
, s
);
2931 float_raise(float_flag_divbyzero
, s
);
2932 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
2933 } else if (a_exp
>= 253) {
2934 float_raise(float_flag_underflow
, s
);
2935 return float32_set_sign(float32_zero
, float32_is_neg(a
));
2938 f64
= make_float64((0x3feULL
<< 52)
2939 | ((int64_t)(val32
& 0x7fffff) << 29));
2941 result_exp
= 253 - a_exp
;
2943 f64
= recip_estimate(f64
, env
);
2946 | ((result_exp
& 0xff) << 23)
2947 | ((float64_val(f64
) >> 29) & 0x7fffff);
2948 return make_float32(val32
);
2951 /* The algorithm that must be used to calculate the estimate
2952 * is specified by the ARM ARM.
2954 static float64
recip_sqrt_estimate(float64 a
, CPUARMState
*env
)
2956 /* These calculations mustn't set any fp exception flags,
2957 * so we use a local copy of the fp_status.
2959 float_status dummy_status
= env
->vfp
.standard_fp_status
;
2960 float_status
*s
= &dummy_status
;
2964 if (float64_lt(a
, float64_half
, s
)) {
2965 /* range 0.25 <= a < 0.5 */
2967 /* a in units of 1/512 rounded down */
2968 /* q0 = (int)(a * 512.0); */
2969 q
= float64_mul(float64_512
, a
, s
);
2970 q_int
= float64_to_int64_round_to_zero(q
, s
);
2972 /* reciprocal root r */
2973 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
2974 q
= int64_to_float64(q_int
, s
);
2975 q
= float64_add(q
, float64_half
, s
);
2976 q
= float64_div(q
, float64_512
, s
);
2977 q
= float64_sqrt(q
, s
);
2978 q
= float64_div(float64_one
, q
, s
);
2980 /* range 0.5 <= a < 1.0 */
2982 /* a in units of 1/256 rounded down */
2983 /* q1 = (int)(a * 256.0); */
2984 q
= float64_mul(float64_256
, a
, s
);
2985 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
2987 /* reciprocal root r */
2988 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
2989 q
= int64_to_float64(q_int
, s
);
2990 q
= float64_add(q
, float64_half
, s
);
2991 q
= float64_div(q
, float64_256
, s
);
2992 q
= float64_sqrt(q
, s
);
2993 q
= float64_div(float64_one
, q
, s
);
2995 /* r in units of 1/256 rounded to nearest */
2996 /* s = (int)(256.0 * r + 0.5); */
2998 q
= float64_mul(q
, float64_256
,s
);
2999 q
= float64_add(q
, float64_half
, s
);
3000 q_int
= float64_to_int64_round_to_zero(q
, s
);
3002 /* return (double)s / 256.0;*/
3003 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
3006 float32
HELPER(rsqrte_f32
)(float32 a
, CPUARMState
*env
)
3008 float_status
*s
= &env
->vfp
.standard_fp_status
;
3014 val
= float32_val(a
);
3016 if (float32_is_any_nan(a
)) {
3017 if (float32_is_signaling_nan(a
)) {
3018 float_raise(float_flag_invalid
, s
);
3020 return float32_default_nan
;
3021 } else if (float32_is_zero_or_denormal(a
)) {
3022 if (!float32_is_zero(a
)) {
3023 float_raise(float_flag_input_denormal
, s
);
3025 float_raise(float_flag_divbyzero
, s
);
3026 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
3027 } else if (float32_is_neg(a
)) {
3028 float_raise(float_flag_invalid
, s
);
3029 return float32_default_nan
;
3030 } else if (float32_is_infinity(a
)) {
3031 return float32_zero
;
3034 /* Normalize to a double-precision value between 0.25 and 1.0,
3035 * preserving the parity of the exponent. */
3036 if ((val
& 0x800000) == 0) {
3037 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3039 | ((uint64_t)(val
& 0x7fffff) << 29));
3041 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3043 | ((uint64_t)(val
& 0x7fffff) << 29));
3046 result_exp
= (380 - ((val
& 0x7f800000) >> 23)) / 2;
3048 f64
= recip_sqrt_estimate(f64
, env
);
3050 val64
= float64_val(f64
);
3052 val
= ((result_exp
& 0xff) << 23)
3053 | ((val64
>> 29) & 0x7fffff);
3054 return make_float32(val
);
3057 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUARMState
*env
)
3061 if ((a
& 0x80000000) == 0) {
3065 f64
= make_float64((0x3feULL
<< 52)
3066 | ((int64_t)(a
& 0x7fffffff) << 21));
3068 f64
= recip_estimate (f64
, env
);
3070 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3073 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUARMState
*env
)
3077 if ((a
& 0xc0000000) == 0) {
3081 if (a
& 0x80000000) {
3082 f64
= make_float64((0x3feULL
<< 52)
3083 | ((uint64_t)(a
& 0x7fffffff) << 21));
3084 } else { /* bits 31-30 == '01' */
3085 f64
= make_float64((0x3fdULL
<< 52)
3086 | ((uint64_t)(a
& 0x3fffffff) << 22));
3089 f64
= recip_sqrt_estimate(f64
, env
);
3091 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3094 /* VFPv4 fused multiply-accumulate */
3095 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
3097 float_status
*fpst
= fpstp
;
3098 return float32_muladd(a
, b
, c
, 0, fpst
);
3101 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
3103 float_status
*fpst
= fpstp
;
3104 return float64_muladd(a
, b
, c
, 0, fpst
);