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exec.c: Drop TARGET_HAS_ICE define and checks
[qemu/ar7.git] / target-ppc / cpu.h
blobaae33a9237d7cdbbfd04ca37cfa4fa38043244f6
1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #if !defined (__CPU_PPC_H__)
20 #define __CPU_PPC_H__
21
22 #include "config.h"
23 #include "qemu-common.h"
24
25 //#define PPC_EMULATE_32BITS_HYPV
26
27 #if defined (TARGET_PPC64)
28 /* PowerPC 64 definitions */
29 #define TARGET_LONG_BITS 64
30 #define TARGET_PAGE_BITS 12
31
32 #define TARGET_IS_BIENDIAN 1
33
34 /* Note that the official physical address space bits is 62-M where M
35 is implementation dependent. I've not looked up M for the set of
36 cpus we emulate at the system level. */
37 #define TARGET_PHYS_ADDR_SPACE_BITS 62
38
39 /* Note that the PPC environment architecture talks about 80 bit virtual
40 addresses, with segmentation. Obviously that's not all visible to a
41 single process, which is all we're concerned with here. */
42 #ifdef TARGET_ABI32
43 # define TARGET_VIRT_ADDR_SPACE_BITS 32
44 #else
45 # define TARGET_VIRT_ADDR_SPACE_BITS 64
46 #endif
47
48 #define TARGET_PAGE_BITS_16M 24
49
50 #else /* defined (TARGET_PPC64) */
51 /* PowerPC 32 definitions */
52 #define TARGET_LONG_BITS 32
53
54 #if defined(TARGET_PPCEMB)
55 /* Specific definitions for PowerPC embedded */
56 /* BookE have 36 bits physical address space */
57 #if defined(CONFIG_USER_ONLY)
58 /* It looks like a lot of Linux programs assume page size
59 * is 4kB long. This is evil, but we have to deal with it...
60 */
61 #define TARGET_PAGE_BITS 12
62 #else /* defined(CONFIG_USER_ONLY) */
63 /* Pages can be 1 kB small */
64 #define TARGET_PAGE_BITS 10
65 #endif /* defined(CONFIG_USER_ONLY) */
66 #else /* defined(TARGET_PPCEMB) */
67 /* "standard" PowerPC 32 definitions */
68 #define TARGET_PAGE_BITS 12
69 #endif /* defined(TARGET_PPCEMB) */
70
71 #define TARGET_PHYS_ADDR_SPACE_BITS 36
72 #define TARGET_VIRT_ADDR_SPACE_BITS 32
73
74 #endif /* defined (TARGET_PPC64) */
75
76 #define CPUArchState struct CPUPPCState
77
78 #include "exec/cpu-defs.h"
79
80 #include "fpu/softfloat.h"
81
82 #if defined (TARGET_PPC64)
83 #define ELF_MACHINE EM_PPC64
84 #else
85 #define ELF_MACHINE EM_PPC
86 #endif
87
88 /*****************************************************************************/
89 /* MMU model */
90 typedef enum powerpc_mmu_t powerpc_mmu_t;
91 enum powerpc_mmu_t {
92 POWERPC_MMU_UNKNOWN = 0x00000000,
93 /* Standard 32 bits PowerPC MMU */
94 POWERPC_MMU_32B = 0x00000001,
95 /* PowerPC 6xx MMU with software TLB */
96 POWERPC_MMU_SOFT_6xx = 0x00000002,
97 /* PowerPC 74xx MMU with software TLB */
98 POWERPC_MMU_SOFT_74xx = 0x00000003,
99 /* PowerPC 4xx MMU with software TLB */
100 POWERPC_MMU_SOFT_4xx = 0x00000004,
101 /* PowerPC 4xx MMU with software TLB and zones protections */
102 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
103 /* PowerPC MMU in real mode only */
104 POWERPC_MMU_REAL = 0x00000006,
105 /* Freescale MPC8xx MMU model */
106 POWERPC_MMU_MPC8xx = 0x00000007,
107 /* BookE MMU model */
108 POWERPC_MMU_BOOKE = 0x00000008,
109 /* BookE 2.06 MMU model */
110 POWERPC_MMU_BOOKE206 = 0x00000009,
111 /* PowerPC 601 MMU model (specific BATs format) */
112 POWERPC_MMU_601 = 0x0000000A,
113 #if defined(TARGET_PPC64)
114 #define POWERPC_MMU_64 0x00010000
115 #define POWERPC_MMU_1TSEG 0x00020000
116 #define POWERPC_MMU_AMR 0x00040000
117 /* 64 bits PowerPC MMU */
118 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
119 /* Architecture 2.06 variant */
120 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
121 | POWERPC_MMU_AMR | 0x00000003,
122 /* Architecture 2.06 "degraded" (no 1T segments) */
123 POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR
124 | 0x00000003,
125 /* Architecture 2.06 "degraded" (no 1T segments or AMR) */
126 POWERPC_MMU_2_06d = POWERPC_MMU_64 | 0x00000003,
127 #endif /* defined(TARGET_PPC64) */
128 };
129
130 /*****************************************************************************/
131 /* Exception model */
132 typedef enum powerpc_excp_t powerpc_excp_t;
133 enum powerpc_excp_t {
134 POWERPC_EXCP_UNKNOWN = 0,
135 /* Standard PowerPC exception model */
136 POWERPC_EXCP_STD,
137 /* PowerPC 40x exception model */
138 POWERPC_EXCP_40x,
139 /* PowerPC 601 exception model */
140 POWERPC_EXCP_601,
141 /* PowerPC 602 exception model */
142 POWERPC_EXCP_602,
143 /* PowerPC 603 exception model */
144 POWERPC_EXCP_603,
145 /* PowerPC 603e exception model */
146 POWERPC_EXCP_603E,
147 /* PowerPC G2 exception model */
148 POWERPC_EXCP_G2,
149 /* PowerPC 604 exception model */
150 POWERPC_EXCP_604,
151 /* PowerPC 7x0 exception model */
152 POWERPC_EXCP_7x0,
153 /* PowerPC 7x5 exception model */
154 POWERPC_EXCP_7x5,
155 /* PowerPC 74xx exception model */
156 POWERPC_EXCP_74xx,
157 /* BookE exception model */
158 POWERPC_EXCP_BOOKE,
159 #if defined(TARGET_PPC64)
160 /* PowerPC 970 exception model */
161 POWERPC_EXCP_970,
162 /* POWER7 exception model */
163 POWERPC_EXCP_POWER7,
164 #endif /* defined(TARGET_PPC64) */
165 };
166
167 /*****************************************************************************/
168 /* Exception vectors definitions */
169 enum {
170 POWERPC_EXCP_NONE = -1,
171 /* The 64 first entries are used by the PowerPC embedded specification */
172 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
173 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
174 POWERPC_EXCP_DSI = 2, /* Data storage exception */
175 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
176 POWERPC_EXCP_EXTERNAL = 4, /* External input */
177 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
178 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
179 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
180 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
181 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
182 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
183 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
184 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
185 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
186 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
187 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
188 /* Vectors 16 to 31 are reserved */
189 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
190 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
191 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
192 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
193 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
194 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
195 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
196 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
197 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
198 /* Vectors 42 to 63 are reserved */
199 /* Exceptions defined in the PowerPC server specification */
200 POWERPC_EXCP_RESET = 64, /* System reset exception */
201 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
202 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
203 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
204 POWERPC_EXCP_TRACE = 68, /* Trace exception */
205 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
206 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
207 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
208 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
209 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
210 /* 40x specific exceptions */
211 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
212 /* 601 specific exceptions */
213 POWERPC_EXCP_IO = 75, /* IO error exception */
214 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
215 /* 602 specific exceptions */
216 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
217 /* 602/603 specific exceptions */
218 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
219 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
220 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
221 /* Exceptions available on most PowerPC */
222 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
223 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
224 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
225 POWERPC_EXCP_SMI = 84, /* System management interrupt */
226 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
227 /* 7xx/74xx specific exceptions */
228 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
229 /* 74xx specific exceptions */
230 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
231 /* 970FX specific exceptions */
232 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
233 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
234 /* Freescale embedded cores specific exceptions */
235 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
236 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
237 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
238 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
239 /* VSX Unavailable (Power ISA 2.06 and later) */
240 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
241 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
242 /* EOL */
243 POWERPC_EXCP_NB = 96,
244 /* QEMU exceptions: used internally during code translation */
245 POWERPC_EXCP_STOP = 0x200, /* stop translation */
246 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
247 /* QEMU exceptions: special cases we want to stop translation */
248 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
249 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
250 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
251 };
252
253 /* Exceptions error codes */
254 enum {
255 /* Exception subtypes for POWERPC_EXCP_ALIGN */
256 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
257 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
258 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
259 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
260 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
261 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
262 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
263 /* FP exceptions */
264 POWERPC_EXCP_FP = 0x10,
265 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
266 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
267 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
268 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
269 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
270 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
271 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
272 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
273 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
274 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
275 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
276 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
277 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
278 /* Invalid instruction */
279 POWERPC_EXCP_INVAL = 0x20,
280 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
281 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
282 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
283 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
284 /* Privileged instruction */
285 POWERPC_EXCP_PRIV = 0x30,
286 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
287 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
288 /* Trap */
289 POWERPC_EXCP_TRAP = 0x40,
290 };
291
292 /*****************************************************************************/
293 /* Input pins model */
294 typedef enum powerpc_input_t powerpc_input_t;
295 enum powerpc_input_t {
296 PPC_FLAGS_INPUT_UNKNOWN = 0,
297 /* PowerPC 6xx bus */
298 PPC_FLAGS_INPUT_6xx,
299 /* BookE bus */
300 PPC_FLAGS_INPUT_BookE,
301 /* PowerPC 405 bus */
302 PPC_FLAGS_INPUT_405,
303 /* PowerPC 970 bus */
304 PPC_FLAGS_INPUT_970,
305 /* PowerPC POWER7 bus */
306 PPC_FLAGS_INPUT_POWER7,
307 /* PowerPC 401 bus */
308 PPC_FLAGS_INPUT_401,
309 /* Freescale RCPU bus */
310 PPC_FLAGS_INPUT_RCPU,
311 };
312
313 #define PPC_INPUT(env) (env->bus_model)
314
315 /*****************************************************************************/
316 typedef struct opc_handler_t opc_handler_t;
317
318 /*****************************************************************************/
319 /* Types used to describe some PowerPC registers */
320 typedef struct CPUPPCState CPUPPCState;
321 typedef struct DisasContext DisasContext;
322 typedef struct ppc_tb_t ppc_tb_t;
323 typedef struct ppc_spr_t ppc_spr_t;
324 typedef struct ppc_dcr_t ppc_dcr_t;
325 typedef union ppc_avr_t ppc_avr_t;
326 typedef union ppc_tlb_t ppc_tlb_t;
327
328 /* SPR access micro-ops generations callbacks */
329 struct ppc_spr_t {
330 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
331 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
332 #if !defined(CONFIG_USER_ONLY)
333 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
334 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
335 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
336 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
337 #endif
338 const char *name;
339 target_ulong default_value;
340 #ifdef CONFIG_KVM
341 /* We (ab)use the fact that all the SPRs will have ids for the
342 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
343 * don't sync this */
344 uint64_t one_reg_id;
345 #endif
346 };
347
348 /* Altivec registers (128 bits) */
349 union ppc_avr_t {
350 float32 f[4];
351 uint8_t u8[16];
352 uint16_t u16[8];
353 uint32_t u32[4];
354 int8_t s8[16];
355 int16_t s16[8];
356 int32_t s32[4];
357 uint64_t u64[2];
358 int64_t s64[2];
359 #ifdef CONFIG_INT128
360 __uint128_t u128;
361 #endif
362 };
363
364 #if !defined(CONFIG_USER_ONLY)
365 /* Software TLB cache */
366 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
367 struct ppc6xx_tlb_t {
368 target_ulong pte0;
369 target_ulong pte1;
370 target_ulong EPN;
371 };
372
373 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
374 struct ppcemb_tlb_t {
375 uint64_t RPN;
376 target_ulong EPN;
377 target_ulong PID;
378 target_ulong size;
379 uint32_t prot;
380 uint32_t attr; /* Storage attributes */
381 };
382
383 typedef struct ppcmas_tlb_t {
384 uint32_t mas8;
385 uint32_t mas1;
386 uint64_t mas2;
387 uint64_t mas7_3;
388 } ppcmas_tlb_t;
389
390 union ppc_tlb_t {
391 ppc6xx_tlb_t *tlb6;
392 ppcemb_tlb_t *tlbe;
393 ppcmas_tlb_t *tlbm;
394 };
395
396 /* possible TLB variants */
397 #define TLB_NONE 0
398 #define TLB_6XX 1
399 #define TLB_EMB 2
400 #define TLB_MAS 3
401 #endif
402
403 #define SDR_32_HTABORG 0xFFFF0000UL
404 #define SDR_32_HTABMASK 0x000001FFUL
405
406 #if defined(TARGET_PPC64)
407 #define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
408 #define SDR_64_HTABSIZE 0x000000000000001FULL
409 #endif /* defined(TARGET_PPC64 */
410
411 typedef struct ppc_slb_t ppc_slb_t;
412 struct ppc_slb_t {
413 uint64_t esid;
414 uint64_t vsid;
415 };
416
417 #define MAX_SLB_ENTRIES 64
418 #define SEGMENT_SHIFT_256M 28
419 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
420
421 #define SEGMENT_SHIFT_1T 40
422 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
423
424
425 /*****************************************************************************/
426 /* Machine state register bits definition */
427 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
428 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
429 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
430 #define MSR_SHV 60 /* hypervisor state hflags */
431 #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
432 #define MSR_TS1 33
433 #define MSR_TM 32 /* Transactional Memory Available (Book3s) */
434 #define MSR_CM 31 /* Computation mode for BookE hflags */
435 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
436 #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
437 #define MSR_GS 28 /* guest state for BookE */
438 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
439 #define MSR_VR 25 /* altivec available x hflags */
440 #define MSR_SPE 25 /* SPE enable for BookE x hflags */
441 #define MSR_AP 23 /* Access privilege state on 602 hflags */
442 #define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
443 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
444 #define MSR_KEY 19 /* key bit on 603e */
445 #define MSR_POW 18 /* Power management */
446 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
447 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
448 #define MSR_ILE 16 /* Interrupt little-endian mode */
449 #define MSR_EE 15 /* External interrupt enable */
450 #define MSR_PR 14 /* Problem state hflags */
451 #define MSR_FP 13 /* Floating point available hflags */
452 #define MSR_ME 12 /* Machine check interrupt enable */
453 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
454 #define MSR_SE 10 /* Single-step trace enable x hflags */
455 #define MSR_DWE 10 /* Debug wait enable on 405 x */
456 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
457 #define MSR_BE 9 /* Branch trace enable x hflags */
458 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
459 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
460 #define MSR_AL 7 /* AL bit on POWER */
461 #define MSR_EP 6 /* Exception prefix on 601 */
462 #define MSR_IR 5 /* Instruction relocate */
463 #define MSR_DR 4 /* Data relocate */
464 #define MSR_PE 3 /* Protection enable on 403 */
465 #define MSR_PX 2 /* Protection exclusive on 403 x */
466 #define MSR_PMM 2 /* Performance monitor mark on POWER x */
467 #define MSR_RI 1 /* Recoverable interrupt 1 */
468 #define MSR_LE 0 /* Little-endian mode 1 hflags */
469
470 #define LPCR_ILE (1 << (63-38))
471 #define LPCR_AIL_SHIFT (63-40) /* Alternate interrupt location */
472 #define LPCR_AIL (3 << LPCR_AIL_SHIFT)
473
474 #define msr_sf ((env->msr >> MSR_SF) & 1)
475 #define msr_isf ((env->msr >> MSR_ISF) & 1)
476 #define msr_shv ((env->msr >> MSR_SHV) & 1)
477 #define msr_cm ((env->msr >> MSR_CM) & 1)
478 #define msr_icm ((env->msr >> MSR_ICM) & 1)
479 #define msr_thv ((env->msr >> MSR_THV) & 1)
480 #define msr_gs ((env->msr >> MSR_GS) & 1)
481 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
482 #define msr_vr ((env->msr >> MSR_VR) & 1)
483 #define msr_spe ((env->msr >> MSR_SPE) & 1)
484 #define msr_ap ((env->msr >> MSR_AP) & 1)
485 #define msr_vsx ((env->msr >> MSR_VSX) & 1)
486 #define msr_sa ((env->msr >> MSR_SA) & 1)
487 #define msr_key ((env->msr >> MSR_KEY) & 1)
488 #define msr_pow ((env->msr >> MSR_POW) & 1)
489 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
490 #define msr_ce ((env->msr >> MSR_CE) & 1)
491 #define msr_ile ((env->msr >> MSR_ILE) & 1)
492 #define msr_ee ((env->msr >> MSR_EE) & 1)
493 #define msr_pr ((env->msr >> MSR_PR) & 1)
494 #define msr_fp ((env->msr >> MSR_FP) & 1)
495 #define msr_me ((env->msr >> MSR_ME) & 1)
496 #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
497 #define msr_se ((env->msr >> MSR_SE) & 1)
498 #define msr_dwe ((env->msr >> MSR_DWE) & 1)
499 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
500 #define msr_be ((env->msr >> MSR_BE) & 1)
501 #define msr_de ((env->msr >> MSR_DE) & 1)
502 #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
503 #define msr_al ((env->msr >> MSR_AL) & 1)
504 #define msr_ep ((env->msr >> MSR_EP) & 1)
505 #define msr_ir ((env->msr >> MSR_IR) & 1)
506 #define msr_dr ((env->msr >> MSR_DR) & 1)
507 #define msr_pe ((env->msr >> MSR_PE) & 1)
508 #define msr_px ((env->msr >> MSR_PX) & 1)
509 #define msr_pmm ((env->msr >> MSR_PMM) & 1)
510 #define msr_ri ((env->msr >> MSR_RI) & 1)
511 #define msr_le ((env->msr >> MSR_LE) & 1)
512 #define msr_ts ((env->msr >> MSR_TS1) & 3)
513 #define msr_tm ((env->msr >> MSR_TM) & 1)
514
515 /* Hypervisor bit is more specific */
516 #if defined(TARGET_PPC64)
517 #define MSR_HVB (1ULL << MSR_SHV)
518 #define msr_hv msr_shv
519 #else
520 #if defined(PPC_EMULATE_32BITS_HYPV)
521 #define MSR_HVB (1ULL << MSR_THV)
522 #define msr_hv msr_thv
523 #else
524 #define MSR_HVB (0ULL)
525 #define msr_hv (0)
526 #endif
527 #endif
528
529 /* Facility Status and Control (FSCR) bits */
530 #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
531 #define FSCR_TAR (63 - 55) /* Target Address Register */
532 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
533 #define FSCR_IC_MASK (0xFFULL)
534 #define FSCR_IC_POS (63 - 7)
535 #define FSCR_IC_DSCR_SPR3 2
536 #define FSCR_IC_PMU 3
537 #define FSCR_IC_BHRB 4
538 #define FSCR_IC_TM 5
539 #define FSCR_IC_EBB 7
540 #define FSCR_IC_TAR 8
541
542 /* Exception state register bits definition */
543 #define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
544 #define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
545 #define ESR_PTR (1 << (63 - 38)) /* Trap */
546 #define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
547 #define ESR_ST (1 << (63 - 40)) /* Store Operation */
548 #define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
549 #define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
550 #define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
551 #define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
552 #define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
553 #define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
554 #define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
555 #define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
556 #define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
557 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
558 #define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
559
560 /* Transaction EXception And Summary Register bits */
561 #define TEXASR_FAILURE_PERSISTENT (63 - 7)
562 #define TEXASR_DISALLOWED (63 - 8)
563 #define TEXASR_NESTING_OVERFLOW (63 - 9)
564 #define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
565 #define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
566 #define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
567 #define TEXASR_TRANSACTION_CONFLICT (63 - 13)
568 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
569 #define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
570 #define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
571 #define TEXASR_ABORT (63 - 31)
572 #define TEXASR_SUSPENDED (63 - 32)
573 #define TEXASR_PRIVILEGE_HV (63 - 34)
574 #define TEXASR_PRIVILEGE_PR (63 - 35)
575 #define TEXASR_FAILURE_SUMMARY (63 - 36)
576 #define TEXASR_TFIAR_EXACT (63 - 37)
577 #define TEXASR_ROT (63 - 38)
578 #define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
579
580 enum {
581 POWERPC_FLAG_NONE = 0x00000000,
582 /* Flag for MSR bit 25 signification (VRE/SPE) */
583 POWERPC_FLAG_SPE = 0x00000001,
584 POWERPC_FLAG_VRE = 0x00000002,
585 /* Flag for MSR bit 17 signification (TGPR/CE) */
586 POWERPC_FLAG_TGPR = 0x00000004,
587 POWERPC_FLAG_CE = 0x00000008,
588 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
589 POWERPC_FLAG_SE = 0x00000010,
590 POWERPC_FLAG_DWE = 0x00000020,
591 POWERPC_FLAG_UBLE = 0x00000040,
592 /* Flag for MSR bit 9 signification (BE/DE) */
593 POWERPC_FLAG_BE = 0x00000080,
594 POWERPC_FLAG_DE = 0x00000100,
595 /* Flag for MSR bit 2 signification (PX/PMM) */
596 POWERPC_FLAG_PX = 0x00000200,
597 POWERPC_FLAG_PMM = 0x00000400,
598 /* Flag for special features */
599 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
600 POWERPC_FLAG_RTC_CLK = 0x00010000,
601 POWERPC_FLAG_BUS_CLK = 0x00020000,
602 /* Has CFAR */
603 POWERPC_FLAG_CFAR = 0x00040000,
604 /* Has VSX */
605 POWERPC_FLAG_VSX = 0x00080000,
606 /* Has Transaction Memory (ISA 2.07) */
607 POWERPC_FLAG_TM = 0x00100000,
608 };
609
610 /*****************************************************************************/
611 /* Floating point status and control register */
612 #define FPSCR_FX 31 /* Floating-point exception summary */
613 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
614 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
615 #define FPSCR_OX 28 /* Floating-point overflow exception */
616 #define FPSCR_UX 27 /* Floating-point underflow exception */
617 #define FPSCR_ZX 26 /* Floating-point zero divide exception */
618 #define FPSCR_XX 25 /* Floating-point inexact exception */
619 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
620 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
621 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
622 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
623 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
624 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
625 #define FPSCR_FR 18 /* Floating-point fraction rounded */
626 #define FPSCR_FI 17 /* Floating-point fraction inexact */
627 #define FPSCR_C 16 /* Floating-point result class descriptor */
628 #define FPSCR_FL 15 /* Floating-point less than or negative */
629 #define FPSCR_FG 14 /* Floating-point greater than or negative */
630 #define FPSCR_FE 13 /* Floating-point equal or zero */
631 #define FPSCR_FU 12 /* Floating-point unordered or NaN */
632 #define FPSCR_FPCC 12 /* Floating-point condition code */
633 #define FPSCR_FPRF 12 /* Floating-point result flags */
634 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
635 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
636 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
637 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
638 #define FPSCR_OE 6 /* Floating-point overflow exception enable */
639 #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
640 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
641 #define FPSCR_XE 3 /* Floating-point inexact exception enable */
642 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
643 #define FPSCR_RN1 1
644 #define FPSCR_RN 0 /* Floating-point rounding control */
645 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
646 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
647 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
648 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
649 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
650 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
651 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
652 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
653 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
654 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
655 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
656 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
657 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
658 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
659 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
660 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
661 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
662 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
663 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
664 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
665 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
666 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
667 #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
668 /* Invalid operation exception summary */
669 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
670 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
671 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
672 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
673 (1 << FPSCR_VXCVI)))
674 /* exception summary */
675 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
676 /* enabled exception summary */
677 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
678 0x1F)
679
680 /*****************************************************************************/
681 /* Vector status and control register */
682 #define VSCR_NJ 16 /* Vector non-java */
683 #define VSCR_SAT 0 /* Vector saturation */
684 #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
685 #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
686
687 /*****************************************************************************/
688 /* BookE e500 MMU registers */
689
690 #define MAS0_NV_SHIFT 0
691 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
692
693 #define MAS0_WQ_SHIFT 12
694 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
695 /* Write TLB entry regardless of reservation */
696 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
697 /* Write TLB entry only already in use */
698 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
699 /* Clear TLB entry */
700 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
701
702 #define MAS0_HES_SHIFT 14
703 #define MAS0_HES (1 << MAS0_HES_SHIFT)
704
705 #define MAS0_ESEL_SHIFT 16
706 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
707
708 #define MAS0_TLBSEL_SHIFT 28
709 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
710 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
711 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
712 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
713 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
714
715 #define MAS0_ATSEL_SHIFT 31
716 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
717 #define MAS0_ATSEL_TLB 0
718 #define MAS0_ATSEL_LRAT MAS0_ATSEL
719
720 #define MAS1_TSIZE_SHIFT 7
721 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
722
723 #define MAS1_TS_SHIFT 12
724 #define MAS1_TS (1 << MAS1_TS_SHIFT)
725
726 #define MAS1_IND_SHIFT 13
727 #define MAS1_IND (1 << MAS1_IND_SHIFT)
728
729 #define MAS1_TID_SHIFT 16
730 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
731
732 #define MAS1_IPROT_SHIFT 30
733 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
734
735 #define MAS1_VALID_SHIFT 31
736 #define MAS1_VALID 0x80000000
737
738 #define MAS2_EPN_SHIFT 12
739 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
740
741 #define MAS2_ACM_SHIFT 6
742 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
743
744 #define MAS2_VLE_SHIFT 5
745 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
746
747 #define MAS2_W_SHIFT 4
748 #define MAS2_W (1 << MAS2_W_SHIFT)
749
750 #define MAS2_I_SHIFT 3
751 #define MAS2_I (1 << MAS2_I_SHIFT)
752
753 #define MAS2_M_SHIFT 2
754 #define MAS2_M (1 << MAS2_M_SHIFT)
755
756 #define MAS2_G_SHIFT 1
757 #define MAS2_G (1 << MAS2_G_SHIFT)
758
759 #define MAS2_E_SHIFT 0
760 #define MAS2_E (1 << MAS2_E_SHIFT)
761
762 #define MAS3_RPN_SHIFT 12
763 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
764
765 #define MAS3_U0 0x00000200
766 #define MAS3_U1 0x00000100
767 #define MAS3_U2 0x00000080
768 #define MAS3_U3 0x00000040
769 #define MAS3_UX 0x00000020
770 #define MAS3_SX 0x00000010
771 #define MAS3_UW 0x00000008
772 #define MAS3_SW 0x00000004
773 #define MAS3_UR 0x00000002
774 #define MAS3_SR 0x00000001
775 #define MAS3_SPSIZE_SHIFT 1
776 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
777
778 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
779 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
780 #define MAS4_TIDSELD_MASK 0x00030000
781 #define MAS4_TIDSELD_PID0 0x00000000
782 #define MAS4_TIDSELD_PID1 0x00010000
783 #define MAS4_TIDSELD_PID2 0x00020000
784 #define MAS4_TIDSELD_PIDZ 0x00030000
785 #define MAS4_INDD 0x00008000 /* Default IND */
786 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
787 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
788 #define MAS4_ACMD 0x00000040
789 #define MAS4_VLED 0x00000020
790 #define MAS4_WD 0x00000010
791 #define MAS4_ID 0x00000008
792 #define MAS4_MD 0x00000004
793 #define MAS4_GD 0x00000002
794 #define MAS4_ED 0x00000001
795 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
796 #define MAS4_WIMGED_SHIFT 0
797
798 #define MAS5_SGS 0x80000000
799 #define MAS5_SLPID_MASK 0x00000fff
800
801 #define MAS6_SPID0 0x3fff0000
802 #define MAS6_SPID1 0x00007ffe
803 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
804 #define MAS6_SAS 0x00000001
805 #define MAS6_SPID MAS6_SPID0
806 #define MAS6_SIND 0x00000002 /* Indirect page */
807 #define MAS6_SIND_SHIFT 1
808 #define MAS6_SPID_MASK 0x3fff0000
809 #define MAS6_SPID_SHIFT 16
810 #define MAS6_ISIZE_MASK 0x00000f80
811 #define MAS6_ISIZE_SHIFT 7
812
813 #define MAS7_RPN 0xffffffff
814
815 #define MAS8_TGS 0x80000000
816 #define MAS8_VF 0x40000000
817 #define MAS8_TLBPID 0x00000fff
818
819 /* Bit definitions for MMUCFG */
820 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
821 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
822 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
823 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
824 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
825 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
826 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
827 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
828 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
829
830 /* Bit definitions for MMUCSR0 */
831 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
832 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
833 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
834 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
835 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
836 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
837 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
838 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
839 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
840 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
841
842 /* TLBnCFG encoding */
843 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
844 #define TLBnCFG_HES 0x00002000 /* HW select supported */
845 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
846 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
847 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
848 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
849 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
850 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
851 #define TLBnCFG_MINSIZE_SHIFT 20
852 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
853 #define TLBnCFG_MAXSIZE_SHIFT 16
854 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
855 #define TLBnCFG_ASSOC_SHIFT 24
856
857 /* TLBnPS encoding */
858 #define TLBnPS_4K 0x00000004
859 #define TLBnPS_8K 0x00000008
860 #define TLBnPS_16K 0x00000010
861 #define TLBnPS_32K 0x00000020
862 #define TLBnPS_64K 0x00000040
863 #define TLBnPS_128K 0x00000080
864 #define TLBnPS_256K 0x00000100
865 #define TLBnPS_512K 0x00000200
866 #define TLBnPS_1M 0x00000400
867 #define TLBnPS_2M 0x00000800
868 #define TLBnPS_4M 0x00001000
869 #define TLBnPS_8M 0x00002000
870 #define TLBnPS_16M 0x00004000
871 #define TLBnPS_32M 0x00008000
872 #define TLBnPS_64M 0x00010000
873 #define TLBnPS_128M 0x00020000
874 #define TLBnPS_256M 0x00040000
875 #define TLBnPS_512M 0x00080000
876 #define TLBnPS_1G 0x00100000
877 #define TLBnPS_2G 0x00200000
878 #define TLBnPS_4G 0x00400000
879 #define TLBnPS_8G 0x00800000
880 #define TLBnPS_16G 0x01000000
881 #define TLBnPS_32G 0x02000000
882 #define TLBnPS_64G 0x04000000
883 #define TLBnPS_128G 0x08000000
884 #define TLBnPS_256G 0x10000000
885
886 /* tlbilx action encoding */
887 #define TLBILX_T_ALL 0
888 #define TLBILX_T_TID 1
889 #define TLBILX_T_FULLMATCH 3
890 #define TLBILX_T_CLASS0 4
891 #define TLBILX_T_CLASS1 5
892 #define TLBILX_T_CLASS2 6
893 #define TLBILX_T_CLASS3 7
894
895 /* BookE 2.06 helper defines */
896
897 #define BOOKE206_FLUSH_TLB0 (1 << 0)
898 #define BOOKE206_FLUSH_TLB1 (1 << 1)
899 #define BOOKE206_FLUSH_TLB2 (1 << 2)
900 #define BOOKE206_FLUSH_TLB3 (1 << 3)
901
902 /* number of possible TLBs */
903 #define BOOKE206_MAX_TLBN 4
904
905 /*****************************************************************************/
906 /* Embedded.Processor Control */
907
908 #define DBELL_TYPE_SHIFT 27
909 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
910 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
911 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
912 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
913 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
914 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
915
916 #define DBELL_BRDCAST (1 << 26)
917 #define DBELL_LPIDTAG_SHIFT 14
918 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
919 #define DBELL_PIRTAG_MASK 0x3fff
920
921 /*****************************************************************************/
922 /* Segment page size information, used by recent hash MMUs
923 * The format of this structure mirrors kvm_ppc_smmu_info
924 */
925
926 #define PPC_PAGE_SIZES_MAX_SZ 8
927
928 struct ppc_one_page_size {
929 uint32_t page_shift; /* Page shift (or 0) */
930 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
931 };
932
933 struct ppc_one_seg_page_size {
934 uint32_t page_shift; /* Base page shift of segment (or 0) */
935 uint32_t slb_enc; /* SLB encoding for BookS */
936 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
937 };
938
939 struct ppc_segment_page_sizes {
940 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
941 };
942
943
944 /*****************************************************************************/
945 /* The whole PowerPC CPU context */
946 #define NB_MMU_MODES 3
947
948 #define PPC_CPU_OPCODES_LEN 0x40
949 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
950
951 struct CPUPPCState {
952 /* First are the most commonly used resources
953 * during translated code execution
954 */
955 /* general purpose registers */
956 target_ulong gpr[32];
957 /* Storage for GPR MSB, used by the SPE extension */
958 target_ulong gprh[32];
959 /* LR */
960 target_ulong lr;
961 /* CTR */
962 target_ulong ctr;
963 /* condition register */
964 uint32_t crf[8];
965 #if defined(TARGET_PPC64)
966 /* CFAR */
967 target_ulong cfar;
968 #endif
969 /* XER (with SO, OV, CA split out) */
970 target_ulong xer;
971 target_ulong so;
972 target_ulong ov;
973 target_ulong ca;
974 /* Reservation address */
975 target_ulong reserve_addr;
976 /* Reservation value */
977 target_ulong reserve_val;
978 target_ulong reserve_val2;
979 /* Reservation store address */
980 target_ulong reserve_ea;
981 /* Reserved store source register and size */
982 target_ulong reserve_info;
983
984 /* Those ones are used in supervisor mode only */
985 /* machine state register */
986 target_ulong msr;
987 /* temporary general purpose registers */
988 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
989
990 /* Floating point execution context */
991 float_status fp_status;
992 /* floating point registers */
993 float64 fpr[32];
994 /* floating point status and control register */
995 target_ulong fpscr;
996
997 /* Next instruction pointer */
998 target_ulong nip;
999
1000 int access_type; /* when a memory exception occurs, the access
1001 type is stored here */
1002
1003 CPU_COMMON
1004
1005 /* MMU context - only relevant for full system emulation */
1006 #if !defined(CONFIG_USER_ONLY)
1007 #if defined(TARGET_PPC64)
1008 /* PowerPC 64 SLB area */
1009 ppc_slb_t slb[MAX_SLB_ENTRIES];
1010 int32_t slb_nr;
1011 #endif
1012 /* segment registers */
1013 hwaddr htab_base;
1014 /* mask used to normalize hash value to PTEG index */
1015 hwaddr htab_mask;
1016 target_ulong sr[32];
1017 /* externally stored hash table */
1018 uint8_t *external_htab;
1019 /* BATs */
1020 uint32_t nb_BATs;
1021 target_ulong DBAT[2][8];
1022 target_ulong IBAT[2][8];
1023 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1024 int32_t nb_tlb; /* Total number of TLB */
1025 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1026 int nb_ways; /* Number of ways in the TLB set */
1027 int last_way; /* Last used way used to allocate TLB in a LRU way */
1028 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
1029 int nb_pids; /* Number of available PID registers */
1030 int tlb_type; /* Type of TLB we're dealing with */
1031 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
1032 /* 403 dedicated access protection registers */
1033 target_ulong pb[4];
1034 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1035 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1036 #endif
1037
1038 /* Other registers */
1039 /* Special purpose registers */
1040 target_ulong spr[1024];
1041 ppc_spr_t spr_cb[1024];
1042 /* Altivec registers */
1043 ppc_avr_t avr[32];
1044 uint32_t vscr;
1045 /* VSX registers */
1046 uint64_t vsr[32];
1047 /* SPE registers */
1048 uint64_t spe_acc;
1049 uint32_t spe_fscr;
1050 /* SPE and Altivec can share a status since they will never be used
1051 * simultaneously */
1052 float_status vec_status;
1053
1054 /* Internal devices resources */
1055 /* Time base and decrementer */
1056 ppc_tb_t *tb_env;
1057 /* Device control registers */
1058 ppc_dcr_t *dcr_env;
1059
1060 int dcache_line_size;
1061 int icache_line_size;
1062
1063 /* Those resources are used during exception processing */
1064 /* CPU model definition */
1065 target_ulong msr_mask;
1066 powerpc_mmu_t mmu_model;
1067 powerpc_excp_t excp_model;
1068 powerpc_input_t bus_model;
1069 int bfd_mach;
1070 uint32_t flags;
1071 uint64_t insns_flags;
1072 uint64_t insns_flags2;
1073 #if defined(TARGET_PPC64)
1074 struct ppc_segment_page_sizes sps;
1075 #endif
1076
1077 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1078 uint64_t vpa_addr;
1079 uint64_t slb_shadow_addr, slb_shadow_size;
1080 uint64_t dtl_addr, dtl_size;
1081 #endif /* TARGET_PPC64 */
1082
1083 int error_code;
1084 uint32_t pending_interrupts;
1085 #if !defined(CONFIG_USER_ONLY)
1086 /* This is the IRQ controller, which is implementation dependent
1087 * and only relevant when emulating a complete machine.
1088 */
1089 uint32_t irq_input_state;
1090 void **irq_inputs;
1091 /* Exception vectors */
1092 target_ulong excp_vectors[POWERPC_EXCP_NB];
1093 target_ulong excp_prefix;
1094 target_ulong ivor_mask;
1095 target_ulong ivpr_mask;
1096 target_ulong hreset_vector;
1097 hwaddr mpic_iack;
1098 /* true when the external proxy facility mode is enabled */
1099 bool mpic_proxy;
1100 #endif
1101
1102 /* Those resources are used only during code translation */
1103 /* opcode handlers */
1104 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1105
1106 /* Those resources are used only in QEMU core */
1107 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
1108 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1109 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
1110
1111 /* Power management */
1112 int (*check_pow)(CPUPPCState *env);
1113
1114 #if !defined(CONFIG_USER_ONLY)
1115 void *load_info; /* Holds boot loading state. */
1116 #endif
1117
1118 /* booke timers */
1119
1120 /* Specifies bit locations of the Time Base used to signal a fixed timer
1121 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1122 *
1123 * 0 selects the least significant bit.
1124 * 63 selects the most significant bit.
1125 */
1126 uint8_t fit_period[4];
1127 uint8_t wdt_period[4];
1128
1129 /* Transactional memory state */
1130 target_ulong tm_gpr[32];
1131 ppc_avr_t tm_vsr[64];
1132 uint64_t tm_cr;
1133 uint64_t tm_lr;
1134 uint64_t tm_ctr;
1135 uint64_t tm_fpscr;
1136 uint64_t tm_amr;
1137 uint64_t tm_ppr;
1138 uint64_t tm_vrsave;
1139 uint32_t tm_vscr;
1140 uint64_t tm_dscr;
1141 uint64_t tm_tar;
1142 };
1143
1144 #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1145 do { \
1146 env->fit_period[0] = (a_); \
1147 env->fit_period[1] = (b_); \
1148 env->fit_period[2] = (c_); \
1149 env->fit_period[3] = (d_); \
1150 } while (0)
1151
1152 #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1153 do { \
1154 env->wdt_period[0] = (a_); \
1155 env->wdt_period[1] = (b_); \
1156 env->wdt_period[2] = (c_); \
1157 env->wdt_period[3] = (d_); \
1158 } while (0)
1159
1160 #include "cpu-qom.h"
1161
1162 /*****************************************************************************/
1163 PowerPCCPU *cpu_ppc_init(const char *cpu_model);
1164 void ppc_translate_init(void);
1165 void gen_update_current_nip(void *opaque);
1166 int cpu_ppc_exec (CPUPPCState *s);
1167 /* you can call this signal handler from your SIGBUS and SIGSEGV
1168 signal handlers to inform the virtual CPU of exceptions. non zero
1169 is returned if the signal was handled by the virtual CPU. */
1170 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1171 void *puc);
1172 #if defined(CONFIG_USER_ONLY)
1173 int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1174 int mmu_idx);
1175 #endif
1176
1177 #if !defined(CONFIG_USER_ONLY)
1178 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1179 #endif /* !defined(CONFIG_USER_ONLY) */
1180 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1181
1182 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1183 int ppc_get_compat_smt_threads(PowerPCCPU *cpu);
1184 int ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version);
1185
1186 /* Time-base and decrementer management */
1187 #ifndef NO_CPU_IO_DEFS
1188 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1189 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1190 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1191 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1192 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1193 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1194 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1195 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1196 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1197 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1198 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1199 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1200 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1201 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1202 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1203 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1204 #if !defined(CONFIG_USER_ONLY)
1205 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1206 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1207 target_ulong load_40x_pit (CPUPPCState *env);
1208 void store_40x_pit (CPUPPCState *env, target_ulong val);
1209 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1210 void store_40x_sler (CPUPPCState *env, uint32_t val);
1211 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1212 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1213 void ppc_tlb_invalidate_all (CPUPPCState *env);
1214 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1215 #endif
1216 #endif
1217
1218 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1219
1220 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1221 {
1222 uint64_t gprv;
1223
1224 gprv = env->gpr[gprn];
1225 if (env->flags & POWERPC_FLAG_SPE) {
1226 /* If the CPU implements the SPE extension, we have to get the
1227 * high bits of the GPR from the gprh storage area
1228 */
1229 gprv &= 0xFFFFFFFFULL;
1230 gprv |= (uint64_t)env->gprh[gprn] << 32;
1231 }
1232
1233 return gprv;
1234 }
1235
1236 /* Device control registers */
1237 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1238 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1239
1240 static inline CPUPPCState *cpu_init(const char *cpu_model)
1241 {
1242 PowerPCCPU *cpu = cpu_ppc_init(cpu_model);
1243 if (cpu == NULL) {
1244 return NULL;
1245 }
1246 return &cpu->env;
1247 }
1248
1249 #define cpu_exec cpu_ppc_exec
1250 #define cpu_gen_code cpu_ppc_gen_code
1251 #define cpu_signal_handler cpu_ppc_signal_handler
1252 #define cpu_list ppc_cpu_list
1253
1254 /* MMU modes definitions */
1255 #define MMU_MODE0_SUFFIX _user
1256 #define MMU_MODE1_SUFFIX _kernel
1257 #define MMU_MODE2_SUFFIX _hypv
1258 #define MMU_USER_IDX 0
1259 static inline int cpu_mmu_index (CPUPPCState *env)
1260 {
1261 return env->mmu_idx;
1262 }
1263
1264 #include "exec/cpu-all.h"
1265
1266 /*****************************************************************************/
1267 /* CRF definitions */
1268 #define CRF_LT 3
1269 #define CRF_GT 2
1270 #define CRF_EQ 1
1271 #define CRF_SO 0
1272 #define CRF_CH (1 << CRF_LT)
1273 #define CRF_CL (1 << CRF_GT)
1274 #define CRF_CH_OR_CL (1 << CRF_EQ)
1275 #define CRF_CH_AND_CL (1 << CRF_SO)
1276
1277 /* XER definitions */
1278 #define XER_SO 31
1279 #define XER_OV 30
1280 #define XER_CA 29
1281 #define XER_CMP 8
1282 #define XER_BC 0
1283 #define xer_so (env->so)
1284 #define xer_ov (env->ov)
1285 #define xer_ca (env->ca)
1286 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1287 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1288
1289 /* SPR definitions */
1290 #define SPR_MQ (0x000)
1291 #define SPR_XER (0x001)
1292 #define SPR_601_VRTCU (0x004)
1293 #define SPR_601_VRTCL (0x005)
1294 #define SPR_601_UDECR (0x006)
1295 #define SPR_LR (0x008)
1296 #define SPR_CTR (0x009)
1297 #define SPR_UAMR (0x00C)
1298 #define SPR_DSCR (0x011)
1299 #define SPR_DSISR (0x012)
1300 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1301 #define SPR_601_RTCU (0x014)
1302 #define SPR_601_RTCL (0x015)
1303 #define SPR_DECR (0x016)
1304 #define SPR_SDR1 (0x019)
1305 #define SPR_SRR0 (0x01A)
1306 #define SPR_SRR1 (0x01B)
1307 #define SPR_CFAR (0x01C)
1308 #define SPR_AMR (0x01D)
1309 #define SPR_BOOKE_PID (0x030)
1310 #define SPR_BOOKE_DECAR (0x036)
1311 #define SPR_BOOKE_CSRR0 (0x03A)
1312 #define SPR_BOOKE_CSRR1 (0x03B)
1313 #define SPR_BOOKE_DEAR (0x03D)
1314 #define SPR_BOOKE_ESR (0x03E)
1315 #define SPR_BOOKE_IVPR (0x03F)
1316 #define SPR_MPC_EIE (0x050)
1317 #define SPR_MPC_EID (0x051)
1318 #define SPR_MPC_NRI (0x052)
1319 #define SPR_TFHAR (0x080)
1320 #define SPR_TFIAR (0x081)
1321 #define SPR_TEXASR (0x082)
1322 #define SPR_TEXASRU (0x083)
1323 #define SPR_UCTRL (0x088)
1324 #define SPR_MPC_CMPA (0x090)
1325 #define SPR_MPC_CMPB (0x091)
1326 #define SPR_MPC_CMPC (0x092)
1327 #define SPR_MPC_CMPD (0x093)
1328 #define SPR_MPC_ECR (0x094)
1329 #define SPR_MPC_DER (0x095)
1330 #define SPR_MPC_COUNTA (0x096)
1331 #define SPR_MPC_COUNTB (0x097)
1332 #define SPR_CTRL (0x098)
1333 #define SPR_MPC_CMPE (0x098)
1334 #define SPR_MPC_CMPF (0x099)
1335 #define SPR_FSCR (0x099)
1336 #define SPR_MPC_CMPG (0x09A)
1337 #define SPR_MPC_CMPH (0x09B)
1338 #define SPR_MPC_LCTRL1 (0x09C)
1339 #define SPR_MPC_LCTRL2 (0x09D)
1340 #define SPR_UAMOR (0x09D)
1341 #define SPR_MPC_ICTRL (0x09E)
1342 #define SPR_MPC_BAR (0x09F)
1343 #define SPR_VRSAVE (0x100)
1344 #define SPR_USPRG0 (0x100)
1345 #define SPR_USPRG1 (0x101)
1346 #define SPR_USPRG2 (0x102)
1347 #define SPR_USPRG3 (0x103)
1348 #define SPR_USPRG4 (0x104)
1349 #define SPR_USPRG5 (0x105)
1350 #define SPR_USPRG6 (0x106)
1351 #define SPR_USPRG7 (0x107)
1352 #define SPR_VTBL (0x10C)
1353 #define SPR_VTBU (0x10D)
1354 #define SPR_SPRG0 (0x110)
1355 #define SPR_SPRG1 (0x111)
1356 #define SPR_SPRG2 (0x112)
1357 #define SPR_SPRG3 (0x113)
1358 #define SPR_SPRG4 (0x114)
1359 #define SPR_SCOMC (0x114)
1360 #define SPR_SPRG5 (0x115)
1361 #define SPR_SCOMD (0x115)
1362 #define SPR_SPRG6 (0x116)
1363 #define SPR_SPRG7 (0x117)
1364 #define SPR_ASR (0x118)
1365 #define SPR_EAR (0x11A)
1366 #define SPR_TBL (0x11C)
1367 #define SPR_TBU (0x11D)
1368 #define SPR_TBU40 (0x11E)
1369 #define SPR_SVR (0x11E)
1370 #define SPR_BOOKE_PIR (0x11E)
1371 #define SPR_PVR (0x11F)
1372 #define SPR_HSPRG0 (0x130)
1373 #define SPR_BOOKE_DBSR (0x130)
1374 #define SPR_HSPRG1 (0x131)
1375 #define SPR_HDSISR (0x132)
1376 #define SPR_HDAR (0x133)
1377 #define SPR_BOOKE_EPCR (0x133)
1378 #define SPR_SPURR (0x134)
1379 #define SPR_BOOKE_DBCR0 (0x134)
1380 #define SPR_IBCR (0x135)
1381 #define SPR_PURR (0x135)
1382 #define SPR_BOOKE_DBCR1 (0x135)
1383 #define SPR_DBCR (0x136)
1384 #define SPR_HDEC (0x136)
1385 #define SPR_BOOKE_DBCR2 (0x136)
1386 #define SPR_HIOR (0x137)
1387 #define SPR_MBAR (0x137)
1388 #define SPR_RMOR (0x138)
1389 #define SPR_BOOKE_IAC1 (0x138)
1390 #define SPR_HRMOR (0x139)
1391 #define SPR_BOOKE_IAC2 (0x139)
1392 #define SPR_HSRR0 (0x13A)
1393 #define SPR_BOOKE_IAC3 (0x13A)
1394 #define SPR_HSRR1 (0x13B)
1395 #define SPR_BOOKE_IAC4 (0x13B)
1396 #define SPR_BOOKE_DAC1 (0x13C)
1397 #define SPR_LPIDR (0x13D)
1398 #define SPR_DABR2 (0x13D)
1399 #define SPR_BOOKE_DAC2 (0x13D)
1400 #define SPR_BOOKE_DVC1 (0x13E)
1401 #define SPR_LPCR (0x13E)
1402 #define SPR_BOOKE_DVC2 (0x13F)
1403 #define SPR_BOOKE_TSR (0x150)
1404 #define SPR_PCR (0x152)
1405 #define SPR_BOOKE_TCR (0x154)
1406 #define SPR_BOOKE_TLB0PS (0x158)
1407 #define SPR_BOOKE_TLB1PS (0x159)
1408 #define SPR_BOOKE_TLB2PS (0x15A)
1409 #define SPR_BOOKE_TLB3PS (0x15B)
1410 #define SPR_BOOKE_MAS7_MAS3 (0x174)
1411 #define SPR_BOOKE_IVOR0 (0x190)
1412 #define SPR_BOOKE_IVOR1 (0x191)
1413 #define SPR_BOOKE_IVOR2 (0x192)
1414 #define SPR_BOOKE_IVOR3 (0x193)
1415 #define SPR_BOOKE_IVOR4 (0x194)
1416 #define SPR_BOOKE_IVOR5 (0x195)
1417 #define SPR_BOOKE_IVOR6 (0x196)
1418 #define SPR_BOOKE_IVOR7 (0x197)
1419 #define SPR_BOOKE_IVOR8 (0x198)
1420 #define SPR_BOOKE_IVOR9 (0x199)
1421 #define SPR_BOOKE_IVOR10 (0x19A)
1422 #define SPR_BOOKE_IVOR11 (0x19B)
1423 #define SPR_BOOKE_IVOR12 (0x19C)
1424 #define SPR_BOOKE_IVOR13 (0x19D)
1425 #define SPR_BOOKE_IVOR14 (0x19E)
1426 #define SPR_BOOKE_IVOR15 (0x19F)
1427 #define SPR_BOOKE_IVOR38 (0x1B0)
1428 #define SPR_BOOKE_IVOR39 (0x1B1)
1429 #define SPR_BOOKE_IVOR40 (0x1B2)
1430 #define SPR_BOOKE_IVOR41 (0x1B3)
1431 #define SPR_BOOKE_IVOR42 (0x1B4)
1432 #define SPR_BOOKE_GIVOR2 (0x1B8)
1433 #define SPR_BOOKE_GIVOR3 (0x1B9)
1434 #define SPR_BOOKE_GIVOR4 (0x1BA)
1435 #define SPR_BOOKE_GIVOR8 (0x1BB)
1436 #define SPR_BOOKE_GIVOR13 (0x1BC)
1437 #define SPR_BOOKE_GIVOR14 (0x1BD)
1438 #define SPR_TIR (0x1BE)
1439 #define SPR_BOOKE_SPEFSCR (0x200)
1440 #define SPR_Exxx_BBEAR (0x201)
1441 #define SPR_Exxx_BBTAR (0x202)
1442 #define SPR_Exxx_L1CFG0 (0x203)
1443 #define SPR_Exxx_L1CFG1 (0x204)
1444 #define SPR_Exxx_NPIDR (0x205)
1445 #define SPR_ATBL (0x20E)
1446 #define SPR_ATBU (0x20F)
1447 #define SPR_IBAT0U (0x210)
1448 #define SPR_BOOKE_IVOR32 (0x210)
1449 #define SPR_RCPU_MI_GRA (0x210)
1450 #define SPR_IBAT0L (0x211)
1451 #define SPR_BOOKE_IVOR33 (0x211)
1452 #define SPR_IBAT1U (0x212)
1453 #define SPR_BOOKE_IVOR34 (0x212)
1454 #define SPR_IBAT1L (0x213)
1455 #define SPR_BOOKE_IVOR35 (0x213)
1456 #define SPR_IBAT2U (0x214)
1457 #define SPR_BOOKE_IVOR36 (0x214)
1458 #define SPR_IBAT2L (0x215)
1459 #define SPR_BOOKE_IVOR37 (0x215)
1460 #define SPR_IBAT3U (0x216)
1461 #define SPR_IBAT3L (0x217)
1462 #define SPR_DBAT0U (0x218)
1463 #define SPR_RCPU_L2U_GRA (0x218)
1464 #define SPR_DBAT0L (0x219)
1465 #define SPR_DBAT1U (0x21A)
1466 #define SPR_DBAT1L (0x21B)
1467 #define SPR_DBAT2U (0x21C)
1468 #define SPR_DBAT2L (0x21D)
1469 #define SPR_DBAT3U (0x21E)
1470 #define SPR_DBAT3L (0x21F)
1471 #define SPR_IBAT4U (0x230)
1472 #define SPR_RPCU_BBCMCR (0x230)
1473 #define SPR_MPC_IC_CST (0x230)
1474 #define SPR_Exxx_CTXCR (0x230)
1475 #define SPR_IBAT4L (0x231)
1476 #define SPR_MPC_IC_ADR (0x231)
1477 #define SPR_Exxx_DBCR3 (0x231)
1478 #define SPR_IBAT5U (0x232)
1479 #define SPR_MPC_IC_DAT (0x232)
1480 #define SPR_Exxx_DBCNT (0x232)
1481 #define SPR_IBAT5L (0x233)
1482 #define SPR_IBAT6U (0x234)
1483 #define SPR_IBAT6L (0x235)
1484 #define SPR_IBAT7U (0x236)
1485 #define SPR_IBAT7L (0x237)
1486 #define SPR_DBAT4U (0x238)
1487 #define SPR_RCPU_L2U_MCR (0x238)
1488 #define SPR_MPC_DC_CST (0x238)
1489 #define SPR_Exxx_ALTCTXCR (0x238)
1490 #define SPR_DBAT4L (0x239)
1491 #define SPR_MPC_DC_ADR (0x239)
1492 #define SPR_DBAT5U (0x23A)
1493 #define SPR_BOOKE_MCSRR0 (0x23A)
1494 #define SPR_MPC_DC_DAT (0x23A)
1495 #define SPR_DBAT5L (0x23B)
1496 #define SPR_BOOKE_MCSRR1 (0x23B)
1497 #define SPR_DBAT6U (0x23C)
1498 #define SPR_BOOKE_MCSR (0x23C)
1499 #define SPR_DBAT6L (0x23D)
1500 #define SPR_Exxx_MCAR (0x23D)
1501 #define SPR_DBAT7U (0x23E)
1502 #define SPR_BOOKE_DSRR0 (0x23E)
1503 #define SPR_DBAT7L (0x23F)
1504 #define SPR_BOOKE_DSRR1 (0x23F)
1505 #define SPR_BOOKE_SPRG8 (0x25C)
1506 #define SPR_BOOKE_SPRG9 (0x25D)
1507 #define SPR_BOOKE_MAS0 (0x270)
1508 #define SPR_BOOKE_MAS1 (0x271)
1509 #define SPR_BOOKE_MAS2 (0x272)
1510 #define SPR_BOOKE_MAS3 (0x273)
1511 #define SPR_BOOKE_MAS4 (0x274)
1512 #define SPR_BOOKE_MAS5 (0x275)
1513 #define SPR_BOOKE_MAS6 (0x276)
1514 #define SPR_BOOKE_PID1 (0x279)
1515 #define SPR_BOOKE_PID2 (0x27A)
1516 #define SPR_MPC_DPDR (0x280)
1517 #define SPR_MPC_IMMR (0x288)
1518 #define SPR_BOOKE_TLB0CFG (0x2B0)
1519 #define SPR_BOOKE_TLB1CFG (0x2B1)
1520 #define SPR_BOOKE_TLB2CFG (0x2B2)
1521 #define SPR_BOOKE_TLB3CFG (0x2B3)
1522 #define SPR_BOOKE_EPR (0x2BE)
1523 #define SPR_PERF0 (0x300)
1524 #define SPR_RCPU_MI_RBA0 (0x300)
1525 #define SPR_MPC_MI_CTR (0x300)
1526 #define SPR_PERF1 (0x301)
1527 #define SPR_RCPU_MI_RBA1 (0x301)
1528 #define SPR_POWER_UMMCR2 (0x301)
1529 #define SPR_PERF2 (0x302)
1530 #define SPR_RCPU_MI_RBA2 (0x302)
1531 #define SPR_MPC_MI_AP (0x302)
1532 #define SPR_POWER_UMMCRA (0x302)
1533 #define SPR_PERF3 (0x303)
1534 #define SPR_RCPU_MI_RBA3 (0x303)
1535 #define SPR_MPC_MI_EPN (0x303)
1536 #define SPR_POWER_UPMC1 (0x303)
1537 #define SPR_PERF4 (0x304)
1538 #define SPR_POWER_UPMC2 (0x304)
1539 #define SPR_PERF5 (0x305)
1540 #define SPR_MPC_MI_TWC (0x305)
1541 #define SPR_POWER_UPMC3 (0x305)
1542 #define SPR_PERF6 (0x306)
1543 #define SPR_MPC_MI_RPN (0x306)
1544 #define SPR_POWER_UPMC4 (0x306)
1545 #define SPR_PERF7 (0x307)
1546 #define SPR_POWER_UPMC5 (0x307)
1547 #define SPR_PERF8 (0x308)
1548 #define SPR_RCPU_L2U_RBA0 (0x308)
1549 #define SPR_MPC_MD_CTR (0x308)
1550 #define SPR_POWER_UPMC6 (0x308)
1551 #define SPR_PERF9 (0x309)
1552 #define SPR_RCPU_L2U_RBA1 (0x309)
1553 #define SPR_MPC_MD_CASID (0x309)
1554 #define SPR_970_UPMC7 (0X309)
1555 #define SPR_PERFA (0x30A)
1556 #define SPR_RCPU_L2U_RBA2 (0x30A)
1557 #define SPR_MPC_MD_AP (0x30A)
1558 #define SPR_970_UPMC8 (0X30A)
1559 #define SPR_PERFB (0x30B)
1560 #define SPR_RCPU_L2U_RBA3 (0x30B)
1561 #define SPR_MPC_MD_EPN (0x30B)
1562 #define SPR_POWER_UMMCR0 (0X30B)
1563 #define SPR_PERFC (0x30C)
1564 #define SPR_MPC_MD_TWB (0x30C)
1565 #define SPR_POWER_USIAR (0X30C)
1566 #define SPR_PERFD (0x30D)
1567 #define SPR_MPC_MD_TWC (0x30D)
1568 #define SPR_POWER_USDAR (0X30D)
1569 #define SPR_PERFE (0x30E)
1570 #define SPR_MPC_MD_RPN (0x30E)
1571 #define SPR_POWER_UMMCR1 (0X30E)
1572 #define SPR_PERFF (0x30F)
1573 #define SPR_MPC_MD_TW (0x30F)
1574 #define SPR_UPERF0 (0x310)
1575 #define SPR_UPERF1 (0x311)
1576 #define SPR_POWER_MMCR2 (0x311)
1577 #define SPR_UPERF2 (0x312)
1578 #define SPR_POWER_MMCRA (0X312)
1579 #define SPR_UPERF3 (0x313)
1580 #define SPR_POWER_PMC1 (0X313)
1581 #define SPR_UPERF4 (0x314)
1582 #define SPR_POWER_PMC2 (0X314)
1583 #define SPR_UPERF5 (0x315)
1584 #define SPR_POWER_PMC3 (0X315)
1585 #define SPR_UPERF6 (0x316)
1586 #define SPR_POWER_PMC4 (0X316)
1587 #define SPR_UPERF7 (0x317)
1588 #define SPR_POWER_PMC5 (0X317)
1589 #define SPR_UPERF8 (0x318)
1590 #define SPR_POWER_PMC6 (0X318)
1591 #define SPR_UPERF9 (0x319)
1592 #define SPR_970_PMC7 (0X319)
1593 #define SPR_UPERFA (0x31A)
1594 #define SPR_970_PMC8 (0X31A)
1595 #define SPR_UPERFB (0x31B)
1596 #define SPR_POWER_MMCR0 (0X31B)
1597 #define SPR_UPERFC (0x31C)
1598 #define SPR_POWER_SIAR (0X31C)
1599 #define SPR_UPERFD (0x31D)
1600 #define SPR_POWER_SDAR (0X31D)
1601 #define SPR_UPERFE (0x31E)
1602 #define SPR_POWER_MMCR1 (0X31E)
1603 #define SPR_UPERFF (0x31F)
1604 #define SPR_RCPU_MI_RA0 (0x320)
1605 #define SPR_MPC_MI_DBCAM (0x320)
1606 #define SPR_BESCRS (0x320)
1607 #define SPR_RCPU_MI_RA1 (0x321)
1608 #define SPR_MPC_MI_DBRAM0 (0x321)
1609 #define SPR_BESCRSU (0x321)
1610 #define SPR_RCPU_MI_RA2 (0x322)
1611 #define SPR_MPC_MI_DBRAM1 (0x322)
1612 #define SPR_BESCRR (0x322)
1613 #define SPR_RCPU_MI_RA3 (0x323)
1614 #define SPR_BESCRRU (0x323)
1615 #define SPR_EBBHR (0x324)
1616 #define SPR_EBBRR (0x325)
1617 #define SPR_BESCR (0x326)
1618 #define SPR_RCPU_L2U_RA0 (0x328)
1619 #define SPR_MPC_MD_DBCAM (0x328)
1620 #define SPR_RCPU_L2U_RA1 (0x329)
1621 #define SPR_MPC_MD_DBRAM0 (0x329)
1622 #define SPR_RCPU_L2U_RA2 (0x32A)
1623 #define SPR_MPC_MD_DBRAM1 (0x32A)
1624 #define SPR_RCPU_L2U_RA3 (0x32B)
1625 #define SPR_TAR (0x32F)
1626 #define SPR_440_INV0 (0x370)
1627 #define SPR_440_INV1 (0x371)
1628 #define SPR_440_INV2 (0x372)
1629 #define SPR_440_INV3 (0x373)
1630 #define SPR_440_ITV0 (0x374)
1631 #define SPR_440_ITV1 (0x375)
1632 #define SPR_440_ITV2 (0x376)
1633 #define SPR_440_ITV3 (0x377)
1634 #define SPR_440_CCR1 (0x378)
1635 #define SPR_DCRIPR (0x37B)
1636 #define SPR_POWER_MMCRS (0x37E)
1637 #define SPR_PPR (0x380)
1638 #define SPR_750_GQR0 (0x390)
1639 #define SPR_440_DNV0 (0x390)
1640 #define SPR_750_GQR1 (0x391)
1641 #define SPR_440_DNV1 (0x391)
1642 #define SPR_750_GQR2 (0x392)
1643 #define SPR_440_DNV2 (0x392)
1644 #define SPR_750_GQR3 (0x393)
1645 #define SPR_440_DNV3 (0x393)
1646 #define SPR_750_GQR4 (0x394)
1647 #define SPR_440_DTV0 (0x394)
1648 #define SPR_750_GQR5 (0x395)
1649 #define SPR_440_DTV1 (0x395)
1650 #define SPR_750_GQR6 (0x396)
1651 #define SPR_440_DTV2 (0x396)
1652 #define SPR_750_GQR7 (0x397)
1653 #define SPR_440_DTV3 (0x397)
1654 #define SPR_750_THRM4 (0x398)
1655 #define SPR_750CL_HID2 (0x398)
1656 #define SPR_440_DVLIM (0x398)
1657 #define SPR_750_WPAR (0x399)
1658 #define SPR_440_IVLIM (0x399)
1659 #define SPR_750_DMAU (0x39A)
1660 #define SPR_750_DMAL (0x39B)
1661 #define SPR_440_RSTCFG (0x39B)
1662 #define SPR_BOOKE_DCDBTRL (0x39C)
1663 #define SPR_BOOKE_DCDBTRH (0x39D)
1664 #define SPR_BOOKE_ICDBTRL (0x39E)
1665 #define SPR_BOOKE_ICDBTRH (0x39F)
1666 #define SPR_74XX_UMMCR2 (0x3A0)
1667 #define SPR_7XX_UPMC5 (0x3A1)
1668 #define SPR_7XX_UPMC6 (0x3A2)
1669 #define SPR_UBAMR (0x3A7)
1670 #define SPR_7XX_UMMCR0 (0x3A8)
1671 #define SPR_7XX_UPMC1 (0x3A9)
1672 #define SPR_7XX_UPMC2 (0x3AA)
1673 #define SPR_7XX_USIAR (0x3AB)
1674 #define SPR_7XX_UMMCR1 (0x3AC)
1675 #define SPR_7XX_UPMC3 (0x3AD)
1676 #define SPR_7XX_UPMC4 (0x3AE)
1677 #define SPR_USDA (0x3AF)
1678 #define SPR_40x_ZPR (0x3B0)
1679 #define SPR_BOOKE_MAS7 (0x3B0)
1680 #define SPR_74XX_MMCR2 (0x3B0)
1681 #define SPR_7XX_PMC5 (0x3B1)
1682 #define SPR_40x_PID (0x3B1)
1683 #define SPR_7XX_PMC6 (0x3B2)
1684 #define SPR_440_MMUCR (0x3B2)
1685 #define SPR_4xx_CCR0 (0x3B3)
1686 #define SPR_BOOKE_EPLC (0x3B3)
1687 #define SPR_405_IAC3 (0x3B4)
1688 #define SPR_BOOKE_EPSC (0x3B4)
1689 #define SPR_405_IAC4 (0x3B5)
1690 #define SPR_405_DVC1 (0x3B6)
1691 #define SPR_405_DVC2 (0x3B7)
1692 #define SPR_BAMR (0x3B7)
1693 #define SPR_7XX_MMCR0 (0x3B8)
1694 #define SPR_7XX_PMC1 (0x3B9)
1695 #define SPR_40x_SGR (0x3B9)
1696 #define SPR_7XX_PMC2 (0x3BA)
1697 #define SPR_40x_DCWR (0x3BA)
1698 #define SPR_7XX_SIAR (0x3BB)
1699 #define SPR_405_SLER (0x3BB)
1700 #define SPR_7XX_MMCR1 (0x3BC)
1701 #define SPR_405_SU0R (0x3BC)
1702 #define SPR_401_SKR (0x3BC)
1703 #define SPR_7XX_PMC3 (0x3BD)
1704 #define SPR_405_DBCR1 (0x3BD)
1705 #define SPR_7XX_PMC4 (0x3BE)
1706 #define SPR_SDA (0x3BF)
1707 #define SPR_403_VTBL (0x3CC)
1708 #define SPR_403_VTBU (0x3CD)
1709 #define SPR_DMISS (0x3D0)
1710 #define SPR_DCMP (0x3D1)
1711 #define SPR_HASH1 (0x3D2)
1712 #define SPR_HASH2 (0x3D3)
1713 #define SPR_BOOKE_ICDBDR (0x3D3)
1714 #define SPR_TLBMISS (0x3D4)
1715 #define SPR_IMISS (0x3D4)
1716 #define SPR_40x_ESR (0x3D4)
1717 #define SPR_PTEHI (0x3D5)
1718 #define SPR_ICMP (0x3D5)
1719 #define SPR_40x_DEAR (0x3D5)
1720 #define SPR_PTELO (0x3D6)
1721 #define SPR_RPA (0x3D6)
1722 #define SPR_40x_EVPR (0x3D6)
1723 #define SPR_L3PM (0x3D7)
1724 #define SPR_403_CDBCR (0x3D7)
1725 #define SPR_L3ITCR0 (0x3D8)
1726 #define SPR_TCR (0x3D8)
1727 #define SPR_40x_TSR (0x3D8)
1728 #define SPR_IBR (0x3DA)
1729 #define SPR_40x_TCR (0x3DA)
1730 #define SPR_ESASRR (0x3DB)
1731 #define SPR_40x_PIT (0x3DB)
1732 #define SPR_403_TBL (0x3DC)
1733 #define SPR_403_TBU (0x3DD)
1734 #define SPR_SEBR (0x3DE)
1735 #define SPR_40x_SRR2 (0x3DE)
1736 #define SPR_SER (0x3DF)
1737 #define SPR_40x_SRR3 (0x3DF)
1738 #define SPR_L3OHCR (0x3E8)
1739 #define SPR_L3ITCR1 (0x3E9)
1740 #define SPR_L3ITCR2 (0x3EA)
1741 #define SPR_L3ITCR3 (0x3EB)
1742 #define SPR_HID0 (0x3F0)
1743 #define SPR_40x_DBSR (0x3F0)
1744 #define SPR_HID1 (0x3F1)
1745 #define SPR_IABR (0x3F2)
1746 #define SPR_40x_DBCR0 (0x3F2)
1747 #define SPR_601_HID2 (0x3F2)
1748 #define SPR_Exxx_L1CSR0 (0x3F2)
1749 #define SPR_ICTRL (0x3F3)
1750 #define SPR_HID2 (0x3F3)
1751 #define SPR_750CL_HID4 (0x3F3)
1752 #define SPR_Exxx_L1CSR1 (0x3F3)
1753 #define SPR_440_DBDR (0x3F3)
1754 #define SPR_LDSTDB (0x3F4)
1755 #define SPR_750_TDCL (0x3F4)
1756 #define SPR_40x_IAC1 (0x3F4)
1757 #define SPR_MMUCSR0 (0x3F4)
1758 #define SPR_970_HID4 (0x3F4)
1759 #define SPR_DABR (0x3F5)
1760 #define DABR_MASK (~(target_ulong)0x7)
1761 #define SPR_Exxx_BUCSR (0x3F5)
1762 #define SPR_40x_IAC2 (0x3F5)
1763 #define SPR_601_HID5 (0x3F5)
1764 #define SPR_40x_DAC1 (0x3F6)
1765 #define SPR_MSSCR0 (0x3F6)
1766 #define SPR_970_HID5 (0x3F6)
1767 #define SPR_MSSSR0 (0x3F7)
1768 #define SPR_MSSCR1 (0x3F7)
1769 #define SPR_DABRX (0x3F7)
1770 #define SPR_40x_DAC2 (0x3F7)
1771 #define SPR_MMUCFG (0x3F7)
1772 #define SPR_LDSTCR (0x3F8)
1773 #define SPR_L2PMCR (0x3F8)
1774 #define SPR_750FX_HID2 (0x3F8)
1775 #define SPR_Exxx_L1FINV0 (0x3F8)
1776 #define SPR_L2CR (0x3F9)
1777 #define SPR_L3CR (0x3FA)
1778 #define SPR_750_TDCH (0x3FA)
1779 #define SPR_IABR2 (0x3FA)
1780 #define SPR_40x_DCCR (0x3FA)
1781 #define SPR_ICTC (0x3FB)
1782 #define SPR_40x_ICCR (0x3FB)
1783 #define SPR_THRM1 (0x3FC)
1784 #define SPR_403_PBL1 (0x3FC)
1785 #define SPR_SP (0x3FD)
1786 #define SPR_THRM2 (0x3FD)
1787 #define SPR_403_PBU1 (0x3FD)
1788 #define SPR_604_HID13 (0x3FD)
1789 #define SPR_LT (0x3FE)
1790 #define SPR_THRM3 (0x3FE)
1791 #define SPR_RCPU_FPECR (0x3FE)
1792 #define SPR_403_PBL2 (0x3FE)
1793 #define SPR_PIR (0x3FF)
1794 #define SPR_403_PBU2 (0x3FF)
1795 #define SPR_601_HID15 (0x3FF)
1796 #define SPR_604_HID15 (0x3FF)
1797 #define SPR_E500_SVR (0x3FF)
1798
1799 /* Disable MAS Interrupt Updates for Hypervisor */
1800 #define EPCR_DMIUH (1 << 22)
1801 /* Disable Guest TLB Management Instructions */
1802 #define EPCR_DGTMI (1 << 23)
1803 /* Guest Interrupt Computation Mode */
1804 #define EPCR_GICM (1 << 24)
1805 /* Interrupt Computation Mode */
1806 #define EPCR_ICM (1 << 25)
1807 /* Disable Embedded Hypervisor Debug */
1808 #define EPCR_DUVD (1 << 26)
1809 /* Instruction Storage Interrupt Directed to Guest State */
1810 #define EPCR_ISIGS (1 << 27)
1811 /* Data Storage Interrupt Directed to Guest State */
1812 #define EPCR_DSIGS (1 << 28)
1813 /* Instruction TLB Error Interrupt Directed to Guest State */
1814 #define EPCR_ITLBGS (1 << 29)
1815 /* Data TLB Error Interrupt Directed to Guest State */
1816 #define EPCR_DTLBGS (1 << 30)
1817 /* External Input Interrupt Directed to Guest State */
1818 #define EPCR_EXTGS (1 << 31)
1819
1820 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
1821 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
1822 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
1823 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
1824 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
1825
1826 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
1827 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
1828 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
1829 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
1830 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
1831
1832 /* HID0 bits */
1833 #define HID0_DEEPNAP (1 << 24)
1834 #define HID0_DOZE (1 << 23)
1835 #define HID0_NAP (1 << 22)
1836
1837 /*****************************************************************************/
1838 /* PowerPC Instructions types definitions */
1839 enum {
1840 PPC_NONE = 0x0000000000000000ULL,
1841 /* PowerPC base instructions set */
1842 PPC_INSNS_BASE = 0x0000000000000001ULL,
1843 /* integer operations instructions */
1844 #define PPC_INTEGER PPC_INSNS_BASE
1845 /* flow control instructions */
1846 #define PPC_FLOW PPC_INSNS_BASE
1847 /* virtual memory instructions */
1848 #define PPC_MEM PPC_INSNS_BASE
1849 /* ld/st with reservation instructions */
1850 #define PPC_RES PPC_INSNS_BASE
1851 /* spr/msr access instructions */
1852 #define PPC_MISC PPC_INSNS_BASE
1853 /* Deprecated instruction sets */
1854 /* Original POWER instruction set */
1855 PPC_POWER = 0x0000000000000002ULL,
1856 /* POWER2 instruction set extension */
1857 PPC_POWER2 = 0x0000000000000004ULL,
1858 /* Power RTC support */
1859 PPC_POWER_RTC = 0x0000000000000008ULL,
1860 /* Power-to-PowerPC bridge (601) */
1861 PPC_POWER_BR = 0x0000000000000010ULL,
1862 /* 64 bits PowerPC instruction set */
1863 PPC_64B = 0x0000000000000020ULL,
1864 /* New 64 bits extensions (PowerPC 2.0x) */
1865 PPC_64BX = 0x0000000000000040ULL,
1866 /* 64 bits hypervisor extensions */
1867 PPC_64H = 0x0000000000000080ULL,
1868 /* New wait instruction (PowerPC 2.0x) */
1869 PPC_WAIT = 0x0000000000000100ULL,
1870 /* Time base mftb instruction */
1871 PPC_MFTB = 0x0000000000000200ULL,
1872
1873 /* Fixed-point unit extensions */
1874 /* PowerPC 602 specific */
1875 PPC_602_SPEC = 0x0000000000000400ULL,
1876 /* isel instruction */
1877 PPC_ISEL = 0x0000000000000800ULL,
1878 /* popcntb instruction */
1879 PPC_POPCNTB = 0x0000000000001000ULL,
1880 /* string load / store */
1881 PPC_STRING = 0x0000000000002000ULL,
1882
1883 /* Floating-point unit extensions */
1884 /* Optional floating point instructions */
1885 PPC_FLOAT = 0x0000000000010000ULL,
1886 /* New floating-point extensions (PowerPC 2.0x) */
1887 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1888 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1889 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1890 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1891 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1892 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1893 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1894
1895 /* Vector/SIMD extensions */
1896 /* Altivec support */
1897 PPC_ALTIVEC = 0x0000000001000000ULL,
1898 /* PowerPC 2.03 SPE extension */
1899 PPC_SPE = 0x0000000002000000ULL,
1900 /* PowerPC 2.03 SPE single-precision floating-point extension */
1901 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1902 /* PowerPC 2.03 SPE double-precision floating-point extension */
1903 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1904
1905 /* Optional memory control instructions */
1906 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1907 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1908 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1909 /* sync instruction */
1910 PPC_MEM_SYNC = 0x0000000080000000ULL,
1911 /* eieio instruction */
1912 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1913
1914 /* Cache control instructions */
1915 PPC_CACHE = 0x0000000200000000ULL,
1916 /* icbi instruction */
1917 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1918 /* dcbz instruction */
1919 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1920 /* dcba instruction */
1921 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1922 /* Freescale cache locking instructions */
1923 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1924
1925 /* MMU related extensions */
1926 /* external control instructions */
1927 PPC_EXTERN = 0x0000010000000000ULL,
1928 /* segment register access instructions */
1929 PPC_SEGMENT = 0x0000020000000000ULL,
1930 /* PowerPC 6xx TLB management instructions */
1931 PPC_6xx_TLB = 0x0000040000000000ULL,
1932 /* PowerPC 74xx TLB management instructions */
1933 PPC_74xx_TLB = 0x0000080000000000ULL,
1934 /* PowerPC 40x TLB management instructions */
1935 PPC_40x_TLB = 0x0000100000000000ULL,
1936 /* segment register access instructions for PowerPC 64 "bridge" */
1937 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1938 /* SLB management */
1939 PPC_SLBI = 0x0000400000000000ULL,
1940
1941 /* Embedded PowerPC dedicated instructions */
1942 PPC_WRTEE = 0x0001000000000000ULL,
1943 /* PowerPC 40x exception model */
1944 PPC_40x_EXCP = 0x0002000000000000ULL,
1945 /* PowerPC 405 Mac instructions */
1946 PPC_405_MAC = 0x0004000000000000ULL,
1947 /* PowerPC 440 specific instructions */
1948 PPC_440_SPEC = 0x0008000000000000ULL,
1949 /* BookE (embedded) PowerPC specification */
1950 PPC_BOOKE = 0x0010000000000000ULL,
1951 /* mfapidi instruction */
1952 PPC_MFAPIDI = 0x0020000000000000ULL,
1953 /* tlbiva instruction */
1954 PPC_TLBIVA = 0x0040000000000000ULL,
1955 /* tlbivax instruction */
1956 PPC_TLBIVAX = 0x0080000000000000ULL,
1957 /* PowerPC 4xx dedicated instructions */
1958 PPC_4xx_COMMON = 0x0100000000000000ULL,
1959 /* PowerPC 40x ibct instructions */
1960 PPC_40x_ICBT = 0x0200000000000000ULL,
1961 /* rfmci is not implemented in all BookE PowerPC */
1962 PPC_RFMCI = 0x0400000000000000ULL,
1963 /* rfdi instruction */
1964 PPC_RFDI = 0x0800000000000000ULL,
1965 /* DCR accesses */
1966 PPC_DCR = 0x1000000000000000ULL,
1967 /* DCR extended accesse */
1968 PPC_DCRX = 0x2000000000000000ULL,
1969 /* user-mode DCR access, implemented in PowerPC 460 */
1970 PPC_DCRUX = 0x4000000000000000ULL,
1971 /* popcntw and popcntd instructions */
1972 PPC_POPCNTWD = 0x8000000000000000ULL,
1973
1974 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
1975 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
1976 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
1977 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
1978 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
1979 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
1980 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
1981 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
1982 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
1983 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
1984 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
1985 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
1986 | PPC_CACHE | PPC_CACHE_ICBI \
1987 | PPC_CACHE_DCBZ \
1988 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
1989 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
1990 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
1991 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
1992 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
1993 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
1994 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
1995 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
1996 | PPC_POPCNTWD)
1997
1998 /* extended type values */
1999
2000 /* BookE 2.06 PowerPC specification */
2001 PPC2_BOOKE206 = 0x0000000000000001ULL,
2002 /* VSX (extensions to Altivec / VMX) */
2003 PPC2_VSX = 0x0000000000000002ULL,
2004 /* Decimal Floating Point (DFP) */
2005 PPC2_DFP = 0x0000000000000004ULL,
2006 /* Embedded.Processor Control */
2007 PPC2_PRCNTL = 0x0000000000000008ULL,
2008 /* Byte-reversed, indexed, double-word load and store */
2009 PPC2_DBRX = 0x0000000000000010ULL,
2010 /* Book I 2.05 PowerPC specification */
2011 PPC2_ISA205 = 0x0000000000000020ULL,
2012 /* VSX additions in ISA 2.07 */
2013 PPC2_VSX207 = 0x0000000000000040ULL,
2014 /* ISA 2.06B bpermd */
2015 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
2016 /* ISA 2.06B divide extended variants */
2017 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
2018 /* ISA 2.06B larx/stcx. instructions */
2019 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2020 /* ISA 2.06B floating point integer conversion */
2021 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2022 /* ISA 2.06B floating point test instructions */
2023 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2024 /* ISA 2.07 bctar instruction */
2025 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
2026 /* ISA 2.07 load/store quadword */
2027 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
2028 /* ISA 2.07 Altivec */
2029 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
2030 /* PowerISA 2.07 Book3s specification */
2031 PPC2_ISA207S = 0x0000000000008000ULL,
2032 /* Double precision floating point conversion for signed integer 64 */
2033 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
2034 /* Transactional Memory (ISA 2.07, Book II) */
2035 PPC2_TM = 0x0000000000020000ULL,
2036
2037 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2038 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2039 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2040 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2041 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2042 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2043 PPC2_FP_CVT_S64 | PPC2_TM)
2044 };
2045
2046 /*****************************************************************************/
2047 /* Memory access type :
2048 * may be needed for precise access rights control and precise exceptions.
2049 */
2050 enum {
2051 /* 1 bit to define user level / supervisor access */
2052 ACCESS_USER = 0x00,
2053 ACCESS_SUPER = 0x01,
2054 /* Type of instruction that generated the access */
2055 ACCESS_CODE = 0x10, /* Code fetch access */
2056 ACCESS_INT = 0x20, /* Integer load/store access */
2057 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2058 ACCESS_RES = 0x40, /* load/store with reservation */
2059 ACCESS_EXT = 0x50, /* external access */
2060 ACCESS_CACHE = 0x60, /* Cache manipulation */
2061 };
2062
2063 /* Hardware interruption sources:
2064 * all those exception can be raised simulteaneously
2065 */
2066 /* Input pins definitions */
2067 enum {
2068 /* 6xx bus input pins */
2069 PPC6xx_INPUT_HRESET = 0,
2070 PPC6xx_INPUT_SRESET = 1,
2071 PPC6xx_INPUT_CKSTP_IN = 2,
2072 PPC6xx_INPUT_MCP = 3,
2073 PPC6xx_INPUT_SMI = 4,
2074 PPC6xx_INPUT_INT = 5,
2075 PPC6xx_INPUT_TBEN = 6,
2076 PPC6xx_INPUT_WAKEUP = 7,
2077 PPC6xx_INPUT_NB,
2078 };
2079
2080 enum {
2081 /* Embedded PowerPC input pins */
2082 PPCBookE_INPUT_HRESET = 0,
2083 PPCBookE_INPUT_SRESET = 1,
2084 PPCBookE_INPUT_CKSTP_IN = 2,
2085 PPCBookE_INPUT_MCP = 3,
2086 PPCBookE_INPUT_SMI = 4,
2087 PPCBookE_INPUT_INT = 5,
2088 PPCBookE_INPUT_CINT = 6,
2089 PPCBookE_INPUT_NB,
2090 };
2091
2092 enum {
2093 /* PowerPC E500 input pins */
2094 PPCE500_INPUT_RESET_CORE = 0,
2095 PPCE500_INPUT_MCK = 1,
2096 PPCE500_INPUT_CINT = 3,
2097 PPCE500_INPUT_INT = 4,
2098 PPCE500_INPUT_DEBUG = 6,
2099 PPCE500_INPUT_NB,
2100 };
2101
2102 enum {
2103 /* PowerPC 40x input pins */
2104 PPC40x_INPUT_RESET_CORE = 0,
2105 PPC40x_INPUT_RESET_CHIP = 1,
2106 PPC40x_INPUT_RESET_SYS = 2,
2107 PPC40x_INPUT_CINT = 3,
2108 PPC40x_INPUT_INT = 4,
2109 PPC40x_INPUT_HALT = 5,
2110 PPC40x_INPUT_DEBUG = 6,
2111 PPC40x_INPUT_NB,
2112 };
2113
2114 enum {
2115 /* RCPU input pins */
2116 PPCRCPU_INPUT_PORESET = 0,
2117 PPCRCPU_INPUT_HRESET = 1,
2118 PPCRCPU_INPUT_SRESET = 2,
2119 PPCRCPU_INPUT_IRQ0 = 3,
2120 PPCRCPU_INPUT_IRQ1 = 4,
2121 PPCRCPU_INPUT_IRQ2 = 5,
2122 PPCRCPU_INPUT_IRQ3 = 6,
2123 PPCRCPU_INPUT_IRQ4 = 7,
2124 PPCRCPU_INPUT_IRQ5 = 8,
2125 PPCRCPU_INPUT_IRQ6 = 9,
2126 PPCRCPU_INPUT_IRQ7 = 10,
2127 PPCRCPU_INPUT_NB,
2128 };
2129
2130 #if defined(TARGET_PPC64)
2131 enum {
2132 /* PowerPC 970 input pins */
2133 PPC970_INPUT_HRESET = 0,
2134 PPC970_INPUT_SRESET = 1,
2135 PPC970_INPUT_CKSTP = 2,
2136 PPC970_INPUT_TBEN = 3,
2137 PPC970_INPUT_MCP = 4,
2138 PPC970_INPUT_INT = 5,
2139 PPC970_INPUT_THINT = 6,
2140 PPC970_INPUT_NB,
2141 };
2142
2143 enum {
2144 /* POWER7 input pins */
2145 POWER7_INPUT_INT = 0,
2146 /* POWER7 probably has other inputs, but we don't care about them
2147 * for any existing machine. We can wire these up when we need
2148 * them */
2149 POWER7_INPUT_NB,
2150 };
2151 #endif
2152
2153 /* Hardware exceptions definitions */
2154 enum {
2155 /* External hardware exception sources */
2156 PPC_INTERRUPT_RESET = 0, /* Reset exception */
2157 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2158 PPC_INTERRUPT_MCK, /* Machine check exception */
2159 PPC_INTERRUPT_EXT, /* External interrupt */
2160 PPC_INTERRUPT_SMI, /* System management interrupt */
2161 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2162 PPC_INTERRUPT_DEBUG, /* External debug exception */
2163 PPC_INTERRUPT_THERM, /* Thermal exception */
2164 /* Internal hardware exception sources */
2165 PPC_INTERRUPT_DECR, /* Decrementer exception */
2166 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2167 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2168 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2169 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2170 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2171 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2172 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
2173 };
2174
2175 /* Processor Compatibility mask (PCR) */
2176 enum {
2177 PCR_COMPAT_2_05 = 1ull << (63-62),
2178 PCR_COMPAT_2_06 = 1ull << (63-61),
2179 PCR_VEC_DIS = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */
2180 PCR_VSX_DIS = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */
2181 PCR_TM_DIS = 1ull << (63-2), /* Trans. memory disable (POWER8) */
2182 };
2183
2184 /*****************************************************************************/
2185
2186 static inline target_ulong cpu_read_xer(CPUPPCState *env)
2187 {
2188 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2189 }
2190
2191 static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2192 {
2193 env->so = (xer >> XER_SO) & 1;
2194 env->ov = (xer >> XER_OV) & 1;
2195 env->ca = (xer >> XER_CA) & 1;
2196 env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2197 }
2198
2199 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2200 target_ulong *cs_base, int *flags)
2201 {
2202 *pc = env->nip;
2203 *cs_base = 0;
2204 *flags = env->hflags;
2205 }
2206
2207 #if !defined(CONFIG_USER_ONLY)
2208 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2209 {
2210 uintptr_t tlbml = (uintptr_t)tlbm;
2211 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2212
2213 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2214 }
2215
2216 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2217 {
2218 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2219 int r = tlbncfg & TLBnCFG_N_ENTRY;
2220 return r;
2221 }
2222
2223 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2224 {
2225 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2226 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2227 return r;
2228 }
2229
2230 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2231 {
2232 int id = booke206_tlbm_id(env, tlbm);
2233 int end = 0;
2234 int i;
2235
2236 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2237 end += booke206_tlb_size(env, i);
2238 if (id < end) {
2239 return i;
2240 }
2241 }
2242
2243 cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
2244 return 0;
2245 }
2246
2247 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2248 {
2249 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2250 int tlbid = booke206_tlbm_id(env, tlb);
2251 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2252 }
2253
2254 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2255 target_ulong ea, int way)
2256 {
2257 int r;
2258 uint32_t ways = booke206_tlb_ways(env, tlbn);
2259 int ways_bits = ffs(ways) - 1;
2260 int tlb_bits = ffs(booke206_tlb_size(env, tlbn)) - 1;
2261 int i;
2262
2263 way &= ways - 1;
2264 ea >>= MAS2_EPN_SHIFT;
2265 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2266 r = (ea << ways_bits) | way;
2267
2268 if (r >= booke206_tlb_size(env, tlbn)) {
2269 return NULL;
2270 }
2271
2272 /* bump up to tlbn index */
2273 for (i = 0; i < tlbn; i++) {
2274 r += booke206_tlb_size(env, i);
2275 }
2276
2277 return &env->tlb.tlbm[r];
2278 }
2279
2280 /* returns bitmap of supported page sizes for a given TLB */
2281 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2282 {
2283 bool mav2 = false;
2284 uint32_t ret = 0;
2285
2286 if (mav2) {
2287 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2288 } else {
2289 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2290 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2291 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2292 int i;
2293 for (i = min; i <= max; i++) {
2294 ret |= (1 << (i << 1));
2295 }
2296 }
2297
2298 return ret;
2299 }
2300
2301 #endif
2302
2303 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2304 {
2305 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2306 return msr & (1ULL << MSR_CM);
2307 }
2308
2309 return msr & (1ULL << MSR_SF);
2310 }
2311
2312 extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
2313
2314 #include "exec/exec-all.h"
2315
2316 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2317
2318 /**
2319 * ppc_get_vcpu_dt_id:
2320 * @cs: a PowerPCCPU struct.
2321 *
2322 * Returns a device-tree ID for a CPU.
2323 */
2324 int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
2325
2326 /**
2327 * ppc_get_vcpu_by_dt_id:
2328 * @cpu_dt_id: a device tree id
2329 *
2330 * Searches for a CPU by @cpu_dt_id.
2331 *
2332 * Returns: a PowerPCCPU struct
2333 */
2334 PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
2335
2336 #endif /* !defined (__CPU_PPC_H__) */
AR7 emulation for QEMU