hw/s390x/s390-pci-inst.c

   1 /*
   2  * s390 PCI instructions
   3  *
   4  * Copyright 2014 IBM Corp.
   5  * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
   6  *            Hong Bo Li <lihbbj@cn.ibm.com>
   7  *            Yi Min Zhao <zyimin@cn.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or (at
  10  * your option) any later version. See the COPYING file in the top-level
  11  * directory.
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "qemu-common.h"
  16 #include "cpu.h"
  17 #include "s390-pci-inst.h"
  18 #include "s390-pci-bus.h"
  19 #include "exec/memory-internal.h"
  20 #include "qemu/error-report.h"
  21 #include "sysemu/hw_accel.h"
  22
  23 /* #define DEBUG_S390PCI_INST */
  24 #ifdef DEBUG_S390PCI_INST
  25 #define DPRINTF(fmt, ...) \
  26     do { fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); } while (0)
  27 #else
  28 #define DPRINTF(fmt, ...) \
  29     do { } while (0)
  30 #endif
  31
  32 static void s390_set_status_code(CPUS390XState *env,
  33                                  uint8_t r, uint64_t status_code)
  34 {
  35     env->regs[r] &= ~0xff000000ULL;
  36     env->regs[r] |= (status_code & 0xff) << 24;
  37 }
  38
  39 static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc)
  40 {
  41     S390PCIBusDevice *pbdev = NULL;
  42     S390pciState *s = s390_get_phb();
  43     uint32_t res_code, initial_l2, g_l2;
  44     int rc, i;
  45     uint64_t resume_token;
  46
  47     rc = 0;
  48     if (lduw_p(&rrb->request.hdr.len) != 32) {
  49         res_code = CLP_RC_LEN;
  50         rc = -EINVAL;
  51         goto out;
  52     }
  53
  54     if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) {
  55         res_code = CLP_RC_FMT;
  56         rc = -EINVAL;
  57         goto out;
  58     }
  59
  60     if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 ||
  61         ldq_p(&rrb->request.reserved1) != 0) {
  62         res_code = CLP_RC_RESNOT0;
  63         rc = -EINVAL;
  64         goto out;
  65     }
  66
  67     resume_token = ldq_p(&rrb->request.resume_token);
  68
  69     if (resume_token) {
  70         pbdev = s390_pci_find_dev_by_idx(s, resume_token);
  71         if (!pbdev) {
  72             res_code = CLP_RC_LISTPCI_BADRT;
  73             rc = -EINVAL;
  74             goto out;
  75         }
  76     } else {
  77         pbdev = s390_pci_find_next_avail_dev(s, NULL);
  78     }
  79
  80     if (lduw_p(&rrb->response.hdr.len) < 48) {
  81         res_code = CLP_RC_8K;
  82         rc = -EINVAL;
  83         goto out;
  84     }
  85
  86     initial_l2 = lduw_p(&rrb->response.hdr.len);
  87     if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry)
  88         != 0) {
  89         res_code = CLP_RC_LEN;
  90         rc = -EINVAL;
  91         *cc = 3;
  92         goto out;
  93     }
  94
  95     stl_p(&rrb->response.fmt, 0);
  96     stq_p(&rrb->response.reserved1, 0);
  97     stl_p(&rrb->response.mdd, FH_MASK_SHM);
  98     stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS);
  99     rrb->response.flags = UID_CHECKING_ENABLED;
 100     rrb->response.entry_size = sizeof(ClpFhListEntry);
 101
 102     i = 0;
 103     g_l2 = LIST_PCI_HDR_LEN;
 104     while (g_l2 < initial_l2 && pbdev) {
 105         stw_p(&rrb->response.fh_list[i].device_id,
 106             pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID));
 107         stw_p(&rrb->response.fh_list[i].vendor_id,
 108             pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID));
 109         /* Ignore RESERVED devices. */
 110         stl_p(&rrb->response.fh_list[i].config,
 111             pbdev->state == ZPCI_FS_STANDBY ? 0 : 1 << 31);
 112         stl_p(&rrb->response.fh_list[i].fid, pbdev->fid);
 113         stl_p(&rrb->response.fh_list[i].fh, pbdev->fh);
 114
 115         g_l2 += sizeof(ClpFhListEntry);
 116         /* Add endian check for DPRINTF? */
 117         DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n",
 118                 g_l2,
 119                 lduw_p(&rrb->response.fh_list[i].vendor_id),
 120                 lduw_p(&rrb->response.fh_list[i].device_id),
 121                 ldl_p(&rrb->response.fh_list[i].fid),
 122                 ldl_p(&rrb->response.fh_list[i].fh));
 123         pbdev = s390_pci_find_next_avail_dev(s, pbdev);
 124         i++;
 125     }
 126
 127     if (!pbdev) {
 128         resume_token = 0;
 129     } else {
 130         resume_token = pbdev->fh & FH_MASK_INDEX;
 131     }
 132     stq_p(&rrb->response.resume_token, resume_token);
 133     stw_p(&rrb->response.hdr.len, g_l2);
 134     stw_p(&rrb->response.hdr.rsp, CLP_RC_OK);
 135 out:
 136     if (rc) {
 137         DPRINTF("list pci failed rc 0x%x\n", rc);
 138         stw_p(&rrb->response.hdr.rsp, res_code);
 139     }
 140     return rc;
 141 }
 142
 143 int clp_service_call(S390CPU *cpu, uint8_t r2)
 144 {
 145     ClpReqHdr *reqh;
 146     ClpRspHdr *resh;
 147     S390PCIBusDevice *pbdev;
 148     uint32_t req_len;
 149     uint32_t res_len;
 150     uint8_t buffer[4096 * 2];
 151     uint8_t cc = 0;
 152     CPUS390XState *env = &cpu->env;
 153     S390pciState *s = s390_get_phb();
 154     int i;
 155
 156     cpu_synchronize_state(CPU(cpu));
 157
 158     if (env->psw.mask & PSW_MASK_PSTATE) {
 159         program_interrupt(env, PGM_PRIVILEGED, 4);
 160         return 0;
 161     }
 162
 163     if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, sizeof(*reqh))) {
 164         return 0;
 165     }
 166     reqh = (ClpReqHdr *)buffer;
 167     req_len = lduw_p(&reqh->len);
 168     if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) {
 169         program_interrupt(env, PGM_OPERAND, 4);
 170         return 0;
 171     }
 172
 173     if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer,
 174                                req_len + sizeof(*resh))) {
 175         return 0;
 176     }
 177     resh = (ClpRspHdr *)(buffer + req_len);
 178     res_len = lduw_p(&resh->len);
 179     if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) {
 180         program_interrupt(env, PGM_OPERAND, 4);
 181         return 0;
 182     }
 183     if ((req_len + res_len) > 8192) {
 184         program_interrupt(env, PGM_OPERAND, 4);
 185         return 0;
 186     }
 187
 188     if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer,
 189                                req_len + res_len)) {
 190         return 0;
 191     }
 192
 193     if (req_len != 32) {
 194         stw_p(&resh->rsp, CLP_RC_LEN);
 195         goto out;
 196     }
 197
 198     switch (lduw_p(&reqh->cmd)) {
 199     case CLP_LIST_PCI: {
 200         ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer;
 201         list_pci(rrb, &cc);
 202         break;
 203     }
 204     case CLP_SET_PCI_FN: {
 205         ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh;
 206         ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh;
 207
 208         pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqsetpci->fh));
 209         if (!pbdev) {
 210                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH);
 211                 goto out;
 212         }
 213
 214         switch (reqsetpci->oc) {
 215         case CLP_SET_ENABLE_PCI_FN:
 216             switch (reqsetpci->ndas) {
 217             case 0:
 218                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS);
 219                 goto out;
 220             case 1:
 221                 break;
 222             default:
 223                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES);
 224                 goto out;
 225             }
 226
 227             if (pbdev->fh & FH_MASK_ENABLE) {
 228                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
 229                 goto out;
 230             }
 231
 232             pbdev->fh |= FH_MASK_ENABLE;
 233             pbdev->state = ZPCI_FS_ENABLED;
 234             stl_p(&ressetpci->fh, pbdev->fh);
 235             stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
 236             break;
 237         case CLP_SET_DISABLE_PCI_FN:
 238             if (!(pbdev->fh & FH_MASK_ENABLE)) {
 239                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
 240                 goto out;
 241             }
 242             device_reset(DEVICE(pbdev));
 243             pbdev->fh &= ~FH_MASK_ENABLE;
 244             pbdev->state = ZPCI_FS_DISABLED;
 245             stl_p(&ressetpci->fh, pbdev->fh);
 246             stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
 247             break;
 248         default:
 249             DPRINTF("unknown set pci command\n");
 250             stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
 251             break;
 252         }
 253         break;
 254     }
 255     case CLP_QUERY_PCI_FN: {
 256         ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh;
 257         ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh;
 258
 259         pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqquery->fh));
 260         if (!pbdev) {
 261             DPRINTF("query pci no pci dev\n");
 262             stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH);
 263             goto out;
 264         }
 265
 266         for (i = 0; i < PCI_BAR_COUNT; i++) {
 267             uint32_t data = pci_get_long(pbdev->pdev->config +
 268                 PCI_BASE_ADDRESS_0 + (i * 4));
 269
 270             stl_p(&resquery->bar[i], data);
 271             resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ?
 272                                     ctz64(pbdev->pdev->io_regions[i].size) : 0;
 273             DPRINTF("bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x\n", i,
 274                     ldl_p(&resquery->bar[i]),
 275                     pbdev->pdev->io_regions[i].size,
 276                     resquery->bar_size[i]);
 277         }
 278
 279         stq_p(&resquery->sdma, ZPCI_SDMA_ADDR);
 280         stq_p(&resquery->edma, ZPCI_EDMA_ADDR);
 281         stl_p(&resquery->fid, pbdev->fid);
 282         stw_p(&resquery->pchid, 0);
 283         stw_p(&resquery->ug, 1);
 284         stl_p(&resquery->uid, pbdev->uid);
 285         stw_p(&resquery->hdr.rsp, CLP_RC_OK);
 286         break;
 287     }
 288     case CLP_QUERY_PCI_FNGRP: {
 289         ClpRspQueryPciGrp *resgrp = (ClpRspQueryPciGrp *)resh;
 290         resgrp->fr = 1;
 291         stq_p(&resgrp->dasm, 0);
 292         stq_p(&resgrp->msia, ZPCI_MSI_ADDR);
 293         stw_p(&resgrp->mui, 0);
 294         stw_p(&resgrp->i, 128);
 295         resgrp->version = 0;
 296
 297         stw_p(&resgrp->hdr.rsp, CLP_RC_OK);
 298         break;
 299     }
 300     default:
 301         DPRINTF("unknown clp command\n");
 302         stw_p(&resh->rsp, CLP_RC_CMD);
 303         break;
 304     }
 305
 306 out:
 307     if (s390_cpu_virt_mem_write(cpu, env->regs[r2], r2, buffer,
 308                                 req_len + res_len)) {
 309         return 0;
 310     }
 311     setcc(cpu, cc);
 312     return 0;
 313 }
 314
 315 int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2)
 316 {
 317     CPUS390XState *env = &cpu->env;
 318     S390PCIBusDevice *pbdev;
 319     uint64_t offset;
 320     uint64_t data;
 321     MemoryRegion *mr;
 322     MemTxResult result;
 323     uint8_t len;
 324     uint32_t fh;
 325     uint8_t pcias;
 326
 327     cpu_synchronize_state(CPU(cpu));
 328
 329     if (env->psw.mask & PSW_MASK_PSTATE) {
 330         program_interrupt(env, PGM_PRIVILEGED, 4);
 331         return 0;
 332     }
 333
 334     if (r2 & 0x1) {
 335         program_interrupt(env, PGM_SPECIFICATION, 4);
 336         return 0;
 337     }
 338
 339     fh = env->regs[r2] >> 32;
 340     pcias = (env->regs[r2] >> 16) & 0xf;
 341     len = env->regs[r2] & 0xf;
 342     offset = env->regs[r2 + 1];
 343
 344     pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
 345     if (!pbdev) {
 346         DPRINTF("pcilg no pci dev\n");
 347         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 348         return 0;
 349     }
 350
 351     switch (pbdev->state) {
 352     case ZPCI_FS_RESERVED:
 353     case ZPCI_FS_STANDBY:
 354     case ZPCI_FS_DISABLED:
 355     case ZPCI_FS_PERMANENT_ERROR:
 356         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 357         return 0;
 358     case ZPCI_FS_ERROR:
 359         setcc(cpu, ZPCI_PCI_LS_ERR);
 360         s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
 361         return 0;
 362     default:
 363         break;
 364     }
 365
 366     if (pcias < 6) {
 367         if ((8 - (offset & 0x7)) < len) {
 368             program_interrupt(env, PGM_OPERAND, 4);
 369             return 0;
 370         }
 371         mr = pbdev->pdev->io_regions[pcias].memory;
 372         result = memory_region_dispatch_read(mr, offset, &data, len,
 373                                              MEMTXATTRS_UNSPECIFIED);
 374         if (result != MEMTX_OK) {
 375             program_interrupt(env, PGM_OPERAND, 4);
 376             return 0;
 377         }
 378     } else if (pcias == 15) {
 379         if ((4 - (offset & 0x3)) < len) {
 380             program_interrupt(env, PGM_OPERAND, 4);
 381             return 0;
 382         }
 383         data =  pci_host_config_read_common(
 384                    pbdev->pdev, offset, pci_config_size(pbdev->pdev), len);
 385
 386         switch (len) {
 387         case 1:
 388             break;
 389         case 2:
 390             data = bswap16(data);
 391             break;
 392         case 4:
 393             data = bswap32(data);
 394             break;
 395         case 8:
 396             data = bswap64(data);
 397             break;
 398         default:
 399             program_interrupt(env, PGM_OPERAND, 4);
 400             return 0;
 401         }
 402     } else {
 403         DPRINTF("invalid space\n");
 404         setcc(cpu, ZPCI_PCI_LS_ERR);
 405         s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
 406         return 0;
 407     }
 408
 409     env->regs[r1] = data;
 410     setcc(cpu, ZPCI_PCI_LS_OK);
 411     return 0;
 412 }
 413
 414 static void update_msix_table_msg_data(S390PCIBusDevice *pbdev, uint64_t offset,
 415                                        uint64_t *data, uint8_t len)
 416 {
 417     uint32_t val;
 418     uint8_t *msg_data;
 419
 420     if (offset % PCI_MSIX_ENTRY_SIZE != 8) {
 421         return;
 422     }
 423
 424     if (len != 4) {
 425         DPRINTF("access msix table msg data but len is %d\n", len);
 426         return;
 427     }
 428
 429     msg_data = (uint8_t *)data - offset % PCI_MSIX_ENTRY_SIZE +
 430                PCI_MSIX_ENTRY_VECTOR_CTRL;
 431     val = pci_get_long(msg_data) |
 432         ((pbdev->fh & FH_MASK_INDEX) << ZPCI_MSI_VEC_BITS);
 433     pci_set_long(msg_data, val);
 434     DPRINTF("update msix msg_data to 0x%" PRIx64 "\n", *data);
 435 }
 436
 437 static int trap_msix(S390PCIBusDevice *pbdev, uint64_t offset, uint8_t pcias)
 438 {
 439     if (pbdev->msix.available && pbdev->msix.table_bar == pcias &&
 440         offset >= pbdev->msix.table_offset &&
 441         offset <= pbdev->msix.table_offset +
 442                   (pbdev->msix.entries - 1) * PCI_MSIX_ENTRY_SIZE) {
 443         return 1;
 444     } else {
 445         return 0;
 446     }
 447 }
 448
 449 int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2)
 450 {
 451     CPUS390XState *env = &cpu->env;
 452     uint64_t offset, data;
 453     S390PCIBusDevice *pbdev;
 454     MemoryRegion *mr;
 455     MemTxResult result;
 456     uint8_t len;
 457     uint32_t fh;
 458     uint8_t pcias;
 459
 460     cpu_synchronize_state(CPU(cpu));
 461
 462     if (env->psw.mask & PSW_MASK_PSTATE) {
 463         program_interrupt(env, PGM_PRIVILEGED, 4);
 464         return 0;
 465     }
 466
 467     if (r2 & 0x1) {
 468         program_interrupt(env, PGM_SPECIFICATION, 4);
 469         return 0;
 470     }
 471
 472     fh = env->regs[r2] >> 32;
 473     pcias = (env->regs[r2] >> 16) & 0xf;
 474     len = env->regs[r2] & 0xf;
 475     offset = env->regs[r2 + 1];
 476
 477     pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
 478     if (!pbdev) {
 479         DPRINTF("pcistg no pci dev\n");
 480         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 481         return 0;
 482     }
 483
 484     switch (pbdev->state) {
 485     case ZPCI_FS_RESERVED:
 486     case ZPCI_FS_STANDBY:
 487     case ZPCI_FS_DISABLED:
 488     case ZPCI_FS_PERMANENT_ERROR:
 489         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 490         return 0;
 491     case ZPCI_FS_ERROR:
 492         setcc(cpu, ZPCI_PCI_LS_ERR);
 493         s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
 494         return 0;
 495     default:
 496         break;
 497     }
 498
 499     data = env->regs[r1];
 500     if (pcias < 6) {
 501         if ((8 - (offset & 0x7)) < len) {
 502             program_interrupt(env, PGM_OPERAND, 4);
 503             return 0;
 504         }
 505
 506         if (trap_msix(pbdev, offset, pcias)) {
 507             offset = offset - pbdev->msix.table_offset;
 508             mr = &pbdev->pdev->msix_table_mmio;
 509             update_msix_table_msg_data(pbdev, offset, &data, len);
 510         } else {
 511             mr = pbdev->pdev->io_regions[pcias].memory;
 512         }
 513
 514         result = memory_region_dispatch_write(mr, offset, data, len,
 515                                      MEMTXATTRS_UNSPECIFIED);
 516         if (result != MEMTX_OK) {
 517             program_interrupt(env, PGM_OPERAND, 4);
 518             return 0;
 519         }
 520     } else if (pcias == 15) {
 521         if ((4 - (offset & 0x3)) < len) {
 522             program_interrupt(env, PGM_OPERAND, 4);
 523             return 0;
 524         }
 525         switch (len) {
 526         case 1:
 527             break;
 528         case 2:
 529             data = bswap16(data);
 530             break;
 531         case 4:
 532             data = bswap32(data);
 533             break;
 534         case 8:
 535             data = bswap64(data);
 536             break;
 537         default:
 538             program_interrupt(env, PGM_OPERAND, 4);
 539             return 0;
 540         }
 541
 542         pci_host_config_write_common(pbdev->pdev, offset,
 543                                      pci_config_size(pbdev->pdev),
 544                                      data, len);
 545     } else {
 546         DPRINTF("pcistg invalid space\n");
 547         setcc(cpu, ZPCI_PCI_LS_ERR);
 548         s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
 549         return 0;
 550     }
 551
 552     setcc(cpu, ZPCI_PCI_LS_OK);
 553     return 0;
 554 }
 555
 556 int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2)
 557 {
 558     CPUS390XState *env = &cpu->env;
 559     uint32_t fh;
 560     S390PCIBusDevice *pbdev;
 561     S390PCIIOMMU *iommu;
 562     hwaddr start, end;
 563     IOMMUTLBEntry entry;
 564     MemoryRegion *mr;
 565
 566     cpu_synchronize_state(CPU(cpu));
 567
 568     if (env->psw.mask & PSW_MASK_PSTATE) {
 569         program_interrupt(env, PGM_PRIVILEGED, 4);
 570         goto out;
 571     }
 572
 573     if (r2 & 0x1) {
 574         program_interrupt(env, PGM_SPECIFICATION, 4);
 575         goto out;
 576     }
 577
 578     fh = env->regs[r1] >> 32;
 579     start = env->regs[r2];
 580     end = start + env->regs[r2 + 1];
 581
 582     pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
 583     if (!pbdev) {
 584         DPRINTF("rpcit no pci dev\n");
 585         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 586         goto out;
 587     }
 588
 589     switch (pbdev->state) {
 590     case ZPCI_FS_RESERVED:
 591     case ZPCI_FS_STANDBY:
 592     case ZPCI_FS_DISABLED:
 593     case ZPCI_FS_PERMANENT_ERROR:
 594         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 595         return 0;
 596     case ZPCI_FS_ERROR:
 597         setcc(cpu, ZPCI_PCI_LS_ERR);
 598         s390_set_status_code(env, r1, ZPCI_MOD_ST_ERROR_RECOVER);
 599         return 0;
 600     default:
 601         break;
 602     }
 603
 604     iommu = pbdev->iommu;
 605     if (!iommu->g_iota) {
 606         pbdev->state = ZPCI_FS_ERROR;
 607         setcc(cpu, ZPCI_PCI_LS_ERR);
 608         s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES);
 609         s390_pci_generate_error_event(ERR_EVENT_INVALAS, pbdev->fh, pbdev->fid,
 610                                       start, 0);
 611         goto out;
 612     }
 613
 614     if (end < iommu->pba || start > iommu->pal) {
 615         pbdev->state = ZPCI_FS_ERROR;
 616         setcc(cpu, ZPCI_PCI_LS_ERR);
 617         s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES);
 618         s390_pci_generate_error_event(ERR_EVENT_OORANGE, pbdev->fh, pbdev->fid,
 619                                       start, 0);
 620         goto out;
 621     }
 622
 623     mr = &iommu->iommu_mr;
 624     while (start < end) {
 625         entry = mr->iommu_ops->translate(mr, start, 0);
 626
 627         if (!entry.translated_addr) {
 628             pbdev->state = ZPCI_FS_ERROR;
 629             setcc(cpu, ZPCI_PCI_LS_ERR);
 630             s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES);
 631             s390_pci_generate_error_event(ERR_EVENT_SERR, pbdev->fh, pbdev->fid,
 632                                           start, ERR_EVENT_Q_BIT);
 633             goto out;
 634         }
 635
 636         memory_region_notify_iommu(mr, entry);
 637         start += entry.addr_mask + 1;
 638     }
 639
 640     setcc(cpu, ZPCI_PCI_LS_OK);
 641 out:
 642     return 0;
 643 }
 644
 645 int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
 646                         uint8_t ar)
 647 {
 648     CPUS390XState *env = &cpu->env;
 649     S390PCIBusDevice *pbdev;
 650     MemoryRegion *mr;
 651     MemTxResult result;
 652     int i;
 653     uint32_t fh;
 654     uint8_t pcias;
 655     uint8_t len;
 656     uint8_t buffer[128];
 657
 658     if (env->psw.mask & PSW_MASK_PSTATE) {
 659         program_interrupt(env, PGM_PRIVILEGED, 6);
 660         return 0;
 661     }
 662
 663     fh = env->regs[r1] >> 32;
 664     pcias = (env->regs[r1] >> 16) & 0xf;
 665     len = env->regs[r1] & 0xff;
 666
 667     if (pcias > 5) {
 668         DPRINTF("pcistb invalid space\n");
 669         setcc(cpu, ZPCI_PCI_LS_ERR);
 670         s390_set_status_code(env, r1, ZPCI_PCI_ST_INVAL_AS);
 671         return 0;
 672     }
 673
 674     switch (len) {
 675     case 16:
 676     case 32:
 677     case 64:
 678     case 128:
 679         break;
 680     default:
 681         program_interrupt(env, PGM_SPECIFICATION, 6);
 682         return 0;
 683     }
 684
 685     pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
 686     if (!pbdev) {
 687         DPRINTF("pcistb no pci dev fh 0x%x\n", fh);
 688         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 689         return 0;
 690     }
 691
 692     switch (pbdev->state) {
 693     case ZPCI_FS_RESERVED:
 694     case ZPCI_FS_STANDBY:
 695     case ZPCI_FS_DISABLED:
 696     case ZPCI_FS_PERMANENT_ERROR:
 697         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 698         return 0;
 699     case ZPCI_FS_ERROR:
 700         setcc(cpu, ZPCI_PCI_LS_ERR);
 701         s390_set_status_code(env, r1, ZPCI_PCI_ST_BLOCKED);
 702         return 0;
 703     default:
 704         break;
 705     }
 706
 707     mr = pbdev->pdev->io_regions[pcias].memory;
 708     if (!memory_region_access_valid(mr, env->regs[r3], len, true)) {
 709         program_interrupt(env, PGM_OPERAND, 6);
 710         return 0;
 711     }
 712
 713     if (s390_cpu_virt_mem_read(cpu, gaddr, ar, buffer, len)) {
 714         return 0;
 715     }
 716
 717     for (i = 0; i < len / 8; i++) {
 718         result = memory_region_dispatch_write(mr, env->regs[r3] + i * 8,
 719                                      ldq_p(buffer + i * 8), 8,
 720                                      MEMTXATTRS_UNSPECIFIED);
 721         if (result != MEMTX_OK) {
 722             program_interrupt(env, PGM_OPERAND, 6);
 723             return 0;
 724         }
 725     }
 726
 727     setcc(cpu, ZPCI_PCI_LS_OK);
 728     return 0;
 729 }
 730
 731 static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib)
 732 {
 733     int ret, len;
 734
 735     ret = css_register_io_adapter(S390_PCIPT_ADAPTER,
 736                                   FIB_DATA_ISC(ldl_p(&fib.data)), true, false,
 737                                   &pbdev->routes.adapter.adapter_id);
 738     assert(ret == 0);
 739
 740     pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t));
 741     len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long);
 742     pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len);
 743
 744     ret = map_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
 745     if (ret) {
 746         goto out;
 747     }
 748
 749     ret = map_indicator(&pbdev->routes.adapter, pbdev->indicator);
 750     if (ret) {
 751         goto out;
 752     }
 753
 754     pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb);
 755     pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data));
 756     pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv);
 757     pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data));
 758     pbdev->isc = FIB_DATA_ISC(ldl_p(&fib.data));
 759     pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data));
 760     pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data));
 761
 762     DPRINTF("reg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
 763     return 0;
 764 out:
 765     release_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
 766     release_indicator(&pbdev->routes.adapter, pbdev->indicator);
 767     pbdev->summary_ind = NULL;
 768     pbdev->indicator = NULL;
 769     return ret;
 770 }
 771
 772 int pci_dereg_irqs(S390PCIBusDevice *pbdev)
 773 {
 774     release_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
 775     release_indicator(&pbdev->routes.adapter, pbdev->indicator);
 776
 777     pbdev->summary_ind = NULL;
 778     pbdev->indicator = NULL;
 779     pbdev->routes.adapter.summary_addr = 0;
 780     pbdev->routes.adapter.summary_offset = 0;
 781     pbdev->routes.adapter.ind_addr = 0;
 782     pbdev->routes.adapter.ind_offset = 0;
 783     pbdev->isc = 0;
 784     pbdev->noi = 0;
 785     pbdev->sum = 0;
 786
 787     DPRINTF("dereg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
 788     return 0;
 789 }
 790
 791 static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib)
 792 {
 793     uint64_t pba = ldq_p(&fib.pba);
 794     uint64_t pal = ldq_p(&fib.pal);
 795     uint64_t g_iota = ldq_p(&fib.iota);
 796     uint8_t dt = (g_iota >> 2) & 0x7;
 797     uint8_t t = (g_iota >> 11) & 0x1;
 798
 799     if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) {
 800         program_interrupt(env, PGM_OPERAND, 6);
 801         return -EINVAL;
 802     }
 803
 804     /* currently we only support designation type 1 with translation */
 805     if (!(dt == ZPCI_IOTA_RTTO && t)) {
 806         error_report("unsupported ioat dt %d t %d", dt, t);
 807         program_interrupt(env, PGM_OPERAND, 6);
 808         return -EINVAL;
 809     }
 810
 811     iommu->pba = pba;
 812     iommu->pal = pal;
 813     iommu->g_iota = g_iota;
 814
 815     s390_pci_iommu_enable(iommu);
 816
 817     return 0;
 818 }
 819
 820 void pci_dereg_ioat(S390PCIIOMMU *iommu)
 821 {
 822     s390_pci_iommu_disable(iommu);
 823     iommu->pba = 0;
 824     iommu->pal = 0;
 825     iommu->g_iota = 0;
 826 }
 827
 828 int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar)
 829 {
 830     CPUS390XState *env = &cpu->env;
 831     uint8_t oc, dmaas;
 832     uint32_t fh;
 833     ZpciFib fib;
 834     S390PCIBusDevice *pbdev;
 835     uint64_t cc = ZPCI_PCI_LS_OK;
 836
 837     if (env->psw.mask & PSW_MASK_PSTATE) {
 838         program_interrupt(env, PGM_PRIVILEGED, 6);
 839         return 0;
 840     }
 841
 842     oc = env->regs[r1] & 0xff;
 843     dmaas = (env->regs[r1] >> 16) & 0xff;
 844     fh = env->regs[r1] >> 32;
 845
 846     if (fiba & 0x7) {
 847         program_interrupt(env, PGM_SPECIFICATION, 6);
 848         return 0;
 849     }
 850
 851     pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
 852     if (!pbdev) {
 853         DPRINTF("mpcifc no pci dev fh 0x%x\n", fh);
 854         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 855         return 0;
 856     }
 857
 858     switch (pbdev->state) {
 859     case ZPCI_FS_RESERVED:
 860     case ZPCI_FS_STANDBY:
 861     case ZPCI_FS_DISABLED:
 862     case ZPCI_FS_PERMANENT_ERROR:
 863         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 864         return 0;
 865     default:
 866         break;
 867     }
 868
 869     if (s390_cpu_virt_mem_read(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {
 870         return 0;
 871     }
 872
 873     if (fib.fmt != 0) {
 874         program_interrupt(env, PGM_OPERAND, 6);
 875         return 0;
 876     }
 877
 878     switch (oc) {
 879     case ZPCI_MOD_FC_REG_INT:
 880         if (pbdev->summary_ind) {
 881             cc = ZPCI_PCI_LS_ERR;
 882             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
 883         } else if (reg_irqs(env, pbdev, fib)) {
 884             cc = ZPCI_PCI_LS_ERR;
 885             s390_set_status_code(env, r1, ZPCI_MOD_ST_RES_NOT_AVAIL);
 886         }
 887         break;
 888     case ZPCI_MOD_FC_DEREG_INT:
 889         if (!pbdev->summary_ind) {
 890             cc = ZPCI_PCI_LS_ERR;
 891             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
 892         } else {
 893             pci_dereg_irqs(pbdev);
 894         }
 895         break;
 896     case ZPCI_MOD_FC_REG_IOAT:
 897         if (dmaas != 0) {
 898             cc = ZPCI_PCI_LS_ERR;
 899             s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
 900         } else if (pbdev->iommu->enabled) {
 901             cc = ZPCI_PCI_LS_ERR;
 902             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
 903         } else if (reg_ioat(env, pbdev->iommu, fib)) {
 904             cc = ZPCI_PCI_LS_ERR;
 905             s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES);
 906         }
 907         break;
 908     case ZPCI_MOD_FC_DEREG_IOAT:
 909         if (dmaas != 0) {
 910             cc = ZPCI_PCI_LS_ERR;
 911             s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
 912         } else if (!pbdev->iommu->enabled) {
 913             cc = ZPCI_PCI_LS_ERR;
 914             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
 915         } else {
 916             pci_dereg_ioat(pbdev->iommu);
 917         }
 918         break;
 919     case ZPCI_MOD_FC_REREG_IOAT:
 920         if (dmaas != 0) {
 921             cc = ZPCI_PCI_LS_ERR;
 922             s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
 923         } else if (!pbdev->iommu->enabled) {
 924             cc = ZPCI_PCI_LS_ERR;
 925             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
 926         } else {
 927             pci_dereg_ioat(pbdev->iommu);
 928             if (reg_ioat(env, pbdev->iommu, fib)) {
 929                 cc = ZPCI_PCI_LS_ERR;
 930                 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES);
 931             }
 932         }
 933         break;
 934     case ZPCI_MOD_FC_RESET_ERROR:
 935         switch (pbdev->state) {
 936         case ZPCI_FS_BLOCKED:
 937         case ZPCI_FS_ERROR:
 938             pbdev->state = ZPCI_FS_ENABLED;
 939             break;
 940         default:
 941             cc = ZPCI_PCI_LS_ERR;
 942             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
 943         }
 944         break;
 945     case ZPCI_MOD_FC_RESET_BLOCK:
 946         switch (pbdev->state) {
 947         case ZPCI_FS_ERROR:
 948             pbdev->state = ZPCI_FS_BLOCKED;
 949             break;
 950         default:
 951             cc = ZPCI_PCI_LS_ERR;
 952             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
 953         }
 954         break;
 955     case ZPCI_MOD_FC_SET_MEASURE:
 956         pbdev->fmb_addr = ldq_p(&fib.fmb_addr);
 957         break;
 958     default:
 959         program_interrupt(&cpu->env, PGM_OPERAND, 6);
 960         cc = ZPCI_PCI_LS_ERR;
 961     }
 962
 963     setcc(cpu, cc);
 964     return 0;
 965 }
 966
 967 int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar)
 968 {
 969     CPUS390XState *env = &cpu->env;
 970     uint8_t dmaas;
 971     uint32_t fh;
 972     ZpciFib fib;
 973     S390PCIBusDevice *pbdev;
 974     uint32_t data;
 975     uint64_t cc = ZPCI_PCI_LS_OK;
 976
 977     if (env->psw.mask & PSW_MASK_PSTATE) {
 978         program_interrupt(env, PGM_PRIVILEGED, 6);
 979         return 0;
 980     }
 981
 982     fh = env->regs[r1] >> 32;
 983     dmaas = (env->regs[r1] >> 16) & 0xff;
 984
 985     if (dmaas) {
 986         setcc(cpu, ZPCI_PCI_LS_ERR);
 987         s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_INVAL_DMAAS);
 988         return 0;
 989     }
 990
 991     if (fiba & 0x7) {
 992         program_interrupt(env, PGM_SPECIFICATION, 6);
 993         return 0;
 994     }
 995
 996     pbdev = s390_pci_find_dev_by_idx(s390_get_phb(), fh & FH_MASK_INDEX);
 997     if (!pbdev) {
 998         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 999         return 0;
1000     }
1001
1002     memset(&fib, 0, sizeof(fib));
1003
1004     switch (pbdev->state) {
1005     case ZPCI_FS_RESERVED:
1006     case ZPCI_FS_STANDBY:
1007         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1008         return 0;
1009     case ZPCI_FS_DISABLED:
1010         if (fh & FH_MASK_ENABLE) {
1011             setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1012             return 0;
1013         }
1014         goto out;
1015     /* BLOCKED bit is set to one coincident with the setting of ERROR bit.
1016      * FH Enabled bit is set to one in states of ENABLED, BLOCKED or ERROR. */
1017     case ZPCI_FS_ERROR:
1018         fib.fc |= 0x20;
1019     case ZPCI_FS_BLOCKED:
1020         fib.fc |= 0x40;
1021     case ZPCI_FS_ENABLED:
1022         fib.fc |= 0x80;
1023         if (pbdev->iommu->enabled) {
1024             fib.fc |= 0x10;
1025         }
1026         if (!(fh & FH_MASK_ENABLE)) {
1027             env->regs[r1] |= 1ULL << 63;
1028         }
1029         break;
1030     case ZPCI_FS_PERMANENT_ERROR:
1031         setcc(cpu, ZPCI_PCI_LS_ERR);
1032         s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_PERM_ERROR);
1033         return 0;
1034     }
1035
1036     stq_p(&fib.pba, pbdev->iommu->pba);
1037     stq_p(&fib.pal, pbdev->iommu->pal);
1038     stq_p(&fib.iota, pbdev->iommu->g_iota);
1039     stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr);
1040     stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr);
1041     stq_p(&fib.fmb_addr, pbdev->fmb_addr);
1042
1043     data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) |
1044            ((uint32_t)pbdev->routes.adapter.ind_offset << 8) |
1045            ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset;
1046     stl_p(&fib.data, data);
1047
1048 out:
1049     if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {
1050         return 0;
1051     }
1052
1053     setcc(cpu, cc);
1054     return 0;
1055 }