2 * QEMU PowerPC sPAPR XIVE interrupt controller model
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/module.h"
13 #include "qapi/error.h"
14 #include "qemu/error-report.h"
15 #include "target/ppc/cpu.h"
16 #include "sysemu/cpus.h"
17 #include "sysemu/reset.h"
18 #include "migration/vmstate.h"
19 #include "monitor/monitor.h"
20 #include "hw/ppc/fdt.h"
21 #include "hw/ppc/spapr.h"
22 #include "hw/ppc/spapr_cpu_core.h"
23 #include "hw/ppc/spapr_xive.h"
24 #include "hw/ppc/xive.h"
25 #include "hw/ppc/xive_regs.h"
26 #include "hw/qdev-properties.h"
29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we
30 * use for the ESB pages and the TIMA pages
32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull
33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull
36 * The allocation of VP blocks is a complex operation in OPAL and the
37 * VP identifiers have a relation with the number of HW chips, the
38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE
39 * controller model does not have the same constraints and can use a
40 * simple mapping scheme of the CPU vcpu_id
42 * These identifiers are never returned to the OS.
45 #define SPAPR_XIVE_NVT_BASE 0x400
48 * sPAPR NVT and END indexing helpers
50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk
, uint32_t nvt_idx
)
52 return nvt_idx
- SPAPR_XIVE_NVT_BASE
;
55 static void spapr_xive_cpu_to_nvt(PowerPCCPU
*cpu
,
56 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
61 *out_nvt_blk
= SPAPR_XIVE_BLOCK_ID
;
65 *out_nvt_idx
= SPAPR_XIVE_NVT_BASE
+ cpu
->vcpu_id
;
69 static int spapr_xive_target_to_nvt(uint32_t target
,
70 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
72 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
78 spapr_xive_cpu_to_nvt(cpu
, out_nvt_blk
, out_nvt_idx
);
83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8
86 int spapr_xive_end_to_target(uint8_t end_blk
, uint32_t end_idx
,
87 uint32_t *out_server
, uint8_t *out_prio
)
90 assert(end_blk
== SPAPR_XIVE_BLOCK_ID
);
93 *out_server
= end_idx
>> 3;
97 *out_prio
= end_idx
& 0x7;
102 static void spapr_xive_cpu_to_end(PowerPCCPU
*cpu
, uint8_t prio
,
103 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
108 *out_end_blk
= SPAPR_XIVE_BLOCK_ID
;
112 *out_end_idx
= (cpu
->vcpu_id
<< 3) + prio
;
116 static int spapr_xive_target_to_end(uint32_t target
, uint8_t prio
,
117 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
119 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
125 spapr_xive_cpu_to_end(cpu
, prio
, out_end_blk
, out_end_idx
);
130 * On sPAPR machines, use a simplified output for the XIVE END
131 * structure dumping only the information related to the OS EQ.
133 static void spapr_xive_end_pic_print_info(SpaprXive
*xive
, XiveEND
*end
,
136 uint64_t qaddr_base
= xive_end_qaddr(end
);
137 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
138 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
139 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
140 uint32_t qentries
= 1 << (qsize
+ 10);
141 uint32_t nvt
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
142 uint8_t priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
144 monitor_printf(mon
, "%3d/%d % 6d/%5d @%"PRIx64
" ^%d",
145 spapr_xive_nvt_to_target(0, nvt
),
146 priority
, qindex
, qentries
, qaddr_base
, qgen
);
148 xive_end_queue_pic_print_info(end
, 6, mon
);
151 void spapr_xive_pic_print_info(SpaprXive
*xive
, Monitor
*mon
)
153 XiveSource
*xsrc
= &xive
->source
;
156 if (kvm_irqchip_in_kernel()) {
157 Error
*local_err
= NULL
;
159 kvmppc_xive_synchronize_state(xive
, &local_err
);
161 error_report_err(local_err
);
166 monitor_printf(mon
, " LISN PQ EISN CPU/PRIO EQ\n");
168 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
169 uint8_t pq
= xive_source_esb_get(xsrc
, i
);
170 XiveEAS
*eas
= &xive
->eat
[i
];
172 if (!xive_eas_is_valid(eas
)) {
176 monitor_printf(mon
, " %08x %s %c%c%c %s %08x ", i
,
177 xive_source_irq_is_lsi(xsrc
, i
) ? "LSI" : "MSI",
178 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
179 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
180 xsrc
->status
[i
] & XIVE_STATUS_ASSERTED
? 'A' : ' ',
181 xive_eas_is_masked(eas
) ? "M" : " ",
182 (int) xive_get_field64(EAS_END_DATA
, eas
->w
));
184 if (!xive_eas_is_masked(eas
)) {
185 uint32_t end_idx
= xive_get_field64(EAS_END_INDEX
, eas
->w
);
188 assert(end_idx
< xive
->nr_ends
);
189 end
= &xive
->endt
[end_idx
];
191 if (xive_end_is_valid(end
)) {
192 spapr_xive_end_pic_print_info(xive
, end
, mon
);
195 monitor_printf(mon
, "\n");
199 void spapr_xive_mmio_set_enabled(SpaprXive
*xive
, bool enable
)
201 memory_region_set_enabled(&xive
->source
.esb_mmio
, enable
);
202 memory_region_set_enabled(&xive
->tm_mmio
, enable
);
204 /* Disable the END ESBs until a guest OS makes use of them */
205 memory_region_set_enabled(&xive
->end_source
.esb_mmio
, false);
209 * When a Virtual Processor is scheduled to run on a HW thread, the
210 * hypervisor pushes its identifier in the OS CAM line. Emulate the
211 * same behavior under QEMU.
213 void spapr_xive_set_tctx_os_cam(XiveTCTX
*tctx
)
219 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx
->cs
), &nvt_blk
, &nvt_idx
);
221 nvt_cam
= cpu_to_be32(TM_QW1W2_VO
| xive_nvt_cam_line(nvt_blk
, nvt_idx
));
222 memcpy(&tctx
->regs
[TM_QW1_OS
+ TM_WORD2
], &nvt_cam
, 4);
225 static void spapr_xive_end_reset(XiveEND
*end
)
227 memset(end
, 0, sizeof(*end
));
229 /* switch off the escalation and notification ESBs */
230 end
->w1
= cpu_to_be32(END_W1_ESe_Q
| END_W1_ESn_Q
);
233 static void spapr_xive_reset(void *dev
)
235 SpaprXive
*xive
= SPAPR_XIVE(dev
);
239 * The XiveSource has its own reset handler, which mask off all
243 /* Mask all valid EASs in the IRQ number space. */
244 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
245 XiveEAS
*eas
= &xive
->eat
[i
];
246 if (xive_eas_is_valid(eas
)) {
247 eas
->w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
254 for (i
= 0; i
< xive
->nr_ends
; i
++) {
255 spapr_xive_end_reset(&xive
->endt
[i
]);
259 static void spapr_xive_instance_init(Object
*obj
)
261 SpaprXive
*xive
= SPAPR_XIVE(obj
);
263 object_initialize_child(obj
, "source", &xive
->source
, sizeof(xive
->source
),
264 TYPE_XIVE_SOURCE
, &error_abort
, NULL
);
266 object_initialize_child(obj
, "end_source", &xive
->end_source
,
267 sizeof(xive
->end_source
), TYPE_XIVE_END_SOURCE
,
270 /* Not connected to the KVM XIVE device */
274 static void spapr_xive_realize(DeviceState
*dev
, Error
**errp
)
276 SpaprXive
*xive
= SPAPR_XIVE(dev
);
277 XiveSource
*xsrc
= &xive
->source
;
278 XiveENDSource
*end_xsrc
= &xive
->end_source
;
279 Error
*local_err
= NULL
;
281 if (!xive
->nr_irqs
) {
282 error_setg(errp
, "Number of interrupt needs to be greater 0");
286 if (!xive
->nr_ends
) {
287 error_setg(errp
, "Number of interrupt needs to be greater 0");
292 * Initialize the internal sources, for IPIs and virtual devices.
294 object_property_set_int(OBJECT(xsrc
), xive
->nr_irqs
, "nr-irqs",
296 object_property_add_const_link(OBJECT(xsrc
), "xive", OBJECT(xive
),
298 object_property_set_bool(OBJECT(xsrc
), true, "realized", &local_err
);
300 error_propagate(errp
, local_err
);
303 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xsrc
->esb_mmio
);
306 * Initialize the END ESB source
308 object_property_set_int(OBJECT(end_xsrc
), xive
->nr_irqs
, "nr-ends",
310 object_property_add_const_link(OBJECT(end_xsrc
), "xive", OBJECT(xive
),
312 object_property_set_bool(OBJECT(end_xsrc
), true, "realized", &local_err
);
314 error_propagate(errp
, local_err
);
317 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &end_xsrc
->esb_mmio
);
319 /* Set the mapping address of the END ESB pages after the source ESBs */
320 xive
->end_base
= xive
->vc_base
+ (1ull << xsrc
->esb_shift
) * xsrc
->nr_irqs
;
323 * Allocate the routing tables
325 xive
->eat
= g_new0(XiveEAS
, xive
->nr_irqs
);
326 xive
->endt
= g_new0(XiveEND
, xive
->nr_ends
);
328 xive
->nodename
= g_strdup_printf("interrupt-controller@%" PRIx64
,
329 xive
->tm_base
+ XIVE_TM_USER_PAGE
* (1 << TM_SHIFT
));
331 qemu_register_reset(spapr_xive_reset
, dev
);
333 /* TIMA initialization */
334 memory_region_init_io(&xive
->tm_mmio
, OBJECT(xive
), &xive_tm_ops
, xive
,
335 "xive.tima", 4ull << TM_SHIFT
);
336 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xive
->tm_mmio
);
339 * Map all regions. These will be enabled or disabled at reset and
340 * can also be overridden by KVM memory regions if active
342 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 0, xive
->vc_base
);
343 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 1, xive
->end_base
);
344 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 2, xive
->tm_base
);
347 static int spapr_xive_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
,
348 uint32_t eas_idx
, XiveEAS
*eas
)
350 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
352 if (eas_idx
>= xive
->nr_irqs
) {
356 *eas
= xive
->eat
[eas_idx
];
360 static int spapr_xive_get_end(XiveRouter
*xrtr
,
361 uint8_t end_blk
, uint32_t end_idx
, XiveEND
*end
)
363 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
365 if (end_idx
>= xive
->nr_ends
) {
369 memcpy(end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
373 static int spapr_xive_write_end(XiveRouter
*xrtr
, uint8_t end_blk
,
374 uint32_t end_idx
, XiveEND
*end
,
377 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
379 if (end_idx
>= xive
->nr_ends
) {
383 memcpy(&xive
->endt
[end_idx
], end
, sizeof(XiveEND
));
387 static int spapr_xive_get_nvt(XiveRouter
*xrtr
,
388 uint8_t nvt_blk
, uint32_t nvt_idx
, XiveNVT
*nvt
)
390 uint32_t vcpu_id
= spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
391 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
394 /* TODO: should we assert() if we can find a NVT ? */
399 * sPAPR does not maintain a NVT table. Return that the NVT is
400 * valid if we have found a matching CPU
402 nvt
->w0
= cpu_to_be32(NVT_W0_VALID
);
406 static int spapr_xive_write_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
,
407 uint32_t nvt_idx
, XiveNVT
*nvt
,
411 * We don't need to write back to the NVTs because the sPAPR
412 * machine should never hit a non-scheduled NVT. It should never
415 g_assert_not_reached();
418 static XiveTCTX
*spapr_xive_get_tctx(XiveRouter
*xrtr
, CPUState
*cs
)
420 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
422 return spapr_cpu_state(cpu
)->tctx
;
425 static const VMStateDescription vmstate_spapr_xive_end
= {
426 .name
= TYPE_SPAPR_XIVE
"/end",
428 .minimum_version_id
= 1,
429 .fields
= (VMStateField
[]) {
430 VMSTATE_UINT32(w0
, XiveEND
),
431 VMSTATE_UINT32(w1
, XiveEND
),
432 VMSTATE_UINT32(w2
, XiveEND
),
433 VMSTATE_UINT32(w3
, XiveEND
),
434 VMSTATE_UINT32(w4
, XiveEND
),
435 VMSTATE_UINT32(w5
, XiveEND
),
436 VMSTATE_UINT32(w6
, XiveEND
),
437 VMSTATE_UINT32(w7
, XiveEND
),
438 VMSTATE_END_OF_LIST()
442 static const VMStateDescription vmstate_spapr_xive_eas
= {
443 .name
= TYPE_SPAPR_XIVE
"/eas",
445 .minimum_version_id
= 1,
446 .fields
= (VMStateField
[]) {
447 VMSTATE_UINT64(w
, XiveEAS
),
448 VMSTATE_END_OF_LIST()
452 static int vmstate_spapr_xive_pre_save(void *opaque
)
454 if (kvm_irqchip_in_kernel()) {
455 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque
));
462 * Called by the sPAPR IRQ backend 'post_load' method at the machine
465 int spapr_xive_post_load(SpaprXive
*xive
, int version_id
)
467 if (kvm_irqchip_in_kernel()) {
468 return kvmppc_xive_post_load(xive
, version_id
);
474 static const VMStateDescription vmstate_spapr_xive
= {
475 .name
= TYPE_SPAPR_XIVE
,
477 .minimum_version_id
= 1,
478 .pre_save
= vmstate_spapr_xive_pre_save
,
479 .post_load
= NULL
, /* handled at the machine level */
480 .fields
= (VMStateField
[]) {
481 VMSTATE_UINT32_EQUAL(nr_irqs
, SpaprXive
, NULL
),
482 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat
, SpaprXive
, nr_irqs
,
483 vmstate_spapr_xive_eas
, XiveEAS
),
484 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt
, SpaprXive
, nr_ends
,
485 vmstate_spapr_xive_end
, XiveEND
),
486 VMSTATE_END_OF_LIST()
490 static Property spapr_xive_properties
[] = {
491 DEFINE_PROP_UINT32("nr-irqs", SpaprXive
, nr_irqs
, 0),
492 DEFINE_PROP_UINT32("nr-ends", SpaprXive
, nr_ends
, 0),
493 DEFINE_PROP_UINT64("vc-base", SpaprXive
, vc_base
, SPAPR_XIVE_VC_BASE
),
494 DEFINE_PROP_UINT64("tm-base", SpaprXive
, tm_base
, SPAPR_XIVE_TM_BASE
),
495 DEFINE_PROP_END_OF_LIST(),
498 static int spapr_xive_cpu_intc_create(SpaprInterruptController
*intc
,
499 PowerPCCPU
*cpu
, Error
**errp
)
501 SpaprXive
*xive
= SPAPR_XIVE(intc
);
503 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
505 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_ROUTER(xive
), errp
);
510 spapr_cpu
->tctx
= XIVE_TCTX(obj
);
513 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
514 * don't beneficiate from the reset of the XIVE IRQ backend
516 spapr_xive_set_tctx_os_cam(spapr_cpu
->tctx
);
520 static void spapr_xive_class_init(ObjectClass
*klass
, void *data
)
522 DeviceClass
*dc
= DEVICE_CLASS(klass
);
523 XiveRouterClass
*xrc
= XIVE_ROUTER_CLASS(klass
);
524 SpaprInterruptControllerClass
*sicc
= SPAPR_INTC_CLASS(klass
);
526 dc
->desc
= "sPAPR XIVE Interrupt Controller";
527 dc
->props
= spapr_xive_properties
;
528 dc
->realize
= spapr_xive_realize
;
529 dc
->vmsd
= &vmstate_spapr_xive
;
531 xrc
->get_eas
= spapr_xive_get_eas
;
532 xrc
->get_end
= spapr_xive_get_end
;
533 xrc
->write_end
= spapr_xive_write_end
;
534 xrc
->get_nvt
= spapr_xive_get_nvt
;
535 xrc
->write_nvt
= spapr_xive_write_nvt
;
536 xrc
->get_tctx
= spapr_xive_get_tctx
;
538 sicc
->cpu_intc_create
= spapr_xive_cpu_intc_create
;
541 static const TypeInfo spapr_xive_info
= {
542 .name
= TYPE_SPAPR_XIVE
,
543 .parent
= TYPE_XIVE_ROUTER
,
544 .instance_init
= spapr_xive_instance_init
,
545 .instance_size
= sizeof(SpaprXive
),
546 .class_init
= spapr_xive_class_init
,
547 .interfaces
= (InterfaceInfo
[]) {
553 static void spapr_xive_register_types(void)
555 type_register_static(&spapr_xive_info
);
558 type_init(spapr_xive_register_types
)
560 int spapr_xive_irq_claim(SpaprXive
*xive
, int lisn
, bool lsi
, Error
**errp
)
562 XiveSource
*xsrc
= &xive
->source
;
564 assert(lisn
< xive
->nr_irqs
);
566 if (xive_eas_is_valid(&xive
->eat
[lisn
])) {
567 error_setg(errp
, "IRQ %d is not free", lisn
);
572 * Set default values when allocating an IRQ number
574 xive
->eat
[lisn
].w
|= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
576 xive_source_irq_set_lsi(xsrc
, lisn
);
579 if (kvm_irqchip_in_kernel()) {
580 return kvmppc_xive_source_reset_one(xsrc
, lisn
, errp
);
586 void spapr_xive_irq_free(SpaprXive
*xive
, int lisn
)
588 assert(lisn
< xive
->nr_irqs
);
590 xive
->eat
[lisn
].w
&= cpu_to_be64(~EAS_VALID
);
596 * The terminology used by the XIVE hcalls is the following :
599 * EQ Event Queue assigned by OS to receive event data
600 * ESB page for source interrupt management
601 * LISN Logical Interrupt Source Number identifying a source in the
603 * EISN Effective Interrupt Source Number used by guest OS to
604 * identify source in the guest
606 * The EAS, END, NVT structures are not exposed.
610 * Linux hosts under OPAL reserve priority 7 for their own escalation
611 * interrupts (DD2.X POWER9). So we only allow the guest to use
614 static bool spapr_xive_priority_is_reserved(uint8_t priority
)
619 case 7: /* OPAL escalation queue */
626 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical
627 * real address of the MMIO page through which the Event State Buffer
628 * entry associated with the value of the "lisn" parameter is managed.
634 * - R5: "lisn" is per "interrupts", "interrupt-map", or
635 * "ibm,xive-lisn-ranges" properties, or as returned by the
636 * ibm,query-interrupt-source-number RTAS call, or as returned
637 * by the H_ALLOCATE_VAS_WINDOW hcall
641 * Bits 0-59: Reserved
642 * Bit 60: H_INT_ESB must be used for Event State Buffer
644 * Bit 61: 1 == LSI 0 == MSI
645 * Bit 62: the full function page supports trigger
646 * Bit 63: Store EOI Supported
647 * - R5: Logical Real address of full function Event State Buffer
648 * management page, -1 if H_INT_ESB hcall flag is set to 1.
649 * - R6: Logical Real Address of trigger only Event State Buffer
650 * management page or -1.
651 * - R7: Power of 2 page size for the ESB management pages returned in
655 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */
656 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */
657 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management
659 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */
661 static target_ulong
h_int_get_source_info(PowerPCCPU
*cpu
,
662 SpaprMachineState
*spapr
,
666 SpaprXive
*xive
= spapr
->xive
;
667 XiveSource
*xsrc
= &xive
->source
;
668 target_ulong flags
= args
[0];
669 target_ulong lisn
= args
[1];
671 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
679 if (lisn
>= xive
->nr_irqs
) {
680 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
685 if (!xive_eas_is_valid(&xive
->eat
[lisn
])) {
686 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
692 * All sources are emulated under the main XIVE object and share
693 * the same characteristics.
696 if (!xive_source_esb_has_2page(xsrc
)) {
697 args
[0] |= SPAPR_XIVE_SRC_TRIGGER
;
699 if (xsrc
->esb_flags
& XIVE_SRC_STORE_EOI
) {
700 args
[0] |= SPAPR_XIVE_SRC_STORE_EOI
;
704 * Force the use of the H_INT_ESB hcall in case of an LSI
705 * interrupt. This is necessary under KVM to re-trigger the
706 * interrupt if the level is still asserted
708 if (xive_source_irq_is_lsi(xsrc
, lisn
)) {
709 args
[0] |= SPAPR_XIVE_SRC_H_INT_ESB
| SPAPR_XIVE_SRC_LSI
;
712 if (!(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
713 args
[1] = xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
);
718 if (xive_source_esb_has_2page(xsrc
) &&
719 !(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
720 args
[2] = xive
->vc_base
+ xive_source_esb_page(xsrc
, lisn
);
725 if (xive_source_esb_has_2page(xsrc
)) {
726 args
[3] = xsrc
->esb_shift
- 1;
728 args
[3] = xsrc
->esb_shift
;
735 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical
736 * Interrupt Source to a target. The Logical Interrupt Source is
737 * designated with the "lisn" parameter and the target is designated
738 * with the "target" and "priority" parameters. Upon return from the
739 * hcall(), no additional interrupts will be directed to the old EQ.
744 * Bits 0-61: Reserved
745 * Bit 62: set the "eisn" in the EAS
746 * Bit 63: masks the interrupt source in the hardware interrupt
747 * control structure. An interrupt masked by this mechanism will
748 * be dropped, but it's source state bits will still be
749 * set. There is no race-free way of unmasking and restoring the
750 * source. Thus this should only be used in interrupts that are
751 * also masked at the source, and only in cases where the
752 * interrupt is not meant to be used for a large amount of time
753 * because no valid target exists for it for example
754 * - R5: "lisn" is per "interrupts", "interrupt-map", or
755 * "ibm,xive-lisn-ranges" properties, or as returned by the
756 * ibm,query-interrupt-source-number RTAS call, or as returned by
757 * the H_ALLOCATE_VAS_WINDOW hcall
758 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or
759 * "ibm,ppc-interrupt-gserver#s"
760 * - R7: "priority" is a valid priority not in
761 * "ibm,plat-res-int-priorities"
762 * - R8: "eisn" is the guest EISN associated with the "lisn"
768 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62)
769 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63)
771 static target_ulong
h_int_set_source_config(PowerPCCPU
*cpu
,
772 SpaprMachineState
*spapr
,
776 SpaprXive
*xive
= spapr
->xive
;
777 XiveEAS eas
, new_eas
;
778 target_ulong flags
= args
[0];
779 target_ulong lisn
= args
[1];
780 target_ulong target
= args
[2];
781 target_ulong priority
= args
[3];
782 target_ulong eisn
= args
[4];
786 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
790 if (flags
& ~(SPAPR_XIVE_SRC_SET_EISN
| SPAPR_XIVE_SRC_MASK
)) {
794 if (lisn
>= xive
->nr_irqs
) {
795 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
800 eas
= xive
->eat
[lisn
];
801 if (!xive_eas_is_valid(&eas
)) {
802 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
807 /* priority 0xff is used to reset the EAS */
808 if (priority
== 0xff) {
809 new_eas
.w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
813 if (flags
& SPAPR_XIVE_SRC_MASK
) {
814 new_eas
.w
= eas
.w
| cpu_to_be64(EAS_MASKED
);
816 new_eas
.w
= eas
.w
& cpu_to_be64(~EAS_MASKED
);
819 if (spapr_xive_priority_is_reserved(priority
)) {
820 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
821 " is reserved\n", priority
);
826 * Validate that "target" is part of the list of threads allocated
827 * to the partition. For that, find the END corresponding to the
830 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
834 new_eas
.w
= xive_set_field64(EAS_END_BLOCK
, new_eas
.w
, end_blk
);
835 new_eas
.w
= xive_set_field64(EAS_END_INDEX
, new_eas
.w
, end_idx
);
837 if (flags
& SPAPR_XIVE_SRC_SET_EISN
) {
838 new_eas
.w
= xive_set_field64(EAS_END_DATA
, new_eas
.w
, eisn
);
841 if (kvm_irqchip_in_kernel()) {
842 Error
*local_err
= NULL
;
844 kvmppc_xive_set_source_config(xive
, lisn
, &new_eas
, &local_err
);
846 error_report_err(local_err
);
852 xive
->eat
[lisn
] = new_eas
;
857 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which
858 * target/priority pair is assigned to the specified Logical Interrupt
865 * - R5: "lisn" is per "interrupts", "interrupt-map", or
866 * "ibm,xive-lisn-ranges" properties, or as returned by the
867 * ibm,query-interrupt-source-number RTAS call, or as
868 * returned by the H_ALLOCATE_VAS_WINDOW hcall
871 * - R4: Target to which the specified Logical Interrupt Source is
873 * - R5: Priority to which the specified Logical Interrupt Source is
875 * - R6: EISN for the specified Logical Interrupt Source (this will be
876 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG)
878 static target_ulong
h_int_get_source_config(PowerPCCPU
*cpu
,
879 SpaprMachineState
*spapr
,
883 SpaprXive
*xive
= spapr
->xive
;
884 target_ulong flags
= args
[0];
885 target_ulong lisn
= args
[1];
889 uint32_t end_idx
, nvt_idx
;
891 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
899 if (lisn
>= xive
->nr_irqs
) {
900 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
905 eas
= xive
->eat
[lisn
];
906 if (!xive_eas_is_valid(&eas
)) {
907 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
912 /* EAS_END_BLOCK is unused on sPAPR */
913 end_idx
= xive_get_field64(EAS_END_INDEX
, eas
.w
);
915 assert(end_idx
< xive
->nr_ends
);
916 end
= &xive
->endt
[end_idx
];
918 nvt_blk
= xive_get_field32(END_W6_NVT_BLOCK
, end
->w6
);
919 nvt_idx
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
920 args
[0] = spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
922 if (xive_eas_is_masked(&eas
)) {
925 args
[1] = xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
928 args
[2] = xive_get_field64(EAS_END_DATA
, eas
.w
);
934 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real
935 * address of the notification management page associated with the
936 * specified target and priority.
942 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
943 * "ibm,ppc-interrupt-gserver#s"
944 * - R6: "priority" is a valid priority not in
945 * "ibm,plat-res-int-priorities"
948 * - R4: Logical real address of notification page
949 * - R5: Power of 2 page size of the notification page
951 static target_ulong
h_int_get_queue_info(PowerPCCPU
*cpu
,
952 SpaprMachineState
*spapr
,
956 SpaprXive
*xive
= spapr
->xive
;
957 XiveENDSource
*end_xsrc
= &xive
->end_source
;
958 target_ulong flags
= args
[0];
959 target_ulong target
= args
[1];
960 target_ulong priority
= args
[2];
965 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
974 * H_STATE should be returned if a H_INT_RESET is in progress.
975 * This is not needed when running the emulation under QEMU
978 if (spapr_xive_priority_is_reserved(priority
)) {
979 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
980 " is reserved\n", priority
);
985 * Validate that "target" is part of the list of threads allocated
986 * to the partition. For that, find the END corresponding to the
989 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
993 assert(end_idx
< xive
->nr_ends
);
994 end
= &xive
->endt
[end_idx
];
996 args
[0] = xive
->end_base
+ (1ull << (end_xsrc
->esb_shift
+ 1)) * end_idx
;
997 if (xive_end_is_enqueue(end
)) {
998 args
[1] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
1007 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for
1008 * a given "target" and "priority". It is also used to set the
1009 * notification config associated with the EQ. An EQ size of 0 is
1010 * used to reset the EQ config for a given target and priority. If
1011 * resetting the EQ config, the END associated with the given "target"
1012 * and "priority" will be changed to disable queueing.
1014 * Upon return from the hcall(), no additional interrupts will be
1015 * directed to the old EQ (if one was set). The old EQ (if one was
1016 * set) should be investigated for interrupts that occurred prior to
1017 * or during the hcall().
1022 * Bits 0-62: Reserved
1023 * Bit 63: Unconditional Notify (n) per the XIVE spec
1024 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1025 * "ibm,ppc-interrupt-gserver#s"
1026 * - R6: "priority" is a valid priority not in
1027 * "ibm,plat-res-int-priorities"
1028 * - R7: "eventQueue": The logical real address of the start of the EQ
1029 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes"
1035 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63)
1037 static target_ulong
h_int_set_queue_config(PowerPCCPU
*cpu
,
1038 SpaprMachineState
*spapr
,
1039 target_ulong opcode
,
1042 SpaprXive
*xive
= spapr
->xive
;
1043 target_ulong flags
= args
[0];
1044 target_ulong target
= args
[1];
1045 target_ulong priority
= args
[2];
1046 target_ulong qpage
= args
[3];
1047 target_ulong qsize
= args
[4];
1049 uint8_t end_blk
, nvt_blk
;
1050 uint32_t end_idx
, nvt_idx
;
1052 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1056 if (flags
& ~SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
1061 * H_STATE should be returned if a H_INT_RESET is in progress.
1062 * This is not needed when running the emulation under QEMU
1065 if (spapr_xive_priority_is_reserved(priority
)) {
1066 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1067 " is reserved\n", priority
);
1072 * Validate that "target" is part of the list of threads allocated
1073 * to the partition. For that, find the END corresponding to the
1077 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1081 assert(end_idx
< xive
->nr_ends
);
1082 memcpy(&end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
1089 if (!QEMU_IS_ALIGNED(qpage
, 1ul << qsize
)) {
1090 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: EQ @0x%" HWADDR_PRIx
1091 " is not naturally aligned with %" HWADDR_PRIx
"\n",
1092 qpage
, (hwaddr
)1 << qsize
);
1095 end
.w2
= cpu_to_be32((qpage
>> 32) & 0x0fffffff);
1096 end
.w3
= cpu_to_be32(qpage
& 0xffffffff);
1097 end
.w0
|= cpu_to_be32(END_W0_ENQUEUE
);
1098 end
.w0
= xive_set_field32(END_W0_QSIZE
, end
.w0
, qsize
- 12);
1101 /* reset queue and disable queueing */
1102 spapr_xive_end_reset(&end
);
1106 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid EQ size %"PRIx64
"\n",
1112 hwaddr plen
= 1 << qsize
;
1116 * Validate the guest EQ. We should also check that the queue
1117 * has been zeroed by the OS.
1119 eq
= address_space_map(CPU(cpu
)->as
, qpage
, &plen
, true,
1120 MEMTXATTRS_UNSPECIFIED
);
1121 if (plen
!= 1 << qsize
) {
1122 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to map EQ @0x%"
1123 HWADDR_PRIx
"\n", qpage
);
1126 address_space_unmap(CPU(cpu
)->as
, eq
, plen
, true, plen
);
1129 /* "target" should have been validated above */
1130 if (spapr_xive_target_to_nvt(target
, &nvt_blk
, &nvt_idx
)) {
1131 g_assert_not_reached();
1135 * Ensure the priority and target are correctly set (they will not
1136 * be right after allocation)
1138 end
.w6
= xive_set_field32(END_W6_NVT_BLOCK
, 0ul, nvt_blk
) |
1139 xive_set_field32(END_W6_NVT_INDEX
, 0ul, nvt_idx
);
1140 end
.w7
= xive_set_field32(END_W7_F0_PRIORITY
, 0ul, priority
);
1142 if (flags
& SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
1143 end
.w0
|= cpu_to_be32(END_W0_UCOND_NOTIFY
);
1145 end
.w0
&= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY
);
1149 * The generation bit for the END starts at 1 and The END page
1150 * offset counter starts at 0.
1152 end
.w1
= cpu_to_be32(END_W1_GENERATION
) |
1153 xive_set_field32(END_W1_PAGE_OFF
, 0ul, 0ul);
1154 end
.w0
|= cpu_to_be32(END_W0_VALID
);
1157 * TODO: issue syncs required to ensure all in-flight interrupts
1158 * are complete on the old END
1162 if (kvm_irqchip_in_kernel()) {
1163 Error
*local_err
= NULL
;
1165 kvmppc_xive_set_queue_config(xive
, end_blk
, end_idx
, &end
, &local_err
);
1167 error_report_err(local_err
);
1173 memcpy(&xive
->endt
[end_idx
], &end
, sizeof(XiveEND
));
1178 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given
1179 * target and priority.
1184 * Bits 0-62: Reserved
1185 * Bit 63: Debug: Return debug data
1186 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1187 * "ibm,ppc-interrupt-gserver#s"
1188 * - R6: "priority" is a valid priority not in
1189 * "ibm,plat-res-int-priorities"
1193 * Bits 0-61: Reserved
1194 * Bit 62: The value of Event Queue Generation Number (g) per
1195 * the XIVE spec if "Debug" = 1
1196 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec
1197 * - R5: The logical real address of the start of the EQ
1198 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes"
1199 * - R7: The value of Event Queue Offset Counter per XIVE spec
1200 * if "Debug" = 1, else 0
1204 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63)
1206 static target_ulong
h_int_get_queue_config(PowerPCCPU
*cpu
,
1207 SpaprMachineState
*spapr
,
1208 target_ulong opcode
,
1211 SpaprXive
*xive
= spapr
->xive
;
1212 target_ulong flags
= args
[0];
1213 target_ulong target
= args
[1];
1214 target_ulong priority
= args
[2];
1219 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1223 if (flags
& ~SPAPR_XIVE_END_DEBUG
) {
1228 * H_STATE should be returned if a H_INT_RESET is in progress.
1229 * This is not needed when running the emulation under QEMU
1232 if (spapr_xive_priority_is_reserved(priority
)) {
1233 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1234 " is reserved\n", priority
);
1239 * Validate that "target" is part of the list of threads allocated
1240 * to the partition. For that, find the END corresponding to the
1243 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1247 assert(end_idx
< xive
->nr_ends
);
1248 end
= &xive
->endt
[end_idx
];
1251 if (xive_end_is_notify(end
)) {
1252 args
[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY
;
1255 if (xive_end_is_enqueue(end
)) {
1256 args
[1] = xive_end_qaddr(end
);
1257 args
[2] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
1263 if (kvm_irqchip_in_kernel()) {
1264 Error
*local_err
= NULL
;
1266 kvmppc_xive_get_queue_config(xive
, end_blk
, end_idx
, end
, &local_err
);
1268 error_report_err(local_err
);
1273 /* TODO: do we need any locking on the END ? */
1274 if (flags
& SPAPR_XIVE_END_DEBUG
) {
1275 /* Load the event queue generation number into the return flags */
1276 args
[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION
, end
->w1
) << 62;
1278 /* Load R7 with the event queue offset counter */
1279 args
[3] = xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1288 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the
1289 * reporting cache line pair for the calling thread. The reporting
1290 * cache lines will contain the OS interrupt context when the OS
1291 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS
1292 * interrupt. The reporting cache lines can be reset by inputting -1
1293 * in "reportingLine". Issuing the CI store byte without reporting
1294 * cache lines registered will result in the data not being accessible
1300 * Bits 0-63: Reserved
1301 * - R5: "reportingLine": The logical real address of the reporting cache
1307 static target_ulong
h_int_set_os_reporting_line(PowerPCCPU
*cpu
,
1308 SpaprMachineState
*spapr
,
1309 target_ulong opcode
,
1312 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1317 * H_STATE should be returned if a H_INT_RESET is in progress.
1318 * This is not needed when running the emulation under QEMU
1321 /* TODO: H_INT_SET_OS_REPORTING_LINE */
1326 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical
1327 * real address of the reporting cache line pair set for the input
1328 * "target". If no reporting cache line pair has been set, -1 is
1334 * Bits 0-63: Reserved
1335 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1336 * "ibm,ppc-interrupt-gserver#s"
1337 * - R6: "reportingLine": The logical real address of the reporting
1341 * - R4: The logical real address of the reporting line if set, else -1
1343 static target_ulong
h_int_get_os_reporting_line(PowerPCCPU
*cpu
,
1344 SpaprMachineState
*spapr
,
1345 target_ulong opcode
,
1348 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1353 * H_STATE should be returned if a H_INT_RESET is in progress.
1354 * This is not needed when running the emulation under QEMU
1357 /* TODO: H_INT_GET_OS_REPORTING_LINE */
1362 * The H_INT_ESB hcall() is used to issue a load or store to the ESB
1363 * page for the input "lisn". This hcall is only supported for LISNs
1364 * that have the ESB hcall flag set to 1 when returned from hcall()
1365 * H_INT_GET_SOURCE_INFO.
1370 * Bits 0-62: Reserved
1371 * bit 63: Store: Store=1, store operation, else load operation
1372 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1373 * "ibm,xive-lisn-ranges" properties, or as returned by the
1374 * ibm,query-interrupt-source-number RTAS call, or as
1375 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1376 * - R6: "esbOffset" is the offset into the ESB page for the load or
1378 * - R7: "storeData" is the data to write for a store operation
1381 * - R4: The value of the load if load operation, else -1
1384 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63)
1386 static target_ulong
h_int_esb(PowerPCCPU
*cpu
,
1387 SpaprMachineState
*spapr
,
1388 target_ulong opcode
,
1391 SpaprXive
*xive
= spapr
->xive
;
1393 target_ulong flags
= args
[0];
1394 target_ulong lisn
= args
[1];
1395 target_ulong offset
= args
[2];
1396 target_ulong data
= args
[3];
1398 XiveSource
*xsrc
= &xive
->source
;
1400 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1404 if (flags
& ~SPAPR_XIVE_ESB_STORE
) {
1408 if (lisn
>= xive
->nr_irqs
) {
1409 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1414 eas
= xive
->eat
[lisn
];
1415 if (!xive_eas_is_valid(&eas
)) {
1416 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1421 if (offset
> (1ull << xsrc
->esb_shift
)) {
1425 if (kvm_irqchip_in_kernel()) {
1426 args
[0] = kvmppc_xive_esb_rw(xsrc
, lisn
, offset
, data
,
1427 flags
& SPAPR_XIVE_ESB_STORE
);
1429 mmio_addr
= xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
) + offset
;
1431 if (dma_memory_rw(&address_space_memory
, mmio_addr
, &data
, 8,
1432 (flags
& SPAPR_XIVE_ESB_STORE
))) {
1433 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to access ESB @0x%"
1434 HWADDR_PRIx
"\n", mmio_addr
);
1437 args
[0] = (flags
& SPAPR_XIVE_ESB_STORE
) ? -1 : data
;
1443 * The H_INT_SYNC hcall() is used to issue hardware syncs that will
1444 * ensure any in flight events for the input lisn are in the event
1450 * Bits 0-63: Reserved
1451 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1452 * "ibm,xive-lisn-ranges" properties, or as returned by the
1453 * ibm,query-interrupt-source-number RTAS call, or as
1454 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1459 static target_ulong
h_int_sync(PowerPCCPU
*cpu
,
1460 SpaprMachineState
*spapr
,
1461 target_ulong opcode
,
1464 SpaprXive
*xive
= spapr
->xive
;
1466 target_ulong flags
= args
[0];
1467 target_ulong lisn
= args
[1];
1469 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1477 if (lisn
>= xive
->nr_irqs
) {
1478 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1483 eas
= xive
->eat
[lisn
];
1484 if (!xive_eas_is_valid(&eas
)) {
1485 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1491 * H_STATE should be returned if a H_INT_RESET is in progress.
1492 * This is not needed when running the emulation under QEMU
1496 * This is not real hardware. Nothing to be done unless when
1500 if (kvm_irqchip_in_kernel()) {
1501 Error
*local_err
= NULL
;
1503 kvmppc_xive_sync_source(xive
, lisn
, &local_err
);
1505 error_report_err(local_err
);
1513 * The H_INT_RESET hcall() is used to reset all of the partition's
1514 * interrupt exploitation structures to their initial state. This
1515 * means losing all previously set interrupt state set via
1516 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG.
1521 * Bits 0-63: Reserved
1526 static target_ulong
h_int_reset(PowerPCCPU
*cpu
,
1527 SpaprMachineState
*spapr
,
1528 target_ulong opcode
,
1531 SpaprXive
*xive
= spapr
->xive
;
1532 target_ulong flags
= args
[0];
1534 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1542 device_reset(DEVICE(xive
));
1544 if (kvm_irqchip_in_kernel()) {
1545 Error
*local_err
= NULL
;
1547 kvmppc_xive_reset(xive
, &local_err
);
1549 error_report_err(local_err
);
1556 void spapr_xive_hcall_init(SpaprMachineState
*spapr
)
1558 spapr_register_hypercall(H_INT_GET_SOURCE_INFO
, h_int_get_source_info
);
1559 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG
, h_int_set_source_config
);
1560 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG
, h_int_get_source_config
);
1561 spapr_register_hypercall(H_INT_GET_QUEUE_INFO
, h_int_get_queue_info
);
1562 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG
, h_int_set_queue_config
);
1563 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG
, h_int_get_queue_config
);
1564 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE
,
1565 h_int_set_os_reporting_line
);
1566 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE
,
1567 h_int_get_os_reporting_line
);
1568 spapr_register_hypercall(H_INT_ESB
, h_int_esb
);
1569 spapr_register_hypercall(H_INT_SYNC
, h_int_sync
);
1570 spapr_register_hypercall(H_INT_RESET
, h_int_reset
);
1573 void spapr_dt_xive(SpaprMachineState
*spapr
, uint32_t nr_servers
, void *fdt
,
1576 SpaprXive
*xive
= spapr
->xive
;
1578 uint64_t timas
[2 * 2];
1579 /* Interrupt number ranges for the IPIs */
1580 uint32_t lisn_ranges
[] = {
1582 cpu_to_be32(nr_servers
),
1585 * EQ size - the sizes of pages supported by the system 4K, 64K,
1586 * 2M, 16M. We only advertise 64K for the moment.
1588 uint32_t eq_sizes
[] = {
1589 cpu_to_be32(16), /* 64K */
1592 * The following array is in sync with the reserved priorities
1593 * defined by the 'spapr_xive_priority_is_reserved' routine.
1595 uint32_t plat_res_int_priorities
[] = {
1596 cpu_to_be32(7), /* start */
1597 cpu_to_be32(0xf8), /* count */
1600 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */
1601 timas
[0] = cpu_to_be64(xive
->tm_base
+
1602 XIVE_TM_USER_PAGE
* (1ull << TM_SHIFT
));
1603 timas
[1] = cpu_to_be64(1ull << TM_SHIFT
);
1604 timas
[2] = cpu_to_be64(xive
->tm_base
+
1605 XIVE_TM_OS_PAGE
* (1ull << TM_SHIFT
));
1606 timas
[3] = cpu_to_be64(1ull << TM_SHIFT
);
1608 _FDT(node
= fdt_add_subnode(fdt
, 0, xive
->nodename
));
1610 _FDT(fdt_setprop_string(fdt
, node
, "device_type", "power-ivpe"));
1611 _FDT(fdt_setprop(fdt
, node
, "reg", timas
, sizeof(timas
)));
1613 _FDT(fdt_setprop_string(fdt
, node
, "compatible", "ibm,power-ivpe"));
1614 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-eq-sizes", eq_sizes
,
1616 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-lisn-ranges", lisn_ranges
,
1617 sizeof(lisn_ranges
)));
1619 /* For Linux to link the LSIs to the interrupt controller. */
1620 _FDT(fdt_setprop(fdt
, node
, "interrupt-controller", NULL
, 0));
1621 _FDT(fdt_setprop_cell(fdt
, node
, "#interrupt-cells", 2));
1624 _FDT(fdt_setprop_cell(fdt
, node
, "linux,phandle", phandle
));
1625 _FDT(fdt_setprop_cell(fdt
, node
, "phandle", phandle
));
1628 * The "ibm,plat-res-int-priorities" property defines the priority
1629 * ranges reserved by the hypervisor
1631 _FDT(fdt_setprop(fdt
, 0, "ibm,plat-res-int-priorities",
1632 plat_res_int_priorities
, sizeof(plat_res_int_priorities
)));