target/hppa: Include priv level in user-only iaoq
[qemu/ar7.git] / hw / ppc / e500.c
blob9a85a41362a8e721aacd928f600d65314c44df5a
1 /*
2 * QEMU PowerPC e500-based platforms
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
6 * Author: Yu Liu, <yu.liu@freescale.com>
8 * This file is derived from hw/ppc440_bamboo.c,
9 * the copyright for that material belongs to the original owners.
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include "qemu/osdep.h"
18 #include "qapi/error.h"
19 #include "e500.h"
20 #include "e500-ccsr.h"
21 #include "net/net.h"
22 #include "qemu/config-file.h"
23 #include "hw/hw.h"
24 #include "hw/char/serial.h"
25 #include "hw/pci/pci.h"
26 #include "hw/boards.h"
27 #include "sysemu/sysemu.h"
28 #include "sysemu/kvm.h"
29 #include "kvm_ppc.h"
30 #include "sysemu/device_tree.h"
31 #include "hw/ppc/openpic.h"
32 #include "hw/ppc/openpic_kvm.h"
33 #include "hw/ppc/ppc.h"
34 #include "hw/loader.h"
35 #include "elf.h"
36 #include "hw/sysbus.h"
37 #include "exec/address-spaces.h"
38 #include "qemu/host-utils.h"
39 #include "qemu/option.h"
40 #include "hw/pci-host/ppce500.h"
41 #include "qemu/error-report.h"
42 #include "hw/platform-bus.h"
43 #include "hw/net/fsl_etsec/etsec.h"
45 #define EPAPR_MAGIC (0x45504150)
46 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
47 #define DTC_LOAD_PAD 0x1800000
48 #define DTC_PAD_MASK 0xFFFFF
49 #define DTB_MAX_SIZE (8 * 1024 * 1024)
50 #define INITRD_LOAD_PAD 0x2000000
51 #define INITRD_PAD_MASK 0xFFFFFF
53 #define RAM_SIZES_ALIGN (64UL << 20)
55 /* TODO: parameterize */
56 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL
57 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL
58 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL
59 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
60 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
61 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL
62 #define MPC8544_PCI_REGS_SIZE 0x1000ULL
63 #define MPC8544_UTIL_OFFSET 0xe0000ULL
64 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL
65 #define MPC8XXX_GPIO_IRQ 47
67 struct boot_info
69 uint32_t dt_base;
70 uint32_t dt_size;
71 uint32_t entry;
74 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
75 int nr_slots, int *len)
77 int i = 0;
78 int slot;
79 int pci_irq;
80 int host_irq;
81 int last_slot = first_slot + nr_slots;
82 uint32_t *pci_map;
84 *len = nr_slots * 4 * 7 * sizeof(uint32_t);
85 pci_map = g_malloc(*len);
87 for (slot = first_slot; slot < last_slot; slot++) {
88 for (pci_irq = 0; pci_irq < 4; pci_irq++) {
89 pci_map[i++] = cpu_to_be32(slot << 11);
90 pci_map[i++] = cpu_to_be32(0x0);
91 pci_map[i++] = cpu_to_be32(0x0);
92 pci_map[i++] = cpu_to_be32(pci_irq + 1);
93 pci_map[i++] = cpu_to_be32(mpic);
94 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq);
95 pci_map[i++] = cpu_to_be32(host_irq + 1);
96 pci_map[i++] = cpu_to_be32(0x1);
100 assert((i * sizeof(uint32_t)) == *len);
102 return pci_map;
105 static void dt_serial_create(void *fdt, unsigned long long offset,
106 const char *soc, const char *mpic,
107 const char *alias, int idx, bool defcon)
109 char ser[128];
111 snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset);
112 qemu_fdt_add_subnode(fdt, ser);
113 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial");
114 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550");
115 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100);
116 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx);
117 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0);
118 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2);
119 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
120 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser);
122 if (defcon) {
124 * "linux,stdout-path" and "stdout" properties are deprecated by linux
125 * kernel. New platforms should only use the "stdout-path" property. Set
126 * the new property and continue using older property to remain
127 * compatible with the existing firmware.
129 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser);
130 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser);
134 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic)
136 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET;
137 int irq0 = MPC8XXX_GPIO_IRQ;
138 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0);
139 gchar *poweroff = g_strdup_printf("%s/power-off", soc);
140 int gpio_ph;
142 qemu_fdt_add_subnode(fdt, node);
143 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio");
144 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000);
145 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2);
146 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
147 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2);
148 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0);
149 gpio_ph = qemu_fdt_alloc_phandle(fdt);
150 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph);
151 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph);
153 /* Power Off Pin */
154 qemu_fdt_add_subnode(fdt, poweroff);
155 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff");
156 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0);
158 g_free(node);
159 g_free(poweroff);
162 typedef struct PlatformDevtreeData {
163 void *fdt;
164 const char *mpic;
165 int irq_start;
166 const char *node;
167 PlatformBusDevice *pbus;
168 } PlatformDevtreeData;
170 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data)
172 eTSEC *etsec = ETSEC_COMMON(sbdev);
173 PlatformBusDevice *pbus = data->pbus;
174 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0);
175 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0);
176 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1);
177 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2);
178 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0);
179 gchar *group = g_strdup_printf("%s/queue-group", node);
180 void *fdt = data->fdt;
182 assert((int64_t)mmio0 >= 0);
183 assert(irq0 >= 0);
184 assert(irq1 >= 0);
185 assert(irq2 >= 0);
187 qemu_fdt_add_subnode(fdt, node);
188 qemu_fdt_setprop_string(fdt, node, "device_type", "network");
189 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2");
190 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC");
191 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6);
192 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0);
194 qemu_fdt_add_subnode(fdt, group);
195 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000);
196 qemu_fdt_setprop_cells(fdt, group, "interrupts",
197 data->irq_start + irq0, 0x2,
198 data->irq_start + irq1, 0x2,
199 data->irq_start + irq2, 0x2);
201 g_free(node);
202 g_free(group);
204 return 0;
207 static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque)
209 PlatformDevtreeData *data = opaque;
210 bool matched = false;
212 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) {
213 create_devtree_etsec(sbdev, data);
214 matched = true;
217 if (!matched) {
218 error_report("Device %s is not supported by this machine yet.",
219 qdev_fw_name(DEVICE(sbdev)));
220 exit(1);
224 static void platform_bus_create_devtree(PPCE500Params *params, void *fdt,
225 const char *mpic)
227 gchar *node = g_strdup_printf("/platform@%"PRIx64, params->platform_bus_base);
228 const char platcomp[] = "qemu,platform\0simple-bus";
229 uint64_t addr = params->platform_bus_base;
230 uint64_t size = params->platform_bus_size;
231 int irq_start = params->platform_bus_first_irq;
232 PlatformBusDevice *pbus;
233 DeviceState *dev;
235 /* Create a /platform node that we can put all devices into */
237 qemu_fdt_add_subnode(fdt, node);
238 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp));
240 /* Our platform bus region is less than 32bit big, so 1 cell is enough for
241 address and size */
242 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1);
243 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1);
244 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size);
246 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
248 dev = qdev_find_recursive(sysbus_get_default(), TYPE_PLATFORM_BUS_DEVICE);
249 pbus = PLATFORM_BUS_DEVICE(dev);
251 /* We can only create dt nodes for dynamic devices when they're ready */
252 if (pbus->done_gathering) {
253 PlatformDevtreeData data = {
254 .fdt = fdt,
255 .mpic = mpic,
256 .irq_start = irq_start,
257 .node = node,
258 .pbus = pbus,
261 /* Loop through all dynamic sysbus devices and create nodes for them */
262 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data);
265 g_free(node);
268 static int ppce500_load_device_tree(MachineState *machine,
269 PPCE500Params *params,
270 hwaddr addr,
271 hwaddr initrd_base,
272 hwaddr initrd_size,
273 hwaddr kernel_base,
274 hwaddr kernel_size,
275 bool dry_run)
277 CPUPPCState *env = first_cpu->env_ptr;
278 int ret = -1;
279 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) };
280 int fdt_size;
281 void *fdt;
282 uint8_t hypercall[16];
283 uint32_t clock_freq = 400000000;
284 uint32_t tb_freq = 400000000;
285 int i;
286 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
287 char soc[128];
288 char mpic[128];
289 uint32_t mpic_ph;
290 uint32_t msi_ph;
291 char gutil[128];
292 char pci[128];
293 char msi[128];
294 uint32_t *pci_map = NULL;
295 int len;
296 uint32_t pci_ranges[14] =
298 0x2000000, 0x0, params->pci_mmio_bus_base,
299 params->pci_mmio_base >> 32, params->pci_mmio_base,
300 0x0, 0x20000000,
302 0x1000000, 0x0, 0x0,
303 params->pci_pio_base >> 32, params->pci_pio_base,
304 0x0, 0x10000,
306 QemuOpts *machine_opts = qemu_get_machine_opts();
307 const char *dtb_file = qemu_opt_get(machine_opts, "dtb");
308 const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible");
310 if (dtb_file) {
311 char *filename;
312 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);
313 if (!filename) {
314 goto out;
317 fdt = load_device_tree(filename, &fdt_size);
318 g_free(filename);
319 if (!fdt) {
320 goto out;
322 goto done;
325 fdt = create_device_tree(&fdt_size);
326 if (fdt == NULL) {
327 goto out;
330 /* Manipulate device tree in memory. */
331 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2);
332 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2);
334 qemu_fdt_add_subnode(fdt, "/memory");
335 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
336 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
337 sizeof(mem_reg_property));
339 qemu_fdt_add_subnode(fdt, "/chosen");
340 if (initrd_size) {
341 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
342 initrd_base);
343 if (ret < 0) {
344 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
347 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
348 (initrd_base + initrd_size));
349 if (ret < 0) {
350 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
355 if (kernel_base != -1ULL) {
356 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel",
357 kernel_base >> 32, kernel_base,
358 kernel_size >> 32, kernel_size);
361 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
362 machine->kernel_cmdline);
363 if (ret < 0)
364 fprintf(stderr, "couldn't set /chosen/bootargs\n");
366 if (kvm_enabled()) {
367 /* Read out host's frequencies */
368 clock_freq = kvmppc_get_clockfreq();
369 tb_freq = kvmppc_get_tbfreq();
371 /* indicate KVM hypercall interface */
372 qemu_fdt_add_subnode(fdt, "/hypervisor");
373 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible",
374 "linux,kvm");
375 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
376 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions",
377 hypercall, sizeof(hypercall));
378 /* if KVM supports the idle hcall, set property indicating this */
379 if (kvmppc_get_hasidle(env)) {
380 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0);
384 /* Create CPU nodes */
385 qemu_fdt_add_subnode(fdt, "/cpus");
386 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);
387 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);
389 /* We need to generate the cpu nodes in reverse order, so Linux can pick
390 the first node as boot node and be happy */
391 for (i = smp_cpus - 1; i >= 0; i--) {
392 CPUState *cpu;
393 char cpu_name[128];
394 uint64_t cpu_release_addr = params->spin_base + (i * 0x20);
396 cpu = qemu_get_cpu(i);
397 if (cpu == NULL) {
398 continue;
400 env = cpu->env_ptr;
402 snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", i);
403 qemu_fdt_add_subnode(fdt, cpu_name);
404 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
405 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
406 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
407 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i);
408 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size",
409 env->dcache_line_size);
410 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size",
411 env->icache_line_size);
412 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
413 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
414 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
415 if (cpu->cpu_index) {
416 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled");
417 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method",
418 "spin-table");
419 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr",
420 cpu_release_addr);
421 } else {
422 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
426 qemu_fdt_add_subnode(fdt, "/aliases");
427 /* XXX These should go into their respective devices' code */
428 snprintf(soc, sizeof(soc), "/soc@%"PRIx64, params->ccsrbar_base);
429 qemu_fdt_add_subnode(fdt, soc);
430 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc");
431 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb,
432 sizeof(compatible_sb));
433 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1);
434 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1);
435 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0,
436 params->ccsrbar_base >> 32, params->ccsrbar_base,
437 MPC8544_CCSRBAR_SIZE);
438 /* XXX should contain a reasonable value */
439 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0);
441 snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
442 qemu_fdt_add_subnode(fdt, mpic);
443 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic");
444 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic");
445 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
446 0x40000);
447 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0);
448 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
449 mpic_ph = qemu_fdt_alloc_phandle(fdt);
450 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph);
451 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
452 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
455 * We have to generate ser1 first, because Linux takes the first
456 * device it finds in the dt as serial output device. And we generate
457 * devices in reverse order to the dt.
459 if (serial_hds[1]) {
460 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
461 soc, mpic, "serial1", 1, false);
464 if (serial_hds[0]) {
465 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
466 soc, mpic, "serial0", 0, true);
469 snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc,
470 MPC8544_UTIL_OFFSET);
471 qemu_fdt_add_subnode(fdt, gutil);
472 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
473 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
474 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
476 snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
477 qemu_fdt_add_subnode(fdt, msi);
478 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");
479 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);
480 msi_ph = qemu_fdt_alloc_phandle(fdt);
481 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);
482 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
483 qemu_fdt_setprop_cells(fdt, msi, "interrupts",
484 0xe0, 0x0,
485 0xe1, 0x0,
486 0xe2, 0x0,
487 0xe3, 0x0,
488 0xe4, 0x0,
489 0xe5, 0x0,
490 0xe6, 0x0,
491 0xe7, 0x0);
492 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph);
493 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
495 snprintf(pci, sizeof(pci), "/pci@%llx",
496 params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET);
497 qemu_fdt_add_subnode(fdt, pci);
498 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0);
499 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
500 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci");
501 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
502 0x0, 0x7);
503 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic),
504 params->pci_first_slot, params->pci_nr_slots,
505 &len);
506 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len);
507 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
508 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2);
509 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255);
510 for (i = 0; i < 14; i++) {
511 pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
513 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
514 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
515 qemu_fdt_setprop_cells(fdt, pci, "reg",
516 (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32,
517 (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET),
518 0, 0x1000);
519 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666);
520 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1);
521 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2);
522 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3);
523 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci);
525 if (params->has_mpc8xxx_gpio) {
526 create_dt_mpc8xxx_gpio(fdt, soc, mpic);
529 if (params->has_platform_bus) {
530 platform_bus_create_devtree(params, fdt, mpic);
533 params->fixup_devtree(params, fdt);
535 if (toplevel_compat) {
536 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat,
537 strlen(toplevel_compat) + 1);
540 done:
541 if (!dry_run) {
542 qemu_fdt_dumpdtb(fdt, fdt_size);
543 cpu_physical_memory_write(addr, fdt, fdt_size);
545 ret = fdt_size;
547 out:
548 g_free(pci_map);
550 return ret;
553 typedef struct DeviceTreeParams {
554 MachineState *machine;
555 PPCE500Params params;
556 hwaddr addr;
557 hwaddr initrd_base;
558 hwaddr initrd_size;
559 hwaddr kernel_base;
560 hwaddr kernel_size;
561 Notifier notifier;
562 } DeviceTreeParams;
564 static void ppce500_reset_device_tree(void *opaque)
566 DeviceTreeParams *p = opaque;
567 ppce500_load_device_tree(p->machine, &p->params, p->addr, p->initrd_base,
568 p->initrd_size, p->kernel_base, p->kernel_size,
569 false);
572 static void ppce500_init_notify(Notifier *notifier, void *data)
574 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier);
575 ppce500_reset_device_tree(p);
578 static int ppce500_prep_device_tree(MachineState *machine,
579 PPCE500Params *params,
580 hwaddr addr,
581 hwaddr initrd_base,
582 hwaddr initrd_size,
583 hwaddr kernel_base,
584 hwaddr kernel_size)
586 DeviceTreeParams *p = g_new(DeviceTreeParams, 1);
587 p->machine = machine;
588 p->params = *params;
589 p->addr = addr;
590 p->initrd_base = initrd_base;
591 p->initrd_size = initrd_size;
592 p->kernel_base = kernel_base;
593 p->kernel_size = kernel_size;
595 qemu_register_reset(ppce500_reset_device_tree, p);
596 p->notifier.notify = ppce500_init_notify;
597 qemu_add_machine_init_done_notifier(&p->notifier);
599 /* Issue the device tree loader once, so that we get the size of the blob */
600 return ppce500_load_device_tree(machine, params, addr, initrd_base,
601 initrd_size, kernel_base, kernel_size,
602 true);
605 /* Create -kernel TLB entries for BookE. */
606 hwaddr booke206_page_size_to_tlb(uint64_t size)
608 return 63 - clz64(size >> 10);
611 static int booke206_initial_map_tsize(CPUPPCState *env)
613 struct boot_info *bi = env->load_info;
614 hwaddr dt_end;
615 int ps;
617 /* Our initial TLB entry needs to cover everything from 0 to
618 the device tree top */
619 dt_end = bi->dt_base + bi->dt_size;
620 ps = booke206_page_size_to_tlb(dt_end) + 1;
621 if (ps & 1) {
622 /* e500v2 can only do even TLB size bits */
623 ps++;
625 return ps;
628 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env)
630 int tsize;
632 tsize = booke206_initial_map_tsize(env);
633 return (1ULL << 10 << tsize);
636 static void mmubooke_create_initial_mapping(CPUPPCState *env)
638 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
639 hwaddr size;
640 int ps;
642 ps = booke206_initial_map_tsize(env);
643 size = (ps << MAS1_TSIZE_SHIFT);
644 tlb->mas1 = MAS1_VALID | size;
645 tlb->mas2 = 0;
646 tlb->mas7_3 = 0;
647 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
649 env->tlb_dirty = true;
652 static void ppce500_cpu_reset_sec(void *opaque)
654 PowerPCCPU *cpu = opaque;
655 CPUState *cs = CPU(cpu);
657 cpu_reset(cs);
659 /* Secondary CPU starts in halted state for now. Needs to change when
660 implementing non-kernel boot. */
661 cs->halted = 1;
662 cs->exception_index = EXCP_HLT;
665 static void ppce500_cpu_reset(void *opaque)
667 PowerPCCPU *cpu = opaque;
668 CPUState *cs = CPU(cpu);
669 CPUPPCState *env = &cpu->env;
670 struct boot_info *bi = env->load_info;
672 cpu_reset(cs);
674 /* Set initial guest state. */
675 cs->halted = 0;
676 env->gpr[1] = (16<<20) - 8;
677 env->gpr[3] = bi->dt_base;
678 env->gpr[4] = 0;
679 env->gpr[5] = 0;
680 env->gpr[6] = EPAPR_MAGIC;
681 env->gpr[7] = mmubooke_initial_mapsize(env);
682 env->gpr[8] = 0;
683 env->gpr[9] = 0;
684 env->nip = bi->entry;
685 mmubooke_create_initial_mapping(env);
688 static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params,
689 qemu_irq **irqs)
691 DeviceState *dev;
692 SysBusDevice *s;
693 int i, j, k;
695 dev = qdev_create(NULL, TYPE_OPENPIC);
696 object_property_add_child(qdev_get_machine(), "pic", OBJECT(dev),
697 &error_fatal);
698 qdev_prop_set_uint32(dev, "model", params->mpic_version);
699 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
701 qdev_init_nofail(dev);
702 s = SYS_BUS_DEVICE(dev);
704 k = 0;
705 for (i = 0; i < smp_cpus; i++) {
706 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
707 sysbus_connect_irq(s, k++, irqs[i][j]);
711 return dev;
714 static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params,
715 qemu_irq **irqs, Error **errp)
717 Error *err = NULL;
718 DeviceState *dev;
719 CPUState *cs;
721 dev = qdev_create(NULL, TYPE_KVM_OPENPIC);
722 qdev_prop_set_uint32(dev, "model", params->mpic_version);
724 object_property_set_bool(OBJECT(dev), true, "realized", &err);
725 if (err) {
726 error_propagate(errp, err);
727 object_unparent(OBJECT(dev));
728 return NULL;
731 CPU_FOREACH(cs) {
732 if (kvm_openpic_connect_vcpu(dev, cs)) {
733 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n",
734 __func__);
735 abort();
739 return dev;
742 static DeviceState *ppce500_init_mpic(MachineState *machine,
743 PPCE500Params *params,
744 MemoryRegion *ccsr,
745 qemu_irq **irqs)
747 DeviceState *dev = NULL;
748 SysBusDevice *s;
750 if (kvm_enabled()) {
751 Error *err = NULL;
753 if (machine_kernel_irqchip_allowed(machine)) {
754 dev = ppce500_init_mpic_kvm(params, irqs, &err);
756 if (machine_kernel_irqchip_required(machine) && !dev) {
757 error_reportf_err(err,
758 "kernel_irqchip requested but unavailable: ");
759 exit(1);
763 if (!dev) {
764 dev = ppce500_init_mpic_qemu(params, irqs);
767 s = SYS_BUS_DEVICE(dev);
768 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET,
769 s->mmio[0].memory);
771 return dev;
774 static void ppce500_power_off(void *opaque, int line, int on)
776 if (on) {
777 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
781 void ppce500_init(MachineState *machine, PPCE500Params *params)
783 MemoryRegion *address_space_mem = get_system_memory();
784 MemoryRegion *ram = g_new(MemoryRegion, 1);
785 PCIBus *pci_bus;
786 CPUPPCState *env = NULL;
787 uint64_t loadaddr;
788 hwaddr kernel_base = -1LL;
789 int kernel_size = 0;
790 hwaddr dt_base = 0;
791 hwaddr initrd_base = 0;
792 int initrd_size = 0;
793 hwaddr cur_base = 0;
794 char *filename;
795 const char *payload_name;
796 bool kernel_as_payload;
797 hwaddr bios_entry = 0;
798 target_long payload_size;
799 struct boot_info *boot_info;
800 int dt_size;
801 int i;
802 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
803 * 4 respectively */
804 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
805 qemu_irq **irqs;
806 DeviceState *dev, *mpicdev;
807 CPUPPCState *firstenv = NULL;
808 MemoryRegion *ccsr_addr_space;
809 SysBusDevice *s;
810 PPCE500CCSRState *ccsr;
812 irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
813 irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
814 for (i = 0; i < smp_cpus; i++) {
815 PowerPCCPU *cpu;
816 CPUState *cs;
817 qemu_irq *input;
819 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
820 env = &cpu->env;
821 cs = CPU(cpu);
823 if (env->mmu_model != POWERPC_MMU_BOOKE206) {
824 error_report("MMU model %i not supported by this machine",
825 env->mmu_model);
826 exit(1);
829 if (!firstenv) {
830 firstenv = env;
833 irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
834 input = (qemu_irq *)env->irq_inputs;
835 irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
836 irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
837 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
838 env->mpic_iack = params->ccsrbar_base +
839 MPC8544_MPIC_REGS_OFFSET + 0xa0;
841 ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
843 /* Register reset handler */
844 if (!i) {
845 /* Primary CPU */
846 struct boot_info *boot_info;
847 boot_info = g_malloc0(sizeof(struct boot_info));
848 qemu_register_reset(ppce500_cpu_reset, cpu);
849 env->load_info = boot_info;
850 } else {
851 /* Secondary CPUs */
852 qemu_register_reset(ppce500_cpu_reset_sec, cpu);
856 env = firstenv;
858 /* Fixup Memory size on a alignment boundary */
859 ram_size &= ~(RAM_SIZES_ALIGN - 1);
860 machine->ram_size = ram_size;
862 /* Register Memory */
863 memory_region_allocate_system_memory(ram, NULL, "mpc8544ds.ram", ram_size);
864 memory_region_add_subregion(address_space_mem, 0, ram);
866 dev = qdev_create(NULL, "e500-ccsr");
867 object_property_add_child(qdev_get_machine(), "e500-ccsr",
868 OBJECT(dev), NULL);
869 qdev_init_nofail(dev);
870 ccsr = CCSR(dev);
871 ccsr_addr_space = &ccsr->ccsr_space;
872 memory_region_add_subregion(address_space_mem, params->ccsrbar_base,
873 ccsr_addr_space);
875 mpicdev = ppce500_init_mpic(machine, params, ccsr_addr_space, irqs);
877 /* Serial */
878 if (serial_hds[0]) {
879 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
880 0, qdev_get_gpio_in(mpicdev, 42), 399193,
881 serial_hds[0], DEVICE_BIG_ENDIAN);
884 if (serial_hds[1]) {
885 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
886 0, qdev_get_gpio_in(mpicdev, 42), 399193,
887 serial_hds[1], DEVICE_BIG_ENDIAN);
890 /* General Utility device */
891 dev = qdev_create(NULL, "mpc8544-guts");
892 qdev_init_nofail(dev);
893 s = SYS_BUS_DEVICE(dev);
894 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
895 sysbus_mmio_get_region(s, 0));
897 /* PCI */
898 dev = qdev_create(NULL, "e500-pcihost");
899 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev),
900 &error_abort);
901 qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot);
902 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]);
903 qdev_init_nofail(dev);
904 s = SYS_BUS_DEVICE(dev);
905 for (i = 0; i < PCI_NUM_PINS; i++) {
906 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i]));
909 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
910 sysbus_mmio_get_region(s, 0));
912 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
913 if (!pci_bus)
914 printf("couldn't create PCI controller!\n");
916 if (pci_bus) {
917 /* Register network interfaces. */
918 for (i = 0; i < nb_nics; i++) {
919 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio-net-pci", NULL);
923 /* Register spinning region */
924 sysbus_create_simple("e500-spin", params->spin_base, NULL);
926 if (params->has_mpc8xxx_gpio) {
927 qemu_irq poweroff_irq;
929 dev = qdev_create(NULL, "mpc8xxx_gpio");
930 s = SYS_BUS_DEVICE(dev);
931 qdev_init_nofail(dev);
932 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ));
933 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET,
934 sysbus_mmio_get_region(s, 0));
936 /* Power Off GPIO at Pin 0 */
937 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0);
938 qdev_connect_gpio_out(dev, 0, poweroff_irq);
941 /* Platform Bus Device */
942 if (params->has_platform_bus) {
943 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
944 dev->id = TYPE_PLATFORM_BUS_DEVICE;
945 qdev_prop_set_uint32(dev, "num_irqs", params->platform_bus_num_irqs);
946 qdev_prop_set_uint32(dev, "mmio_size", params->platform_bus_size);
947 qdev_init_nofail(dev);
948 s = SYS_BUS_DEVICE(dev);
950 for (i = 0; i < params->platform_bus_num_irqs; i++) {
951 int irqn = params->platform_bus_first_irq + i;
952 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn));
955 memory_region_add_subregion(address_space_mem,
956 params->platform_bus_base,
957 sysbus_mmio_get_region(s, 0));
961 * Smart firmware defaults ahead!
963 * We follow the following table to select which payload we execute.
965 * -kernel | -bios | payload
966 * ---------+-------+---------
967 * N | Y | u-boot
968 * N | N | u-boot
969 * Y | Y | u-boot
970 * Y | N | kernel
972 * This ensures backwards compatibility with how we used to expose
973 * -kernel to users but allows them to run through u-boot as well.
975 kernel_as_payload = false;
976 if (bios_name == NULL) {
977 if (machine->kernel_filename) {
978 payload_name = machine->kernel_filename;
979 kernel_as_payload = true;
980 } else {
981 payload_name = "u-boot.e500";
983 } else {
984 payload_name = bios_name;
987 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name);
989 payload_size = load_elf(filename, NULL, NULL, &bios_entry, &loadaddr, NULL,
990 1, PPC_ELF_MACHINE, 0, 0);
991 if (payload_size < 0) {
993 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an
994 * ePAPR compliant kernel
996 payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL,
997 NULL, NULL);
998 if (payload_size < 0) {
999 error_report("qemu: could not load firmware '%s'", filename);
1000 exit(1);
1004 g_free(filename);
1006 if (kernel_as_payload) {
1007 kernel_base = loadaddr;
1008 kernel_size = payload_size;
1011 cur_base = loadaddr + payload_size;
1012 if (cur_base < (32 * 1024 * 1024)) {
1013 /* u-boot occupies memory up to 32MB, so load blobs above */
1014 cur_base = (32 * 1024 * 1024);
1017 /* Load bare kernel only if no bios/u-boot has been provided */
1018 if (machine->kernel_filename && !kernel_as_payload) {
1019 kernel_base = cur_base;
1020 kernel_size = load_image_targphys(machine->kernel_filename,
1021 cur_base,
1022 ram_size - cur_base);
1023 if (kernel_size < 0) {
1024 error_report("could not load kernel '%s'",
1025 machine->kernel_filename);
1026 exit(1);
1029 cur_base += kernel_size;
1032 /* Load initrd. */
1033 if (machine->initrd_filename) {
1034 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
1035 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
1036 ram_size - initrd_base);
1038 if (initrd_size < 0) {
1039 error_report("could not load initial ram disk '%s'",
1040 machine->initrd_filename);
1041 exit(1);
1044 cur_base = initrd_base + initrd_size;
1048 * Reserve space for dtb behind the kernel image because Linux has a bug
1049 * where it can only handle the dtb if it's within the first 64MB of where
1050 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD
1051 * ensures enough space between kernel and initrd.
1053 dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
1054 if (dt_base + DTB_MAX_SIZE > ram_size) {
1055 error_report("qemu: not enough memory for device tree");
1056 exit(1);
1059 dt_size = ppce500_prep_device_tree(machine, params, dt_base,
1060 initrd_base, initrd_size,
1061 kernel_base, kernel_size);
1062 if (dt_size < 0) {
1063 error_report("couldn't load device tree");
1064 exit(1);
1066 assert(dt_size < DTB_MAX_SIZE);
1068 boot_info = env->load_info;
1069 boot_info->entry = bios_entry;
1070 boot_info->dt_base = dt_base;
1071 boot_info->dt_size = dt_size;
1074 static void e500_ccsr_initfn(Object *obj)
1076 PPCE500CCSRState *ccsr = CCSR(obj);
1077 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr",
1078 MPC8544_CCSRBAR_SIZE);
1081 static const TypeInfo e500_ccsr_info = {
1082 .name = TYPE_CCSR,
1083 .parent = TYPE_SYS_BUS_DEVICE,
1084 .instance_size = sizeof(PPCE500CCSRState),
1085 .instance_init = e500_ccsr_initfn,
1088 static void e500_register_types(void)
1090 type_register_static(&e500_ccsr_info);
1093 type_init(e500_register_types)