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virtio-9p: use QEMU thread pool
[qemu/ar7.git] / target-i386 / kvm.c
blob6dc9846398c0bb0486f190c255a0d2f1353d918e
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
17 #include <sys/mman.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm_int.h"
26 #include "kvm_i386.h"
27 #include "cpu.h"
28 #include "exec/gdbstub.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/config-file.h"
31 #include "qemu/error-report.h"
32 #include "hw/i386/pc.h"
33 #include "hw/i386/apic.h"
34 #include "hw/i386/apic_internal.h"
35 #include "hw/i386/apic-msidef.h"
36 #include "exec/ioport.h"
37 #include "standard-headers/asm-x86/hyperv.h"
38 #include "hw/pci/pci.h"
39 #include "migration/migration.h"
40 #include "exec/memattrs.h"
41
42 //#define DEBUG_KVM
43
44 #ifdef DEBUG_KVM
45 #define DPRINTF(fmt, ...) \
46 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
47 #else
48 #define DPRINTF(fmt, ...) \
49 do { } while (0)
50 #endif
51
52 #define MSR_KVM_WALL_CLOCK 0x11
53 #define MSR_KVM_SYSTEM_TIME 0x12
54
55 #ifndef BUS_MCEERR_AR
56 #define BUS_MCEERR_AR 4
57 #endif
58 #ifndef BUS_MCEERR_AO
59 #define BUS_MCEERR_AO 5
60 #endif
61
62 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
63 KVM_CAP_INFO(SET_TSS_ADDR),
64 KVM_CAP_INFO(EXT_CPUID),
65 KVM_CAP_INFO(MP_STATE),
66 KVM_CAP_LAST_INFO
67 };
68
69 static bool has_msr_star;
70 static bool has_msr_hsave_pa;
71 static bool has_msr_tsc_aux;
72 static bool has_msr_tsc_adjust;
73 static bool has_msr_tsc_deadline;
74 static bool has_msr_feature_control;
75 static bool has_msr_async_pf_en;
76 static bool has_msr_pv_eoi_en;
77 static bool has_msr_misc_enable;
78 static bool has_msr_smbase;
79 static bool has_msr_bndcfgs;
80 static bool has_msr_kvm_steal_time;
81 static int lm_capable_kernel;
82 static bool has_msr_hv_hypercall;
83 static bool has_msr_hv_vapic;
84 static bool has_msr_hv_tsc;
85 static bool has_msr_hv_crash;
86 static bool has_msr_hv_reset;
87 static bool has_msr_hv_vpindex;
88 static bool has_msr_hv_runtime;
89 static bool has_msr_mtrr;
90 static bool has_msr_xss;
91
92 static bool has_msr_architectural_pmu;
93 static uint32_t num_architectural_pmu_counters;
94
95 static int has_xsave;
96 static int has_xcrs;
97 static int has_pit_state2;
98
99 int kvm_has_pit_state2(void)
100 {
101 return has_pit_state2;
102 }
103
104 bool kvm_has_smm(void)
105 {
106 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
107 }
108
109 bool kvm_allows_irq0_override(void)
110 {
111 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
112 }
113
114 static int kvm_get_tsc(CPUState *cs)
115 {
116 X86CPU *cpu = X86_CPU(cs);
117 CPUX86State *env = &cpu->env;
118 struct {
119 struct kvm_msrs info;
120 struct kvm_msr_entry entries[1];
121 } msr_data;
122 int ret;
123
124 if (env->tsc_valid) {
125 return 0;
126 }
127
128 msr_data.info.nmsrs = 1;
129 msr_data.entries[0].index = MSR_IA32_TSC;
130 env->tsc_valid = !runstate_is_running();
131
132 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
133 if (ret < 0) {
134 return ret;
135 }
136
137 env->tsc = msr_data.entries[0].data;
138 return 0;
139 }
140
141 static inline void do_kvm_synchronize_tsc(void *arg)
142 {
143 CPUState *cpu = arg;
144
145 kvm_get_tsc(cpu);
146 }
147
148 void kvm_synchronize_all_tsc(void)
149 {
150 CPUState *cpu;
151
152 if (kvm_enabled()) {
153 CPU_FOREACH(cpu) {
154 run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu);
155 }
156 }
157 }
158
159 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
160 {
161 struct kvm_cpuid2 *cpuid;
162 int r, size;
163
164 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
165 cpuid = g_malloc0(size);
166 cpuid->nent = max;
167 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
168 if (r == 0 && cpuid->nent >= max) {
169 r = -E2BIG;
170 }
171 if (r < 0) {
172 if (r == -E2BIG) {
173 g_free(cpuid);
174 return NULL;
175 } else {
176 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
177 strerror(-r));
178 exit(1);
179 }
180 }
181 return cpuid;
182 }
183
184 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
185 * for all entries.
186 */
187 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
188 {
189 struct kvm_cpuid2 *cpuid;
190 int max = 1;
191 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
192 max *= 2;
193 }
194 return cpuid;
195 }
196
197 static const struct kvm_para_features {
198 int cap;
199 int feature;
200 } para_features[] = {
201 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
202 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
203 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
204 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
205 };
206
207 static int get_para_features(KVMState *s)
208 {
209 int i, features = 0;
210
211 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
212 if (kvm_check_extension(s, para_features[i].cap)) {
213 features |= (1 << para_features[i].feature);
214 }
215 }
216
217 return features;
218 }
219
220
221 /* Returns the value for a specific register on the cpuid entry
222 */
223 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
224 {
225 uint32_t ret = 0;
226 switch (reg) {
227 case R_EAX:
228 ret = entry->eax;
229 break;
230 case R_EBX:
231 ret = entry->ebx;
232 break;
233 case R_ECX:
234 ret = entry->ecx;
235 break;
236 case R_EDX:
237 ret = entry->edx;
238 break;
239 }
240 return ret;
241 }
242
243 /* Find matching entry for function/index on kvm_cpuid2 struct
244 */
245 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
246 uint32_t function,
247 uint32_t index)
248 {
249 int i;
250 for (i = 0; i < cpuid->nent; ++i) {
251 if (cpuid->entries[i].function == function &&
252 cpuid->entries[i].index == index) {
253 return &cpuid->entries[i];
254 }
255 }
256 /* not found: */
257 return NULL;
258 }
259
260 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
261 uint32_t index, int reg)
262 {
263 struct kvm_cpuid2 *cpuid;
264 uint32_t ret = 0;
265 uint32_t cpuid_1_edx;
266 bool found = false;
267
268 cpuid = get_supported_cpuid(s);
269
270 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
271 if (entry) {
272 found = true;
273 ret = cpuid_entry_get_reg(entry, reg);
274 }
275
276 /* Fixups for the data returned by KVM, below */
277
278 if (function == 1 && reg == R_EDX) {
279 /* KVM before 2.6.30 misreports the following features */
280 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
281 } else if (function == 1 && reg == R_ECX) {
282 /* We can set the hypervisor flag, even if KVM does not return it on
283 * GET_SUPPORTED_CPUID
284 */
285 ret |= CPUID_EXT_HYPERVISOR;
286 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
287 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
288 * and the irqchip is in the kernel.
289 */
290 if (kvm_irqchip_in_kernel() &&
291 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
292 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
293 }
294
295 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
296 * without the in-kernel irqchip
297 */
298 if (!kvm_irqchip_in_kernel()) {
299 ret &= ~CPUID_EXT_X2APIC;
300 }
301 } else if (function == 6 && reg == R_EAX) {
302 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
303 } else if (function == 0x80000001 && reg == R_EDX) {
304 /* On Intel, kvm returns cpuid according to the Intel spec,
305 * so add missing bits according to the AMD spec:
306 */
307 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
308 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
309 }
310
311 g_free(cpuid);
312
313 /* fallback for older kernels */
314 if ((function == KVM_CPUID_FEATURES) && !found) {
315 ret = get_para_features(s);
316 }
317
318 return ret;
319 }
320
321 typedef struct HWPoisonPage {
322 ram_addr_t ram_addr;
323 QLIST_ENTRY(HWPoisonPage) list;
324 } HWPoisonPage;
325
326 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
327 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
328
329 static void kvm_unpoison_all(void *param)
330 {
331 HWPoisonPage *page, *next_page;
332
333 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
334 QLIST_REMOVE(page, list);
335 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
336 g_free(page);
337 }
338 }
339
340 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
341 {
342 HWPoisonPage *page;
343
344 QLIST_FOREACH(page, &hwpoison_page_list, list) {
345 if (page->ram_addr == ram_addr) {
346 return;
347 }
348 }
349 page = g_new(HWPoisonPage, 1);
350 page->ram_addr = ram_addr;
351 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
352 }
353
354 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
355 int *max_banks)
356 {
357 int r;
358
359 r = kvm_check_extension(s, KVM_CAP_MCE);
360 if (r > 0) {
361 *max_banks = r;
362 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
363 }
364 return -ENOSYS;
365 }
366
367 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
368 {
369 CPUX86State *env = &cpu->env;
370 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
371 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
372 uint64_t mcg_status = MCG_STATUS_MCIP;
373
374 if (code == BUS_MCEERR_AR) {
375 status |= MCI_STATUS_AR | 0x134;
376 mcg_status |= MCG_STATUS_EIPV;
377 } else {
378 status |= 0xc0;
379 mcg_status |= MCG_STATUS_RIPV;
380 }
381 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
382 (MCM_ADDR_PHYS << 6) | 0xc,
383 cpu_x86_support_mca_broadcast(env) ?
384 MCE_INJECT_BROADCAST : 0);
385 }
386
387 static void hardware_memory_error(void)
388 {
389 fprintf(stderr, "Hardware memory error!\n");
390 exit(1);
391 }
392
393 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
394 {
395 X86CPU *cpu = X86_CPU(c);
396 CPUX86State *env = &cpu->env;
397 ram_addr_t ram_addr;
398 hwaddr paddr;
399
400 if ((env->mcg_cap & MCG_SER_P) && addr
401 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
402 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
403 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
404 fprintf(stderr, "Hardware memory error for memory used by "
405 "QEMU itself instead of guest system!\n");
406 /* Hope we are lucky for AO MCE */
407 if (code == BUS_MCEERR_AO) {
408 return 0;
409 } else {
410 hardware_memory_error();
411 }
412 }
413 kvm_hwpoison_page_add(ram_addr);
414 kvm_mce_inject(cpu, paddr, code);
415 } else {
416 if (code == BUS_MCEERR_AO) {
417 return 0;
418 } else if (code == BUS_MCEERR_AR) {
419 hardware_memory_error();
420 } else {
421 return 1;
422 }
423 }
424 return 0;
425 }
426
427 int kvm_arch_on_sigbus(int code, void *addr)
428 {
429 X86CPU *cpu = X86_CPU(first_cpu);
430
431 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
432 ram_addr_t ram_addr;
433 hwaddr paddr;
434
435 /* Hope we are lucky for AO MCE */
436 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
437 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
438 addr, &paddr)) {
439 fprintf(stderr, "Hardware memory error for memory used by "
440 "QEMU itself instead of guest system!: %p\n", addr);
441 return 0;
442 }
443 kvm_hwpoison_page_add(ram_addr);
444 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
445 } else {
446 if (code == BUS_MCEERR_AO) {
447 return 0;
448 } else if (code == BUS_MCEERR_AR) {
449 hardware_memory_error();
450 } else {
451 return 1;
452 }
453 }
454 return 0;
455 }
456
457 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
458 {
459 CPUX86State *env = &cpu->env;
460
461 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
462 unsigned int bank, bank_num = env->mcg_cap & 0xff;
463 struct kvm_x86_mce mce;
464
465 env->exception_injected = -1;
466
467 /*
468 * There must be at least one bank in use if an MCE is pending.
469 * Find it and use its values for the event injection.
470 */
471 for (bank = 0; bank < bank_num; bank++) {
472 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
473 break;
474 }
475 }
476 assert(bank < bank_num);
477
478 mce.bank = bank;
479 mce.status = env->mce_banks[bank * 4 + 1];
480 mce.mcg_status = env->mcg_status;
481 mce.addr = env->mce_banks[bank * 4 + 2];
482 mce.misc = env->mce_banks[bank * 4 + 3];
483
484 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
485 }
486 return 0;
487 }
488
489 static void cpu_update_state(void *opaque, int running, RunState state)
490 {
491 CPUX86State *env = opaque;
492
493 if (running) {
494 env->tsc_valid = false;
495 }
496 }
497
498 unsigned long kvm_arch_vcpu_id(CPUState *cs)
499 {
500 X86CPU *cpu = X86_CPU(cs);
501 return cpu->apic_id;
502 }
503
504 #ifndef KVM_CPUID_SIGNATURE_NEXT
505 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
506 #endif
507
508 static bool hyperv_hypercall_available(X86CPU *cpu)
509 {
510 return cpu->hyperv_vapic ||
511 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
512 }
513
514 static bool hyperv_enabled(X86CPU *cpu)
515 {
516 CPUState *cs = CPU(cpu);
517 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
518 (hyperv_hypercall_available(cpu) ||
519 cpu->hyperv_time ||
520 cpu->hyperv_relaxed_timing ||
521 cpu->hyperv_crash ||
522 cpu->hyperv_reset ||
523 cpu->hyperv_vpindex ||
524 cpu->hyperv_runtime);
525 }
526
527 static Error *invtsc_mig_blocker;
528
529 #define KVM_MAX_CPUID_ENTRIES 100
530
531 int kvm_arch_init_vcpu(CPUState *cs)
532 {
533 struct {
534 struct kvm_cpuid2 cpuid;
535 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
536 } QEMU_PACKED cpuid_data;
537 X86CPU *cpu = X86_CPU(cs);
538 CPUX86State *env = &cpu->env;
539 uint32_t limit, i, j, cpuid_i;
540 uint32_t unused;
541 struct kvm_cpuid_entry2 *c;
542 uint32_t signature[3];
543 int kvm_base = KVM_CPUID_SIGNATURE;
544 int r;
545
546 memset(&cpuid_data, 0, sizeof(cpuid_data));
547
548 cpuid_i = 0;
549
550 /* Paravirtualization CPUIDs */
551 if (hyperv_enabled(cpu)) {
552 c = &cpuid_data.entries[cpuid_i++];
553 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
554 if (!cpu->hyperv_vendor_id) {
555 memcpy(signature, "Microsoft Hv", 12);
556 } else {
557 size_t len = strlen(cpu->hyperv_vendor_id);
558
559 if (len > 12) {
560 error_report("hv-vendor-id truncated to 12 characters");
561 len = 12;
562 }
563 memset(signature, 0, 12);
564 memcpy(signature, cpu->hyperv_vendor_id, len);
565 }
566 c->eax = HYPERV_CPUID_MIN;
567 c->ebx = signature[0];
568 c->ecx = signature[1];
569 c->edx = signature[2];
570
571 c = &cpuid_data.entries[cpuid_i++];
572 c->function = HYPERV_CPUID_INTERFACE;
573 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
574 c->eax = signature[0];
575 c->ebx = 0;
576 c->ecx = 0;
577 c->edx = 0;
578
579 c = &cpuid_data.entries[cpuid_i++];
580 c->function = HYPERV_CPUID_VERSION;
581 c->eax = 0x00001bbc;
582 c->ebx = 0x00060001;
583
584 c = &cpuid_data.entries[cpuid_i++];
585 c->function = HYPERV_CPUID_FEATURES;
586 if (cpu->hyperv_relaxed_timing) {
587 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
588 }
589 if (cpu->hyperv_vapic) {
590 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
591 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
592 has_msr_hv_vapic = true;
593 }
594 if (cpu->hyperv_time &&
595 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
596 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
597 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
598 c->eax |= 0x200;
599 has_msr_hv_tsc = true;
600 }
601 if (cpu->hyperv_crash && has_msr_hv_crash) {
602 c->edx |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
603 }
604 if (cpu->hyperv_reset && has_msr_hv_reset) {
605 c->eax |= HV_X64_MSR_RESET_AVAILABLE;
606 }
607 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
608 c->eax |= HV_X64_MSR_VP_INDEX_AVAILABLE;
609 }
610 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
611 c->eax |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
612 }
613 c = &cpuid_data.entries[cpuid_i++];
614 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
615 if (cpu->hyperv_relaxed_timing) {
616 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
617 }
618 if (has_msr_hv_vapic) {
619 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
620 }
621 c->ebx = cpu->hyperv_spinlock_attempts;
622
623 c = &cpuid_data.entries[cpuid_i++];
624 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
625 c->eax = 0x40;
626 c->ebx = 0x40;
627
628 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
629 has_msr_hv_hypercall = true;
630 }
631
632 if (cpu->expose_kvm) {
633 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
634 c = &cpuid_data.entries[cpuid_i++];
635 c->function = KVM_CPUID_SIGNATURE | kvm_base;
636 c->eax = KVM_CPUID_FEATURES | kvm_base;
637 c->ebx = signature[0];
638 c->ecx = signature[1];
639 c->edx = signature[2];
640
641 c = &cpuid_data.entries[cpuid_i++];
642 c->function = KVM_CPUID_FEATURES | kvm_base;
643 c->eax = env->features[FEAT_KVM];
644
645 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
646
647 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
648
649 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
650 }
651
652 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
653
654 for (i = 0; i <= limit; i++) {
655 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
656 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
657 abort();
658 }
659 c = &cpuid_data.entries[cpuid_i++];
660
661 switch (i) {
662 case 2: {
663 /* Keep reading function 2 till all the input is received */
664 int times;
665
666 c->function = i;
667 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
668 KVM_CPUID_FLAG_STATE_READ_NEXT;
669 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
670 times = c->eax & 0xff;
671
672 for (j = 1; j < times; ++j) {
673 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
674 fprintf(stderr, "cpuid_data is full, no space for "
675 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
676 abort();
677 }
678 c = &cpuid_data.entries[cpuid_i++];
679 c->function = i;
680 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
681 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
682 }
683 break;
684 }
685 case 4:
686 case 0xb:
687 case 0xd:
688 for (j = 0; ; j++) {
689 if (i == 0xd && j == 64) {
690 break;
691 }
692 c->function = i;
693 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
694 c->index = j;
695 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
696
697 if (i == 4 && c->eax == 0) {
698 break;
699 }
700 if (i == 0xb && !(c->ecx & 0xff00)) {
701 break;
702 }
703 if (i == 0xd && c->eax == 0) {
704 continue;
705 }
706 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
707 fprintf(stderr, "cpuid_data is full, no space for "
708 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
709 abort();
710 }
711 c = &cpuid_data.entries[cpuid_i++];
712 }
713 break;
714 default:
715 c->function = i;
716 c->flags = 0;
717 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
718 break;
719 }
720 }
721
722 if (limit >= 0x0a) {
723 uint32_t ver;
724
725 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
726 if ((ver & 0xff) > 0) {
727 has_msr_architectural_pmu = true;
728 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
729
730 /* Shouldn't be more than 32, since that's the number of bits
731 * available in EBX to tell us _which_ counters are available.
732 * Play it safe.
733 */
734 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
735 num_architectural_pmu_counters = MAX_GP_COUNTERS;
736 }
737 }
738 }
739
740 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
741
742 for (i = 0x80000000; i <= limit; i++) {
743 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
744 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
745 abort();
746 }
747 c = &cpuid_data.entries[cpuid_i++];
748
749 c->function = i;
750 c->flags = 0;
751 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
752 }
753
754 /* Call Centaur's CPUID instructions they are supported. */
755 if (env->cpuid_xlevel2 > 0) {
756 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
757
758 for (i = 0xC0000000; i <= limit; i++) {
759 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
760 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
761 abort();
762 }
763 c = &cpuid_data.entries[cpuid_i++];
764
765 c->function = i;
766 c->flags = 0;
767 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
768 }
769 }
770
771 cpuid_data.cpuid.nent = cpuid_i;
772
773 if (((env->cpuid_version >> 8)&0xF) >= 6
774 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
775 (CPUID_MCE | CPUID_MCA)
776 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
777 uint64_t mcg_cap, unsupported_caps;
778 int banks;
779 int ret;
780
781 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
782 if (ret < 0) {
783 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
784 return ret;
785 }
786
787 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
788 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
789 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
790 return -ENOTSUP;
791 }
792
793 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
794 if (unsupported_caps) {
795 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
796 unsupported_caps);
797 }
798
799 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
800 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
801 if (ret < 0) {
802 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
803 return ret;
804 }
805 }
806
807 qemu_add_vm_change_state_handler(cpu_update_state, env);
808
809 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
810 if (c) {
811 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
812 !!(c->ecx & CPUID_EXT_SMX);
813 }
814
815 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
816 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
817 /* for migration */
818 error_setg(&invtsc_mig_blocker,
819 "State blocked by non-migratable CPU device"
820 " (invtsc flag)");
821 migrate_add_blocker(invtsc_mig_blocker);
822 /* for savevm */
823 vmstate_x86_cpu.unmigratable = 1;
824 }
825
826 cpuid_data.cpuid.padding = 0;
827 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
828 if (r) {
829 return r;
830 }
831
832 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
833 if (r && env->tsc_khz) {
834 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
835 if (r < 0) {
836 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
837 return r;
838 }
839 }
840
841 if (has_xsave) {
842 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
843 }
844
845 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
846 has_msr_mtrr = true;
847 }
848
849 return 0;
850 }
851
852 void kvm_arch_reset_vcpu(X86CPU *cpu)
853 {
854 CPUX86State *env = &cpu->env;
855
856 env->exception_injected = -1;
857 env->interrupt_injected = -1;
858 env->xcr0 = 1;
859 if (kvm_irqchip_in_kernel()) {
860 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
861 KVM_MP_STATE_UNINITIALIZED;
862 } else {
863 env->mp_state = KVM_MP_STATE_RUNNABLE;
864 }
865 }
866
867 void kvm_arch_do_init_vcpu(X86CPU *cpu)
868 {
869 CPUX86State *env = &cpu->env;
870
871 /* APs get directly into wait-for-SIPI state. */
872 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
873 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
874 }
875 }
876
877 static int kvm_get_supported_msrs(KVMState *s)
878 {
879 static int kvm_supported_msrs;
880 int ret = 0;
881
882 /* first time */
883 if (kvm_supported_msrs == 0) {
884 struct kvm_msr_list msr_list, *kvm_msr_list;
885
886 kvm_supported_msrs = -1;
887
888 /* Obtain MSR list from KVM. These are the MSRs that we must
889 * save/restore */
890 msr_list.nmsrs = 0;
891 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
892 if (ret < 0 && ret != -E2BIG) {
893 return ret;
894 }
895 /* Old kernel modules had a bug and could write beyond the provided
896 memory. Allocate at least a safe amount of 1K. */
897 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
898 msr_list.nmsrs *
899 sizeof(msr_list.indices[0])));
900
901 kvm_msr_list->nmsrs = msr_list.nmsrs;
902 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
903 if (ret >= 0) {
904 int i;
905
906 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
907 if (kvm_msr_list->indices[i] == MSR_STAR) {
908 has_msr_star = true;
909 continue;
910 }
911 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
912 has_msr_hsave_pa = true;
913 continue;
914 }
915 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
916 has_msr_tsc_aux = true;
917 continue;
918 }
919 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
920 has_msr_tsc_adjust = true;
921 continue;
922 }
923 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
924 has_msr_tsc_deadline = true;
925 continue;
926 }
927 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
928 has_msr_smbase = true;
929 continue;
930 }
931 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
932 has_msr_misc_enable = true;
933 continue;
934 }
935 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
936 has_msr_bndcfgs = true;
937 continue;
938 }
939 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
940 has_msr_xss = true;
941 continue;
942 }
943 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
944 has_msr_hv_crash = true;
945 continue;
946 }
947 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
948 has_msr_hv_reset = true;
949 continue;
950 }
951 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
952 has_msr_hv_vpindex = true;
953 continue;
954 }
955 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
956 has_msr_hv_runtime = true;
957 continue;
958 }
959 }
960 }
961
962 g_free(kvm_msr_list);
963 }
964
965 return ret;
966 }
967
968 static Notifier smram_machine_done;
969 static KVMMemoryListener smram_listener;
970 static AddressSpace smram_address_space;
971 static MemoryRegion smram_as_root;
972 static MemoryRegion smram_as_mem;
973
974 static void register_smram_listener(Notifier *n, void *unused)
975 {
976 MemoryRegion *smram =
977 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
978
979 /* Outer container... */
980 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
981 memory_region_set_enabled(&smram_as_root, true);
982
983 /* ... with two regions inside: normal system memory with low
984 * priority, and...
985 */
986 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
987 get_system_memory(), 0, ~0ull);
988 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
989 memory_region_set_enabled(&smram_as_mem, true);
990
991 if (smram) {
992 /* ... SMRAM with higher priority */
993 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
994 memory_region_set_enabled(smram, true);
995 }
996
997 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
998 kvm_memory_listener_register(kvm_state, &smram_listener,
999 &smram_address_space, 1);
1000 }
1001
1002 int kvm_arch_init(MachineState *ms, KVMState *s)
1003 {
1004 uint64_t identity_base = 0xfffbc000;
1005 uint64_t shadow_mem;
1006 int ret;
1007 struct utsname utsname;
1008
1009 #ifdef KVM_CAP_XSAVE
1010 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1011 #endif
1012
1013 #ifdef KVM_CAP_XCRS
1014 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1015 #endif
1016
1017 #ifdef KVM_CAP_PIT_STATE2
1018 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1019 #endif
1020
1021 ret = kvm_get_supported_msrs(s);
1022 if (ret < 0) {
1023 return ret;
1024 }
1025
1026 uname(&utsname);
1027 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1028
1029 /*
1030 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1031 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1032 * Since these must be part of guest physical memory, we need to allocate
1033 * them, both by setting their start addresses in the kernel and by
1034 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1035 *
1036 * Older KVM versions may not support setting the identity map base. In
1037 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1038 * size.
1039 */
1040 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1041 /* Allows up to 16M BIOSes. */
1042 identity_base = 0xfeffc000;
1043
1044 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1045 if (ret < 0) {
1046 return ret;
1047 }
1048 }
1049
1050 /* Set TSS base one page after EPT identity map. */
1051 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1052 if (ret < 0) {
1053 return ret;
1054 }
1055
1056 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1057 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1058 if (ret < 0) {
1059 fprintf(stderr, "e820_add_entry() table is full\n");
1060 return ret;
1061 }
1062 qemu_register_reset(kvm_unpoison_all, NULL);
1063
1064 shadow_mem = machine_kvm_shadow_mem(ms);
1065 if (shadow_mem != -1) {
1066 shadow_mem /= 4096;
1067 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1068 if (ret < 0) {
1069 return ret;
1070 }
1071 }
1072
1073 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1074 smram_machine_done.notify = register_smram_listener;
1075 qemu_add_machine_init_done_notifier(&smram_machine_done);
1076 }
1077 return 0;
1078 }
1079
1080 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1081 {
1082 lhs->selector = rhs->selector;
1083 lhs->base = rhs->base;
1084 lhs->limit = rhs->limit;
1085 lhs->type = 3;
1086 lhs->present = 1;
1087 lhs->dpl = 3;
1088 lhs->db = 0;
1089 lhs->s = 1;
1090 lhs->l = 0;
1091 lhs->g = 0;
1092 lhs->avl = 0;
1093 lhs->unusable = 0;
1094 }
1095
1096 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1097 {
1098 unsigned flags = rhs->flags;
1099 lhs->selector = rhs->selector;
1100 lhs->base = rhs->base;
1101 lhs->limit = rhs->limit;
1102 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1103 lhs->present = (flags & DESC_P_MASK) != 0;
1104 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1105 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1106 lhs->s = (flags & DESC_S_MASK) != 0;
1107 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1108 lhs->g = (flags & DESC_G_MASK) != 0;
1109 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1110 lhs->unusable = 0;
1111 lhs->padding = 0;
1112 }
1113
1114 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1115 {
1116 lhs->selector = rhs->selector;
1117 lhs->base = rhs->base;
1118 lhs->limit = rhs->limit;
1119 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1120 (rhs->present * DESC_P_MASK) |
1121 (rhs->dpl << DESC_DPL_SHIFT) |
1122 (rhs->db << DESC_B_SHIFT) |
1123 (rhs->s * DESC_S_MASK) |
1124 (rhs->l << DESC_L_SHIFT) |
1125 (rhs->g * DESC_G_MASK) |
1126 (rhs->avl * DESC_AVL_MASK);
1127 }
1128
1129 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1130 {
1131 if (set) {
1132 *kvm_reg = *qemu_reg;
1133 } else {
1134 *qemu_reg = *kvm_reg;
1135 }
1136 }
1137
1138 static int kvm_getput_regs(X86CPU *cpu, int set)
1139 {
1140 CPUX86State *env = &cpu->env;
1141 struct kvm_regs regs;
1142 int ret = 0;
1143
1144 if (!set) {
1145 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1146 if (ret < 0) {
1147 return ret;
1148 }
1149 }
1150
1151 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1152 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1153 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1154 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1155 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1156 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1157 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1158 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1159 #ifdef TARGET_X86_64
1160 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1161 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1162 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1163 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1164 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1165 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1166 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1167 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1168 #endif
1169
1170 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1171 kvm_getput_reg(&regs.rip, &env->eip, set);
1172
1173 if (set) {
1174 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1175 }
1176
1177 return ret;
1178 }
1179
1180 static int kvm_put_fpu(X86CPU *cpu)
1181 {
1182 CPUX86State *env = &cpu->env;
1183 struct kvm_fpu fpu;
1184 int i;
1185
1186 memset(&fpu, 0, sizeof fpu);
1187 fpu.fsw = env->fpus & ~(7 << 11);
1188 fpu.fsw |= (env->fpstt & 7) << 11;
1189 fpu.fcw = env->fpuc;
1190 fpu.last_opcode = env->fpop;
1191 fpu.last_ip = env->fpip;
1192 fpu.last_dp = env->fpdp;
1193 for (i = 0; i < 8; ++i) {
1194 fpu.ftwx |= (!env->fptags[i]) << i;
1195 }
1196 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1197 for (i = 0; i < CPU_NB_REGS; i++) {
1198 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].XMM_Q(0));
1199 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].XMM_Q(1));
1200 }
1201 fpu.mxcsr = env->mxcsr;
1202
1203 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1204 }
1205
1206 #define XSAVE_FCW_FSW 0
1207 #define XSAVE_FTW_FOP 1
1208 #define XSAVE_CWD_RIP 2
1209 #define XSAVE_CWD_RDP 4
1210 #define XSAVE_MXCSR 6
1211 #define XSAVE_ST_SPACE 8
1212 #define XSAVE_XMM_SPACE 40
1213 #define XSAVE_XSTATE_BV 128
1214 #define XSAVE_YMMH_SPACE 144
1215 #define XSAVE_BNDREGS 240
1216 #define XSAVE_BNDCSR 256
1217 #define XSAVE_OPMASK 272
1218 #define XSAVE_ZMM_Hi256 288
1219 #define XSAVE_Hi16_ZMM 416
1220
1221 static int kvm_put_xsave(X86CPU *cpu)
1222 {
1223 CPUX86State *env = &cpu->env;
1224 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1225 uint16_t cwd, swd, twd;
1226 uint8_t *xmm, *ymmh, *zmmh;
1227 int i, r;
1228
1229 if (!has_xsave) {
1230 return kvm_put_fpu(cpu);
1231 }
1232
1233 memset(xsave, 0, sizeof(struct kvm_xsave));
1234 twd = 0;
1235 swd = env->fpus & ~(7 << 11);
1236 swd |= (env->fpstt & 7) << 11;
1237 cwd = env->fpuc;
1238 for (i = 0; i < 8; ++i) {
1239 twd |= (!env->fptags[i]) << i;
1240 }
1241 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1242 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
1243 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1244 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
1245 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1246 sizeof env->fpregs);
1247 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1248 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
1249 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1250 sizeof env->bnd_regs);
1251 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1252 sizeof(env->bndcs_regs));
1253 memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs,
1254 sizeof env->opmask_regs);
1255
1256 xmm = (uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
1257 ymmh = (uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1258 zmmh = (uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1259 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
1260 stq_p(xmm, env->xmm_regs[i].XMM_Q(0));
1261 stq_p(xmm+8, env->xmm_regs[i].XMM_Q(1));
1262 stq_p(ymmh, env->xmm_regs[i].XMM_Q(2));
1263 stq_p(ymmh+8, env->xmm_regs[i].XMM_Q(3));
1264 stq_p(zmmh, env->xmm_regs[i].XMM_Q(4));
1265 stq_p(zmmh+8, env->xmm_regs[i].XMM_Q(5));
1266 stq_p(zmmh+16, env->xmm_regs[i].XMM_Q(6));
1267 stq_p(zmmh+24, env->xmm_regs[i].XMM_Q(7));
1268 }
1269
1270 #ifdef TARGET_X86_64
1271 memcpy(&xsave->region[XSAVE_Hi16_ZMM], &env->xmm_regs[16],
1272 16 * sizeof env->xmm_regs[16]);
1273 #endif
1274 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1275 return r;
1276 }
1277
1278 static int kvm_put_xcrs(X86CPU *cpu)
1279 {
1280 CPUX86State *env = &cpu->env;
1281 struct kvm_xcrs xcrs = {};
1282
1283 if (!has_xcrs) {
1284 return 0;
1285 }
1286
1287 xcrs.nr_xcrs = 1;
1288 xcrs.flags = 0;
1289 xcrs.xcrs[0].xcr = 0;
1290 xcrs.xcrs[0].value = env->xcr0;
1291 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1292 }
1293
1294 static int kvm_put_sregs(X86CPU *cpu)
1295 {
1296 CPUX86State *env = &cpu->env;
1297 struct kvm_sregs sregs;
1298
1299 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1300 if (env->interrupt_injected >= 0) {
1301 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1302 (uint64_t)1 << (env->interrupt_injected % 64);
1303 }
1304
1305 if ((env->eflags & VM_MASK)) {
1306 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1307 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1308 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1309 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1310 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1311 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1312 } else {
1313 set_seg(&sregs.cs, &env->segs[R_CS]);
1314 set_seg(&sregs.ds, &env->segs[R_DS]);
1315 set_seg(&sregs.es, &env->segs[R_ES]);
1316 set_seg(&sregs.fs, &env->segs[R_FS]);
1317 set_seg(&sregs.gs, &env->segs[R_GS]);
1318 set_seg(&sregs.ss, &env->segs[R_SS]);
1319 }
1320
1321 set_seg(&sregs.tr, &env->tr);
1322 set_seg(&sregs.ldt, &env->ldt);
1323
1324 sregs.idt.limit = env->idt.limit;
1325 sregs.idt.base = env->idt.base;
1326 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1327 sregs.gdt.limit = env->gdt.limit;
1328 sregs.gdt.base = env->gdt.base;
1329 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1330
1331 sregs.cr0 = env->cr[0];
1332 sregs.cr2 = env->cr[2];
1333 sregs.cr3 = env->cr[3];
1334 sregs.cr4 = env->cr[4];
1335
1336 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1337 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1338
1339 sregs.efer = env->efer;
1340
1341 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1342 }
1343
1344 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1345 uint32_t index, uint64_t value)
1346 {
1347 entry->index = index;
1348 entry->reserved = 0;
1349 entry->data = value;
1350 }
1351
1352 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1353 {
1354 CPUX86State *env = &cpu->env;
1355 struct {
1356 struct kvm_msrs info;
1357 struct kvm_msr_entry entries[1];
1358 } msr_data;
1359 struct kvm_msr_entry *msrs = msr_data.entries;
1360
1361 if (!has_msr_tsc_deadline) {
1362 return 0;
1363 }
1364
1365 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1366
1367 msr_data.info = (struct kvm_msrs) {
1368 .nmsrs = 1,
1369 };
1370
1371 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1372 }
1373
1374 /*
1375 * Provide a separate write service for the feature control MSR in order to
1376 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1377 * before writing any other state because forcibly leaving nested mode
1378 * invalidates the VCPU state.
1379 */
1380 static int kvm_put_msr_feature_control(X86CPU *cpu)
1381 {
1382 struct {
1383 struct kvm_msrs info;
1384 struct kvm_msr_entry entry;
1385 } msr_data;
1386
1387 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1388 cpu->env.msr_ia32_feature_control);
1389
1390 msr_data.info = (struct kvm_msrs) {
1391 .nmsrs = 1,
1392 };
1393
1394 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1395 }
1396
1397 static int kvm_put_msrs(X86CPU *cpu, int level)
1398 {
1399 CPUX86State *env = &cpu->env;
1400 struct {
1401 struct kvm_msrs info;
1402 struct kvm_msr_entry entries[150];
1403 } msr_data;
1404 struct kvm_msr_entry *msrs = msr_data.entries;
1405 int n = 0, i;
1406
1407 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1408 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1409 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1410 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1411 if (has_msr_star) {
1412 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1413 }
1414 if (has_msr_hsave_pa) {
1415 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1416 }
1417 if (has_msr_tsc_aux) {
1418 kvm_msr_entry_set(&msrs[n++], MSR_TSC_AUX, env->tsc_aux);
1419 }
1420 if (has_msr_tsc_adjust) {
1421 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1422 }
1423 if (has_msr_misc_enable) {
1424 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1425 env->msr_ia32_misc_enable);
1426 }
1427 if (has_msr_smbase) {
1428 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SMBASE, env->smbase);
1429 }
1430 if (has_msr_bndcfgs) {
1431 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1432 }
1433 if (has_msr_xss) {
1434 kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
1435 }
1436 #ifdef TARGET_X86_64
1437 if (lm_capable_kernel) {
1438 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1439 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1440 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1441 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1442 }
1443 #endif
1444 /*
1445 * The following MSRs have side effects on the guest or are too heavy
1446 * for normal writeback. Limit them to reset or full state updates.
1447 */
1448 if (level >= KVM_PUT_RESET_STATE) {
1449 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1450 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1451 env->system_time_msr);
1452 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1453 if (has_msr_async_pf_en) {
1454 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1455 env->async_pf_en_msr);
1456 }
1457 if (has_msr_pv_eoi_en) {
1458 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1459 env->pv_eoi_en_msr);
1460 }
1461 if (has_msr_kvm_steal_time) {
1462 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1463 env->steal_time_msr);
1464 }
1465 if (has_msr_architectural_pmu) {
1466 /* Stop the counter. */
1467 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1468 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1469
1470 /* Set the counter values. */
1471 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1472 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1473 env->msr_fixed_counters[i]);
1474 }
1475 for (i = 0; i < num_architectural_pmu_counters; i++) {
1476 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1477 env->msr_gp_counters[i]);
1478 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1479 env->msr_gp_evtsel[i]);
1480 }
1481 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1482 env->msr_global_status);
1483 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1484 env->msr_global_ovf_ctrl);
1485
1486 /* Now start the PMU. */
1487 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1488 env->msr_fixed_ctr_ctrl);
1489 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1490 env->msr_global_ctrl);
1491 }
1492 if (has_msr_hv_hypercall) {
1493 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1494 env->msr_hv_guest_os_id);
1495 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1496 env->msr_hv_hypercall);
1497 }
1498 if (has_msr_hv_vapic) {
1499 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1500 env->msr_hv_vapic);
1501 }
1502 if (has_msr_hv_tsc) {
1503 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1504 env->msr_hv_tsc);
1505 }
1506 if (has_msr_hv_crash) {
1507 int j;
1508
1509 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1510 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_P0 + j,
1511 env->msr_hv_crash_params[j]);
1512
1513 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_CTL,
1514 HV_X64_MSR_CRASH_CTL_NOTIFY);
1515 }
1516 if (has_msr_hv_runtime) {
1517 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_VP_RUNTIME,
1518 env->msr_hv_runtime);
1519 }
1520 if (has_msr_mtrr) {
1521 kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype);
1522 kvm_msr_entry_set(&msrs[n++],
1523 MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1524 kvm_msr_entry_set(&msrs[n++],
1525 MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1526 kvm_msr_entry_set(&msrs[n++],
1527 MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1528 kvm_msr_entry_set(&msrs[n++],
1529 MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1530 kvm_msr_entry_set(&msrs[n++],
1531 MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1532 kvm_msr_entry_set(&msrs[n++],
1533 MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1534 kvm_msr_entry_set(&msrs[n++],
1535 MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1536 kvm_msr_entry_set(&msrs[n++],
1537 MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1538 kvm_msr_entry_set(&msrs[n++],
1539 MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1540 kvm_msr_entry_set(&msrs[n++],
1541 MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1542 kvm_msr_entry_set(&msrs[n++],
1543 MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1544 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1545 kvm_msr_entry_set(&msrs[n++],
1546 MSR_MTRRphysBase(i), env->mtrr_var[i].base);
1547 kvm_msr_entry_set(&msrs[n++],
1548 MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
1549 }
1550 }
1551
1552 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1553 * kvm_put_msr_feature_control. */
1554 }
1555 if (env->mcg_cap) {
1556 int i;
1557
1558 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1559 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1560 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1561 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1562 }
1563 }
1564
1565 msr_data.info = (struct kvm_msrs) {
1566 .nmsrs = n,
1567 };
1568
1569 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1570
1571 }
1572
1573
1574 static int kvm_get_fpu(X86CPU *cpu)
1575 {
1576 CPUX86State *env = &cpu->env;
1577 struct kvm_fpu fpu;
1578 int i, ret;
1579
1580 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1581 if (ret < 0) {
1582 return ret;
1583 }
1584
1585 env->fpstt = (fpu.fsw >> 11) & 7;
1586 env->fpus = fpu.fsw;
1587 env->fpuc = fpu.fcw;
1588 env->fpop = fpu.last_opcode;
1589 env->fpip = fpu.last_ip;
1590 env->fpdp = fpu.last_dp;
1591 for (i = 0; i < 8; ++i) {
1592 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1593 }
1594 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1595 for (i = 0; i < CPU_NB_REGS; i++) {
1596 env->xmm_regs[i].XMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1597 env->xmm_regs[i].XMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1598 }
1599 env->mxcsr = fpu.mxcsr;
1600
1601 return 0;
1602 }
1603
1604 static int kvm_get_xsave(X86CPU *cpu)
1605 {
1606 CPUX86State *env = &cpu->env;
1607 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1608 int ret, i;
1609 const uint8_t *xmm, *ymmh, *zmmh;
1610 uint16_t cwd, swd, twd;
1611
1612 if (!has_xsave) {
1613 return kvm_get_fpu(cpu);
1614 }
1615
1616 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1617 if (ret < 0) {
1618 return ret;
1619 }
1620
1621 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1622 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1623 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1624 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1625 env->fpstt = (swd >> 11) & 7;
1626 env->fpus = swd;
1627 env->fpuc = cwd;
1628 for (i = 0; i < 8; ++i) {
1629 env->fptags[i] = !((twd >> i) & 1);
1630 }
1631 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1632 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1633 env->mxcsr = xsave->region[XSAVE_MXCSR];
1634 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1635 sizeof env->fpregs);
1636 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1637 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1638 sizeof env->bnd_regs);
1639 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1640 sizeof(env->bndcs_regs));
1641 memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK],
1642 sizeof env->opmask_regs);
1643
1644 xmm = (const uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
1645 ymmh = (const uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1646 zmmh = (const uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1647 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
1648 env->xmm_regs[i].XMM_Q(0) = ldq_p(xmm);
1649 env->xmm_regs[i].XMM_Q(1) = ldq_p(xmm+8);
1650 env->xmm_regs[i].XMM_Q(2) = ldq_p(ymmh);
1651 env->xmm_regs[i].XMM_Q(3) = ldq_p(ymmh+8);
1652 env->xmm_regs[i].XMM_Q(4) = ldq_p(zmmh);
1653 env->xmm_regs[i].XMM_Q(5) = ldq_p(zmmh+8);
1654 env->xmm_regs[i].XMM_Q(6) = ldq_p(zmmh+16);
1655 env->xmm_regs[i].XMM_Q(7) = ldq_p(zmmh+24);
1656 }
1657
1658 #ifdef TARGET_X86_64
1659 memcpy(&env->xmm_regs[16], &xsave->region[XSAVE_Hi16_ZMM],
1660 16 * sizeof env->xmm_regs[16]);
1661 #endif
1662 return 0;
1663 }
1664
1665 static int kvm_get_xcrs(X86CPU *cpu)
1666 {
1667 CPUX86State *env = &cpu->env;
1668 int i, ret;
1669 struct kvm_xcrs xcrs;
1670
1671 if (!has_xcrs) {
1672 return 0;
1673 }
1674
1675 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1676 if (ret < 0) {
1677 return ret;
1678 }
1679
1680 for (i = 0; i < xcrs.nr_xcrs; i++) {
1681 /* Only support xcr0 now */
1682 if (xcrs.xcrs[i].xcr == 0) {
1683 env->xcr0 = xcrs.xcrs[i].value;
1684 break;
1685 }
1686 }
1687 return 0;
1688 }
1689
1690 static int kvm_get_sregs(X86CPU *cpu)
1691 {
1692 CPUX86State *env = &cpu->env;
1693 struct kvm_sregs sregs;
1694 uint32_t hflags;
1695 int bit, i, ret;
1696
1697 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1698 if (ret < 0) {
1699 return ret;
1700 }
1701
1702 /* There can only be one pending IRQ set in the bitmap at a time, so try
1703 to find it and save its number instead (-1 for none). */
1704 env->interrupt_injected = -1;
1705 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1706 if (sregs.interrupt_bitmap[i]) {
1707 bit = ctz64(sregs.interrupt_bitmap[i]);
1708 env->interrupt_injected = i * 64 + bit;
1709 break;
1710 }
1711 }
1712
1713 get_seg(&env->segs[R_CS], &sregs.cs);
1714 get_seg(&env->segs[R_DS], &sregs.ds);
1715 get_seg(&env->segs[R_ES], &sregs.es);
1716 get_seg(&env->segs[R_FS], &sregs.fs);
1717 get_seg(&env->segs[R_GS], &sregs.gs);
1718 get_seg(&env->segs[R_SS], &sregs.ss);
1719
1720 get_seg(&env->tr, &sregs.tr);
1721 get_seg(&env->ldt, &sregs.ldt);
1722
1723 env->idt.limit = sregs.idt.limit;
1724 env->idt.base = sregs.idt.base;
1725 env->gdt.limit = sregs.gdt.limit;
1726 env->gdt.base = sregs.gdt.base;
1727
1728 env->cr[0] = sregs.cr0;
1729 env->cr[2] = sregs.cr2;
1730 env->cr[3] = sregs.cr3;
1731 env->cr[4] = sregs.cr4;
1732
1733 env->efer = sregs.efer;
1734
1735 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1736
1737 #define HFLAG_COPY_MASK \
1738 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1739 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1740 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1741 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1742
1743 hflags = (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1744 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1745 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1746 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1747 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1748 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1749 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1750
1751 if (env->efer & MSR_EFER_LMA) {
1752 hflags |= HF_LMA_MASK;
1753 }
1754
1755 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1756 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1757 } else {
1758 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1759 (DESC_B_SHIFT - HF_CS32_SHIFT);
1760 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1761 (DESC_B_SHIFT - HF_SS32_SHIFT);
1762 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1763 !(hflags & HF_CS32_MASK)) {
1764 hflags |= HF_ADDSEG_MASK;
1765 } else {
1766 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1767 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1768 }
1769 }
1770 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1771
1772 return 0;
1773 }
1774
1775 static int kvm_get_msrs(X86CPU *cpu)
1776 {
1777 CPUX86State *env = &cpu->env;
1778 struct {
1779 struct kvm_msrs info;
1780 struct kvm_msr_entry entries[150];
1781 } msr_data;
1782 struct kvm_msr_entry *msrs = msr_data.entries;
1783 int ret, i, n;
1784
1785 n = 0;
1786 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1787 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1788 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1789 msrs[n++].index = MSR_PAT;
1790 if (has_msr_star) {
1791 msrs[n++].index = MSR_STAR;
1792 }
1793 if (has_msr_hsave_pa) {
1794 msrs[n++].index = MSR_VM_HSAVE_PA;
1795 }
1796 if (has_msr_tsc_aux) {
1797 msrs[n++].index = MSR_TSC_AUX;
1798 }
1799 if (has_msr_tsc_adjust) {
1800 msrs[n++].index = MSR_TSC_ADJUST;
1801 }
1802 if (has_msr_tsc_deadline) {
1803 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1804 }
1805 if (has_msr_misc_enable) {
1806 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1807 }
1808 if (has_msr_smbase) {
1809 msrs[n++].index = MSR_IA32_SMBASE;
1810 }
1811 if (has_msr_feature_control) {
1812 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1813 }
1814 if (has_msr_bndcfgs) {
1815 msrs[n++].index = MSR_IA32_BNDCFGS;
1816 }
1817 if (has_msr_xss) {
1818 msrs[n++].index = MSR_IA32_XSS;
1819 }
1820
1821
1822 if (!env->tsc_valid) {
1823 msrs[n++].index = MSR_IA32_TSC;
1824 env->tsc_valid = !runstate_is_running();
1825 }
1826
1827 #ifdef TARGET_X86_64
1828 if (lm_capable_kernel) {
1829 msrs[n++].index = MSR_CSTAR;
1830 msrs[n++].index = MSR_KERNELGSBASE;
1831 msrs[n++].index = MSR_FMASK;
1832 msrs[n++].index = MSR_LSTAR;
1833 }
1834 #endif
1835 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1836 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1837 if (has_msr_async_pf_en) {
1838 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1839 }
1840 if (has_msr_pv_eoi_en) {
1841 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1842 }
1843 if (has_msr_kvm_steal_time) {
1844 msrs[n++].index = MSR_KVM_STEAL_TIME;
1845 }
1846 if (has_msr_architectural_pmu) {
1847 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1848 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1849 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1850 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1851 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1852 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1853 }
1854 for (i = 0; i < num_architectural_pmu_counters; i++) {
1855 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1856 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1857 }
1858 }
1859
1860 if (env->mcg_cap) {
1861 msrs[n++].index = MSR_MCG_STATUS;
1862 msrs[n++].index = MSR_MCG_CTL;
1863 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1864 msrs[n++].index = MSR_MC0_CTL + i;
1865 }
1866 }
1867
1868 if (has_msr_hv_hypercall) {
1869 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1870 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1871 }
1872 if (has_msr_hv_vapic) {
1873 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1874 }
1875 if (has_msr_hv_tsc) {
1876 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
1877 }
1878 if (has_msr_hv_crash) {
1879 int j;
1880
1881 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
1882 msrs[n++].index = HV_X64_MSR_CRASH_P0 + j;
1883 }
1884 }
1885 if (has_msr_hv_runtime) {
1886 msrs[n++].index = HV_X64_MSR_VP_RUNTIME;
1887 }
1888 if (has_msr_mtrr) {
1889 msrs[n++].index = MSR_MTRRdefType;
1890 msrs[n++].index = MSR_MTRRfix64K_00000;
1891 msrs[n++].index = MSR_MTRRfix16K_80000;
1892 msrs[n++].index = MSR_MTRRfix16K_A0000;
1893 msrs[n++].index = MSR_MTRRfix4K_C0000;
1894 msrs[n++].index = MSR_MTRRfix4K_C8000;
1895 msrs[n++].index = MSR_MTRRfix4K_D0000;
1896 msrs[n++].index = MSR_MTRRfix4K_D8000;
1897 msrs[n++].index = MSR_MTRRfix4K_E0000;
1898 msrs[n++].index = MSR_MTRRfix4K_E8000;
1899 msrs[n++].index = MSR_MTRRfix4K_F0000;
1900 msrs[n++].index = MSR_MTRRfix4K_F8000;
1901 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1902 msrs[n++].index = MSR_MTRRphysBase(i);
1903 msrs[n++].index = MSR_MTRRphysMask(i);
1904 }
1905 }
1906
1907 msr_data.info = (struct kvm_msrs) {
1908 .nmsrs = n,
1909 };
1910
1911 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1912 if (ret < 0) {
1913 return ret;
1914 }
1915
1916 for (i = 0; i < ret; i++) {
1917 uint32_t index = msrs[i].index;
1918 switch (index) {
1919 case MSR_IA32_SYSENTER_CS:
1920 env->sysenter_cs = msrs[i].data;
1921 break;
1922 case MSR_IA32_SYSENTER_ESP:
1923 env->sysenter_esp = msrs[i].data;
1924 break;
1925 case MSR_IA32_SYSENTER_EIP:
1926 env->sysenter_eip = msrs[i].data;
1927 break;
1928 case MSR_PAT:
1929 env->pat = msrs[i].data;
1930 break;
1931 case MSR_STAR:
1932 env->star = msrs[i].data;
1933 break;
1934 #ifdef TARGET_X86_64
1935 case MSR_CSTAR:
1936 env->cstar = msrs[i].data;
1937 break;
1938 case MSR_KERNELGSBASE:
1939 env->kernelgsbase = msrs[i].data;
1940 break;
1941 case MSR_FMASK:
1942 env->fmask = msrs[i].data;
1943 break;
1944 case MSR_LSTAR:
1945 env->lstar = msrs[i].data;
1946 break;
1947 #endif
1948 case MSR_IA32_TSC:
1949 env->tsc = msrs[i].data;
1950 break;
1951 case MSR_TSC_AUX:
1952 env->tsc_aux = msrs[i].data;
1953 break;
1954 case MSR_TSC_ADJUST:
1955 env->tsc_adjust = msrs[i].data;
1956 break;
1957 case MSR_IA32_TSCDEADLINE:
1958 env->tsc_deadline = msrs[i].data;
1959 break;
1960 case MSR_VM_HSAVE_PA:
1961 env->vm_hsave = msrs[i].data;
1962 break;
1963 case MSR_KVM_SYSTEM_TIME:
1964 env->system_time_msr = msrs[i].data;
1965 break;
1966 case MSR_KVM_WALL_CLOCK:
1967 env->wall_clock_msr = msrs[i].data;
1968 break;
1969 case MSR_MCG_STATUS:
1970 env->mcg_status = msrs[i].data;
1971 break;
1972 case MSR_MCG_CTL:
1973 env->mcg_ctl = msrs[i].data;
1974 break;
1975 case MSR_IA32_MISC_ENABLE:
1976 env->msr_ia32_misc_enable = msrs[i].data;
1977 break;
1978 case MSR_IA32_SMBASE:
1979 env->smbase = msrs[i].data;
1980 break;
1981 case MSR_IA32_FEATURE_CONTROL:
1982 env->msr_ia32_feature_control = msrs[i].data;
1983 break;
1984 case MSR_IA32_BNDCFGS:
1985 env->msr_bndcfgs = msrs[i].data;
1986 break;
1987 case MSR_IA32_XSS:
1988 env->xss = msrs[i].data;
1989 break;
1990 default:
1991 if (msrs[i].index >= MSR_MC0_CTL &&
1992 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1993 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1994 }
1995 break;
1996 case MSR_KVM_ASYNC_PF_EN:
1997 env->async_pf_en_msr = msrs[i].data;
1998 break;
1999 case MSR_KVM_PV_EOI_EN:
2000 env->pv_eoi_en_msr = msrs[i].data;
2001 break;
2002 case MSR_KVM_STEAL_TIME:
2003 env->steal_time_msr = msrs[i].data;
2004 break;
2005 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2006 env->msr_fixed_ctr_ctrl = msrs[i].data;
2007 break;
2008 case MSR_CORE_PERF_GLOBAL_CTRL:
2009 env->msr_global_ctrl = msrs[i].data;
2010 break;
2011 case MSR_CORE_PERF_GLOBAL_STATUS:
2012 env->msr_global_status = msrs[i].data;
2013 break;
2014 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2015 env->msr_global_ovf_ctrl = msrs[i].data;
2016 break;
2017 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2018 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2019 break;
2020 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2021 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2022 break;
2023 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2024 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2025 break;
2026 case HV_X64_MSR_HYPERCALL:
2027 env->msr_hv_hypercall = msrs[i].data;
2028 break;
2029 case HV_X64_MSR_GUEST_OS_ID:
2030 env->msr_hv_guest_os_id = msrs[i].data;
2031 break;
2032 case HV_X64_MSR_APIC_ASSIST_PAGE:
2033 env->msr_hv_vapic = msrs[i].data;
2034 break;
2035 case HV_X64_MSR_REFERENCE_TSC:
2036 env->msr_hv_tsc = msrs[i].data;
2037 break;
2038 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2039 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2040 break;
2041 case HV_X64_MSR_VP_RUNTIME:
2042 env->msr_hv_runtime = msrs[i].data;
2043 break;
2044 case MSR_MTRRdefType:
2045 env->mtrr_deftype = msrs[i].data;
2046 break;
2047 case MSR_MTRRfix64K_00000:
2048 env->mtrr_fixed[0] = msrs[i].data;
2049 break;
2050 case MSR_MTRRfix16K_80000:
2051 env->mtrr_fixed[1] = msrs[i].data;
2052 break;
2053 case MSR_MTRRfix16K_A0000:
2054 env->mtrr_fixed[2] = msrs[i].data;
2055 break;
2056 case MSR_MTRRfix4K_C0000:
2057 env->mtrr_fixed[3] = msrs[i].data;
2058 break;
2059 case MSR_MTRRfix4K_C8000:
2060 env->mtrr_fixed[4] = msrs[i].data;
2061 break;
2062 case MSR_MTRRfix4K_D0000:
2063 env->mtrr_fixed[5] = msrs[i].data;
2064 break;
2065 case MSR_MTRRfix4K_D8000:
2066 env->mtrr_fixed[6] = msrs[i].data;
2067 break;
2068 case MSR_MTRRfix4K_E0000:
2069 env->mtrr_fixed[7] = msrs[i].data;
2070 break;
2071 case MSR_MTRRfix4K_E8000:
2072 env->mtrr_fixed[8] = msrs[i].data;
2073 break;
2074 case MSR_MTRRfix4K_F0000:
2075 env->mtrr_fixed[9] = msrs[i].data;
2076 break;
2077 case MSR_MTRRfix4K_F8000:
2078 env->mtrr_fixed[10] = msrs[i].data;
2079 break;
2080 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2081 if (index & 1) {
2082 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
2083 } else {
2084 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2085 }
2086 break;
2087 }
2088 }
2089
2090 return 0;
2091 }
2092
2093 static int kvm_put_mp_state(X86CPU *cpu)
2094 {
2095 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2096
2097 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2098 }
2099
2100 static int kvm_get_mp_state(X86CPU *cpu)
2101 {
2102 CPUState *cs = CPU(cpu);
2103 CPUX86State *env = &cpu->env;
2104 struct kvm_mp_state mp_state;
2105 int ret;
2106
2107 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2108 if (ret < 0) {
2109 return ret;
2110 }
2111 env->mp_state = mp_state.mp_state;
2112 if (kvm_irqchip_in_kernel()) {
2113 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2114 }
2115 return 0;
2116 }
2117
2118 static int kvm_get_apic(X86CPU *cpu)
2119 {
2120 DeviceState *apic = cpu->apic_state;
2121 struct kvm_lapic_state kapic;
2122 int ret;
2123
2124 if (apic && kvm_irqchip_in_kernel()) {
2125 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2126 if (ret < 0) {
2127 return ret;
2128 }
2129
2130 kvm_get_apic_state(apic, &kapic);
2131 }
2132 return 0;
2133 }
2134
2135 static int kvm_put_apic(X86CPU *cpu)
2136 {
2137 DeviceState *apic = cpu->apic_state;
2138 struct kvm_lapic_state kapic;
2139
2140 if (apic && kvm_irqchip_in_kernel()) {
2141 kvm_put_apic_state(apic, &kapic);
2142
2143 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
2144 }
2145 return 0;
2146 }
2147
2148 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2149 {
2150 CPUState *cs = CPU(cpu);
2151 CPUX86State *env = &cpu->env;
2152 struct kvm_vcpu_events events = {};
2153
2154 if (!kvm_has_vcpu_events()) {
2155 return 0;
2156 }
2157
2158 events.exception.injected = (env->exception_injected >= 0);
2159 events.exception.nr = env->exception_injected;
2160 events.exception.has_error_code = env->has_error_code;
2161 events.exception.error_code = env->error_code;
2162 events.exception.pad = 0;
2163
2164 events.interrupt.injected = (env->interrupt_injected >= 0);
2165 events.interrupt.nr = env->interrupt_injected;
2166 events.interrupt.soft = env->soft_interrupt;
2167
2168 events.nmi.injected = env->nmi_injected;
2169 events.nmi.pending = env->nmi_pending;
2170 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2171 events.nmi.pad = 0;
2172
2173 events.sipi_vector = env->sipi_vector;
2174
2175 if (has_msr_smbase) {
2176 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2177 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2178 if (kvm_irqchip_in_kernel()) {
2179 /* As soon as these are moved to the kernel, remove them
2180 * from cs->interrupt_request.
2181 */
2182 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2183 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2184 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2185 } else {
2186 /* Keep these in cs->interrupt_request. */
2187 events.smi.pending = 0;
2188 events.smi.latched_init = 0;
2189 }
2190 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2191 }
2192
2193 events.flags = 0;
2194 if (level >= KVM_PUT_RESET_STATE) {
2195 events.flags |=
2196 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2197 }
2198
2199 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2200 }
2201
2202 static int kvm_get_vcpu_events(X86CPU *cpu)
2203 {
2204 CPUX86State *env = &cpu->env;
2205 struct kvm_vcpu_events events;
2206 int ret;
2207
2208 if (!kvm_has_vcpu_events()) {
2209 return 0;
2210 }
2211
2212 memset(&events, 0, sizeof(events));
2213 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2214 if (ret < 0) {
2215 return ret;
2216 }
2217 env->exception_injected =
2218 events.exception.injected ? events.exception.nr : -1;
2219 env->has_error_code = events.exception.has_error_code;
2220 env->error_code = events.exception.error_code;
2221
2222 env->interrupt_injected =
2223 events.interrupt.injected ? events.interrupt.nr : -1;
2224 env->soft_interrupt = events.interrupt.soft;
2225
2226 env->nmi_injected = events.nmi.injected;
2227 env->nmi_pending = events.nmi.pending;
2228 if (events.nmi.masked) {
2229 env->hflags2 |= HF2_NMI_MASK;
2230 } else {
2231 env->hflags2 &= ~HF2_NMI_MASK;
2232 }
2233
2234 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2235 if (events.smi.smm) {
2236 env->hflags |= HF_SMM_MASK;
2237 } else {
2238 env->hflags &= ~HF_SMM_MASK;
2239 }
2240 if (events.smi.pending) {
2241 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2242 } else {
2243 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2244 }
2245 if (events.smi.smm_inside_nmi) {
2246 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2247 } else {
2248 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2249 }
2250 if (events.smi.latched_init) {
2251 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2252 } else {
2253 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2254 }
2255 }
2256
2257 env->sipi_vector = events.sipi_vector;
2258
2259 return 0;
2260 }
2261
2262 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2263 {
2264 CPUState *cs = CPU(cpu);
2265 CPUX86State *env = &cpu->env;
2266 int ret = 0;
2267 unsigned long reinject_trap = 0;
2268
2269 if (!kvm_has_vcpu_events()) {
2270 if (env->exception_injected == 1) {
2271 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2272 } else if (env->exception_injected == 3) {
2273 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2274 }
2275 env->exception_injected = -1;
2276 }
2277
2278 /*
2279 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2280 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2281 * by updating the debug state once again if single-stepping is on.
2282 * Another reason to call kvm_update_guest_debug here is a pending debug
2283 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2284 * reinject them via SET_GUEST_DEBUG.
2285 */
2286 if (reinject_trap ||
2287 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2288 ret = kvm_update_guest_debug(cs, reinject_trap);
2289 }
2290 return ret;
2291 }
2292
2293 static int kvm_put_debugregs(X86CPU *cpu)
2294 {
2295 CPUX86State *env = &cpu->env;
2296 struct kvm_debugregs dbgregs;
2297 int i;
2298
2299 if (!kvm_has_debugregs()) {
2300 return 0;
2301 }
2302
2303 for (i = 0; i < 4; i++) {
2304 dbgregs.db[i] = env->dr[i];
2305 }
2306 dbgregs.dr6 = env->dr[6];
2307 dbgregs.dr7 = env->dr[7];
2308 dbgregs.flags = 0;
2309
2310 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2311 }
2312
2313 static int kvm_get_debugregs(X86CPU *cpu)
2314 {
2315 CPUX86State *env = &cpu->env;
2316 struct kvm_debugregs dbgregs;
2317 int i, ret;
2318
2319 if (!kvm_has_debugregs()) {
2320 return 0;
2321 }
2322
2323 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2324 if (ret < 0) {
2325 return ret;
2326 }
2327 for (i = 0; i < 4; i++) {
2328 env->dr[i] = dbgregs.db[i];
2329 }
2330 env->dr[4] = env->dr[6] = dbgregs.dr6;
2331 env->dr[5] = env->dr[7] = dbgregs.dr7;
2332
2333 return 0;
2334 }
2335
2336 int kvm_arch_put_registers(CPUState *cpu, int level)
2337 {
2338 X86CPU *x86_cpu = X86_CPU(cpu);
2339 int ret;
2340
2341 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2342
2343 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
2344 ret = kvm_put_msr_feature_control(x86_cpu);
2345 if (ret < 0) {
2346 return ret;
2347 }
2348 }
2349
2350 ret = kvm_getput_regs(x86_cpu, 1);
2351 if (ret < 0) {
2352 return ret;
2353 }
2354 ret = kvm_put_xsave(x86_cpu);
2355 if (ret < 0) {
2356 return ret;
2357 }
2358 ret = kvm_put_xcrs(x86_cpu);
2359 if (ret < 0) {
2360 return ret;
2361 }
2362 ret = kvm_put_sregs(x86_cpu);
2363 if (ret < 0) {
2364 return ret;
2365 }
2366 /* must be before kvm_put_msrs */
2367 ret = kvm_inject_mce_oldstyle(x86_cpu);
2368 if (ret < 0) {
2369 return ret;
2370 }
2371 ret = kvm_put_msrs(x86_cpu, level);
2372 if (ret < 0) {
2373 return ret;
2374 }
2375 if (level >= KVM_PUT_RESET_STATE) {
2376 ret = kvm_put_mp_state(x86_cpu);
2377 if (ret < 0) {
2378 return ret;
2379 }
2380 ret = kvm_put_apic(x86_cpu);
2381 if (ret < 0) {
2382 return ret;
2383 }
2384 }
2385
2386 ret = kvm_put_tscdeadline_msr(x86_cpu);
2387 if (ret < 0) {
2388 return ret;
2389 }
2390
2391 ret = kvm_put_vcpu_events(x86_cpu, level);
2392 if (ret < 0) {
2393 return ret;
2394 }
2395 ret = kvm_put_debugregs(x86_cpu);
2396 if (ret < 0) {
2397 return ret;
2398 }
2399 /* must be last */
2400 ret = kvm_guest_debug_workarounds(x86_cpu);
2401 if (ret < 0) {
2402 return ret;
2403 }
2404 return 0;
2405 }
2406
2407 int kvm_arch_get_registers(CPUState *cs)
2408 {
2409 X86CPU *cpu = X86_CPU(cs);
2410 int ret;
2411
2412 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2413
2414 ret = kvm_getput_regs(cpu, 0);
2415 if (ret < 0) {
2416 return ret;
2417 }
2418 ret = kvm_get_xsave(cpu);
2419 if (ret < 0) {
2420 return ret;
2421 }
2422 ret = kvm_get_xcrs(cpu);
2423 if (ret < 0) {
2424 return ret;
2425 }
2426 ret = kvm_get_sregs(cpu);
2427 if (ret < 0) {
2428 return ret;
2429 }
2430 ret = kvm_get_msrs(cpu);
2431 if (ret < 0) {
2432 return ret;
2433 }
2434 ret = kvm_get_mp_state(cpu);
2435 if (ret < 0) {
2436 return ret;
2437 }
2438 ret = kvm_get_apic(cpu);
2439 if (ret < 0) {
2440 return ret;
2441 }
2442 ret = kvm_get_vcpu_events(cpu);
2443 if (ret < 0) {
2444 return ret;
2445 }
2446 ret = kvm_get_debugregs(cpu);
2447 if (ret < 0) {
2448 return ret;
2449 }
2450 return 0;
2451 }
2452
2453 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2454 {
2455 X86CPU *x86_cpu = X86_CPU(cpu);
2456 CPUX86State *env = &x86_cpu->env;
2457 int ret;
2458
2459 /* Inject NMI */
2460 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2461 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2462 qemu_mutex_lock_iothread();
2463 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2464 qemu_mutex_unlock_iothread();
2465 DPRINTF("injected NMI\n");
2466 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2467 if (ret < 0) {
2468 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2469 strerror(-ret));
2470 }
2471 }
2472 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2473 qemu_mutex_lock_iothread();
2474 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2475 qemu_mutex_unlock_iothread();
2476 DPRINTF("injected SMI\n");
2477 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2478 if (ret < 0) {
2479 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2480 strerror(-ret));
2481 }
2482 }
2483 }
2484
2485 if (!kvm_irqchip_in_kernel()) {
2486 qemu_mutex_lock_iothread();
2487 }
2488
2489 /* Force the VCPU out of its inner loop to process any INIT requests
2490 * or (for userspace APIC, but it is cheap to combine the checks here)
2491 * pending TPR access reports.
2492 */
2493 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2494 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2495 !(env->hflags & HF_SMM_MASK)) {
2496 cpu->exit_request = 1;
2497 }
2498 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2499 cpu->exit_request = 1;
2500 }
2501 }
2502
2503 if (!kvm_irqchip_in_kernel()) {
2504 /* Try to inject an interrupt if the guest can accept it */
2505 if (run->ready_for_interrupt_injection &&
2506 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2507 (env->eflags & IF_MASK)) {
2508 int irq;
2509
2510 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2511 irq = cpu_get_pic_interrupt(env);
2512 if (irq >= 0) {
2513 struct kvm_interrupt intr;
2514
2515 intr.irq = irq;
2516 DPRINTF("injected interrupt %d\n", irq);
2517 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2518 if (ret < 0) {
2519 fprintf(stderr,
2520 "KVM: injection failed, interrupt lost (%s)\n",
2521 strerror(-ret));
2522 }
2523 }
2524 }
2525
2526 /* If we have an interrupt but the guest is not ready to receive an
2527 * interrupt, request an interrupt window exit. This will
2528 * cause a return to userspace as soon as the guest is ready to
2529 * receive interrupts. */
2530 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2531 run->request_interrupt_window = 1;
2532 } else {
2533 run->request_interrupt_window = 0;
2534 }
2535
2536 DPRINTF("setting tpr\n");
2537 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2538
2539 qemu_mutex_unlock_iothread();
2540 }
2541 }
2542
2543 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2544 {
2545 X86CPU *x86_cpu = X86_CPU(cpu);
2546 CPUX86State *env = &x86_cpu->env;
2547
2548 if (run->flags & KVM_RUN_X86_SMM) {
2549 env->hflags |= HF_SMM_MASK;
2550 } else {
2551 env->hflags &= HF_SMM_MASK;
2552 }
2553 if (run->if_flag) {
2554 env->eflags |= IF_MASK;
2555 } else {
2556 env->eflags &= ~IF_MASK;
2557 }
2558
2559 /* We need to protect the apic state against concurrent accesses from
2560 * different threads in case the userspace irqchip is used. */
2561 if (!kvm_irqchip_in_kernel()) {
2562 qemu_mutex_lock_iothread();
2563 }
2564 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2565 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2566 if (!kvm_irqchip_in_kernel()) {
2567 qemu_mutex_unlock_iothread();
2568 }
2569 return cpu_get_mem_attrs(env);
2570 }
2571
2572 int kvm_arch_process_async_events(CPUState *cs)
2573 {
2574 X86CPU *cpu = X86_CPU(cs);
2575 CPUX86State *env = &cpu->env;
2576
2577 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2578 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2579 assert(env->mcg_cap);
2580
2581 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2582
2583 kvm_cpu_synchronize_state(cs);
2584
2585 if (env->exception_injected == EXCP08_DBLE) {
2586 /* this means triple fault */
2587 qemu_system_reset_request();
2588 cs->exit_request = 1;
2589 return 0;
2590 }
2591 env->exception_injected = EXCP12_MCHK;
2592 env->has_error_code = 0;
2593
2594 cs->halted = 0;
2595 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2596 env->mp_state = KVM_MP_STATE_RUNNABLE;
2597 }
2598 }
2599
2600 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2601 !(env->hflags & HF_SMM_MASK)) {
2602 kvm_cpu_synchronize_state(cs);
2603 do_cpu_init(cpu);
2604 }
2605
2606 if (kvm_irqchip_in_kernel()) {
2607 return 0;
2608 }
2609
2610 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2611 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2612 apic_poll_irq(cpu->apic_state);
2613 }
2614 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2615 (env->eflags & IF_MASK)) ||
2616 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2617 cs->halted = 0;
2618 }
2619 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2620 kvm_cpu_synchronize_state(cs);
2621 do_cpu_sipi(cpu);
2622 }
2623 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2624 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2625 kvm_cpu_synchronize_state(cs);
2626 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2627 env->tpr_access_type);
2628 }
2629
2630 return cs->halted;
2631 }
2632
2633 static int kvm_handle_halt(X86CPU *cpu)
2634 {
2635 CPUState *cs = CPU(cpu);
2636 CPUX86State *env = &cpu->env;
2637
2638 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2639 (env->eflags & IF_MASK)) &&
2640 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2641 cs->halted = 1;
2642 return EXCP_HLT;
2643 }
2644
2645 return 0;
2646 }
2647
2648 static int kvm_handle_tpr_access(X86CPU *cpu)
2649 {
2650 CPUState *cs = CPU(cpu);
2651 struct kvm_run *run = cs->kvm_run;
2652
2653 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2654 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2655 : TPR_ACCESS_READ);
2656 return 1;
2657 }
2658
2659 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2660 {
2661 static const uint8_t int3 = 0xcc;
2662
2663 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2664 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2665 return -EINVAL;
2666 }
2667 return 0;
2668 }
2669
2670 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2671 {
2672 uint8_t int3;
2673
2674 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2675 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2676 return -EINVAL;
2677 }
2678 return 0;
2679 }
2680
2681 static struct {
2682 target_ulong addr;
2683 int len;
2684 int type;
2685 } hw_breakpoint[4];
2686
2687 static int nb_hw_breakpoint;
2688
2689 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2690 {
2691 int n;
2692
2693 for (n = 0; n < nb_hw_breakpoint; n++) {
2694 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2695 (hw_breakpoint[n].len == len || len == -1)) {
2696 return n;
2697 }
2698 }
2699 return -1;
2700 }
2701
2702 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2703 target_ulong len, int type)
2704 {
2705 switch (type) {
2706 case GDB_BREAKPOINT_HW:
2707 len = 1;
2708 break;
2709 case GDB_WATCHPOINT_WRITE:
2710 case GDB_WATCHPOINT_ACCESS:
2711 switch (len) {
2712 case 1:
2713 break;
2714 case 2:
2715 case 4:
2716 case 8:
2717 if (addr & (len - 1)) {
2718 return -EINVAL;
2719 }
2720 break;
2721 default:
2722 return -EINVAL;
2723 }
2724 break;
2725 default:
2726 return -ENOSYS;
2727 }
2728
2729 if (nb_hw_breakpoint == 4) {
2730 return -ENOBUFS;
2731 }
2732 if (find_hw_breakpoint(addr, len, type) >= 0) {
2733 return -EEXIST;
2734 }
2735 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2736 hw_breakpoint[nb_hw_breakpoint].len = len;
2737 hw_breakpoint[nb_hw_breakpoint].type = type;
2738 nb_hw_breakpoint++;
2739
2740 return 0;
2741 }
2742
2743 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2744 target_ulong len, int type)
2745 {
2746 int n;
2747
2748 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2749 if (n < 0) {
2750 return -ENOENT;
2751 }
2752 nb_hw_breakpoint--;
2753 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2754
2755 return 0;
2756 }
2757
2758 void kvm_arch_remove_all_hw_breakpoints(void)
2759 {
2760 nb_hw_breakpoint = 0;
2761 }
2762
2763 static CPUWatchpoint hw_watchpoint;
2764
2765 static int kvm_handle_debug(X86CPU *cpu,
2766 struct kvm_debug_exit_arch *arch_info)
2767 {
2768 CPUState *cs = CPU(cpu);
2769 CPUX86State *env = &cpu->env;
2770 int ret = 0;
2771 int n;
2772
2773 if (arch_info->exception == 1) {
2774 if (arch_info->dr6 & (1 << 14)) {
2775 if (cs->singlestep_enabled) {
2776 ret = EXCP_DEBUG;
2777 }
2778 } else {
2779 for (n = 0; n < 4; n++) {
2780 if (arch_info->dr6 & (1 << n)) {
2781 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2782 case 0x0:
2783 ret = EXCP_DEBUG;
2784 break;
2785 case 0x1:
2786 ret = EXCP_DEBUG;
2787 cs->watchpoint_hit = &hw_watchpoint;
2788 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2789 hw_watchpoint.flags = BP_MEM_WRITE;
2790 break;
2791 case 0x3:
2792 ret = EXCP_DEBUG;
2793 cs->watchpoint_hit = &hw_watchpoint;
2794 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2795 hw_watchpoint.flags = BP_MEM_ACCESS;
2796 break;
2797 }
2798 }
2799 }
2800 }
2801 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
2802 ret = EXCP_DEBUG;
2803 }
2804 if (ret == 0) {
2805 cpu_synchronize_state(cs);
2806 assert(env->exception_injected == -1);
2807
2808 /* pass to guest */
2809 env->exception_injected = arch_info->exception;
2810 env->has_error_code = 0;
2811 }
2812
2813 return ret;
2814 }
2815
2816 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2817 {
2818 const uint8_t type_code[] = {
2819 [GDB_BREAKPOINT_HW] = 0x0,
2820 [GDB_WATCHPOINT_WRITE] = 0x1,
2821 [GDB_WATCHPOINT_ACCESS] = 0x3
2822 };
2823 const uint8_t len_code[] = {
2824 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2825 };
2826 int n;
2827
2828 if (kvm_sw_breakpoints_active(cpu)) {
2829 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2830 }
2831 if (nb_hw_breakpoint > 0) {
2832 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2833 dbg->arch.debugreg[7] = 0x0600;
2834 for (n = 0; n < nb_hw_breakpoint; n++) {
2835 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2836 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2837 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2838 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2839 }
2840 }
2841 }
2842
2843 static bool host_supports_vmx(void)
2844 {
2845 uint32_t ecx, unused;
2846
2847 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2848 return ecx & CPUID_EXT_VMX;
2849 }
2850
2851 #define VMX_INVALID_GUEST_STATE 0x80000021
2852
2853 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2854 {
2855 X86CPU *cpu = X86_CPU(cs);
2856 uint64_t code;
2857 int ret;
2858
2859 switch (run->exit_reason) {
2860 case KVM_EXIT_HLT:
2861 DPRINTF("handle_hlt\n");
2862 qemu_mutex_lock_iothread();
2863 ret = kvm_handle_halt(cpu);
2864 qemu_mutex_unlock_iothread();
2865 break;
2866 case KVM_EXIT_SET_TPR:
2867 ret = 0;
2868 break;
2869 case KVM_EXIT_TPR_ACCESS:
2870 qemu_mutex_lock_iothread();
2871 ret = kvm_handle_tpr_access(cpu);
2872 qemu_mutex_unlock_iothread();
2873 break;
2874 case KVM_EXIT_FAIL_ENTRY:
2875 code = run->fail_entry.hardware_entry_failure_reason;
2876 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2877 code);
2878 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2879 fprintf(stderr,
2880 "\nIf you're running a guest on an Intel machine without "
2881 "unrestricted mode\n"
2882 "support, the failure can be most likely due to the guest "
2883 "entering an invalid\n"
2884 "state for Intel VT. For example, the guest maybe running "
2885 "in big real mode\n"
2886 "which is not supported on less recent Intel processors."
2887 "\n\n");
2888 }
2889 ret = -1;
2890 break;
2891 case KVM_EXIT_EXCEPTION:
2892 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2893 run->ex.exception, run->ex.error_code);
2894 ret = -1;
2895 break;
2896 case KVM_EXIT_DEBUG:
2897 DPRINTF("kvm_exit_debug\n");
2898 qemu_mutex_lock_iothread();
2899 ret = kvm_handle_debug(cpu, &run->debug.arch);
2900 qemu_mutex_unlock_iothread();
2901 break;
2902 default:
2903 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2904 ret = -1;
2905 break;
2906 }
2907
2908 return ret;
2909 }
2910
2911 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2912 {
2913 X86CPU *cpu = X86_CPU(cs);
2914 CPUX86State *env = &cpu->env;
2915
2916 kvm_cpu_synchronize_state(cs);
2917 return !(env->cr[0] & CR0_PE_MASK) ||
2918 ((env->segs[R_CS].selector & 3) != 3);
2919 }
2920
2921 void kvm_arch_init_irq_routing(KVMState *s)
2922 {
2923 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2924 /* If kernel can't do irq routing, interrupt source
2925 * override 0->2 cannot be set up as required by HPET.
2926 * So we have to disable it.
2927 */
2928 no_hpet = 1;
2929 }
2930 /* We know at this point that we're using the in-kernel
2931 * irqchip, so we can use irqfds, and on x86 we know
2932 * we can use msi via irqfd and GSI routing.
2933 */
2934 kvm_msi_via_irqfd_allowed = true;
2935 kvm_gsi_routing_allowed = true;
2936 }
2937
2938 /* Classic KVM device assignment interface. Will remain x86 only. */
2939 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2940 uint32_t flags, uint32_t *dev_id)
2941 {
2942 struct kvm_assigned_pci_dev dev_data = {
2943 .segnr = dev_addr->domain,
2944 .busnr = dev_addr->bus,
2945 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2946 .flags = flags,
2947 };
2948 int ret;
2949
2950 dev_data.assigned_dev_id =
2951 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2952
2953 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2954 if (ret < 0) {
2955 return ret;
2956 }
2957
2958 *dev_id = dev_data.assigned_dev_id;
2959
2960 return 0;
2961 }
2962
2963 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2964 {
2965 struct kvm_assigned_pci_dev dev_data = {
2966 .assigned_dev_id = dev_id,
2967 };
2968
2969 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2970 }
2971
2972 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2973 uint32_t irq_type, uint32_t guest_irq)
2974 {
2975 struct kvm_assigned_irq assigned_irq = {
2976 .assigned_dev_id = dev_id,
2977 .guest_irq = guest_irq,
2978 .flags = irq_type,
2979 };
2980
2981 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2982 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2983 } else {
2984 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2985 }
2986 }
2987
2988 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2989 uint32_t guest_irq)
2990 {
2991 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2992 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2993
2994 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2995 }
2996
2997 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2998 {
2999 struct kvm_assigned_pci_dev dev_data = {
3000 .assigned_dev_id = dev_id,
3001 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3002 };
3003
3004 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3005 }
3006
3007 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3008 uint32_t type)
3009 {
3010 struct kvm_assigned_irq assigned_irq = {
3011 .assigned_dev_id = dev_id,
3012 .flags = type,
3013 };
3014
3015 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3016 }
3017
3018 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3019 {
3020 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3021 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3022 }
3023
3024 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3025 {
3026 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3027 KVM_DEV_IRQ_GUEST_MSI, virq);
3028 }
3029
3030 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3031 {
3032 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3033 KVM_DEV_IRQ_HOST_MSI);
3034 }
3035
3036 bool kvm_device_msix_supported(KVMState *s)
3037 {
3038 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3039 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3040 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3041 }
3042
3043 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3044 uint32_t nr_vectors)
3045 {
3046 struct kvm_assigned_msix_nr msix_nr = {
3047 .assigned_dev_id = dev_id,
3048 .entry_nr = nr_vectors,
3049 };
3050
3051 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3052 }
3053
3054 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3055 int virq)
3056 {
3057 struct kvm_assigned_msix_entry msix_entry = {
3058 .assigned_dev_id = dev_id,
3059 .gsi = virq,
3060 .entry = vector,
3061 };
3062
3063 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3064 }
3065
3066 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3067 {
3068 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3069 KVM_DEV_IRQ_GUEST_MSIX, 0);
3070 }
3071
3072 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3073 {
3074 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3075 KVM_DEV_IRQ_HOST_MSIX);
3076 }
3077
3078 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3079 uint64_t address, uint32_t data, PCIDevice *dev)
3080 {
3081 return 0;
3082 }
3083
3084 int kvm_arch_msi_data_to_gsi(uint32_t data)
3085 {
3086 abort();
3087 }
AR7 emulation for QEMU