hw/misc/stm32f2xx_syscfg.c

   1 /*
   2  * STM32F2XX SYSCFG
   3  *
   4  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/misc/stm32f2xx_syscfg.h"
  26
  27 #ifndef STM_SYSCFG_ERR_DEBUG
  28 #define STM_SYSCFG_ERR_DEBUG 0
  29 #endif
  30
  31 #define DB_PRINT_L(lvl, fmt, args...) do { \
  32     if (STM_SYSCFG_ERR_DEBUG >= lvl) { \
  33         qemu_log("%s: " fmt, __func__, ## args); \
  34     } \
  35 } while (0);
  36
  37 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
  38
  39 static void stm32f2xx_syscfg_reset(DeviceState *dev)
  40 {
  41     STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(dev);
  42
  43     s->syscfg_memrmp = 0x00000000;
  44     s->syscfg_pmc = 0x00000000;
  45     s->syscfg_exticr1 = 0x00000000;
  46     s->syscfg_exticr2 = 0x00000000;
  47     s->syscfg_exticr3 = 0x00000000;
  48     s->syscfg_exticr4 = 0x00000000;
  49     s->syscfg_cmpcr = 0x00000000;
  50 }
  51
  52 static uint64_t stm32f2xx_syscfg_read(void *opaque, hwaddr addr,
  53                                      unsigned int size)
  54 {
  55     STM32F2XXSyscfgState *s = opaque;
  56
  57     DB_PRINT("0x%"HWADDR_PRIx"\n", addr);
  58
  59     switch (addr) {
  60     case SYSCFG_MEMRMP:
  61         return s->syscfg_memrmp;
  62     case SYSCFG_PMC:
  63         return s->syscfg_pmc;
  64     case SYSCFG_EXTICR1:
  65         return s->syscfg_exticr1;
  66     case SYSCFG_EXTICR2:
  67         return s->syscfg_exticr2;
  68     case SYSCFG_EXTICR3:
  69         return s->syscfg_exticr3;
  70     case SYSCFG_EXTICR4:
  71         return s->syscfg_exticr4;
  72     case SYSCFG_CMPCR:
  73         return s->syscfg_cmpcr;
  74     default:
  75         qemu_log_mask(LOG_GUEST_ERROR,
  76                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
  77         return 0;
  78     }
  79
  80     return 0;
  81 }
  82
  83 static void stm32f2xx_syscfg_write(void *opaque, hwaddr addr,
  84                        uint64_t val64, unsigned int size)
  85 {
  86     STM32F2XXSyscfgState *s = opaque;
  87     uint32_t value = val64;
  88
  89     DB_PRINT("0x%x, 0x%"HWADDR_PRIx"\n", value, addr);
  90
  91     switch (addr) {
  92     case SYSCFG_MEMRMP:
  93         qemu_log_mask(LOG_UNIMP,
  94                       "%s: Changeing the memory mapping isn't supported " \
  95                       "in QEMU\n", __func__);
  96         return;
  97     case SYSCFG_PMC:
  98         qemu_log_mask(LOG_UNIMP,
  99                       "%s: Changeing the memory mapping isn't supported " \
 100                       "in QEMU\n", __func__);
 101         return;
 102     case SYSCFG_EXTICR1:
 103         s->syscfg_exticr1 = (value & 0xFFFF);
 104         return;
 105     case SYSCFG_EXTICR2:
 106         s->syscfg_exticr2 = (value & 0xFFFF);
 107         return;
 108     case SYSCFG_EXTICR3:
 109         s->syscfg_exticr3 = (value & 0xFFFF);
 110         return;
 111     case SYSCFG_EXTICR4:
 112         s->syscfg_exticr4 = (value & 0xFFFF);
 113         return;
 114     case SYSCFG_CMPCR:
 115         s->syscfg_cmpcr = value;
 116         return;
 117     default:
 118         qemu_log_mask(LOG_GUEST_ERROR,
 119                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 120     }
 121 }
 122
 123 static const MemoryRegionOps stm32f2xx_syscfg_ops = {
 124     .read = stm32f2xx_syscfg_read,
 125     .write = stm32f2xx_syscfg_write,
 126     .endianness = DEVICE_NATIVE_ENDIAN,
 127 };
 128
 129 static void stm32f2xx_syscfg_init(Object *obj)
 130 {
 131     STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj);
 132
 133     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 134
 135     memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s,
 136                           TYPE_STM32F2XX_SYSCFG, 0x400);
 137     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 138 }
 139
 140 static void stm32f2xx_syscfg_class_init(ObjectClass *klass, void *data)
 141 {
 142     DeviceClass *dc = DEVICE_CLASS(klass);
 143
 144     dc->reset = stm32f2xx_syscfg_reset;
 145 }
 146
 147 static const TypeInfo stm32f2xx_syscfg_info = {
 148     .name          = TYPE_STM32F2XX_SYSCFG,
 149     .parent        = TYPE_SYS_BUS_DEVICE,
 150     .instance_size = sizeof(STM32F2XXSyscfgState),
 151     .instance_init = stm32f2xx_syscfg_init,
 152     .class_init    = stm32f2xx_syscfg_class_init,
 153 };
 154
 155 static void stm32f2xx_syscfg_register_types(void)
 156 {
 157     type_register_static(&stm32f2xx_syscfg_info);
 158 }
 159
 160 type_init(stm32f2xx_syscfg_register_types)