hw/gpio/omap_gpio.c

   1 /*
   2  * TI OMAP processors GPIO emulation.
   3  *
   4  * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
   5  * Copyright (C) 2007-2009 Nokia Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 or
  10  * (at your option) version 3 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "hw/hw.h"
  22 #include "hw/arm/omap.h"
  23 #include "hw/sysbus.h"
  24 #include "qemu/error-report.h"
  25
  26 struct omap_gpio_s {
  27     qemu_irq irq;
  28     qemu_irq handler[16];
  29
  30     uint16_t inputs;
  31     uint16_t outputs;
  32     uint16_t dir;
  33     uint16_t edge;
  34     uint16_t mask;
  35     uint16_t ints;
  36     uint16_t pins;
  37 };
  38
  39 #define TYPE_OMAP1_GPIO "omap-gpio"
  40 #define OMAP1_GPIO(obj) \
  41     OBJECT_CHECK(struct omap_gpif_s, (obj), TYPE_OMAP1_GPIO)
  42
  43 struct omap_gpif_s {
  44     SysBusDevice parent_obj;
  45
  46     MemoryRegion iomem;
  47     int mpu_model;
  48     void *clk;
  49     struct omap_gpio_s omap1;
  50 };
  51
  52 /* General-Purpose I/O of OMAP1 */
  53 static void omap_gpio_set(void *opaque, int line, int level)
  54 {
  55     struct omap_gpio_s *s = &((struct omap_gpif_s *) opaque)->omap1;
  56     uint16_t prev = s->inputs;
  57
  58     if (level)
  59         s->inputs |= 1 << line;
  60     else
  61         s->inputs &= ~(1 << line);
  62
  63     if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) &
  64                     (1 << line) & s->dir & ~s->mask) {
  65         s->ints |= 1 << line;
  66         qemu_irq_raise(s->irq);
  67     }
  68 }
  69
  70 static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
  71                                unsigned size)
  72 {
  73     struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
  74     int offset = addr & OMAP_MPUI_REG_MASK;
  75
  76     if (size != 2) {
  77         return omap_badwidth_read16(opaque, addr);
  78     }
  79
  80     switch (offset) {
  81     case 0x00:  /* DATA_INPUT */
  82         return s->inputs & s->pins;
  83
  84     case 0x04:  /* DATA_OUTPUT */
  85         return s->outputs;
  86
  87     case 0x08:  /* DIRECTION_CONTROL */
  88         return s->dir;
  89
  90     case 0x0c:  /* INTERRUPT_CONTROL */
  91         return s->edge;
  92
  93     case 0x10:  /* INTERRUPT_MASK */
  94         return s->mask;
  95
  96     case 0x14:  /* INTERRUPT_STATUS */
  97         return s->ints;
  98
  99     case 0x18:  /* PIN_CONTROL (not in OMAP310) */
 100         OMAP_BAD_REG(addr);
 101         return s->pins;
 102     }
 103
 104     OMAP_BAD_REG(addr);
 105     return 0;
 106 }
 107
 108 static void omap_gpio_write(void *opaque, hwaddr addr,
 109                             uint64_t value, unsigned size)
 110 {
 111     struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
 112     int offset = addr & OMAP_MPUI_REG_MASK;
 113     uint16_t diff;
 114     int ln;
 115
 116     if (size != 2) {
 117         omap_badwidth_write16(opaque, addr, value);
 118         return;
 119     }
 120
 121     switch (offset) {
 122     case 0x00:  /* DATA_INPUT */
 123         OMAP_RO_REG(addr);
 124         return;
 125
 126     case 0x04:  /* DATA_OUTPUT */
 127         diff = (s->outputs ^ value) & ~s->dir;
 128         s->outputs = value;
 129         while ((ln = ctz32(diff)) != 32) {
 130             if (s->handler[ln])
 131                 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
 132             diff &= ~(1 << ln);
 133         }
 134         break;
 135
 136     case 0x08:  /* DIRECTION_CONTROL */
 137         diff = s->outputs & (s->dir ^ value);
 138         s->dir = value;
 139
 140         value = s->outputs & ~s->dir;
 141         while ((ln = ctz32(diff)) != 32) {
 142             if (s->handler[ln])
 143                 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
 144             diff &= ~(1 << ln);
 145         }
 146         break;
 147
 148     case 0x0c:  /* INTERRUPT_CONTROL */
 149         s->edge = value;
 150         break;
 151
 152     case 0x10:  /* INTERRUPT_MASK */
 153         s->mask = value;
 154         break;
 155
 156     case 0x14:  /* INTERRUPT_STATUS */
 157         s->ints &= ~value;
 158         if (!s->ints)
 159             qemu_irq_lower(s->irq);
 160         break;
 161
 162     case 0x18:  /* PIN_CONTROL (not in OMAP310 TRM) */
 163         OMAP_BAD_REG(addr);
 164         s->pins = value;
 165         break;
 166
 167     default:
 168         OMAP_BAD_REG(addr);
 169         return;
 170     }
 171 }
 172
 173 /* *Some* sources say the memory region is 32-bit.  */
 174 static const MemoryRegionOps omap_gpio_ops = {
 175     .read = omap_gpio_read,
 176     .write = omap_gpio_write,
 177     .endianness = DEVICE_NATIVE_ENDIAN,
 178 };
 179
 180 static void omap_gpio_reset(struct omap_gpio_s *s)
 181 {
 182     s->inputs = 0;
 183     s->outputs = ~0;
 184     s->dir = ~0;
 185     s->edge = ~0;
 186     s->mask = ~0;
 187     s->ints = 0;
 188     s->pins = ~0;
 189 }
 190
 191 struct omap2_gpio_s {
 192     qemu_irq irq[2];
 193     qemu_irq wkup;
 194     qemu_irq *handler;
 195     MemoryRegion iomem;
 196
 197     uint8_t revision;
 198     uint8_t config[2];
 199     uint32_t inputs;
 200     uint32_t outputs;
 201     uint32_t dir;
 202     uint32_t level[2];
 203     uint32_t edge[2];
 204     uint32_t mask[2];
 205     uint32_t wumask;
 206     uint32_t ints[2];
 207     uint32_t debounce;
 208     uint8_t delay;
 209 };
 210
 211 #define TYPE_OMAP2_GPIO "omap2-gpio"
 212 #define OMAP2_GPIO(obj) \
 213     OBJECT_CHECK(struct omap2_gpif_s, (obj), TYPE_OMAP2_GPIO)
 214
 215 struct omap2_gpif_s {
 216     SysBusDevice parent_obj;
 217
 218     MemoryRegion iomem;
 219     int mpu_model;
 220     void *iclk;
 221     void *fclk[6];
 222     int modulecount;
 223     struct omap2_gpio_s *modules;
 224     qemu_irq *handler;
 225     int autoidle;
 226     int gpo;
 227 };
 228
 229 /* General-Purpose Interface of OMAP2/3 */
 230 static inline void omap2_gpio_module_int_update(struct omap2_gpio_s *s,
 231                                                 int line)
 232 {
 233     qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]);
 234 }
 235
 236 static void omap2_gpio_module_wake(struct omap2_gpio_s *s, int line)
 237 {
 238     if (!(s->config[0] & (1 << 2)))                     /* ENAWAKEUP */
 239         return;
 240     if (!(s->config[0] & (3 << 3)))                     /* Force Idle */
 241         return;
 242     if (!(s->wumask & (1 << line)))
 243         return;
 244
 245     qemu_irq_raise(s->wkup);
 246 }
 247
 248 static inline void omap2_gpio_module_out_update(struct omap2_gpio_s *s,
 249                 uint32_t diff)
 250 {
 251     int ln;
 252
 253     s->outputs ^= diff;
 254     diff &= ~s->dir;
 255     while ((ln = ctz32(diff)) != 32) {
 256         qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1);
 257         diff &= ~(1 << ln);
 258     }
 259 }
 260
 261 static void omap2_gpio_module_level_update(struct omap2_gpio_s *s, int line)
 262 {
 263     s->ints[line] |= s->dir &
 264             ((s->inputs & s->level[1]) | (~s->inputs & s->level[0]));
 265     omap2_gpio_module_int_update(s, line);
 266 }
 267
 268 static inline void omap2_gpio_module_int(struct omap2_gpio_s *s, int line)
 269 {
 270     s->ints[0] |= 1 << line;
 271     omap2_gpio_module_int_update(s, 0);
 272     s->ints[1] |= 1 << line;
 273     omap2_gpio_module_int_update(s, 1);
 274     omap2_gpio_module_wake(s, line);
 275 }
 276
 277 static void omap2_gpio_set(void *opaque, int line, int level)
 278 {
 279     struct omap2_gpif_s *p = opaque;
 280     struct omap2_gpio_s *s = &p->modules[line >> 5];
 281
 282     line &= 31;
 283     if (level) {
 284         if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1]))
 285             omap2_gpio_module_int(s, line);
 286         s->inputs |= 1 << line;
 287     } else {
 288         if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0]))
 289             omap2_gpio_module_int(s, line);
 290         s->inputs &= ~(1 << line);
 291     }
 292 }
 293
 294 static void omap2_gpio_module_reset(struct omap2_gpio_s *s)
 295 {
 296     s->config[0] = 0;
 297     s->config[1] = 2;
 298     s->ints[0] = 0;
 299     s->ints[1] = 0;
 300     s->mask[0] = 0;
 301     s->mask[1] = 0;
 302     s->wumask = 0;
 303     s->dir = ~0;
 304     s->level[0] = 0;
 305     s->level[1] = 0;
 306     s->edge[0] = 0;
 307     s->edge[1] = 0;
 308     s->debounce = 0;
 309     s->delay = 0;
 310 }
 311
 312 static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr)
 313 {
 314     struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
 315
 316     switch (addr) {
 317     case 0x00:  /* GPIO_REVISION */
 318         return s->revision;
 319
 320     case 0x10:  /* GPIO_SYSCONFIG */
 321         return s->config[0];
 322
 323     case 0x14:  /* GPIO_SYSSTATUS */
 324         return 0x01;
 325
 326     case 0x18:  /* GPIO_IRQSTATUS1 */
 327         return s->ints[0];
 328
 329     case 0x1c:  /* GPIO_IRQENABLE1 */
 330     case 0x60:  /* GPIO_CLEARIRQENABLE1 */
 331     case 0x64:  /* GPIO_SETIRQENABLE1 */
 332         return s->mask[0];
 333
 334     case 0x20:  /* GPIO_WAKEUPENABLE */
 335     case 0x80:  /* GPIO_CLEARWKUENA */
 336     case 0x84:  /* GPIO_SETWKUENA */
 337         return s->wumask;
 338
 339     case 0x28:  /* GPIO_IRQSTATUS2 */
 340         return s->ints[1];
 341
 342     case 0x2c:  /* GPIO_IRQENABLE2 */
 343     case 0x70:  /* GPIO_CLEARIRQENABLE2 */
 344     case 0x74:  /* GPIO_SETIREQNEABLE2 */
 345         return s->mask[1];
 346
 347     case 0x30:  /* GPIO_CTRL */
 348         return s->config[1];
 349
 350     case 0x34:  /* GPIO_OE */
 351         return s->dir;
 352
 353     case 0x38:  /* GPIO_DATAIN */
 354         return s->inputs;
 355
 356     case 0x3c:  /* GPIO_DATAOUT */
 357     case 0x90:  /* GPIO_CLEARDATAOUT */
 358     case 0x94:  /* GPIO_SETDATAOUT */
 359         return s->outputs;
 360
 361     case 0x40:  /* GPIO_LEVELDETECT0 */
 362         return s->level[0];
 363
 364     case 0x44:  /* GPIO_LEVELDETECT1 */
 365         return s->level[1];
 366
 367     case 0x48:  /* GPIO_RISINGDETECT */
 368         return s->edge[0];
 369
 370     case 0x4c:  /* GPIO_FALLINGDETECT */
 371         return s->edge[1];
 372
 373     case 0x50:  /* GPIO_DEBOUNCENABLE */
 374         return s->debounce;
 375
 376     case 0x54:  /* GPIO_DEBOUNCINGTIME */
 377         return s->delay;
 378     }
 379
 380     OMAP_BAD_REG(addr);
 381     return 0;
 382 }
 383
 384 static void omap2_gpio_module_write(void *opaque, hwaddr addr,
 385                 uint32_t value)
 386 {
 387     struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
 388     uint32_t diff;
 389     int ln;
 390
 391     switch (addr) {
 392     case 0x00:  /* GPIO_REVISION */
 393     case 0x14:  /* GPIO_SYSSTATUS */
 394     case 0x38:  /* GPIO_DATAIN */
 395         OMAP_RO_REG(addr);
 396         break;
 397
 398     case 0x10:  /* GPIO_SYSCONFIG */
 399         if (((value >> 3) & 3) == 3)
 400             fprintf(stderr, "%s: bad IDLEMODE value\n", __FUNCTION__);
 401         if (value & 2)
 402             omap2_gpio_module_reset(s);
 403         s->config[0] = value & 0x1d;
 404         break;
 405
 406     case 0x18:  /* GPIO_IRQSTATUS1 */
 407         if (s->ints[0] & value) {
 408             s->ints[0] &= ~value;
 409             omap2_gpio_module_level_update(s, 0);
 410         }
 411         break;
 412
 413     case 0x1c:  /* GPIO_IRQENABLE1 */
 414         s->mask[0] = value;
 415         omap2_gpio_module_int_update(s, 0);
 416         break;
 417
 418     case 0x20:  /* GPIO_WAKEUPENABLE */
 419         s->wumask = value;
 420         break;
 421
 422     case 0x28:  /* GPIO_IRQSTATUS2 */
 423         if (s->ints[1] & value) {
 424             s->ints[1] &= ~value;
 425             omap2_gpio_module_level_update(s, 1);
 426         }
 427         break;
 428
 429     case 0x2c:  /* GPIO_IRQENABLE2 */
 430         s->mask[1] = value;
 431         omap2_gpio_module_int_update(s, 1);
 432         break;
 433
 434     case 0x30:  /* GPIO_CTRL */
 435         s->config[1] = value & 7;
 436         break;
 437
 438     case 0x34:  /* GPIO_OE */
 439         diff = s->outputs & (s->dir ^ value);
 440         s->dir = value;
 441
 442         value = s->outputs & ~s->dir;
 443         while ((ln = ctz32(diff)) != 32) {
 444             diff &= ~(1 << ln);
 445             qemu_set_irq(s->handler[ln], (value >> ln) & 1);
 446         }
 447
 448         omap2_gpio_module_level_update(s, 0);
 449         omap2_gpio_module_level_update(s, 1);
 450         break;
 451
 452     case 0x3c:  /* GPIO_DATAOUT */
 453         omap2_gpio_module_out_update(s, s->outputs ^ value);
 454         break;
 455
 456     case 0x40:  /* GPIO_LEVELDETECT0 */
 457         s->level[0] = value;
 458         omap2_gpio_module_level_update(s, 0);
 459         omap2_gpio_module_level_update(s, 1);
 460         break;
 461
 462     case 0x44:  /* GPIO_LEVELDETECT1 */
 463         s->level[1] = value;
 464         omap2_gpio_module_level_update(s, 0);
 465         omap2_gpio_module_level_update(s, 1);
 466         break;
 467
 468     case 0x48:  /* GPIO_RISINGDETECT */
 469         s->edge[0] = value;
 470         break;
 471
 472     case 0x4c:  /* GPIO_FALLINGDETECT */
 473         s->edge[1] = value;
 474         break;
 475
 476     case 0x50:  /* GPIO_DEBOUNCENABLE */
 477         s->debounce = value;
 478         break;
 479
 480     case 0x54:  /* GPIO_DEBOUNCINGTIME */
 481         s->delay = value;
 482         break;
 483
 484     case 0x60:  /* GPIO_CLEARIRQENABLE1 */
 485         s->mask[0] &= ~value;
 486         omap2_gpio_module_int_update(s, 0);
 487         break;
 488
 489     case 0x64:  /* GPIO_SETIRQENABLE1 */
 490         s->mask[0] |= value;
 491         omap2_gpio_module_int_update(s, 0);
 492         break;
 493
 494     case 0x70:  /* GPIO_CLEARIRQENABLE2 */
 495         s->mask[1] &= ~value;
 496         omap2_gpio_module_int_update(s, 1);
 497         break;
 498
 499     case 0x74:  /* GPIO_SETIREQNEABLE2 */
 500         s->mask[1] |= value;
 501         omap2_gpio_module_int_update(s, 1);
 502         break;
 503
 504     case 0x80:  /* GPIO_CLEARWKUENA */
 505         s->wumask &= ~value;
 506         break;
 507
 508     case 0x84:  /* GPIO_SETWKUENA */
 509         s->wumask |= value;
 510         break;
 511
 512     case 0x90:  /* GPIO_CLEARDATAOUT */
 513         omap2_gpio_module_out_update(s, s->outputs & value);
 514         break;
 515
 516     case 0x94:  /* GPIO_SETDATAOUT */
 517         omap2_gpio_module_out_update(s, ~s->outputs & value);
 518         break;
 519
 520     default:
 521         OMAP_BAD_REG(addr);
 522         return;
 523     }
 524 }
 525
 526 static uint32_t omap2_gpio_module_readp(void *opaque, hwaddr addr)
 527 {
 528     return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3);
 529 }
 530
 531 static void omap2_gpio_module_writep(void *opaque, hwaddr addr,
 532                 uint32_t value)
 533 {
 534     uint32_t cur = 0;
 535     uint32_t mask = 0xffff;
 536
 537     switch (addr & ~3) {
 538     case 0x00:  /* GPIO_REVISION */
 539     case 0x14:  /* GPIO_SYSSTATUS */
 540     case 0x38:  /* GPIO_DATAIN */
 541         OMAP_RO_REG(addr);
 542         break;
 543
 544     case 0x10:  /* GPIO_SYSCONFIG */
 545     case 0x1c:  /* GPIO_IRQENABLE1 */
 546     case 0x20:  /* GPIO_WAKEUPENABLE */
 547     case 0x2c:  /* GPIO_IRQENABLE2 */
 548     case 0x30:  /* GPIO_CTRL */
 549     case 0x34:  /* GPIO_OE */
 550     case 0x3c:  /* GPIO_DATAOUT */
 551     case 0x40:  /* GPIO_LEVELDETECT0 */
 552     case 0x44:  /* GPIO_LEVELDETECT1 */
 553     case 0x48:  /* GPIO_RISINGDETECT */
 554     case 0x4c:  /* GPIO_FALLINGDETECT */
 555     case 0x50:  /* GPIO_DEBOUNCENABLE */
 556     case 0x54:  /* GPIO_DEBOUNCINGTIME */
 557         cur = omap2_gpio_module_read(opaque, addr & ~3) &
 558                 ~(mask << ((addr & 3) << 3));
 559
 560         /* Fall through.  */
 561     case 0x18:  /* GPIO_IRQSTATUS1 */
 562     case 0x28:  /* GPIO_IRQSTATUS2 */
 563     case 0x60:  /* GPIO_CLEARIRQENABLE1 */
 564     case 0x64:  /* GPIO_SETIRQENABLE1 */
 565     case 0x70:  /* GPIO_CLEARIRQENABLE2 */
 566     case 0x74:  /* GPIO_SETIREQNEABLE2 */
 567     case 0x80:  /* GPIO_CLEARWKUENA */
 568     case 0x84:  /* GPIO_SETWKUENA */
 569     case 0x90:  /* GPIO_CLEARDATAOUT */
 570     case 0x94:  /* GPIO_SETDATAOUT */
 571         value <<= (addr & 3) << 3;
 572         omap2_gpio_module_write(opaque, addr, cur | value);
 573         break;
 574
 575     default:
 576         OMAP_BAD_REG(addr);
 577         return;
 578     }
 579 }
 580
 581 static const MemoryRegionOps omap2_gpio_module_ops = {
 582     .old_mmio = {
 583         .read = {
 584             omap2_gpio_module_readp,
 585             omap2_gpio_module_readp,
 586             omap2_gpio_module_read,
 587         },
 588         .write = {
 589             omap2_gpio_module_writep,
 590             omap2_gpio_module_writep,
 591             omap2_gpio_module_write,
 592         },
 593     },
 594     .endianness = DEVICE_NATIVE_ENDIAN,
 595 };
 596
 597 static void omap_gpif_reset(DeviceState *dev)
 598 {
 599     struct omap_gpif_s *s = OMAP1_GPIO(dev);
 600
 601     omap_gpio_reset(&s->omap1);
 602 }
 603
 604 static void omap2_gpif_reset(DeviceState *dev)
 605 {
 606     struct omap2_gpif_s *s = OMAP2_GPIO(dev);
 607     int i;
 608
 609     for (i = 0; i < s->modulecount; i++) {
 610         omap2_gpio_module_reset(&s->modules[i]);
 611     }
 612     s->autoidle = 0;
 613     s->gpo = 0;
 614 }
 615
 616 static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr,
 617                                     unsigned size)
 618 {
 619     struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
 620
 621     switch (addr) {
 622     case 0x00:  /* IPGENERICOCPSPL_REVISION */
 623         return 0x18;
 624
 625     case 0x10:  /* IPGENERICOCPSPL_SYSCONFIG */
 626         return s->autoidle;
 627
 628     case 0x14:  /* IPGENERICOCPSPL_SYSSTATUS */
 629         return 0x01;
 630
 631     case 0x18:  /* IPGENERICOCPSPL_IRQSTATUS */
 632         return 0x00;
 633
 634     case 0x40:  /* IPGENERICOCPSPL_GPO */
 635         return s->gpo;
 636
 637     case 0x50:  /* IPGENERICOCPSPL_GPI */
 638         return 0x00;
 639     }
 640
 641     OMAP_BAD_REG(addr);
 642     return 0;
 643 }
 644
 645 static void omap2_gpif_top_write(void *opaque, hwaddr addr,
 646                                  uint64_t value, unsigned size)
 647 {
 648     struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
 649
 650     switch (addr) {
 651     case 0x00:  /* IPGENERICOCPSPL_REVISION */
 652     case 0x14:  /* IPGENERICOCPSPL_SYSSTATUS */
 653     case 0x18:  /* IPGENERICOCPSPL_IRQSTATUS */
 654     case 0x50:  /* IPGENERICOCPSPL_GPI */
 655         OMAP_RO_REG(addr);
 656         break;
 657
 658     case 0x10:  /* IPGENERICOCPSPL_SYSCONFIG */
 659         if (value & (1 << 1))                                   /* SOFTRESET */
 660             omap2_gpif_reset(DEVICE(s));
 661         s->autoidle = value & 1;
 662         break;
 663
 664     case 0x40:  /* IPGENERICOCPSPL_GPO */
 665         s->gpo = value & 1;
 666         break;
 667
 668     default:
 669         OMAP_BAD_REG(addr);
 670         return;
 671     }
 672 }
 673
 674 static const MemoryRegionOps omap2_gpif_top_ops = {
 675     .read = omap2_gpif_top_read,
 676     .write = omap2_gpif_top_write,
 677     .endianness = DEVICE_NATIVE_ENDIAN,
 678 };
 679
 680 static int omap_gpio_init(SysBusDevice *sbd)
 681 {
 682     DeviceState *dev = DEVICE(sbd);
 683     struct omap_gpif_s *s = OMAP1_GPIO(dev);
 684
 685     if (!s->clk) {
 686         error_report("omap-gpio: clk not connected");
 687         return -1;
 688     }
 689     qdev_init_gpio_in(dev, omap_gpio_set, 16);
 690     qdev_init_gpio_out(dev, s->omap1.handler, 16);
 691     sysbus_init_irq(sbd, &s->omap1.irq);
 692     memory_region_init_io(&s->iomem, OBJECT(s), &omap_gpio_ops, &s->omap1,
 693                           "omap.gpio", 0x1000);
 694     sysbus_init_mmio(sbd, &s->iomem);
 695     return 0;
 696 }
 697
 698 static int omap2_gpio_init(SysBusDevice *sbd)
 699 {
 700     DeviceState *dev = DEVICE(sbd);
 701     struct omap2_gpif_s *s = OMAP2_GPIO(dev);
 702     int i;
 703
 704     if (!s->iclk) {
 705         error_report("omap2-gpio: iclk not connected");
 706         return -1;
 707     }
 708
 709     s->modulecount = s->mpu_model < omap2430 ? 4
 710                    : s->mpu_model < omap3430 ? 5
 711                    : 6;
 712
 713     for (i = 0; i < s->modulecount; i++) {
 714         if (!s->fclk[i]) {
 715             error_report("omap2-gpio: fclk%d not connected", i);
 716             return -1;
 717         }
 718     }
 719
 720     if (s->mpu_model < omap3430) {
 721         memory_region_init_io(&s->iomem, OBJECT(s), &omap2_gpif_top_ops, s,
 722                               "omap2.gpio", 0x1000);
 723         sysbus_init_mmio(sbd, &s->iomem);
 724     }
 725
 726     s->modules = g_new0(struct omap2_gpio_s, s->modulecount);
 727     s->handler = g_new0(qemu_irq, s->modulecount * 32);
 728     qdev_init_gpio_in(dev, omap2_gpio_set, s->modulecount * 32);
 729     qdev_init_gpio_out(dev, s->handler, s->modulecount * 32);
 730
 731     for (i = 0; i < s->modulecount; i++) {
 732         struct omap2_gpio_s *m = &s->modules[i];
 733
 734         m->revision = (s->mpu_model < omap3430) ? 0x18 : 0x25;
 735         m->handler = &s->handler[i * 32];
 736         sysbus_init_irq(sbd, &m->irq[0]); /* mpu irq */
 737         sysbus_init_irq(sbd, &m->irq[1]); /* dsp irq */
 738         sysbus_init_irq(sbd, &m->wkup);
 739         memory_region_init_io(&m->iomem, OBJECT(s), &omap2_gpio_module_ops, m,
 740                               "omap.gpio-module", 0x1000);
 741         sysbus_init_mmio(sbd, &m->iomem);
 742     }
 743
 744     return 0;
 745 }
 746
 747 /* Using qdev pointer properties for the clocks is not ideal.
 748  * qdev should support a generic means of defining a 'port' with
 749  * an arbitrary interface for connecting two devices. Then we
 750  * could reframe the omap clock API in terms of clock ports,
 751  * and get some type safety. For now the best qdev provides is
 752  * passing an arbitrary pointer.
 753  * (It's not possible to pass in the string which is the clock
 754  * name, because this device does not have the necessary information
 755  * (ie the struct omap_mpu_state_s*) to do the clockname to pointer
 756  * translation.)
 757  */
 758
 759 static Property omap_gpio_properties[] = {
 760     DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s, mpu_model, 0),
 761     DEFINE_PROP_PTR("clk", struct omap_gpif_s, clk),
 762     DEFINE_PROP_END_OF_LIST(),
 763 };
 764
 765 static void omap_gpio_class_init(ObjectClass *klass, void *data)
 766 {
 767     DeviceClass *dc = DEVICE_CLASS(klass);
 768     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 769
 770     k->init = omap_gpio_init;
 771     dc->reset = omap_gpif_reset;
 772     dc->props = omap_gpio_properties;
 773     /* Reason: pointer property "clk" */
 774     dc->cannot_instantiate_with_device_add_yet = true;
 775 }
 776
 777 static const TypeInfo omap_gpio_info = {
 778     .name          = TYPE_OMAP1_GPIO,
 779     .parent        = TYPE_SYS_BUS_DEVICE,
 780     .instance_size = sizeof(struct omap_gpif_s),
 781     .class_init    = omap_gpio_class_init,
 782 };
 783
 784 static Property omap2_gpio_properties[] = {
 785     DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s, mpu_model, 0),
 786     DEFINE_PROP_PTR("iclk", struct omap2_gpif_s, iclk),
 787     DEFINE_PROP_PTR("fclk0", struct omap2_gpif_s, fclk[0]),
 788     DEFINE_PROP_PTR("fclk1", struct omap2_gpif_s, fclk[1]),
 789     DEFINE_PROP_PTR("fclk2", struct omap2_gpif_s, fclk[2]),
 790     DEFINE_PROP_PTR("fclk3", struct omap2_gpif_s, fclk[3]),
 791     DEFINE_PROP_PTR("fclk4", struct omap2_gpif_s, fclk[4]),
 792     DEFINE_PROP_PTR("fclk5", struct omap2_gpif_s, fclk[5]),
 793     DEFINE_PROP_END_OF_LIST(),
 794 };
 795
 796 static void omap2_gpio_class_init(ObjectClass *klass, void *data)
 797 {
 798     DeviceClass *dc = DEVICE_CLASS(klass);
 799     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 800
 801     k->init = omap2_gpio_init;
 802     dc->reset = omap2_gpif_reset;
 803     dc->props = omap2_gpio_properties;
 804     /* Reason: pointer properties "iclk", "fclk0", ..., "fclk5" */
 805     dc->cannot_instantiate_with_device_add_yet = true;
 806 }
 807
 808 static const TypeInfo omap2_gpio_info = {
 809     .name          = TYPE_OMAP2_GPIO,
 810     .parent        = TYPE_SYS_BUS_DEVICE,
 811     .instance_size = sizeof(struct omap2_gpif_s),
 812     .class_init    = omap2_gpio_class_init,
 813 };
 814
 815 static void omap_gpio_register_types(void)
 816 {
 817     type_register_static(&omap_gpio_info);
 818     type_register_static(&omap2_gpio_info);
 819 }
 820
 821 type_init(omap_gpio_register_types)