hw/char/cadence_uart.c

   1 /*
   2  * Device model for Cadence UART
   3  *
   4  * Copyright (c) 2010 Xilinx Inc.
   5  * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
   6  * Copyright (c) 2012 PetaLogix Pty Ltd.
   7  * Written by Haibing Ma
   8  *            M.Habib
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version
  13  * 2 of the License, or (at your option) any later version.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "hw/char/cadence_uart.h"
  20
  21 #ifdef CADENCE_UART_ERR_DEBUG
  22 #define DB_PRINT(...) do { \
  23     fprintf(stderr,  ": %s: ", __func__); \
  24     fprintf(stderr, ## __VA_ARGS__); \
  25     } while (0);
  26 #else
  27     #define DB_PRINT(...)
  28 #endif
  29
  30 #define UART_SR_INTR_RTRIG     0x00000001
  31 #define UART_SR_INTR_REMPTY    0x00000002
  32 #define UART_SR_INTR_RFUL      0x00000004
  33 #define UART_SR_INTR_TEMPTY    0x00000008
  34 #define UART_SR_INTR_TFUL      0x00000010
  35 /* somewhat awkwardly, TTRIG is misaligned between SR and ISR */
  36 #define UART_SR_TTRIG          0x00002000
  37 #define UART_INTR_TTRIG        0x00000400
  38 /* bits fields in CSR that correlate to CISR. If any of these bits are set in
  39  * SR, then the same bit in CISR is set high too */
  40 #define UART_SR_TO_CISR_MASK   0x0000001F
  41
  42 #define UART_INTR_ROVR         0x00000020
  43 #define UART_INTR_FRAME        0x00000040
  44 #define UART_INTR_PARE         0x00000080
  45 #define UART_INTR_TIMEOUT      0x00000100
  46 #define UART_INTR_DMSI         0x00000200
  47 #define UART_INTR_TOVR         0x00001000
  48
  49 #define UART_SR_RACTIVE    0x00000400
  50 #define UART_SR_TACTIVE    0x00000800
  51 #define UART_SR_FDELT      0x00001000
  52
  53 #define UART_CR_RXRST       0x00000001
  54 #define UART_CR_TXRST       0x00000002
  55 #define UART_CR_RX_EN       0x00000004
  56 #define UART_CR_RX_DIS      0x00000008
  57 #define UART_CR_TX_EN       0x00000010
  58 #define UART_CR_TX_DIS      0x00000020
  59 #define UART_CR_RST_TO      0x00000040
  60 #define UART_CR_STARTBRK    0x00000080
  61 #define UART_CR_STOPBRK     0x00000100
  62
  63 #define UART_MR_CLKS            0x00000001
  64 #define UART_MR_CHRL            0x00000006
  65 #define UART_MR_CHRL_SH         1
  66 #define UART_MR_PAR             0x00000038
  67 #define UART_MR_PAR_SH          3
  68 #define UART_MR_NBSTOP          0x000000C0
  69 #define UART_MR_NBSTOP_SH       6
  70 #define UART_MR_CHMODE          0x00000300
  71 #define UART_MR_CHMODE_SH       8
  72 #define UART_MR_UCLKEN          0x00000400
  73 #define UART_MR_IRMODE          0x00000800
  74
  75 #define UART_DATA_BITS_6       (0x3 << UART_MR_CHRL_SH)
  76 #define UART_DATA_BITS_7       (0x2 << UART_MR_CHRL_SH)
  77 #define UART_PARITY_ODD        (0x1 << UART_MR_PAR_SH)
  78 #define UART_PARITY_EVEN       (0x0 << UART_MR_PAR_SH)
  79 #define UART_STOP_BITS_1       (0x3 << UART_MR_NBSTOP_SH)
  80 #define UART_STOP_BITS_2       (0x2 << UART_MR_NBSTOP_SH)
  81 #define NORMAL_MODE            (0x0 << UART_MR_CHMODE_SH)
  82 #define ECHO_MODE              (0x1 << UART_MR_CHMODE_SH)
  83 #define LOCAL_LOOPBACK         (0x2 << UART_MR_CHMODE_SH)
  84 #define REMOTE_LOOPBACK        (0x3 << UART_MR_CHMODE_SH)
  85
  86 #define UART_INPUT_CLK         50000000
  87
  88 #define R_CR       (0x00/4)
  89 #define R_MR       (0x04/4)
  90 #define R_IER      (0x08/4)
  91 #define R_IDR      (0x0C/4)
  92 #define R_IMR      (0x10/4)
  93 #define R_CISR     (0x14/4)
  94 #define R_BRGR     (0x18/4)
  95 #define R_RTOR     (0x1C/4)
  96 #define R_RTRIG    (0x20/4)
  97 #define R_MCR      (0x24/4)
  98 #define R_MSR      (0x28/4)
  99 #define R_SR       (0x2C/4)
 100 #define R_TX_RX    (0x30/4)
 101 #define R_BDIV     (0x34/4)
 102 #define R_FDEL     (0x38/4)
 103 #define R_PMIN     (0x3C/4)
 104 #define R_PWID     (0x40/4)
 105 #define R_TTRIG    (0x44/4)
 106
 107
 108 static void uart_update_status(CadenceUARTState *s)
 109 {
 110     s->r[R_SR] = 0;
 111
 112     s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL
 113                                                            : 0;
 114     s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0;
 115     s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0;
 116
 117     s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL
 118                                                            : 0;
 119     s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0;
 120     s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0;
 121
 122     s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK;
 123     s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0;
 124     qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));
 125 }
 126
 127 static void fifo_trigger_update(void *opaque)
 128 {
 129     CadenceUARTState *s = opaque;
 130
 131     s->r[R_CISR] |= UART_INTR_TIMEOUT;
 132
 133     uart_update_status(s);
 134 }
 135
 136 static void uart_rx_reset(CadenceUARTState *s)
 137 {
 138     s->rx_wpos = 0;
 139     s->rx_count = 0;
 140     if (s->chr) {
 141         qemu_chr_accept_input(s->chr);
 142     }
 143 }
 144
 145 static void uart_tx_reset(CadenceUARTState *s)
 146 {
 147     s->tx_count = 0;
 148 }
 149
 150 static void uart_send_breaks(CadenceUARTState *s)
 151 {
 152     int break_enabled = 1;
 153
 154     if (s->chr) {
 155         qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 156                                    &break_enabled);
 157     }
 158 }
 159
 160 static void uart_parameters_setup(CadenceUARTState *s)
 161 {
 162     QEMUSerialSetParams ssp;
 163     unsigned int baud_rate, packet_size;
 164
 165     baud_rate = (s->r[R_MR] & UART_MR_CLKS) ?
 166             UART_INPUT_CLK / 8 : UART_INPUT_CLK;
 167
 168     ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
 169     packet_size = 1;
 170
 171     switch (s->r[R_MR] & UART_MR_PAR) {
 172     case UART_PARITY_EVEN:
 173         ssp.parity = 'E';
 174         packet_size++;
 175         break;
 176     case UART_PARITY_ODD:
 177         ssp.parity = 'O';
 178         packet_size++;
 179         break;
 180     default:
 181         ssp.parity = 'N';
 182         break;
 183     }
 184
 185     switch (s->r[R_MR] & UART_MR_CHRL) {
 186     case UART_DATA_BITS_6:
 187         ssp.data_bits = 6;
 188         break;
 189     case UART_DATA_BITS_7:
 190         ssp.data_bits = 7;
 191         break;
 192     default:
 193         ssp.data_bits = 8;
 194         break;
 195     }
 196
 197     switch (s->r[R_MR] & UART_MR_NBSTOP) {
 198     case UART_STOP_BITS_1:
 199         ssp.stop_bits = 1;
 200         break;
 201     default:
 202         ssp.stop_bits = 2;
 203         break;
 204     }
 205
 206     packet_size += ssp.data_bits + ssp.stop_bits;
 207     s->char_tx_time = (get_ticks_per_sec() / ssp.speed) * packet_size;
 208     if (s->chr) {
 209         qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 210     }
 211 }
 212
 213 static int uart_can_receive(void *opaque)
 214 {
 215     CadenceUARTState *s = opaque;
 216     int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
 217     uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
 218
 219     if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
 220         ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count);
 221     }
 222     if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
 223         ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count);
 224     }
 225     return ret;
 226 }
 227
 228 static void uart_ctrl_update(CadenceUARTState *s)
 229 {
 230     if (s->r[R_CR] & UART_CR_TXRST) {
 231         uart_tx_reset(s);
 232     }
 233
 234     if (s->r[R_CR] & UART_CR_RXRST) {
 235         uart_rx_reset(s);
 236     }
 237
 238     s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST);
 239
 240     if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) {
 241         uart_send_breaks(s);
 242     }
 243 }
 244
 245 static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
 246 {
 247     CadenceUARTState *s = opaque;
 248     uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 249     int i;
 250
 251     if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
 252         return;
 253     }
 254
 255     if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) {
 256         s->r[R_CISR] |= UART_INTR_ROVR;
 257     } else {
 258         for (i = 0; i < size; i++) {
 259             s->rx_fifo[s->rx_wpos] = buf[i];
 260             s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE;
 261             s->rx_count++;
 262         }
 263         timer_mod(s->fifo_trigger_handle, new_rx_time +
 264                                                 (s->char_tx_time * 4));
 265     }
 266     uart_update_status(s);
 267 }
 268
 269 static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
 270                                   void *opaque)
 271 {
 272     CadenceUARTState *s = opaque;
 273     int ret;
 274
 275     /* instant drain the fifo when there's no back-end */
 276     if (!s->chr) {
 277         s->tx_count = 0;
 278         return FALSE;
 279     }
 280
 281     if (!s->tx_count) {
 282         return FALSE;
 283     }
 284
 285     ret = qemu_chr_fe_write(s->chr, s->tx_fifo, s->tx_count);
 286     s->tx_count -= ret;
 287     memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count);
 288
 289     if (s->tx_count) {
 290         int r = qemu_chr_fe_add_watch(s->chr, G_IO_OUT|G_IO_HUP,
 291                                       cadence_uart_xmit, s);
 292         assert(r);
 293     }
 294
 295     uart_update_status(s);
 296     return FALSE;
 297 }
 298
 299 static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
 300                                int size)
 301 {
 302     if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
 303         return;
 304     }
 305
 306     if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) {
 307         size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count;
 308         /*
 309          * This can only be a guest error via a bad tx fifo register push,
 310          * as can_receive() should stop remote loop and echo modes ever getting
 311          * us to here.
 312          */
 313         qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow");
 314         s->r[R_CISR] |= UART_INTR_ROVR;
 315     }
 316
 317     memcpy(s->tx_fifo + s->tx_count, buf, size);
 318     s->tx_count += size;
 319
 320     cadence_uart_xmit(NULL, G_IO_OUT, s);
 321 }
 322
 323 static void uart_receive(void *opaque, const uint8_t *buf, int size)
 324 {
 325     CadenceUARTState *s = opaque;
 326     uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
 327
 328     if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
 329         uart_write_rx_fifo(opaque, buf, size);
 330     }
 331     if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
 332         uart_write_tx_fifo(s, buf, size);
 333     }
 334 }
 335
 336 static void uart_event(void *opaque, int event)
 337 {
 338     CadenceUARTState *s = opaque;
 339     uint8_t buf = '\0';
 340
 341     if (event == CHR_EVENT_BREAK) {
 342         uart_write_rx_fifo(opaque, &buf, 1);
 343     }
 344
 345     uart_update_status(s);
 346 }
 347
 348 static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c)
 349 {
 350     if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
 351         return;
 352     }
 353
 354     if (s->rx_count) {
 355         uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos -
 356                             s->rx_count) % CADENCE_UART_RX_FIFO_SIZE;
 357         *c = s->rx_fifo[rx_rpos];
 358         s->rx_count--;
 359
 360         if (s->chr) {
 361             qemu_chr_accept_input(s->chr);
 362         }
 363     } else {
 364         *c = 0;
 365     }
 366
 367     uart_update_status(s);
 368 }
 369
 370 static void uart_write(void *opaque, hwaddr offset,
 371                           uint64_t value, unsigned size)
 372 {
 373     CadenceUARTState *s = opaque;
 374
 375     DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
 376     offset >>= 2;
 377     switch (offset) {
 378     case R_IER: /* ier (wts imr) */
 379         s->r[R_IMR] |= value;
 380         break;
 381     case R_IDR: /* idr (wtc imr) */
 382         s->r[R_IMR] &= ~value;
 383         break;
 384     case R_IMR: /* imr (read only) */
 385         break;
 386     case R_CISR: /* cisr (wtc) */
 387         s->r[R_CISR] &= ~value;
 388         break;
 389     case R_TX_RX: /* UARTDR */
 390         switch (s->r[R_MR] & UART_MR_CHMODE) {
 391         case NORMAL_MODE:
 392             uart_write_tx_fifo(s, (uint8_t *) &value, 1);
 393             break;
 394         case LOCAL_LOOPBACK:
 395             uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);
 396             break;
 397         }
 398         break;
 399     default:
 400         s->r[offset] = value;
 401     }
 402
 403     switch (offset) {
 404     case R_CR:
 405         uart_ctrl_update(s);
 406         break;
 407     case R_MR:
 408         uart_parameters_setup(s);
 409         break;
 410     }
 411     uart_update_status(s);
 412 }
 413
 414 static uint64_t uart_read(void *opaque, hwaddr offset,
 415         unsigned size)
 416 {
 417     CadenceUARTState *s = opaque;
 418     uint32_t c = 0;
 419
 420     offset >>= 2;
 421     if (offset >= CADENCE_UART_R_MAX) {
 422         c = 0;
 423     } else if (offset == R_TX_RX) {
 424         uart_read_rx_fifo(s, &c);
 425     } else {
 426        c = s->r[offset];
 427     }
 428
 429     DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
 430     return c;
 431 }
 432
 433 static const MemoryRegionOps uart_ops = {
 434     .read = uart_read,
 435     .write = uart_write,
 436     .endianness = DEVICE_NATIVE_ENDIAN,
 437 };
 438
 439 static void cadence_uart_reset(DeviceState *dev)
 440 {
 441     CadenceUARTState *s = CADENCE_UART(dev);
 442
 443     s->r[R_CR] = 0x00000128;
 444     s->r[R_IMR] = 0;
 445     s->r[R_CISR] = 0;
 446     s->r[R_RTRIG] = 0x00000020;
 447     s->r[R_BRGR] = 0x0000000F;
 448     s->r[R_TTRIG] = 0x00000020;
 449
 450     uart_rx_reset(s);
 451     uart_tx_reset(s);
 452
 453     uart_update_status(s);
 454 }
 455
 456 static void cadence_uart_realize(DeviceState *dev, Error **errp)
 457 {
 458     CadenceUARTState *s = CADENCE_UART(dev);
 459
 460     s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 461                                           fifo_trigger_update, s);
 462
 463     /* FIXME use a qdev chardev prop instead of qemu_char_get_next_serial() */
 464     s->chr = qemu_char_get_next_serial();
 465
 466     if (s->chr) {
 467         qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive,
 468                               uart_event, s);
 469     }
 470 }
 471
 472 static void cadence_uart_init(Object *obj)
 473 {
 474     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 475     CadenceUARTState *s = CADENCE_UART(obj);
 476
 477     memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000);
 478     sysbus_init_mmio(sbd, &s->iomem);
 479     sysbus_init_irq(sbd, &s->irq);
 480
 481     s->char_tx_time = (get_ticks_per_sec() / 9600) * 10;
 482 }
 483
 484 static int cadence_uart_post_load(void *opaque, int version_id)
 485 {
 486     CadenceUARTState *s = opaque;
 487
 488     uart_parameters_setup(s);
 489     uart_update_status(s);
 490     return 0;
 491 }
 492
 493 static const VMStateDescription vmstate_cadence_uart = {
 494     .name = "cadence_uart",
 495     .version_id = 2,
 496     .minimum_version_id = 2,
 497     .post_load = cadence_uart_post_load,
 498     .fields = (VMStateField[]) {
 499         VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX),
 500         VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState,
 501                             CADENCE_UART_RX_FIFO_SIZE),
 502         VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState,
 503                             CADENCE_UART_TX_FIFO_SIZE),
 504         VMSTATE_UINT32(rx_count, CadenceUARTState),
 505         VMSTATE_UINT32(tx_count, CadenceUARTState),
 506         VMSTATE_UINT32(rx_wpos, CadenceUARTState),
 507         VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState),
 508         VMSTATE_END_OF_LIST()
 509     }
 510 };
 511
 512 static void cadence_uart_class_init(ObjectClass *klass, void *data)
 513 {
 514     DeviceClass *dc = DEVICE_CLASS(klass);
 515
 516     dc->realize = cadence_uart_realize;
 517     dc->vmsd = &vmstate_cadence_uart;
 518     dc->reset = cadence_uart_reset;
 519     /* Reason: realize() method uses qemu_char_get_next_serial() */
 520     dc->cannot_instantiate_with_device_add_yet = true;
 521 }
 522
 523 static const TypeInfo cadence_uart_info = {
 524     .name          = TYPE_CADENCE_UART,
 525     .parent        = TYPE_SYS_BUS_DEVICE,
 526     .instance_size = sizeof(CadenceUARTState),
 527     .instance_init = cadence_uart_init,
 528     .class_init    = cadence_uart_class_init,
 529 };
 530
 531 static void cadence_uart_register_types(void)
 532 {
 533     type_register_static(&cadence_uart_info);
 534 }
 535
 536 type_init(cadence_uart_register_types)