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Merge remote-tracking branch 'qemu/master'
[qemu/ar7.git] / target / i386 / kvm.c
blob252c1973fc786d1ae4e48bda0a4317942b5040f0
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/kvm_int.h"
28 #include "kvm_i386.h"
29 #include "hyperv.h"
30
31 #include "exec/gdbstub.h"
32 #include "qemu/host-utils.h"
33 #include "qemu/config-file.h"
34 #include "qemu/error-report.h"
35 #include "hw/i386/pc.h"
36 #include "hw/i386/apic.h"
37 #include "hw/i386/apic_internal.h"
38 #include "hw/i386/apic-msidef.h"
39 #include "hw/i386/intel_iommu.h"
40 #include "hw/i386/x86-iommu.h"
41
42 #include "exec/ioport.h"
43 #include "standard-headers/asm-x86/hyperv.h"
44 #include "hw/pci/pci.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci/msix.h"
47 #include "migration/blocker.h"
48 #include "exec/memattrs.h"
49 #include "trace.h"
50
51 //#define DEBUG_KVM
52
53 #ifdef DEBUG_KVM
54 #define DPRINTF(fmt, ...) \
55 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
56 #else
57 #define DPRINTF(fmt, ...) \
58 do { } while (0)
59 #endif
60
61 #define MSR_KVM_WALL_CLOCK 0x11
62 #define MSR_KVM_SYSTEM_TIME 0x12
63
64 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
65 * 255 kvm_msr_entry structs */
66 #define MSR_BUF_SIZE 4096
67
68 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
69 KVM_CAP_INFO(SET_TSS_ADDR),
70 KVM_CAP_INFO(EXT_CPUID),
71 KVM_CAP_INFO(MP_STATE),
72 KVM_CAP_LAST_INFO
73 };
74
75 static bool has_msr_star;
76 static bool has_msr_hsave_pa;
77 static bool has_msr_tsc_aux;
78 static bool has_msr_tsc_adjust;
79 static bool has_msr_tsc_deadline;
80 static bool has_msr_feature_control;
81 static bool has_msr_misc_enable;
82 static bool has_msr_smbase;
83 static bool has_msr_bndcfgs;
84 static int lm_capable_kernel;
85 static bool has_msr_hv_hypercall;
86 static bool has_msr_hv_crash;
87 static bool has_msr_hv_reset;
88 static bool has_msr_hv_vpindex;
89 static bool has_msr_hv_runtime;
90 static bool has_msr_hv_synic;
91 static bool has_msr_hv_stimer;
92 static bool has_msr_xss;
93
94 static bool has_msr_architectural_pmu;
95 static uint32_t num_architectural_pmu_counters;
96
97 static int has_xsave;
98 static int has_xcrs;
99 static int has_pit_state2;
100
101 static bool has_msr_mcg_ext_ctl;
102
103 static struct kvm_cpuid2 *cpuid_cache;
104
105 int kvm_has_pit_state2(void)
106 {
107 return has_pit_state2;
108 }
109
110 bool kvm_has_smm(void)
111 {
112 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
113 }
114
115 bool kvm_has_adjust_clock_stable(void)
116 {
117 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
118
119 return (ret == KVM_CLOCK_TSC_STABLE);
120 }
121
122 bool kvm_allows_irq0_override(void)
123 {
124 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
125 }
126
127 static bool kvm_x2apic_api_set_flags(uint64_t flags)
128 {
129 KVMState *s = KVM_STATE(current_machine->accelerator);
130
131 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
132 }
133
134 #define MEMORIZE(fn, _result) \
135 ({ \
136 static bool _memorized; \
137 \
138 if (_memorized) { \
139 return _result; \
140 } \
141 _memorized = true; \
142 _result = fn; \
143 })
144
145 static bool has_x2apic_api;
146
147 bool kvm_has_x2apic_api(void)
148 {
149 return has_x2apic_api;
150 }
151
152 bool kvm_enable_x2apic(void)
153 {
154 return MEMORIZE(
155 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
156 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
157 has_x2apic_api);
158 }
159
160 static int kvm_get_tsc(CPUState *cs)
161 {
162 X86CPU *cpu = X86_CPU(cs);
163 CPUX86State *env = &cpu->env;
164 struct {
165 struct kvm_msrs info;
166 struct kvm_msr_entry entries[1];
167 } msr_data;
168 int ret;
169
170 if (env->tsc_valid) {
171 return 0;
172 }
173
174 msr_data.info.nmsrs = 1;
175 msr_data.entries[0].index = MSR_IA32_TSC;
176 env->tsc_valid = !runstate_is_running();
177
178 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
179 if (ret < 0) {
180 return ret;
181 }
182
183 assert(ret == 1);
184 env->tsc = msr_data.entries[0].data;
185 return 0;
186 }
187
188 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
189 {
190 kvm_get_tsc(cpu);
191 }
192
193 void kvm_synchronize_all_tsc(void)
194 {
195 CPUState *cpu;
196
197 if (kvm_enabled()) {
198 CPU_FOREACH(cpu) {
199 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
200 }
201 }
202 }
203
204 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
205 {
206 struct kvm_cpuid2 *cpuid;
207 int r, size;
208
209 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
210 cpuid = g_malloc0(size);
211 cpuid->nent = max;
212 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
213 if (r == 0 && cpuid->nent >= max) {
214 r = -E2BIG;
215 }
216 if (r < 0) {
217 if (r == -E2BIG) {
218 g_free(cpuid);
219 return NULL;
220 } else {
221 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
222 strerror(-r));
223 exit(1);
224 }
225 }
226 return cpuid;
227 }
228
229 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
230 * for all entries.
231 */
232 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
233 {
234 struct kvm_cpuid2 *cpuid;
235 int max = 1;
236
237 if (cpuid_cache != NULL) {
238 return cpuid_cache;
239 }
240 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
241 max *= 2;
242 }
243 cpuid_cache = cpuid;
244 return cpuid;
245 }
246
247 static const struct kvm_para_features {
248 int cap;
249 int feature;
250 } para_features[] = {
251 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
252 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
253 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
254 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
255 };
256
257 static int get_para_features(KVMState *s)
258 {
259 int i, features = 0;
260
261 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
262 if (kvm_check_extension(s, para_features[i].cap)) {
263 features |= (1 << para_features[i].feature);
264 }
265 }
266
267 return features;
268 }
269
270 static bool host_tsx_blacklisted(void)
271 {
272 int family, model, stepping;\
273 char vendor[CPUID_VENDOR_SZ + 1];
274
275 host_vendor_fms(vendor, &family, &model, &stepping);
276
277 /* Check if we are running on a Haswell host known to have broken TSX */
278 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
279 (family == 6) &&
280 ((model == 63 && stepping < 4) ||
281 model == 60 || model == 69 || model == 70);
282 }
283
284 /* Returns the value for a specific register on the cpuid entry
285 */
286 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
287 {
288 uint32_t ret = 0;
289 switch (reg) {
290 case R_EAX:
291 ret = entry->eax;
292 break;
293 case R_EBX:
294 ret = entry->ebx;
295 break;
296 case R_ECX:
297 ret = entry->ecx;
298 break;
299 case R_EDX:
300 ret = entry->edx;
301 break;
302 }
303 return ret;
304 }
305
306 /* Find matching entry for function/index on kvm_cpuid2 struct
307 */
308 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
309 uint32_t function,
310 uint32_t index)
311 {
312 int i;
313 for (i = 0; i < cpuid->nent; ++i) {
314 if (cpuid->entries[i].function == function &&
315 cpuid->entries[i].index == index) {
316 return &cpuid->entries[i];
317 }
318 }
319 /* not found: */
320 return NULL;
321 }
322
323 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
324 uint32_t index, int reg)
325 {
326 struct kvm_cpuid2 *cpuid;
327 uint32_t ret = 0;
328 uint32_t cpuid_1_edx;
329 bool found = false;
330
331 cpuid = get_supported_cpuid(s);
332
333 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
334 if (entry) {
335 found = true;
336 ret = cpuid_entry_get_reg(entry, reg);
337 }
338
339 /* Fixups for the data returned by KVM, below */
340
341 if (function == 1 && reg == R_EDX) {
342 /* KVM before 2.6.30 misreports the following features */
343 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
344 } else if (function == 1 && reg == R_ECX) {
345 /* We can set the hypervisor flag, even if KVM does not return it on
346 * GET_SUPPORTED_CPUID
347 */
348 ret |= CPUID_EXT_HYPERVISOR;
349 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
350 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
351 * and the irqchip is in the kernel.
352 */
353 if (kvm_irqchip_in_kernel() &&
354 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
355 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
356 }
357
358 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
359 * without the in-kernel irqchip
360 */
361 if (!kvm_irqchip_in_kernel()) {
362 ret &= ~CPUID_EXT_X2APIC;
363 }
364 } else if (function == 6 && reg == R_EAX) {
365 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
366 } else if (function == 7 && index == 0 && reg == R_EBX) {
367 if (host_tsx_blacklisted()) {
368 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
369 }
370 } else if (function == 0x80000001 && reg == R_EDX) {
371 /* On Intel, kvm returns cpuid according to the Intel spec,
372 * so add missing bits according to the AMD spec:
373 */
374 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
375 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
376 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
377 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
378 * be enabled without the in-kernel irqchip
379 */
380 if (!kvm_irqchip_in_kernel()) {
381 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
382 }
383 }
384
385 /* fallback for older kernels */
386 if ((function == KVM_CPUID_FEATURES) && !found) {
387 ret = get_para_features(s);
388 }
389
390 return ret;
391 }
392
393 typedef struct HWPoisonPage {
394 ram_addr_t ram_addr;
395 QLIST_ENTRY(HWPoisonPage) list;
396 } HWPoisonPage;
397
398 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
399 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
400
401 static void kvm_unpoison_all(void *param)
402 {
403 HWPoisonPage *page, *next_page;
404
405 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
406 QLIST_REMOVE(page, list);
407 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
408 g_free(page);
409 }
410 }
411
412 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
413 {
414 HWPoisonPage *page;
415
416 QLIST_FOREACH(page, &hwpoison_page_list, list) {
417 if (page->ram_addr == ram_addr) {
418 return;
419 }
420 }
421 page = g_new(HWPoisonPage, 1);
422 page->ram_addr = ram_addr;
423 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
424 }
425
426 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
427 int *max_banks)
428 {
429 int r;
430
431 r = kvm_check_extension(s, KVM_CAP_MCE);
432 if (r > 0) {
433 *max_banks = r;
434 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
435 }
436 return -ENOSYS;
437 }
438
439 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
440 {
441 CPUState *cs = CPU(cpu);
442 CPUX86State *env = &cpu->env;
443 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
444 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
445 uint64_t mcg_status = MCG_STATUS_MCIP;
446 int flags = 0;
447
448 if (code == BUS_MCEERR_AR) {
449 status |= MCI_STATUS_AR | 0x134;
450 mcg_status |= MCG_STATUS_EIPV;
451 } else {
452 status |= 0xc0;
453 mcg_status |= MCG_STATUS_RIPV;
454 }
455
456 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
457 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
458 * guest kernel back into env->mcg_ext_ctl.
459 */
460 cpu_synchronize_state(cs);
461 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
462 mcg_status |= MCG_STATUS_LMCE;
463 flags = 0;
464 }
465
466 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
467 (MCM_ADDR_PHYS << 6) | 0xc, flags);
468 }
469
470 static void hardware_memory_error(void)
471 {
472 fprintf(stderr, "Hardware memory error!\n");
473 exit(1);
474 }
475
476 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
477 {
478 X86CPU *cpu = X86_CPU(c);
479 CPUX86State *env = &cpu->env;
480 ram_addr_t ram_addr;
481 hwaddr paddr;
482
483 /* If we get an action required MCE, it has been injected by KVM
484 * while the VM was running. An action optional MCE instead should
485 * be coming from the main thread, which qemu_init_sigbus identifies
486 * as the "early kill" thread.
487 */
488 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
489
490 if ((env->mcg_cap & MCG_SER_P) && addr) {
491 ram_addr = qemu_ram_addr_from_host(addr);
492 if (ram_addr != RAM_ADDR_INVALID &&
493 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
494 kvm_hwpoison_page_add(ram_addr);
495 kvm_mce_inject(cpu, paddr, code);
496 return;
497 }
498
499 fprintf(stderr, "Hardware memory error for memory used by "
500 "QEMU itself instead of guest system!\n");
501 }
502
503 if (code == BUS_MCEERR_AR) {
504 hardware_memory_error();
505 }
506
507 /* Hope we are lucky for AO MCE */
508 }
509
510 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
511 {
512 CPUX86State *env = &cpu->env;
513
514 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
515 unsigned int bank, bank_num = env->mcg_cap & 0xff;
516 struct kvm_x86_mce mce;
517
518 env->exception_injected = -1;
519
520 /*
521 * There must be at least one bank in use if an MCE is pending.
522 * Find it and use its values for the event injection.
523 */
524 for (bank = 0; bank < bank_num; bank++) {
525 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
526 break;
527 }
528 }
529 assert(bank < bank_num);
530
531 mce.bank = bank;
532 mce.status = env->mce_banks[bank * 4 + 1];
533 mce.mcg_status = env->mcg_status;
534 mce.addr = env->mce_banks[bank * 4 + 2];
535 mce.misc = env->mce_banks[bank * 4 + 3];
536
537 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
538 }
539 return 0;
540 }
541
542 static void cpu_update_state(void *opaque, int running, RunState state)
543 {
544 CPUX86State *env = opaque;
545
546 if (running) {
547 env->tsc_valid = false;
548 }
549 }
550
551 unsigned long kvm_arch_vcpu_id(CPUState *cs)
552 {
553 X86CPU *cpu = X86_CPU(cs);
554 return cpu->apic_id;
555 }
556
557 #ifndef KVM_CPUID_SIGNATURE_NEXT
558 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
559 #endif
560
561 static bool hyperv_hypercall_available(X86CPU *cpu)
562 {
563 return cpu->hyperv_vapic ||
564 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
565 }
566
567 static bool hyperv_enabled(X86CPU *cpu)
568 {
569 CPUState *cs = CPU(cpu);
570 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
571 (hyperv_hypercall_available(cpu) ||
572 cpu->hyperv_time ||
573 cpu->hyperv_relaxed_timing ||
574 cpu->hyperv_crash ||
575 cpu->hyperv_reset ||
576 cpu->hyperv_vpindex ||
577 cpu->hyperv_runtime ||
578 cpu->hyperv_synic ||
579 cpu->hyperv_stimer);
580 }
581
582 static int kvm_arch_set_tsc_khz(CPUState *cs)
583 {
584 X86CPU *cpu = X86_CPU(cs);
585 CPUX86State *env = &cpu->env;
586 int r;
587
588 if (!env->tsc_khz) {
589 return 0;
590 }
591
592 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
593 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
594 -ENOTSUP;
595 if (r < 0) {
596 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
597 * TSC frequency doesn't match the one we want.
598 */
599 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
600 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
601 -ENOTSUP;
602 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
603 error_report("warning: TSC frequency mismatch between "
604 "VM (%" PRId64 " kHz) and host (%d kHz), "
605 "and TSC scaling unavailable",
606 env->tsc_khz, cur_freq);
607 return r;
608 }
609 }
610
611 return 0;
612 }
613
614 static int hyperv_handle_properties(CPUState *cs)
615 {
616 X86CPU *cpu = X86_CPU(cs);
617 CPUX86State *env = &cpu->env;
618
619 if (cpu->hyperv_time &&
620 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
621 cpu->hyperv_time = false;
622 }
623
624 if (cpu->hyperv_relaxed_timing) {
625 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
626 }
627 if (cpu->hyperv_vapic) {
628 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
629 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
630 }
631 if (cpu->hyperv_time) {
632 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
633 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
634 env->features[FEAT_HYPERV_EAX] |= 0x200;
635 }
636 if (cpu->hyperv_crash && has_msr_hv_crash) {
637 env->features[FEAT_HYPERV_EDX] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
638 }
639 env->features[FEAT_HYPERV_EDX] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
640 if (cpu->hyperv_reset && has_msr_hv_reset) {
641 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_RESET_AVAILABLE;
642 }
643 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
644 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_INDEX_AVAILABLE;
645 }
646 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
647 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
648 }
649 if (cpu->hyperv_synic) {
650 int sint;
651
652 if (!has_msr_hv_synic ||
653 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
654 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
655 return -ENOSYS;
656 }
657
658 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNIC_AVAILABLE;
659 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
660 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
661 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
662 }
663 }
664 if (cpu->hyperv_stimer) {
665 if (!has_msr_hv_stimer) {
666 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
667 return -ENOSYS;
668 }
669 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNTIMER_AVAILABLE;
670 }
671 return 0;
672 }
673
674 static Error *invtsc_mig_blocker;
675
676 #define KVM_MAX_CPUID_ENTRIES 100
677
678 int kvm_arch_init_vcpu(CPUState *cs)
679 {
680 struct {
681 struct kvm_cpuid2 cpuid;
682 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
683 } QEMU_PACKED cpuid_data;
684 X86CPU *cpu = X86_CPU(cs);
685 CPUX86State *env = &cpu->env;
686 uint32_t limit, i, j, cpuid_i;
687 uint32_t unused;
688 struct kvm_cpuid_entry2 *c;
689 uint32_t signature[3];
690 int kvm_base = KVM_CPUID_SIGNATURE;
691 int r;
692 Error *local_err = NULL;
693
694 memset(&cpuid_data, 0, sizeof(cpuid_data));
695
696 cpuid_i = 0;
697
698 /* Paravirtualization CPUIDs */
699 if (hyperv_enabled(cpu)) {
700 c = &cpuid_data.entries[cpuid_i++];
701 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
702 if (!cpu->hyperv_vendor_id) {
703 memcpy(signature, "Microsoft Hv", 12);
704 } else {
705 size_t len = strlen(cpu->hyperv_vendor_id);
706
707 if (len > 12) {
708 error_report("hv-vendor-id truncated to 12 characters");
709 len = 12;
710 }
711 memset(signature, 0, 12);
712 memcpy(signature, cpu->hyperv_vendor_id, len);
713 }
714 c->eax = HYPERV_CPUID_MIN;
715 c->ebx = signature[0];
716 c->ecx = signature[1];
717 c->edx = signature[2];
718
719 c = &cpuid_data.entries[cpuid_i++];
720 c->function = HYPERV_CPUID_INTERFACE;
721 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
722 c->eax = signature[0];
723 c->ebx = 0;
724 c->ecx = 0;
725 c->edx = 0;
726
727 c = &cpuid_data.entries[cpuid_i++];
728 c->function = HYPERV_CPUID_VERSION;
729 c->eax = 0x00001bbc;
730 c->ebx = 0x00060001;
731
732 c = &cpuid_data.entries[cpuid_i++];
733 c->function = HYPERV_CPUID_FEATURES;
734 r = hyperv_handle_properties(cs);
735 if (r) {
736 return r;
737 }
738 c->eax = env->features[FEAT_HYPERV_EAX];
739 c->ebx = env->features[FEAT_HYPERV_EBX];
740 c->edx = env->features[FEAT_HYPERV_EDX];
741
742 c = &cpuid_data.entries[cpuid_i++];
743 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
744 if (cpu->hyperv_relaxed_timing) {
745 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
746 }
747 if (cpu->hyperv_vapic) {
748 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
749 }
750 c->ebx = cpu->hyperv_spinlock_attempts;
751
752 c = &cpuid_data.entries[cpuid_i++];
753 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
754 c->eax = 0x40;
755 c->ebx = 0x40;
756
757 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
758 has_msr_hv_hypercall = true;
759 }
760
761 if (cpu->expose_kvm) {
762 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
763 c = &cpuid_data.entries[cpuid_i++];
764 c->function = KVM_CPUID_SIGNATURE | kvm_base;
765 c->eax = KVM_CPUID_FEATURES | kvm_base;
766 c->ebx = signature[0];
767 c->ecx = signature[1];
768 c->edx = signature[2];
769
770 c = &cpuid_data.entries[cpuid_i++];
771 c->function = KVM_CPUID_FEATURES | kvm_base;
772 c->eax = env->features[FEAT_KVM];
773 }
774
775 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
776
777 for (i = 0; i <= limit; i++) {
778 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
779 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
780 abort();
781 }
782 c = &cpuid_data.entries[cpuid_i++];
783 assert(cpuid_i < 100);
784
785 switch (i) {
786 case 2: {
787 /* Keep reading function 2 till all the input is received */
788 int times;
789
790 c->function = i;
791 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
792 KVM_CPUID_FLAG_STATE_READ_NEXT;
793 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
794 times = c->eax & 0xff;
795
796 for (j = 1; j < times; ++j) {
797 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
798 fprintf(stderr, "cpuid_data is full, no space for "
799 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
800 abort();
801 }
802 c = &cpuid_data.entries[cpuid_i++];
803 c->function = i;
804 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
805 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
806 }
807 break;
808 }
809 case 4:
810 case 0xb:
811 case 0xd:
812 for (j = 0; ; j++) {
813 if (i == 0xd && j == 64) {
814 break;
815 }
816 c->function = i;
817 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
818 c->index = j;
819 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
820
821 if (i == 4 && c->eax == 0) {
822 break;
823 }
824 if (i == 0xb && !(c->ecx & 0xff00)) {
825 break;
826 }
827 if (i == 0xd && c->eax == 0) {
828 continue;
829 }
830 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
831 fprintf(stderr, "cpuid_data is full, no space for "
832 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
833 abort();
834 }
835 c = &cpuid_data.entries[cpuid_i++];
836 }
837 break;
838 default:
839 c->function = i;
840 c->flags = 0;
841 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
842 break;
843 }
844 }
845
846 if (limit >= 0x0a) {
847 uint32_t ver;
848
849 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
850 if ((ver & 0xff) > 0) {
851 has_msr_architectural_pmu = true;
852 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
853
854 /* Shouldn't be more than 32, since that's the number of bits
855 * available in EBX to tell us _which_ counters are available.
856 * Play it safe.
857 */
858 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
859 num_architectural_pmu_counters = MAX_GP_COUNTERS;
860 }
861 }
862 }
863
864 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
865
866 for (i = 0x80000000; i <= limit; i++) {
867 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
868 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
869 abort();
870 }
871 c = &cpuid_data.entries[cpuid_i++];
872 assert(cpuid_i < 100);
873
874 c->function = i;
875 c->flags = 0;
876 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
877 }
878
879 /* Call Centaur's CPUID instructions they are supported. */
880 if (env->cpuid_xlevel2 > 0) {
881 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
882
883 for (i = 0xC0000000; i <= limit; i++) {
884 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
885 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
886 abort();
887 }
888 c = &cpuid_data.entries[cpuid_i++];
889
890 c->function = i;
891 c->flags = 0;
892 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
893 }
894 }
895
896 cpuid_data.cpuid.nent = cpuid_i;
897
898 if (((env->cpuid_version >> 8)&0xF) >= 6
899 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
900 (CPUID_MCE | CPUID_MCA)
901 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
902 uint64_t mcg_cap, unsupported_caps;
903 int banks;
904 int ret;
905
906 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
907 if (ret < 0) {
908 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
909 return ret;
910 }
911
912 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
913 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
914 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
915 return -ENOTSUP;
916 }
917
918 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
919 if (unsupported_caps) {
920 if (unsupported_caps & MCG_LMCE_P) {
921 error_report("kvm: LMCE not supported");
922 return -ENOTSUP;
923 }
924 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
925 unsupported_caps);
926 }
927
928 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
929 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
930 if (ret < 0) {
931 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
932 return ret;
933 }
934 }
935
936 qemu_add_vm_change_state_handler(cpu_update_state, env);
937
938 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
939 if (c) {
940 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
941 !!(c->ecx & CPUID_EXT_SMX);
942 }
943
944 if (env->mcg_cap & MCG_LMCE_P) {
945 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
946 }
947
948 if (!env->user_tsc_khz) {
949 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
950 invtsc_mig_blocker == NULL) {
951 /* for migration */
952 error_setg(&invtsc_mig_blocker,
953 "State blocked by non-migratable CPU device"
954 " (invtsc flag)");
955 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
956 if (local_err) {
957 error_report_err(local_err);
958 error_free(invtsc_mig_blocker);
959 goto fail;
960 }
961 /* for savevm */
962 vmstate_x86_cpu.unmigratable = 1;
963 }
964 }
965
966 r = kvm_arch_set_tsc_khz(cs);
967 if (r < 0) {
968 goto fail;
969 }
970
971 /* vcpu's TSC frequency is either specified by user, or following
972 * the value used by KVM if the former is not present. In the
973 * latter case, we query it from KVM and record in env->tsc_khz,
974 * so that vcpu's TSC frequency can be migrated later via this field.
975 */
976 if (!env->tsc_khz) {
977 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
978 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
979 -ENOTSUP;
980 if (r > 0) {
981 env->tsc_khz = r;
982 }
983 }
984
985 if (cpu->vmware_cpuid_freq
986 /* Guests depend on 0x40000000 to detect this feature, so only expose
987 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
988 && cpu->expose_kvm
989 && kvm_base == KVM_CPUID_SIGNATURE
990 /* TSC clock must be stable and known for this feature. */
991 && ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
992 || env->user_tsc_khz != 0)
993 && env->tsc_khz != 0) {
994
995 c = &cpuid_data.entries[cpuid_i++];
996 c->function = KVM_CPUID_SIGNATURE | 0x10;
997 c->eax = env->tsc_khz;
998 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
999 * APIC_BUS_CYCLE_NS */
1000 c->ebx = 1000000;
1001 c->ecx = c->edx = 0;
1002
1003 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1004 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1005 }
1006
1007 cpuid_data.cpuid.nent = cpuid_i;
1008
1009 cpuid_data.cpuid.padding = 0;
1010 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1011 if (r) {
1012 goto fail;
1013 }
1014
1015 if (has_xsave) {
1016 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1017 }
1018 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1019
1020 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1021 has_msr_tsc_aux = false;
1022 }
1023
1024 return 0;
1025
1026 fail:
1027 migrate_del_blocker(invtsc_mig_blocker);
1028 return r;
1029 }
1030
1031 void kvm_arch_reset_vcpu(X86CPU *cpu)
1032 {
1033 CPUX86State *env = &cpu->env;
1034
1035 env->exception_injected = -1;
1036 env->interrupt_injected = -1;
1037 env->xcr0 = 1;
1038 if (kvm_irqchip_in_kernel()) {
1039 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1040 KVM_MP_STATE_UNINITIALIZED;
1041 } else {
1042 env->mp_state = KVM_MP_STATE_RUNNABLE;
1043 }
1044 }
1045
1046 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1047 {
1048 CPUX86State *env = &cpu->env;
1049
1050 /* APs get directly into wait-for-SIPI state. */
1051 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1052 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1053 }
1054 }
1055
1056 static int kvm_get_supported_msrs(KVMState *s)
1057 {
1058 static int kvm_supported_msrs;
1059 int ret = 0;
1060
1061 /* first time */
1062 if (kvm_supported_msrs == 0) {
1063 struct kvm_msr_list msr_list, *kvm_msr_list;
1064
1065 kvm_supported_msrs = -1;
1066
1067 /* Obtain MSR list from KVM. These are the MSRs that we must
1068 * save/restore */
1069 msr_list.nmsrs = 0;
1070 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1071 if (ret < 0 && ret != -E2BIG) {
1072 return ret;
1073 }
1074 /* Old kernel modules had a bug and could write beyond the provided
1075 memory. Allocate at least a safe amount of 1K. */
1076 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1077 msr_list.nmsrs *
1078 sizeof(msr_list.indices[0])));
1079
1080 kvm_msr_list->nmsrs = msr_list.nmsrs;
1081 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1082 if (ret >= 0) {
1083 int i;
1084
1085 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1086 if (kvm_msr_list->indices[i] == MSR_STAR) {
1087 has_msr_star = true;
1088 continue;
1089 }
1090 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
1091 has_msr_hsave_pa = true;
1092 continue;
1093 }
1094 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
1095 has_msr_tsc_aux = true;
1096 continue;
1097 }
1098 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1099 has_msr_tsc_adjust = true;
1100 continue;
1101 }
1102 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1103 has_msr_tsc_deadline = true;
1104 continue;
1105 }
1106 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1107 has_msr_smbase = true;
1108 continue;
1109 }
1110 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1111 has_msr_misc_enable = true;
1112 continue;
1113 }
1114 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1115 has_msr_bndcfgs = true;
1116 continue;
1117 }
1118 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1119 has_msr_xss = true;
1120 continue;
1121 }
1122 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1123 has_msr_hv_crash = true;
1124 continue;
1125 }
1126 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1127 has_msr_hv_reset = true;
1128 continue;
1129 }
1130 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1131 has_msr_hv_vpindex = true;
1132 continue;
1133 }
1134 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1135 has_msr_hv_runtime = true;
1136 continue;
1137 }
1138 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1139 has_msr_hv_synic = true;
1140 continue;
1141 }
1142 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1143 has_msr_hv_stimer = true;
1144 continue;
1145 }
1146 }
1147 }
1148
1149 g_free(kvm_msr_list);
1150 }
1151
1152 return ret;
1153 }
1154
1155 static Notifier smram_machine_done;
1156 static KVMMemoryListener smram_listener;
1157 static AddressSpace smram_address_space;
1158 static MemoryRegion smram_as_root;
1159 static MemoryRegion smram_as_mem;
1160
1161 static void register_smram_listener(Notifier *n, void *unused)
1162 {
1163 MemoryRegion *smram =
1164 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1165
1166 /* Outer container... */
1167 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1168 memory_region_set_enabled(&smram_as_root, true);
1169
1170 /* ... with two regions inside: normal system memory with low
1171 * priority, and...
1172 */
1173 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1174 get_system_memory(), 0, ~0ull);
1175 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1176 memory_region_set_enabled(&smram_as_mem, true);
1177
1178 if (smram) {
1179 /* ... SMRAM with higher priority */
1180 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1181 memory_region_set_enabled(smram, true);
1182 }
1183
1184 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1185 kvm_memory_listener_register(kvm_state, &smram_listener,
1186 &smram_address_space, 1);
1187 }
1188
1189 int kvm_arch_init(MachineState *ms, KVMState *s)
1190 {
1191 uint64_t identity_base = 0xfffbc000;
1192 uint64_t shadow_mem;
1193 int ret;
1194 struct utsname utsname;
1195
1196 #ifdef KVM_CAP_XSAVE
1197 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1198 #endif
1199
1200 #ifdef KVM_CAP_XCRS
1201 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1202 #endif
1203
1204 #ifdef KVM_CAP_PIT_STATE2
1205 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1206 #endif
1207
1208 ret = kvm_get_supported_msrs(s);
1209 if (ret < 0) {
1210 return ret;
1211 }
1212
1213 uname(&utsname);
1214 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1215
1216 /*
1217 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1218 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1219 * Since these must be part of guest physical memory, we need to allocate
1220 * them, both by setting their start addresses in the kernel and by
1221 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1222 *
1223 * Older KVM versions may not support setting the identity map base. In
1224 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1225 * size.
1226 */
1227 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1228 /* Allows up to 16M BIOSes. */
1229 identity_base = 0xfeffc000;
1230
1231 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1232 if (ret < 0) {
1233 return ret;
1234 }
1235 }
1236
1237 /* Set TSS base one page after EPT identity map. */
1238 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1239 if (ret < 0) {
1240 return ret;
1241 }
1242
1243 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1244 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1245 if (ret < 0) {
1246 fprintf(stderr, "e820_add_entry() table is full\n");
1247 return ret;
1248 }
1249 qemu_register_reset(kvm_unpoison_all, NULL);
1250
1251 shadow_mem = machine_kvm_shadow_mem(ms);
1252 if (shadow_mem != -1) {
1253 shadow_mem /= 4096;
1254 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1255 if (ret < 0) {
1256 return ret;
1257 }
1258 }
1259
1260 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1261 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1262 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
1263 smram_machine_done.notify = register_smram_listener;
1264 qemu_add_machine_init_done_notifier(&smram_machine_done);
1265 }
1266 return 0;
1267 }
1268
1269 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1270 {
1271 lhs->selector = rhs->selector;
1272 lhs->base = rhs->base;
1273 lhs->limit = rhs->limit;
1274 lhs->type = 3;
1275 lhs->present = 1;
1276 lhs->dpl = 3;
1277 lhs->db = 0;
1278 lhs->s = 1;
1279 lhs->l = 0;
1280 lhs->g = 0;
1281 lhs->avl = 0;
1282 lhs->unusable = 0;
1283 }
1284
1285 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1286 {
1287 unsigned flags = rhs->flags;
1288 lhs->selector = rhs->selector;
1289 lhs->base = rhs->base;
1290 lhs->limit = rhs->limit;
1291 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1292 lhs->present = (flags & DESC_P_MASK) != 0;
1293 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1294 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1295 lhs->s = (flags & DESC_S_MASK) != 0;
1296 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1297 lhs->g = (flags & DESC_G_MASK) != 0;
1298 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1299 lhs->unusable = !lhs->present;
1300 lhs->padding = 0;
1301 }
1302
1303 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1304 {
1305 lhs->selector = rhs->selector;
1306 lhs->base = rhs->base;
1307 lhs->limit = rhs->limit;
1308 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1309 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1310 (rhs->dpl << DESC_DPL_SHIFT) |
1311 (rhs->db << DESC_B_SHIFT) |
1312 (rhs->s * DESC_S_MASK) |
1313 (rhs->l << DESC_L_SHIFT) |
1314 (rhs->g * DESC_G_MASK) |
1315 (rhs->avl * DESC_AVL_MASK);
1316 }
1317
1318 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1319 {
1320 if (set) {
1321 *kvm_reg = *qemu_reg;
1322 } else {
1323 *qemu_reg = *kvm_reg;
1324 }
1325 }
1326
1327 static int kvm_getput_regs(X86CPU *cpu, int set)
1328 {
1329 CPUX86State *env = &cpu->env;
1330 struct kvm_regs regs;
1331 int ret = 0;
1332
1333 if (!set) {
1334 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1335 if (ret < 0) {
1336 return ret;
1337 }
1338 }
1339
1340 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1341 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1342 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1343 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1344 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1345 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1346 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1347 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1348 #ifdef TARGET_X86_64
1349 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1350 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1351 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1352 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1353 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1354 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1355 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1356 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1357 #endif
1358
1359 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1360 kvm_getput_reg(&regs.rip, &env->eip, set);
1361
1362 if (set) {
1363 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1364 }
1365
1366 return ret;
1367 }
1368
1369 static int kvm_put_fpu(X86CPU *cpu)
1370 {
1371 CPUX86State *env = &cpu->env;
1372 struct kvm_fpu fpu;
1373 int i;
1374
1375 memset(&fpu, 0, sizeof fpu);
1376 fpu.fsw = env->fpus & ~(7 << 11);
1377 fpu.fsw |= (env->fpstt & 7) << 11;
1378 fpu.fcw = env->fpuc;
1379 fpu.last_opcode = env->fpop;
1380 fpu.last_ip = env->fpip;
1381 fpu.last_dp = env->fpdp;
1382 for (i = 0; i < 8; ++i) {
1383 fpu.ftwx |= (!env->fptags[i]) << i;
1384 }
1385 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1386 for (i = 0; i < CPU_NB_REGS; i++) {
1387 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1388 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1389 }
1390 fpu.mxcsr = env->mxcsr;
1391
1392 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1393 }
1394
1395 #define XSAVE_FCW_FSW 0
1396 #define XSAVE_FTW_FOP 1
1397 #define XSAVE_CWD_RIP 2
1398 #define XSAVE_CWD_RDP 4
1399 #define XSAVE_MXCSR 6
1400 #define XSAVE_ST_SPACE 8
1401 #define XSAVE_XMM_SPACE 40
1402 #define XSAVE_XSTATE_BV 128
1403 #define XSAVE_YMMH_SPACE 144
1404 #define XSAVE_BNDREGS 240
1405 #define XSAVE_BNDCSR 256
1406 #define XSAVE_OPMASK 272
1407 #define XSAVE_ZMM_Hi256 288
1408 #define XSAVE_Hi16_ZMM 416
1409 #define XSAVE_PKRU 672
1410
1411 #define XSAVE_BYTE_OFFSET(word_offset) \
1412 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1413
1414 #define ASSERT_OFFSET(word_offset, field) \
1415 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1416 offsetof(X86XSaveArea, field))
1417
1418 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1419 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1420 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1421 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1422 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1423 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1424 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1425 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1426 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1427 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1428 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1429 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1430 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1431 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1432 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1433
1434 static int kvm_put_xsave(X86CPU *cpu)
1435 {
1436 CPUX86State *env = &cpu->env;
1437 X86XSaveArea *xsave = env->kvm_xsave_buf;
1438 uint16_t cwd, swd, twd;
1439 int i;
1440
1441 if (!has_xsave) {
1442 return kvm_put_fpu(cpu);
1443 }
1444
1445 memset(xsave, 0, sizeof(struct kvm_xsave));
1446 twd = 0;
1447 swd = env->fpus & ~(7 << 11);
1448 swd |= (env->fpstt & 7) << 11;
1449 cwd = env->fpuc;
1450 for (i = 0; i < 8; ++i) {
1451 twd |= (!env->fptags[i]) << i;
1452 }
1453 xsave->legacy.fcw = cwd;
1454 xsave->legacy.fsw = swd;
1455 xsave->legacy.ftw = twd;
1456 xsave->legacy.fpop = env->fpop;
1457 xsave->legacy.fpip = env->fpip;
1458 xsave->legacy.fpdp = env->fpdp;
1459 memcpy(&xsave->legacy.fpregs, env->fpregs,
1460 sizeof env->fpregs);
1461 xsave->legacy.mxcsr = env->mxcsr;
1462 xsave->header.xstate_bv = env->xstate_bv;
1463 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
1464 sizeof env->bnd_regs);
1465 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1466 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
1467 sizeof env->opmask_regs);
1468
1469 for (i = 0; i < CPU_NB_REGS; i++) {
1470 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1471 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1472 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1473 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1474 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1475 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1476 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1477 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1478 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1479 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1480 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
1481 }
1482
1483 #ifdef TARGET_X86_64
1484 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
1485 16 * sizeof env->xmm_regs[16]);
1486 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
1487 #endif
1488 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1489 }
1490
1491 static int kvm_put_xcrs(X86CPU *cpu)
1492 {
1493 CPUX86State *env = &cpu->env;
1494 struct kvm_xcrs xcrs = {};
1495
1496 if (!has_xcrs) {
1497 return 0;
1498 }
1499
1500 xcrs.nr_xcrs = 1;
1501 xcrs.flags = 0;
1502 xcrs.xcrs[0].xcr = 0;
1503 xcrs.xcrs[0].value = env->xcr0;
1504 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1505 }
1506
1507 static int kvm_put_sregs(X86CPU *cpu)
1508 {
1509 CPUX86State *env = &cpu->env;
1510 struct kvm_sregs sregs;
1511
1512 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1513 if (env->interrupt_injected >= 0) {
1514 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1515 (uint64_t)1 << (env->interrupt_injected % 64);
1516 }
1517
1518 if ((env->eflags & VM_MASK)) {
1519 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1520 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1521 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1522 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1523 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1524 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1525 } else {
1526 set_seg(&sregs.cs, &env->segs[R_CS]);
1527 set_seg(&sregs.ds, &env->segs[R_DS]);
1528 set_seg(&sregs.es, &env->segs[R_ES]);
1529 set_seg(&sregs.fs, &env->segs[R_FS]);
1530 set_seg(&sregs.gs, &env->segs[R_GS]);
1531 set_seg(&sregs.ss, &env->segs[R_SS]);
1532 }
1533
1534 set_seg(&sregs.tr, &env->tr);
1535 set_seg(&sregs.ldt, &env->ldt);
1536
1537 sregs.idt.limit = env->idt.limit;
1538 sregs.idt.base = env->idt.base;
1539 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1540 sregs.gdt.limit = env->gdt.limit;
1541 sregs.gdt.base = env->gdt.base;
1542 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1543
1544 sregs.cr0 = env->cr[0];
1545 sregs.cr2 = env->cr[2];
1546 sregs.cr3 = env->cr[3];
1547 sregs.cr4 = env->cr[4];
1548
1549 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1550 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1551
1552 sregs.efer = env->efer;
1553
1554 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1555 }
1556
1557 static void kvm_msr_buf_reset(X86CPU *cpu)
1558 {
1559 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1560 }
1561
1562 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1563 {
1564 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1565 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1566 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1567
1568 assert((void *)(entry + 1) <= limit);
1569
1570 entry->index = index;
1571 entry->reserved = 0;
1572 entry->data = value;
1573 msrs->nmsrs++;
1574 }
1575
1576 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1577 {
1578 kvm_msr_buf_reset(cpu);
1579 kvm_msr_entry_add(cpu, index, value);
1580
1581 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1582 }
1583
1584 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1585 {
1586 int ret;
1587
1588 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1589 assert(ret == 1);
1590 }
1591
1592 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1593 {
1594 CPUX86State *env = &cpu->env;
1595 int ret;
1596
1597 if (!has_msr_tsc_deadline) {
1598 return 0;
1599 }
1600
1601 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1602 if (ret < 0) {
1603 return ret;
1604 }
1605
1606 assert(ret == 1);
1607 return 0;
1608 }
1609
1610 /*
1611 * Provide a separate write service for the feature control MSR in order to
1612 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1613 * before writing any other state because forcibly leaving nested mode
1614 * invalidates the VCPU state.
1615 */
1616 static int kvm_put_msr_feature_control(X86CPU *cpu)
1617 {
1618 int ret;
1619
1620 if (!has_msr_feature_control) {
1621 return 0;
1622 }
1623
1624 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1625 cpu->env.msr_ia32_feature_control);
1626 if (ret < 0) {
1627 return ret;
1628 }
1629
1630 assert(ret == 1);
1631 return 0;
1632 }
1633
1634 static int kvm_put_msrs(X86CPU *cpu, int level)
1635 {
1636 CPUX86State *env = &cpu->env;
1637 int i;
1638 int ret;
1639
1640 kvm_msr_buf_reset(cpu);
1641
1642 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1643 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1644 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1645 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1646 if (has_msr_star) {
1647 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1648 }
1649 if (has_msr_hsave_pa) {
1650 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1651 }
1652 if (has_msr_tsc_aux) {
1653 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1654 }
1655 if (has_msr_tsc_adjust) {
1656 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1657 }
1658 if (has_msr_misc_enable) {
1659 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1660 env->msr_ia32_misc_enable);
1661 }
1662 if (has_msr_smbase) {
1663 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1664 }
1665 if (has_msr_bndcfgs) {
1666 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1667 }
1668 if (has_msr_xss) {
1669 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1670 }
1671 #ifdef TARGET_X86_64
1672 if (lm_capable_kernel) {
1673 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1674 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1675 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1676 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1677 }
1678 #endif
1679 /*
1680 * The following MSRs have side effects on the guest or are too heavy
1681 * for normal writeback. Limit them to reset or full state updates.
1682 */
1683 if (level >= KVM_PUT_RESET_STATE) {
1684 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1685 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1686 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1687 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
1688 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1689 }
1690 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
1691 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1692 }
1693 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
1694 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1695 }
1696 if (has_msr_architectural_pmu) {
1697 /* Stop the counter. */
1698 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1699 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1700
1701 /* Set the counter values. */
1702 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1703 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1704 env->msr_fixed_counters[i]);
1705 }
1706 for (i = 0; i < num_architectural_pmu_counters; i++) {
1707 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1708 env->msr_gp_counters[i]);
1709 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1710 env->msr_gp_evtsel[i]);
1711 }
1712 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1713 env->msr_global_status);
1714 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1715 env->msr_global_ovf_ctrl);
1716
1717 /* Now start the PMU. */
1718 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1719 env->msr_fixed_ctr_ctrl);
1720 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1721 env->msr_global_ctrl);
1722 }
1723 if (has_msr_hv_hypercall) {
1724 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1725 env->msr_hv_guest_os_id);
1726 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1727 env->msr_hv_hypercall);
1728 }
1729 if (cpu->hyperv_vapic) {
1730 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1731 env->msr_hv_vapic);
1732 }
1733 if (cpu->hyperv_time) {
1734 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
1735 }
1736 if (has_msr_hv_crash) {
1737 int j;
1738
1739 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1740 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1741 env->msr_hv_crash_params[j]);
1742
1743 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
1744 HV_X64_MSR_CRASH_CTL_NOTIFY);
1745 }
1746 if (has_msr_hv_runtime) {
1747 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1748 }
1749 if (cpu->hyperv_synic) {
1750 int j;
1751
1752 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1753 env->msr_hv_synic_control);
1754 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
1755 env->msr_hv_synic_version);
1756 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1757 env->msr_hv_synic_evt_page);
1758 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1759 env->msr_hv_synic_msg_page);
1760
1761 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1762 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1763 env->msr_hv_synic_sint[j]);
1764 }
1765 }
1766 if (has_msr_hv_stimer) {
1767 int j;
1768
1769 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1770 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1771 env->msr_hv_stimer_config[j]);
1772 }
1773
1774 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1775 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1776 env->msr_hv_stimer_count[j]);
1777 }
1778 }
1779 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
1780 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1781
1782 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1783 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1784 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1785 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1786 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1787 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1788 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1789 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1790 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1791 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1792 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1793 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1794 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1795 /* The CPU GPs if we write to a bit above the physical limit of
1796 * the host CPU (and KVM emulates that)
1797 */
1798 uint64_t mask = env->mtrr_var[i].mask;
1799 mask &= phys_mask;
1800
1801 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1802 env->mtrr_var[i].base);
1803 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
1804 }
1805 }
1806
1807 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1808 * kvm_put_msr_feature_control. */
1809 }
1810 if (env->mcg_cap) {
1811 int i;
1812
1813 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1814 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
1815 if (has_msr_mcg_ext_ctl) {
1816 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1817 }
1818 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1819 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
1820 }
1821 }
1822
1823 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1824 if (ret < 0) {
1825 return ret;
1826 }
1827
1828 if (ret < cpu->kvm_msr_buf->nmsrs) {
1829 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
1830 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
1831 (uint32_t)e->index, (uint64_t)e->data);
1832 }
1833
1834 assert(ret == cpu->kvm_msr_buf->nmsrs);
1835 return 0;
1836 }
1837
1838
1839 static int kvm_get_fpu(X86CPU *cpu)
1840 {
1841 CPUX86State *env = &cpu->env;
1842 struct kvm_fpu fpu;
1843 int i, ret;
1844
1845 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1846 if (ret < 0) {
1847 return ret;
1848 }
1849
1850 env->fpstt = (fpu.fsw >> 11) & 7;
1851 env->fpus = fpu.fsw;
1852 env->fpuc = fpu.fcw;
1853 env->fpop = fpu.last_opcode;
1854 env->fpip = fpu.last_ip;
1855 env->fpdp = fpu.last_dp;
1856 for (i = 0; i < 8; ++i) {
1857 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1858 }
1859 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1860 for (i = 0; i < CPU_NB_REGS; i++) {
1861 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1862 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1863 }
1864 env->mxcsr = fpu.mxcsr;
1865
1866 return 0;
1867 }
1868
1869 static int kvm_get_xsave(X86CPU *cpu)
1870 {
1871 CPUX86State *env = &cpu->env;
1872 X86XSaveArea *xsave = env->kvm_xsave_buf;
1873 int ret, i;
1874 uint16_t cwd, swd, twd;
1875
1876 if (!has_xsave) {
1877 return kvm_get_fpu(cpu);
1878 }
1879
1880 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1881 if (ret < 0) {
1882 return ret;
1883 }
1884
1885 cwd = xsave->legacy.fcw;
1886 swd = xsave->legacy.fsw;
1887 twd = xsave->legacy.ftw;
1888 env->fpop = xsave->legacy.fpop;
1889 env->fpstt = (swd >> 11) & 7;
1890 env->fpus = swd;
1891 env->fpuc = cwd;
1892 for (i = 0; i < 8; ++i) {
1893 env->fptags[i] = !((twd >> i) & 1);
1894 }
1895 env->fpip = xsave->legacy.fpip;
1896 env->fpdp = xsave->legacy.fpdp;
1897 env->mxcsr = xsave->legacy.mxcsr;
1898 memcpy(env->fpregs, &xsave->legacy.fpregs,
1899 sizeof env->fpregs);
1900 env->xstate_bv = xsave->header.xstate_bv;
1901 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
1902 sizeof env->bnd_regs);
1903 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1904 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
1905 sizeof env->opmask_regs);
1906
1907 for (i = 0; i < CPU_NB_REGS; i++) {
1908 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1909 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1910 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1911 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1912 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1913 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1914 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1915 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1916 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1917 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1918 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
1919 }
1920
1921 #ifdef TARGET_X86_64
1922 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
1923 16 * sizeof env->xmm_regs[16]);
1924 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
1925 #endif
1926 return 0;
1927 }
1928
1929 static int kvm_get_xcrs(X86CPU *cpu)
1930 {
1931 CPUX86State *env = &cpu->env;
1932 int i, ret;
1933 struct kvm_xcrs xcrs;
1934
1935 if (!has_xcrs) {
1936 return 0;
1937 }
1938
1939 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1940 if (ret < 0) {
1941 return ret;
1942 }
1943
1944 for (i = 0; i < xcrs.nr_xcrs; i++) {
1945 /* Only support xcr0 now */
1946 if (xcrs.xcrs[i].xcr == 0) {
1947 env->xcr0 = xcrs.xcrs[i].value;
1948 break;
1949 }
1950 }
1951 return 0;
1952 }
1953
1954 static int kvm_get_sregs(X86CPU *cpu)
1955 {
1956 CPUX86State *env = &cpu->env;
1957 struct kvm_sregs sregs;
1958 uint32_t hflags;
1959 int bit, i, ret;
1960
1961 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1962 if (ret < 0) {
1963 return ret;
1964 }
1965
1966 /* There can only be one pending IRQ set in the bitmap at a time, so try
1967 to find it and save its number instead (-1 for none). */
1968 env->interrupt_injected = -1;
1969 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1970 if (sregs.interrupt_bitmap[i]) {
1971 bit = ctz64(sregs.interrupt_bitmap[i]);
1972 env->interrupt_injected = i * 64 + bit;
1973 break;
1974 }
1975 }
1976
1977 get_seg(&env->segs[R_CS], &sregs.cs);
1978 get_seg(&env->segs[R_DS], &sregs.ds);
1979 get_seg(&env->segs[R_ES], &sregs.es);
1980 get_seg(&env->segs[R_FS], &sregs.fs);
1981 get_seg(&env->segs[R_GS], &sregs.gs);
1982 get_seg(&env->segs[R_SS], &sregs.ss);
1983
1984 get_seg(&env->tr, &sregs.tr);
1985 get_seg(&env->ldt, &sregs.ldt);
1986
1987 env->idt.limit = sregs.idt.limit;
1988 env->idt.base = sregs.idt.base;
1989 env->gdt.limit = sregs.gdt.limit;
1990 env->gdt.base = sregs.gdt.base;
1991
1992 env->cr[0] = sregs.cr0;
1993 env->cr[2] = sregs.cr2;
1994 env->cr[3] = sregs.cr3;
1995 env->cr[4] = sregs.cr4;
1996
1997 env->efer = sregs.efer;
1998
1999 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
2000
2001 #define HFLAG_COPY_MASK \
2002 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
2003 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
2004 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
2005 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
2006
2007 hflags = env->hflags & HFLAG_COPY_MASK;
2008 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
2009 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
2010 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
2011 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
2012 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
2013
2014 if (env->cr[4] & CR4_OSFXSR_MASK) {
2015 hflags |= HF_OSFXSR_MASK;
2016 }
2017
2018 if (env->efer & MSR_EFER_LMA) {
2019 hflags |= HF_LMA_MASK;
2020 }
2021
2022 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
2023 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
2024 } else {
2025 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
2026 (DESC_B_SHIFT - HF_CS32_SHIFT);
2027 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
2028 (DESC_B_SHIFT - HF_SS32_SHIFT);
2029 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
2030 !(hflags & HF_CS32_MASK)) {
2031 hflags |= HF_ADDSEG_MASK;
2032 } else {
2033 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
2034 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
2035 }
2036 }
2037 env->hflags = hflags;
2038
2039 return 0;
2040 }
2041
2042 static int kvm_get_msrs(X86CPU *cpu)
2043 {
2044 CPUX86State *env = &cpu->env;
2045 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
2046 int ret, i;
2047 uint64_t mtrr_top_bits;
2048
2049 kvm_msr_buf_reset(cpu);
2050
2051 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2052 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2053 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2054 kvm_msr_entry_add(cpu, MSR_PAT, 0);
2055 if (has_msr_star) {
2056 kvm_msr_entry_add(cpu, MSR_STAR, 0);
2057 }
2058 if (has_msr_hsave_pa) {
2059 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
2060 }
2061 if (has_msr_tsc_aux) {
2062 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
2063 }
2064 if (has_msr_tsc_adjust) {
2065 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2066 }
2067 if (has_msr_tsc_deadline) {
2068 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2069 }
2070 if (has_msr_misc_enable) {
2071 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2072 }
2073 if (has_msr_smbase) {
2074 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2075 }
2076 if (has_msr_feature_control) {
2077 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2078 }
2079 if (has_msr_bndcfgs) {
2080 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2081 }
2082 if (has_msr_xss) {
2083 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2084 }
2085
2086
2087 if (!env->tsc_valid) {
2088 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2089 env->tsc_valid = !runstate_is_running();
2090 }
2091
2092 #ifdef TARGET_X86_64
2093 if (lm_capable_kernel) {
2094 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2095 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2096 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2097 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2098 }
2099 #endif
2100 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2101 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2102 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2103 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2104 }
2105 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2106 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2107 }
2108 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2109 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2110 }
2111 if (has_msr_architectural_pmu) {
2112 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2113 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2114 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2115 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2116 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
2117 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2118 }
2119 for (i = 0; i < num_architectural_pmu_counters; i++) {
2120 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2121 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2122 }
2123 }
2124
2125 if (env->mcg_cap) {
2126 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2127 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2128 if (has_msr_mcg_ext_ctl) {
2129 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2130 }
2131 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2132 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2133 }
2134 }
2135
2136 if (has_msr_hv_hypercall) {
2137 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2138 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2139 }
2140 if (cpu->hyperv_vapic) {
2141 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2142 }
2143 if (cpu->hyperv_time) {
2144 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2145 }
2146 if (has_msr_hv_crash) {
2147 int j;
2148
2149 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
2150 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2151 }
2152 }
2153 if (has_msr_hv_runtime) {
2154 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2155 }
2156 if (cpu->hyperv_synic) {
2157 uint32_t msr;
2158
2159 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2160 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2161 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2162 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2163 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2164 kvm_msr_entry_add(cpu, msr, 0);
2165 }
2166 }
2167 if (has_msr_hv_stimer) {
2168 uint32_t msr;
2169
2170 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2171 msr++) {
2172 kvm_msr_entry_add(cpu, msr, 0);
2173 }
2174 }
2175 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2176 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2177 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2178 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2179 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2180 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2181 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2182 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2183 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2184 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2185 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2186 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2187 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2188 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2189 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2190 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2191 }
2192 }
2193
2194 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2195 if (ret < 0) {
2196 return ret;
2197 }
2198
2199 if (ret < cpu->kvm_msr_buf->nmsrs) {
2200 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2201 error_report("error: failed to get MSR 0x%" PRIx32,
2202 (uint32_t)e->index);
2203 }
2204
2205 assert(ret == cpu->kvm_msr_buf->nmsrs);
2206 /*
2207 * MTRR masks: Each mask consists of 5 parts
2208 * a 10..0: must be zero
2209 * b 11 : valid bit
2210 * c n-1.12: actual mask bits
2211 * d 51..n: reserved must be zero
2212 * e 63.52: reserved must be zero
2213 *
2214 * 'n' is the number of physical bits supported by the CPU and is
2215 * apparently always <= 52. We know our 'n' but don't know what
2216 * the destinations 'n' is; it might be smaller, in which case
2217 * it masks (c) on loading. It might be larger, in which case
2218 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2219 * we're migrating to.
2220 */
2221
2222 if (cpu->fill_mtrr_mask) {
2223 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2224 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2225 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2226 } else {
2227 mtrr_top_bits = 0;
2228 }
2229
2230 for (i = 0; i < ret; i++) {
2231 uint32_t index = msrs[i].index;
2232 switch (index) {
2233 case MSR_IA32_SYSENTER_CS:
2234 env->sysenter_cs = msrs[i].data;
2235 break;
2236 case MSR_IA32_SYSENTER_ESP:
2237 env->sysenter_esp = msrs[i].data;
2238 break;
2239 case MSR_IA32_SYSENTER_EIP:
2240 env->sysenter_eip = msrs[i].data;
2241 break;
2242 case MSR_PAT:
2243 env->pat = msrs[i].data;
2244 break;
2245 case MSR_STAR:
2246 env->star = msrs[i].data;
2247 break;
2248 #ifdef TARGET_X86_64
2249 case MSR_CSTAR:
2250 env->cstar = msrs[i].data;
2251 break;
2252 case MSR_KERNELGSBASE:
2253 env->kernelgsbase = msrs[i].data;
2254 break;
2255 case MSR_FMASK:
2256 env->fmask = msrs[i].data;
2257 break;
2258 case MSR_LSTAR:
2259 env->lstar = msrs[i].data;
2260 break;
2261 #endif
2262 case MSR_IA32_TSC:
2263 env->tsc = msrs[i].data;
2264 break;
2265 case MSR_TSC_AUX:
2266 env->tsc_aux = msrs[i].data;
2267 break;
2268 case MSR_TSC_ADJUST:
2269 env->tsc_adjust = msrs[i].data;
2270 break;
2271 case MSR_IA32_TSCDEADLINE:
2272 env->tsc_deadline = msrs[i].data;
2273 break;
2274 case MSR_VM_HSAVE_PA:
2275 env->vm_hsave = msrs[i].data;
2276 break;
2277 case MSR_KVM_SYSTEM_TIME:
2278 env->system_time_msr = msrs[i].data;
2279 break;
2280 case MSR_KVM_WALL_CLOCK:
2281 env->wall_clock_msr = msrs[i].data;
2282 break;
2283 case MSR_MCG_STATUS:
2284 env->mcg_status = msrs[i].data;
2285 break;
2286 case MSR_MCG_CTL:
2287 env->mcg_ctl = msrs[i].data;
2288 break;
2289 case MSR_MCG_EXT_CTL:
2290 env->mcg_ext_ctl = msrs[i].data;
2291 break;
2292 case MSR_IA32_MISC_ENABLE:
2293 env->msr_ia32_misc_enable = msrs[i].data;
2294 break;
2295 case MSR_IA32_SMBASE:
2296 env->smbase = msrs[i].data;
2297 break;
2298 case MSR_IA32_FEATURE_CONTROL:
2299 env->msr_ia32_feature_control = msrs[i].data;
2300 break;
2301 case MSR_IA32_BNDCFGS:
2302 env->msr_bndcfgs = msrs[i].data;
2303 break;
2304 case MSR_IA32_XSS:
2305 env->xss = msrs[i].data;
2306 break;
2307 default:
2308 if (msrs[i].index >= MSR_MC0_CTL &&
2309 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2310 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2311 }
2312 break;
2313 case MSR_KVM_ASYNC_PF_EN:
2314 env->async_pf_en_msr = msrs[i].data;
2315 break;
2316 case MSR_KVM_PV_EOI_EN:
2317 env->pv_eoi_en_msr = msrs[i].data;
2318 break;
2319 case MSR_KVM_STEAL_TIME:
2320 env->steal_time_msr = msrs[i].data;
2321 break;
2322 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2323 env->msr_fixed_ctr_ctrl = msrs[i].data;
2324 break;
2325 case MSR_CORE_PERF_GLOBAL_CTRL:
2326 env->msr_global_ctrl = msrs[i].data;
2327 break;
2328 case MSR_CORE_PERF_GLOBAL_STATUS:
2329 env->msr_global_status = msrs[i].data;
2330 break;
2331 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2332 env->msr_global_ovf_ctrl = msrs[i].data;
2333 break;
2334 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2335 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2336 break;
2337 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2338 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2339 break;
2340 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2341 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2342 break;
2343 case HV_X64_MSR_HYPERCALL:
2344 env->msr_hv_hypercall = msrs[i].data;
2345 break;
2346 case HV_X64_MSR_GUEST_OS_ID:
2347 env->msr_hv_guest_os_id = msrs[i].data;
2348 break;
2349 case HV_X64_MSR_APIC_ASSIST_PAGE:
2350 env->msr_hv_vapic = msrs[i].data;
2351 break;
2352 case HV_X64_MSR_REFERENCE_TSC:
2353 env->msr_hv_tsc = msrs[i].data;
2354 break;
2355 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2356 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2357 break;
2358 case HV_X64_MSR_VP_RUNTIME:
2359 env->msr_hv_runtime = msrs[i].data;
2360 break;
2361 case HV_X64_MSR_SCONTROL:
2362 env->msr_hv_synic_control = msrs[i].data;
2363 break;
2364 case HV_X64_MSR_SVERSION:
2365 env->msr_hv_synic_version = msrs[i].data;
2366 break;
2367 case HV_X64_MSR_SIEFP:
2368 env->msr_hv_synic_evt_page = msrs[i].data;
2369 break;
2370 case HV_X64_MSR_SIMP:
2371 env->msr_hv_synic_msg_page = msrs[i].data;
2372 break;
2373 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2374 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2375 break;
2376 case HV_X64_MSR_STIMER0_CONFIG:
2377 case HV_X64_MSR_STIMER1_CONFIG:
2378 case HV_X64_MSR_STIMER2_CONFIG:
2379 case HV_X64_MSR_STIMER3_CONFIG:
2380 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2381 msrs[i].data;
2382 break;
2383 case HV_X64_MSR_STIMER0_COUNT:
2384 case HV_X64_MSR_STIMER1_COUNT:
2385 case HV_X64_MSR_STIMER2_COUNT:
2386 case HV_X64_MSR_STIMER3_COUNT:
2387 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2388 msrs[i].data;
2389 break;
2390 case MSR_MTRRdefType:
2391 env->mtrr_deftype = msrs[i].data;
2392 break;
2393 case MSR_MTRRfix64K_00000:
2394 env->mtrr_fixed[0] = msrs[i].data;
2395 break;
2396 case MSR_MTRRfix16K_80000:
2397 env->mtrr_fixed[1] = msrs[i].data;
2398 break;
2399 case MSR_MTRRfix16K_A0000:
2400 env->mtrr_fixed[2] = msrs[i].data;
2401 break;
2402 case MSR_MTRRfix4K_C0000:
2403 env->mtrr_fixed[3] = msrs[i].data;
2404 break;
2405 case MSR_MTRRfix4K_C8000:
2406 env->mtrr_fixed[4] = msrs[i].data;
2407 break;
2408 case MSR_MTRRfix4K_D0000:
2409 env->mtrr_fixed[5] = msrs[i].data;
2410 break;
2411 case MSR_MTRRfix4K_D8000:
2412 env->mtrr_fixed[6] = msrs[i].data;
2413 break;
2414 case MSR_MTRRfix4K_E0000:
2415 env->mtrr_fixed[7] = msrs[i].data;
2416 break;
2417 case MSR_MTRRfix4K_E8000:
2418 env->mtrr_fixed[8] = msrs[i].data;
2419 break;
2420 case MSR_MTRRfix4K_F0000:
2421 env->mtrr_fixed[9] = msrs[i].data;
2422 break;
2423 case MSR_MTRRfix4K_F8000:
2424 env->mtrr_fixed[10] = msrs[i].data;
2425 break;
2426 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2427 if (index & 1) {
2428 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2429 mtrr_top_bits;
2430 } else {
2431 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2432 }
2433 break;
2434 }
2435 }
2436
2437 return 0;
2438 }
2439
2440 static int kvm_put_mp_state(X86CPU *cpu)
2441 {
2442 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2443
2444 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2445 }
2446
2447 static int kvm_get_mp_state(X86CPU *cpu)
2448 {
2449 CPUState *cs = CPU(cpu);
2450 CPUX86State *env = &cpu->env;
2451 struct kvm_mp_state mp_state;
2452 int ret;
2453
2454 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2455 if (ret < 0) {
2456 return ret;
2457 }
2458 env->mp_state = mp_state.mp_state;
2459 if (kvm_irqchip_in_kernel()) {
2460 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2461 }
2462 return 0;
2463 }
2464
2465 static int kvm_get_apic(X86CPU *cpu)
2466 {
2467 DeviceState *apic = cpu->apic_state;
2468 struct kvm_lapic_state kapic;
2469 int ret;
2470
2471 if (apic && kvm_irqchip_in_kernel()) {
2472 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2473 if (ret < 0) {
2474 return ret;
2475 }
2476
2477 kvm_get_apic_state(apic, &kapic);
2478 }
2479 return 0;
2480 }
2481
2482 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2483 {
2484 CPUState *cs = CPU(cpu);
2485 CPUX86State *env = &cpu->env;
2486 struct kvm_vcpu_events events = {};
2487
2488 if (!kvm_has_vcpu_events()) {
2489 return 0;
2490 }
2491
2492 events.exception.injected = (env->exception_injected >= 0);
2493 events.exception.nr = env->exception_injected;
2494 events.exception.has_error_code = env->has_error_code;
2495 events.exception.error_code = env->error_code;
2496 events.exception.pad = 0;
2497
2498 events.interrupt.injected = (env->interrupt_injected >= 0);
2499 events.interrupt.nr = env->interrupt_injected;
2500 events.interrupt.soft = env->soft_interrupt;
2501
2502 events.nmi.injected = env->nmi_injected;
2503 events.nmi.pending = env->nmi_pending;
2504 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2505 events.nmi.pad = 0;
2506
2507 events.sipi_vector = env->sipi_vector;
2508 events.flags = 0;
2509
2510 if (has_msr_smbase) {
2511 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2512 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2513 if (kvm_irqchip_in_kernel()) {
2514 /* As soon as these are moved to the kernel, remove them
2515 * from cs->interrupt_request.
2516 */
2517 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2518 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2519 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2520 } else {
2521 /* Keep these in cs->interrupt_request. */
2522 events.smi.pending = 0;
2523 events.smi.latched_init = 0;
2524 }
2525 /* Stop SMI delivery on old machine types to avoid a reboot
2526 * on an inward migration of an old VM.
2527 */
2528 if (!cpu->kvm_no_smi_migration) {
2529 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2530 }
2531 }
2532
2533 if (level >= KVM_PUT_RESET_STATE) {
2534 events.flags |=
2535 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2536 }
2537
2538 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2539 }
2540
2541 static int kvm_get_vcpu_events(X86CPU *cpu)
2542 {
2543 CPUX86State *env = &cpu->env;
2544 struct kvm_vcpu_events events;
2545 int ret;
2546
2547 if (!kvm_has_vcpu_events()) {
2548 return 0;
2549 }
2550
2551 memset(&events, 0, sizeof(events));
2552 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2553 if (ret < 0) {
2554 return ret;
2555 }
2556 env->exception_injected =
2557 events.exception.injected ? events.exception.nr : -1;
2558 env->has_error_code = events.exception.has_error_code;
2559 env->error_code = events.exception.error_code;
2560
2561 env->interrupt_injected =
2562 events.interrupt.injected ? events.interrupt.nr : -1;
2563 env->soft_interrupt = events.interrupt.soft;
2564
2565 env->nmi_injected = events.nmi.injected;
2566 env->nmi_pending = events.nmi.pending;
2567 if (events.nmi.masked) {
2568 env->hflags2 |= HF2_NMI_MASK;
2569 } else {
2570 env->hflags2 &= ~HF2_NMI_MASK;
2571 }
2572
2573 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2574 if (events.smi.smm) {
2575 env->hflags |= HF_SMM_MASK;
2576 } else {
2577 env->hflags &= ~HF_SMM_MASK;
2578 }
2579 if (events.smi.pending) {
2580 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2581 } else {
2582 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2583 }
2584 if (events.smi.smm_inside_nmi) {
2585 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2586 } else {
2587 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2588 }
2589 if (events.smi.latched_init) {
2590 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2591 } else {
2592 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2593 }
2594 }
2595
2596 env->sipi_vector = events.sipi_vector;
2597
2598 return 0;
2599 }
2600
2601 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2602 {
2603 CPUState *cs = CPU(cpu);
2604 CPUX86State *env = &cpu->env;
2605 int ret = 0;
2606 unsigned long reinject_trap = 0;
2607
2608 if (!kvm_has_vcpu_events()) {
2609 if (env->exception_injected == 1) {
2610 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2611 } else if (env->exception_injected == 3) {
2612 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2613 }
2614 env->exception_injected = -1;
2615 }
2616
2617 /*
2618 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2619 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2620 * by updating the debug state once again if single-stepping is on.
2621 * Another reason to call kvm_update_guest_debug here is a pending debug
2622 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2623 * reinject them via SET_GUEST_DEBUG.
2624 */
2625 if (reinject_trap ||
2626 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2627 ret = kvm_update_guest_debug(cs, reinject_trap);
2628 }
2629 return ret;
2630 }
2631
2632 static int kvm_put_debugregs(X86CPU *cpu)
2633 {
2634 CPUX86State *env = &cpu->env;
2635 struct kvm_debugregs dbgregs;
2636 int i;
2637
2638 if (!kvm_has_debugregs()) {
2639 return 0;
2640 }
2641
2642 for (i = 0; i < 4; i++) {
2643 dbgregs.db[i] = env->dr[i];
2644 }
2645 dbgregs.dr6 = env->dr[6];
2646 dbgregs.dr7 = env->dr[7];
2647 dbgregs.flags = 0;
2648
2649 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2650 }
2651
2652 static int kvm_get_debugregs(X86CPU *cpu)
2653 {
2654 CPUX86State *env = &cpu->env;
2655 struct kvm_debugregs dbgregs;
2656 int i, ret;
2657
2658 if (!kvm_has_debugregs()) {
2659 return 0;
2660 }
2661
2662 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2663 if (ret < 0) {
2664 return ret;
2665 }
2666 for (i = 0; i < 4; i++) {
2667 env->dr[i] = dbgregs.db[i];
2668 }
2669 env->dr[4] = env->dr[6] = dbgregs.dr6;
2670 env->dr[5] = env->dr[7] = dbgregs.dr7;
2671
2672 return 0;
2673 }
2674
2675 int kvm_arch_put_registers(CPUState *cpu, int level)
2676 {
2677 X86CPU *x86_cpu = X86_CPU(cpu);
2678 int ret;
2679
2680 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2681
2682 if (level >= KVM_PUT_RESET_STATE) {
2683 ret = kvm_put_msr_feature_control(x86_cpu);
2684 if (ret < 0) {
2685 return ret;
2686 }
2687 }
2688
2689 if (level == KVM_PUT_FULL_STATE) {
2690 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2691 * because TSC frequency mismatch shouldn't abort migration,
2692 * unless the user explicitly asked for a more strict TSC
2693 * setting (e.g. using an explicit "tsc-freq" option).
2694 */
2695 kvm_arch_set_tsc_khz(cpu);
2696 }
2697
2698 ret = kvm_getput_regs(x86_cpu, 1);
2699 if (ret < 0) {
2700 return ret;
2701 }
2702 ret = kvm_put_xsave(x86_cpu);
2703 if (ret < 0) {
2704 return ret;
2705 }
2706 ret = kvm_put_xcrs(x86_cpu);
2707 if (ret < 0) {
2708 return ret;
2709 }
2710 ret = kvm_put_sregs(x86_cpu);
2711 if (ret < 0) {
2712 return ret;
2713 }
2714 /* must be before kvm_put_msrs */
2715 ret = kvm_inject_mce_oldstyle(x86_cpu);
2716 if (ret < 0) {
2717 return ret;
2718 }
2719 ret = kvm_put_msrs(x86_cpu, level);
2720 if (ret < 0) {
2721 return ret;
2722 }
2723 if (level >= KVM_PUT_RESET_STATE) {
2724 ret = kvm_put_mp_state(x86_cpu);
2725 if (ret < 0) {
2726 return ret;
2727 }
2728 }
2729
2730 ret = kvm_put_tscdeadline_msr(x86_cpu);
2731 if (ret < 0) {
2732 return ret;
2733 }
2734
2735 ret = kvm_put_vcpu_events(x86_cpu, level);
2736 if (ret < 0) {
2737 return ret;
2738 }
2739 ret = kvm_put_debugregs(x86_cpu);
2740 if (ret < 0) {
2741 return ret;
2742 }
2743 /* must be last */
2744 ret = kvm_guest_debug_workarounds(x86_cpu);
2745 if (ret < 0) {
2746 return ret;
2747 }
2748 return 0;
2749 }
2750
2751 int kvm_arch_get_registers(CPUState *cs)
2752 {
2753 X86CPU *cpu = X86_CPU(cs);
2754 int ret;
2755
2756 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2757
2758 ret = kvm_getput_regs(cpu, 0);
2759 if (ret < 0) {
2760 goto out;
2761 }
2762 ret = kvm_get_xsave(cpu);
2763 if (ret < 0) {
2764 goto out;
2765 }
2766 ret = kvm_get_xcrs(cpu);
2767 if (ret < 0) {
2768 goto out;
2769 }
2770 ret = kvm_get_sregs(cpu);
2771 if (ret < 0) {
2772 goto out;
2773 }
2774 ret = kvm_get_msrs(cpu);
2775 if (ret < 0) {
2776 goto out;
2777 }
2778 ret = kvm_get_mp_state(cpu);
2779 if (ret < 0) {
2780 goto out;
2781 }
2782 ret = kvm_get_apic(cpu);
2783 if (ret < 0) {
2784 goto out;
2785 }
2786 ret = kvm_get_vcpu_events(cpu);
2787 if (ret < 0) {
2788 goto out;
2789 }
2790 ret = kvm_get_debugregs(cpu);
2791 if (ret < 0) {
2792 goto out;
2793 }
2794 ret = 0;
2795 out:
2796 cpu_sync_bndcs_hflags(&cpu->env);
2797 return ret;
2798 }
2799
2800 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2801 {
2802 X86CPU *x86_cpu = X86_CPU(cpu);
2803 CPUX86State *env = &x86_cpu->env;
2804 int ret;
2805
2806 /* Inject NMI */
2807 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2808 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2809 qemu_mutex_lock_iothread();
2810 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2811 qemu_mutex_unlock_iothread();
2812 DPRINTF("injected NMI\n");
2813 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2814 if (ret < 0) {
2815 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2816 strerror(-ret));
2817 }
2818 }
2819 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2820 qemu_mutex_lock_iothread();
2821 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2822 qemu_mutex_unlock_iothread();
2823 DPRINTF("injected SMI\n");
2824 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2825 if (ret < 0) {
2826 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2827 strerror(-ret));
2828 }
2829 }
2830 }
2831
2832 if (!kvm_pic_in_kernel()) {
2833 qemu_mutex_lock_iothread();
2834 }
2835
2836 /* Force the VCPU out of its inner loop to process any INIT requests
2837 * or (for userspace APIC, but it is cheap to combine the checks here)
2838 * pending TPR access reports.
2839 */
2840 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2841 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2842 !(env->hflags & HF_SMM_MASK)) {
2843 cpu->exit_request = 1;
2844 }
2845 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2846 cpu->exit_request = 1;
2847 }
2848 }
2849
2850 if (!kvm_pic_in_kernel()) {
2851 /* Try to inject an interrupt if the guest can accept it */
2852 if (run->ready_for_interrupt_injection &&
2853 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2854 (env->eflags & IF_MASK)) {
2855 int irq;
2856
2857 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2858 irq = cpu_get_pic_interrupt(env);
2859 if (irq >= 0) {
2860 struct kvm_interrupt intr;
2861
2862 intr.irq = irq;
2863 DPRINTF("injected interrupt %d\n", irq);
2864 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2865 if (ret < 0) {
2866 fprintf(stderr,
2867 "KVM: injection failed, interrupt lost (%s)\n",
2868 strerror(-ret));
2869 }
2870 }
2871 }
2872
2873 /* If we have an interrupt but the guest is not ready to receive an
2874 * interrupt, request an interrupt window exit. This will
2875 * cause a return to userspace as soon as the guest is ready to
2876 * receive interrupts. */
2877 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2878 run->request_interrupt_window = 1;
2879 } else {
2880 run->request_interrupt_window = 0;
2881 }
2882
2883 DPRINTF("setting tpr\n");
2884 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2885
2886 qemu_mutex_unlock_iothread();
2887 }
2888 }
2889
2890 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2891 {
2892 X86CPU *x86_cpu = X86_CPU(cpu);
2893 CPUX86State *env = &x86_cpu->env;
2894
2895 if (run->flags & KVM_RUN_X86_SMM) {
2896 env->hflags |= HF_SMM_MASK;
2897 } else {
2898 env->hflags &= ~HF_SMM_MASK;
2899 }
2900 if (run->if_flag) {
2901 env->eflags |= IF_MASK;
2902 } else {
2903 env->eflags &= ~IF_MASK;
2904 }
2905
2906 /* We need to protect the apic state against concurrent accesses from
2907 * different threads in case the userspace irqchip is used. */
2908 if (!kvm_irqchip_in_kernel()) {
2909 qemu_mutex_lock_iothread();
2910 }
2911 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2912 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2913 if (!kvm_irqchip_in_kernel()) {
2914 qemu_mutex_unlock_iothread();
2915 }
2916 return cpu_get_mem_attrs(env);
2917 }
2918
2919 int kvm_arch_process_async_events(CPUState *cs)
2920 {
2921 X86CPU *cpu = X86_CPU(cs);
2922 CPUX86State *env = &cpu->env;
2923
2924 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2925 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2926 assert(env->mcg_cap);
2927
2928 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2929
2930 kvm_cpu_synchronize_state(cs);
2931
2932 if (env->exception_injected == EXCP08_DBLE) {
2933 /* this means triple fault */
2934 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
2935 cs->exit_request = 1;
2936 return 0;
2937 }
2938 env->exception_injected = EXCP12_MCHK;
2939 env->has_error_code = 0;
2940
2941 cs->halted = 0;
2942 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2943 env->mp_state = KVM_MP_STATE_RUNNABLE;
2944 }
2945 }
2946
2947 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2948 !(env->hflags & HF_SMM_MASK)) {
2949 kvm_cpu_synchronize_state(cs);
2950 do_cpu_init(cpu);
2951 }
2952
2953 if (kvm_irqchip_in_kernel()) {
2954 return 0;
2955 }
2956
2957 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2958 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2959 apic_poll_irq(cpu->apic_state);
2960 }
2961 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2962 (env->eflags & IF_MASK)) ||
2963 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2964 cs->halted = 0;
2965 }
2966 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2967 kvm_cpu_synchronize_state(cs);
2968 do_cpu_sipi(cpu);
2969 }
2970 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2971 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2972 kvm_cpu_synchronize_state(cs);
2973 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2974 env->tpr_access_type);
2975 }
2976
2977 return cs->halted;
2978 }
2979
2980 static int kvm_handle_halt(X86CPU *cpu)
2981 {
2982 CPUState *cs = CPU(cpu);
2983 CPUX86State *env = &cpu->env;
2984
2985 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2986 (env->eflags & IF_MASK)) &&
2987 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2988 cs->halted = 1;
2989 return EXCP_HLT;
2990 }
2991
2992 return 0;
2993 }
2994
2995 static int kvm_handle_tpr_access(X86CPU *cpu)
2996 {
2997 CPUState *cs = CPU(cpu);
2998 struct kvm_run *run = cs->kvm_run;
2999
3000 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
3001 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3002 : TPR_ACCESS_READ);
3003 return 1;
3004 }
3005
3006 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3007 {
3008 static const uint8_t int3 = 0xcc;
3009
3010 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3011 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
3012 return -EINVAL;
3013 }
3014 return 0;
3015 }
3016
3017 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3018 {
3019 uint8_t int3;
3020
3021 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3022 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
3023 return -EINVAL;
3024 }
3025 return 0;
3026 }
3027
3028 static struct {
3029 target_ulong addr;
3030 int len;
3031 int type;
3032 } hw_breakpoint[4];
3033
3034 static int nb_hw_breakpoint;
3035
3036 static int find_hw_breakpoint(target_ulong addr, int len, int type)
3037 {
3038 int n;
3039
3040 for (n = 0; n < nb_hw_breakpoint; n++) {
3041 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
3042 (hw_breakpoint[n].len == len || len == -1)) {
3043 return n;
3044 }
3045 }
3046 return -1;
3047 }
3048
3049 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3050 target_ulong len, int type)
3051 {
3052 switch (type) {
3053 case GDB_BREAKPOINT_HW:
3054 len = 1;
3055 break;
3056 case GDB_WATCHPOINT_WRITE:
3057 case GDB_WATCHPOINT_ACCESS:
3058 switch (len) {
3059 case 1:
3060 break;
3061 case 2:
3062 case 4:
3063 case 8:
3064 if (addr & (len - 1)) {
3065 return -EINVAL;
3066 }
3067 break;
3068 default:
3069 return -EINVAL;
3070 }
3071 break;
3072 default:
3073 return -ENOSYS;
3074 }
3075
3076 if (nb_hw_breakpoint == 4) {
3077 return -ENOBUFS;
3078 }
3079 if (find_hw_breakpoint(addr, len, type) >= 0) {
3080 return -EEXIST;
3081 }
3082 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3083 hw_breakpoint[nb_hw_breakpoint].len = len;
3084 hw_breakpoint[nb_hw_breakpoint].type = type;
3085 nb_hw_breakpoint++;
3086
3087 return 0;
3088 }
3089
3090 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3091 target_ulong len, int type)
3092 {
3093 int n;
3094
3095 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3096 if (n < 0) {
3097 return -ENOENT;
3098 }
3099 nb_hw_breakpoint--;
3100 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3101
3102 return 0;
3103 }
3104
3105 void kvm_arch_remove_all_hw_breakpoints(void)
3106 {
3107 nb_hw_breakpoint = 0;
3108 }
3109
3110 static CPUWatchpoint hw_watchpoint;
3111
3112 static int kvm_handle_debug(X86CPU *cpu,
3113 struct kvm_debug_exit_arch *arch_info)
3114 {
3115 CPUState *cs = CPU(cpu);
3116 CPUX86State *env = &cpu->env;
3117 int ret = 0;
3118 int n;
3119
3120 if (arch_info->exception == 1) {
3121 if (arch_info->dr6 & (1 << 14)) {
3122 if (cs->singlestep_enabled) {
3123 ret = EXCP_DEBUG;
3124 }
3125 } else {
3126 for (n = 0; n < 4; n++) {
3127 if (arch_info->dr6 & (1 << n)) {
3128 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3129 case 0x0:
3130 ret = EXCP_DEBUG;
3131 break;
3132 case 0x1:
3133 ret = EXCP_DEBUG;
3134 cs->watchpoint_hit = &hw_watchpoint;
3135 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3136 hw_watchpoint.flags = BP_MEM_WRITE;
3137 break;
3138 case 0x3:
3139 ret = EXCP_DEBUG;
3140 cs->watchpoint_hit = &hw_watchpoint;
3141 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3142 hw_watchpoint.flags = BP_MEM_ACCESS;
3143 break;
3144 }
3145 }
3146 }
3147 }
3148 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3149 ret = EXCP_DEBUG;
3150 }
3151 if (ret == 0) {
3152 cpu_synchronize_state(cs);
3153 assert(env->exception_injected == -1);
3154
3155 /* pass to guest */
3156 env->exception_injected = arch_info->exception;
3157 env->has_error_code = 0;
3158 }
3159
3160 return ret;
3161 }
3162
3163 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3164 {
3165 const uint8_t type_code[] = {
3166 [GDB_BREAKPOINT_HW] = 0x0,
3167 [GDB_WATCHPOINT_WRITE] = 0x1,
3168 [GDB_WATCHPOINT_ACCESS] = 0x3
3169 };
3170 const uint8_t len_code[] = {
3171 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3172 };
3173 int n;
3174
3175 if (kvm_sw_breakpoints_active(cpu)) {
3176 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3177 }
3178 if (nb_hw_breakpoint > 0) {
3179 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3180 dbg->arch.debugreg[7] = 0x0600;
3181 for (n = 0; n < nb_hw_breakpoint; n++) {
3182 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3183 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3184 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3185 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3186 }
3187 }
3188 }
3189
3190 static bool host_supports_vmx(void)
3191 {
3192 uint32_t ecx, unused;
3193
3194 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3195 return ecx & CPUID_EXT_VMX;
3196 }
3197
3198 #define VMX_INVALID_GUEST_STATE 0x80000021
3199
3200 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3201 {
3202 X86CPU *cpu = X86_CPU(cs);
3203 uint64_t code;
3204 int ret;
3205
3206 switch (run->exit_reason) {
3207 case KVM_EXIT_HLT:
3208 DPRINTF("handle_hlt\n");
3209 qemu_mutex_lock_iothread();
3210 ret = kvm_handle_halt(cpu);
3211 qemu_mutex_unlock_iothread();
3212 break;
3213 case KVM_EXIT_SET_TPR:
3214 ret = 0;
3215 break;
3216 case KVM_EXIT_TPR_ACCESS:
3217 qemu_mutex_lock_iothread();
3218 ret = kvm_handle_tpr_access(cpu);
3219 qemu_mutex_unlock_iothread();
3220 break;
3221 case KVM_EXIT_FAIL_ENTRY:
3222 code = run->fail_entry.hardware_entry_failure_reason;
3223 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3224 code);
3225 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3226 fprintf(stderr,
3227 "\nIf you're running a guest on an Intel machine without "
3228 "unrestricted mode\n"
3229 "support, the failure can be most likely due to the guest "
3230 "entering an invalid\n"
3231 "state for Intel VT. For example, the guest maybe running "
3232 "in big real mode\n"
3233 "which is not supported on less recent Intel processors."
3234 "\n\n");
3235 }
3236 ret = -1;
3237 break;
3238 case KVM_EXIT_EXCEPTION:
3239 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3240 run->ex.exception, run->ex.error_code);
3241 ret = -1;
3242 break;
3243 case KVM_EXIT_DEBUG:
3244 DPRINTF("kvm_exit_debug\n");
3245 qemu_mutex_lock_iothread();
3246 ret = kvm_handle_debug(cpu, &run->debug.arch);
3247 qemu_mutex_unlock_iothread();
3248 break;
3249 case KVM_EXIT_HYPERV:
3250 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3251 break;
3252 case KVM_EXIT_IOAPIC_EOI:
3253 ioapic_eoi_broadcast(run->eoi.vector);
3254 ret = 0;
3255 break;
3256 default:
3257 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3258 ret = -1;
3259 break;
3260 }
3261
3262 return ret;
3263 }
3264
3265 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3266 {
3267 X86CPU *cpu = X86_CPU(cs);
3268 CPUX86State *env = &cpu->env;
3269
3270 kvm_cpu_synchronize_state(cs);
3271 return !(env->cr[0] & CR0_PE_MASK) ||
3272 ((env->segs[R_CS].selector & 3) != 3);
3273 }
3274
3275 void kvm_arch_init_irq_routing(KVMState *s)
3276 {
3277 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3278 /* If kernel can't do irq routing, interrupt source
3279 * override 0->2 cannot be set up as required by HPET.
3280 * So we have to disable it.
3281 */
3282 no_hpet = 1;
3283 }
3284 /* We know at this point that we're using the in-kernel
3285 * irqchip, so we can use irqfds, and on x86 we know
3286 * we can use msi via irqfd and GSI routing.
3287 */
3288 kvm_msi_via_irqfd_allowed = true;
3289 kvm_gsi_routing_allowed = true;
3290
3291 if (kvm_irqchip_is_split()) {
3292 int i;
3293
3294 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3295 MSI routes for signaling interrupts to the local apics. */
3296 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3297 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3298 error_report("Could not enable split IRQ mode.");
3299 exit(1);
3300 }
3301 }
3302 }
3303 }
3304
3305 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3306 {
3307 int ret;
3308 if (machine_kernel_irqchip_split(ms)) {
3309 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3310 if (ret) {
3311 error_report("Could not enable split irqchip mode: %s",
3312 strerror(-ret));
3313 exit(1);
3314 } else {
3315 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3316 kvm_split_irqchip = true;
3317 return 1;
3318 }
3319 } else {
3320 return 0;
3321 }
3322 }
3323
3324 /* Classic KVM device assignment interface. Will remain x86 only. */
3325 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3326 uint32_t flags, uint32_t *dev_id)
3327 {
3328 struct kvm_assigned_pci_dev dev_data = {
3329 .segnr = dev_addr->domain,
3330 .busnr = dev_addr->bus,
3331 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3332 .flags = flags,
3333 };
3334 int ret;
3335
3336 dev_data.assigned_dev_id =
3337 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3338
3339 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3340 if (ret < 0) {
3341 return ret;
3342 }
3343
3344 *dev_id = dev_data.assigned_dev_id;
3345
3346 return 0;
3347 }
3348
3349 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3350 {
3351 struct kvm_assigned_pci_dev dev_data = {
3352 .assigned_dev_id = dev_id,
3353 };
3354
3355 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3356 }
3357
3358 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3359 uint32_t irq_type, uint32_t guest_irq)
3360 {
3361 struct kvm_assigned_irq assigned_irq = {
3362 .assigned_dev_id = dev_id,
3363 .guest_irq = guest_irq,
3364 .flags = irq_type,
3365 };
3366
3367 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3368 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3369 } else {
3370 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3371 }
3372 }
3373
3374 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3375 uint32_t guest_irq)
3376 {
3377 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3378 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3379
3380 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3381 }
3382
3383 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3384 {
3385 struct kvm_assigned_pci_dev dev_data = {
3386 .assigned_dev_id = dev_id,
3387 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3388 };
3389
3390 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3391 }
3392
3393 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3394 uint32_t type)
3395 {
3396 struct kvm_assigned_irq assigned_irq = {
3397 .assigned_dev_id = dev_id,
3398 .flags = type,
3399 };
3400
3401 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3402 }
3403
3404 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3405 {
3406 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3407 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3408 }
3409
3410 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3411 {
3412 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3413 KVM_DEV_IRQ_GUEST_MSI, virq);
3414 }
3415
3416 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3417 {
3418 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3419 KVM_DEV_IRQ_HOST_MSI);
3420 }
3421
3422 bool kvm_device_msix_supported(KVMState *s)
3423 {
3424 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3425 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3426 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3427 }
3428
3429 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3430 uint32_t nr_vectors)
3431 {
3432 struct kvm_assigned_msix_nr msix_nr = {
3433 .assigned_dev_id = dev_id,
3434 .entry_nr = nr_vectors,
3435 };
3436
3437 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3438 }
3439
3440 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3441 int virq)
3442 {
3443 struct kvm_assigned_msix_entry msix_entry = {
3444 .assigned_dev_id = dev_id,
3445 .gsi = virq,
3446 .entry = vector,
3447 };
3448
3449 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3450 }
3451
3452 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3453 {
3454 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3455 KVM_DEV_IRQ_GUEST_MSIX, 0);
3456 }
3457
3458 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3459 {
3460 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3461 KVM_DEV_IRQ_HOST_MSIX);
3462 }
3463
3464 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3465 uint64_t address, uint32_t data, PCIDevice *dev)
3466 {
3467 X86IOMMUState *iommu = x86_iommu_get_default();
3468
3469 if (iommu) {
3470 int ret;
3471 MSIMessage src, dst;
3472 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3473
3474 src.address = route->u.msi.address_hi;
3475 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3476 src.address |= route->u.msi.address_lo;
3477 src.data = route->u.msi.data;
3478
3479 ret = class->int_remap(iommu, &src, &dst, dev ? \
3480 pci_requester_id(dev) : \
3481 X86_IOMMU_SID_INVALID);
3482 if (ret) {
3483 trace_kvm_x86_fixup_msi_error(route->gsi);
3484 return 1;
3485 }
3486
3487 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3488 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3489 route->u.msi.data = dst.data;
3490 }
3491
3492 return 0;
3493 }
3494
3495 typedef struct MSIRouteEntry MSIRouteEntry;
3496
3497 struct MSIRouteEntry {
3498 PCIDevice *dev; /* Device pointer */
3499 int vector; /* MSI/MSIX vector index */
3500 int virq; /* Virtual IRQ index */
3501 QLIST_ENTRY(MSIRouteEntry) list;
3502 };
3503
3504 /* List of used GSI routes */
3505 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3506 QLIST_HEAD_INITIALIZER(msi_route_list);
3507
3508 static void kvm_update_msi_routes_all(void *private, bool global,
3509 uint32_t index, uint32_t mask)
3510 {
3511 int cnt = 0;
3512 MSIRouteEntry *entry;
3513 MSIMessage msg;
3514 PCIDevice *dev;
3515
3516 /* TODO: explicit route update */
3517 QLIST_FOREACH(entry, &msi_route_list, list) {
3518 cnt++;
3519 dev = entry->dev;
3520 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3521 continue;
3522 }
3523 msg = pci_get_msi_message(dev, entry->vector);
3524 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
3525 }
3526 kvm_irqchip_commit_routes(kvm_state);
3527 trace_kvm_x86_update_msi_routes(cnt);
3528 }
3529
3530 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3531 int vector, PCIDevice *dev)
3532 {
3533 static bool notify_list_inited = false;
3534 MSIRouteEntry *entry;
3535
3536 if (!dev) {
3537 /* These are (possibly) IOAPIC routes only used for split
3538 * kernel irqchip mode, while what we are housekeeping are
3539 * PCI devices only. */
3540 return 0;
3541 }
3542
3543 entry = g_new0(MSIRouteEntry, 1);
3544 entry->dev = dev;
3545 entry->vector = vector;
3546 entry->virq = route->gsi;
3547 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3548
3549 trace_kvm_x86_add_msi_route(route->gsi);
3550
3551 if (!notify_list_inited) {
3552 /* For the first time we do add route, add ourselves into
3553 * IOMMU's IEC notify list if needed. */
3554 X86IOMMUState *iommu = x86_iommu_get_default();
3555 if (iommu) {
3556 x86_iommu_iec_register_notifier(iommu,
3557 kvm_update_msi_routes_all,
3558 NULL);
3559 }
3560 notify_list_inited = true;
3561 }
3562 return 0;
3563 }
3564
3565 int kvm_arch_release_virq_post(int virq)
3566 {
3567 MSIRouteEntry *entry, *next;
3568 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3569 if (entry->virq == virq) {
3570 trace_kvm_x86_remove_msi_route(virq);
3571 QLIST_REMOVE(entry, list);
3572 break;
3573 }
3574 }
3575 return 0;
3576 }
3577
3578 int kvm_arch_msi_data_to_gsi(uint32_t data)
3579 {
3580 abort();
3581 }
AR7 emulation for QEMU