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Merge remote-tracking branch 'qemu/master'
[qemu/ar7.git] / linux-user / main.c
blob5dfa39af1e0a465fa65422c503007cbe62885685
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu-version.h"
21 #include <sys/syscall.h>
22 #include <sys/resource.h>
23
24 #include "qapi/error.h"
25 #include "qemu.h"
26 #include "qemu/path.h"
27 #include "qemu/config-file.h"
28 #include "qemu/cutils.h"
29 #include "qemu/help_option.h"
30 #include "cpu.h"
31 #include "exec/exec-all.h"
32 #if defined(CONFIG_USER_ONLY) && defined(TARGET_X86_64)
33 #include "vsyscall.h"
34 #endif
35 #include "tcg.h"
36 #include "qemu/timer.h"
37 #include "qemu/envlist.h"
38 #include "elf.h"
39 #include "exec/log.h"
40 #include "trace/control.h"
41 #include "glib-compat.h"
42
43 char *exec_path;
44
45 int singlestep;
46 static const char *filename;
47 static const char *argv0;
48 static int gdbstub_port;
49 static envlist_t *envlist;
50 static const char *cpu_model;
51 unsigned long mmap_min_addr;
52 uintptr_t guest_base;
53 int have_guest_base;
54
55 #define EXCP_DUMP(env, fmt, ...) \
56 do { \
57 CPUState *cs = ENV_GET_CPU(env); \
58 fprintf(stderr, fmt , ## __VA_ARGS__); \
59 cpu_dump_state(cs, stderr, fprintf, 0); \
60 if (qemu_log_separate()) { \
61 qemu_log(fmt, ## __VA_ARGS__); \
62 log_cpu_state(cs, 0); \
63 } \
64 } while (0)
65
66 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
67 /*
68 * When running 32-on-64 we should make sure we can fit all of the possible
69 * guest address space into a contiguous chunk of virtual host memory.
70 *
71 * This way we will never overlap with our own libraries or binaries or stack
72 * or anything else that QEMU maps.
73 */
74 # if defined(TARGET_MIPS) || defined(TARGET_NIOS2)
75 /*
76 * MIPS only supports 31 bits of virtual address space for user space.
77 * Nios2 also only supports 31 bits.
78 */
79 uintptr_t reserved_va = 0x77000000;
80 # else
81 uintptr_t reserved_va = 0xf7000000;
82 # endif
83 #else
84 uintptr_t reserved_va;
85 #endif
86
87 static void usage(int exitcode);
88
89 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
90 const char *qemu_uname_release;
91
92 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
93 we allocate a bigger stack. Need a better solution, for example
94 by remapping the process stack directly at the right place */
95 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
96
97 void gemu_log(const char *fmt, ...)
98 {
99 va_list ap;
100
101 va_start(ap, fmt);
102 vfprintf(stderr, fmt, ap);
103 va_end(ap);
104 }
105
106 #if defined(TARGET_I386)
107 int cpu_get_pic_interrupt(CPUX86State *env)
108 {
109 return -1;
110 }
111 #endif
112
113 /***********************************************************/
114 /* Helper routines for implementing atomic operations. */
115
116 /* Make sure everything is in a consistent state for calling fork(). */
117 void fork_start(void)
118 {
119 cpu_list_lock();
120 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
121 mmap_fork_start();
122 }
123
124 void fork_end(int child)
125 {
126 mmap_fork_end(child);
127 if (child) {
128 CPUState *cpu, *next_cpu;
129 /* Child processes created by fork() only have a single thread.
130 Discard information about the parent threads. */
131 CPU_FOREACH_SAFE(cpu, next_cpu) {
132 if (cpu != thread_cpu) {
133 QTAILQ_REMOVE(&cpus, cpu, node);
134 }
135 }
136 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
137 qemu_init_cpu_list();
138 gdbserver_fork(thread_cpu);
139 } else {
140 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
141 cpu_list_unlock();
142 }
143 }
144
145 #ifdef TARGET_I386
146 /***********************************************************/
147 /* CPUX86 core interface */
148
149 uint64_t cpu_get_tsc(CPUX86State *env)
150 {
151 return cpu_get_host_ticks();
152 }
153
154 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
155 int flags)
156 {
157 unsigned int e1, e2;
158 uint32_t *p;
159 e1 = (addr << 16) | (limit & 0xffff);
160 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
161 e2 |= flags;
162 p = ptr;
163 p[0] = tswap32(e1);
164 p[1] = tswap32(e2);
165 }
166
167 static uint64_t *idt_table;
168 #ifdef TARGET_X86_64
169 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
170 uint64_t addr, unsigned int sel)
171 {
172 uint32_t *p, e1, e2;
173 e1 = (addr & 0xffff) | (sel << 16);
174 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
175 p = ptr;
176 p[0] = tswap32(e1);
177 p[1] = tswap32(e2);
178 p[2] = tswap32(addr >> 32);
179 p[3] = 0;
180 }
181 /* only dpl matters as we do only user space emulation */
182 static void set_idt(int n, unsigned int dpl)
183 {
184 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
185 }
186 #else
187 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
188 uint32_t addr, unsigned int sel)
189 {
190 uint32_t *p, e1, e2;
191 e1 = (addr & 0xffff) | (sel << 16);
192 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
193 p = ptr;
194 p[0] = tswap32(e1);
195 p[1] = tswap32(e2);
196 }
197
198 /* only dpl matters as we do only user space emulation */
199 static void set_idt(int n, unsigned int dpl)
200 {
201 set_gate(idt_table + n, 0, dpl, 0, 0);
202 }
203 #endif
204
205 void cpu_loop(CPUX86State *env)
206 {
207 CPUState *cs = CPU(x86_env_get_cpu(env));
208 int trapnr;
209 abi_ulong pc;
210 abi_ulong ret;
211 target_siginfo_t info;
212 #ifdef TARGET_X86_64
213 int syscall_num;
214 uint64_t val;
215 #endif
216
217 for(;;) {
218 cpu_exec_start(cs);
219 trapnr = cpu_exec(cs);
220 cpu_exec_end(cs);
221 process_queued_cpu_work(cs);
222
223 switch(trapnr) {
224 case 0x80:
225 /* linux syscall from int $0x80 */
226 ret = do_syscall(env,
227 env->regs[R_EAX],
228 env->regs[R_EBX],
229 env->regs[R_ECX],
230 env->regs[R_EDX],
231 env->regs[R_ESI],
232 env->regs[R_EDI],
233 env->regs[R_EBP],
234 0, 0);
235 if (ret == -TARGET_ERESTARTSYS) {
236 env->eip -= 2;
237 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
238 env->regs[R_EAX] = ret;
239 }
240 break;
241 #ifndef TARGET_ABI32
242 case EXCP_SYSCALL:
243 /* linux syscall from syscall instruction */
244 ret = do_syscall(env,
245 env->regs[R_EAX],
246 env->regs[R_EDI],
247 env->regs[R_ESI],
248 env->regs[R_EDX],
249 env->regs[10],
250 env->regs[8],
251 env->regs[9],
252 0, 0);
253 if (ret == -TARGET_ERESTARTSYS) {
254 env->eip -= 2;
255 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
256 env->regs[R_EAX] = ret;
257 }
258 break;
259 #endif
260 #ifdef TARGET_X86_64
261 case EXCP_VSYSCALL:
262 switch (env->eip) {
263 case TARGET_VSYSCALL_ADDR(__NR_vgettimeofday):
264 syscall_num = __NR_gettimeofday;
265 break;
266 case TARGET_VSYSCALL_ADDR(__NR_vtime):
267 #ifdef __NR_time
268 syscall_num = __NR_time;
269 #else
270 /* XXX: not yet implemented (arm eabi host) */
271 cpu_abort(cs, "Unimplemented vsyscall vtime");
272 #endif
273 break;
274 case TARGET_VSYSCALL_ADDR(__NR_vgetcpu):
275 /* XXX: not yet implemented */
276 cpu_abort(cs, "Unimplemented vsyscall vgetcpu");
277 break;
278 default:
279 cpu_abort(cs,
280 "Invalid vsyscall to address " TARGET_FMT_lx "\n",
281 env->eip);
282 }
283 env->regs[R_EAX] = do_syscall(env,
284 syscall_num,
285 env->regs[R_EDI],
286 env->regs[R_ESI],
287 env->regs[R_EDX],
288 env->regs[10],
289 env->regs[8],
290 env->regs[9],
291 0, 0);
292 /* simulate a ret */
293 get_user_u64(val, env->regs[R_ESP]);
294 env->eip = val;
295 env->regs[R_ESP] += 8;
296 break;
297 #endif
298 case EXCP0B_NOSEG:
299 case EXCP0C_STACK:
300 info.si_signo = TARGET_SIGBUS;
301 info.si_errno = 0;
302 info.si_code = TARGET_SI_KERNEL;
303 info._sifields._sigfault._addr = 0;
304 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
305 break;
306 case EXCP0D_GPF:
307 /* XXX: potential problem if ABI32 */
308 #ifndef TARGET_X86_64
309 if (env->eflags & VM_MASK) {
310 handle_vm86_fault(env);
311 } else
312 #endif
313 {
314 info.si_signo = TARGET_SIGSEGV;
315 info.si_errno = 0;
316 info.si_code = TARGET_SI_KERNEL;
317 info._sifields._sigfault._addr = 0;
318 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
319 }
320 break;
321 case EXCP0E_PAGE:
322 info.si_signo = TARGET_SIGSEGV;
323 info.si_errno = 0;
324 if (!(env->error_code & 1))
325 info.si_code = TARGET_SEGV_MAPERR;
326 else
327 info.si_code = TARGET_SEGV_ACCERR;
328 info._sifields._sigfault._addr = env->cr[2];
329 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
330 break;
331 case EXCP00_DIVZ:
332 #ifndef TARGET_X86_64
333 if (env->eflags & VM_MASK) {
334 handle_vm86_trap(env, trapnr);
335 } else
336 #endif
337 {
338 /* division by zero */
339 info.si_signo = TARGET_SIGFPE;
340 info.si_errno = 0;
341 info.si_code = TARGET_FPE_INTDIV;
342 info._sifields._sigfault._addr = env->eip;
343 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
344 }
345 break;
346 case EXCP01_DB:
347 case EXCP03_INT3:
348 #ifndef TARGET_X86_64
349 if (env->eflags & VM_MASK) {
350 handle_vm86_trap(env, trapnr);
351 } else
352 #endif
353 {
354 info.si_signo = TARGET_SIGTRAP;
355 info.si_errno = 0;
356 if (trapnr == EXCP01_DB) {
357 info.si_code = TARGET_TRAP_BRKPT;
358 info._sifields._sigfault._addr = env->eip;
359 } else {
360 info.si_code = TARGET_SI_KERNEL;
361 info._sifields._sigfault._addr = 0;
362 }
363 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
364 }
365 break;
366 case EXCP04_INTO:
367 case EXCP05_BOUND:
368 #ifndef TARGET_X86_64
369 if (env->eflags & VM_MASK) {
370 handle_vm86_trap(env, trapnr);
371 } else
372 #endif
373 {
374 info.si_signo = TARGET_SIGSEGV;
375 info.si_errno = 0;
376 info.si_code = TARGET_SI_KERNEL;
377 info._sifields._sigfault._addr = 0;
378 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
379 }
380 break;
381 case EXCP06_ILLOP:
382 info.si_signo = TARGET_SIGILL;
383 info.si_errno = 0;
384 info.si_code = TARGET_ILL_ILLOPN;
385 info._sifields._sigfault._addr = env->eip;
386 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
387 break;
388 case EXCP_INTERRUPT:
389 /* just indicate that signals should be handled asap */
390 break;
391 case EXCP_DEBUG:
392 {
393 int sig;
394
395 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
396 if (sig)
397 {
398 info.si_signo = sig;
399 info.si_errno = 0;
400 info.si_code = TARGET_TRAP_BRKPT;
401 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
402 }
403 }
404 break;
405 case EXCP_ATOMIC:
406 cpu_exec_step_atomic(cs);
407 break;
408 default:
409 pc = env->segs[R_CS].base + env->eip;
410 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
411 (long)pc, trapnr);
412 abort();
413 }
414 process_pending_signals(env);
415 }
416 }
417 #endif
418
419 #ifdef TARGET_ARM
420
421 #define get_user_code_u32(x, gaddr, env) \
422 ({ abi_long __r = get_user_u32((x), (gaddr)); \
423 if (!__r && bswap_code(arm_sctlr_b(env))) { \
424 (x) = bswap32(x); \
425 } \
426 __r; \
427 })
428
429 #define get_user_code_u16(x, gaddr, env) \
430 ({ abi_long __r = get_user_u16((x), (gaddr)); \
431 if (!__r && bswap_code(arm_sctlr_b(env))) { \
432 (x) = bswap16(x); \
433 } \
434 __r; \
435 })
436
437 #define get_user_data_u32(x, gaddr, env) \
438 ({ abi_long __r = get_user_u32((x), (gaddr)); \
439 if (!__r && arm_cpu_bswap_data(env)) { \
440 (x) = bswap32(x); \
441 } \
442 __r; \
443 })
444
445 #define get_user_data_u16(x, gaddr, env) \
446 ({ abi_long __r = get_user_u16((x), (gaddr)); \
447 if (!__r && arm_cpu_bswap_data(env)) { \
448 (x) = bswap16(x); \
449 } \
450 __r; \
451 })
452
453 #define put_user_data_u32(x, gaddr, env) \
454 ({ typeof(x) __x = (x); \
455 if (arm_cpu_bswap_data(env)) { \
456 __x = bswap32(__x); \
457 } \
458 put_user_u32(__x, (gaddr)); \
459 })
460
461 #define put_user_data_u16(x, gaddr, env) \
462 ({ typeof(x) __x = (x); \
463 if (arm_cpu_bswap_data(env)) { \
464 __x = bswap16(__x); \
465 } \
466 put_user_u16(__x, (gaddr)); \
467 })
468
469 #ifdef TARGET_ABI32
470 /* Commpage handling -- there is no commpage for AArch64 */
471
472 /*
473 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
474 * Input:
475 * r0 = pointer to oldval
476 * r1 = pointer to newval
477 * r2 = pointer to target value
478 *
479 * Output:
480 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
481 * C set if *ptr was changed, clear if no exchange happened
482 *
483 * Note segv's in kernel helpers are a bit tricky, we can set the
484 * data address sensibly but the PC address is just the entry point.
485 */
486 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
487 {
488 uint64_t oldval, newval, val;
489 uint32_t addr, cpsr;
490 target_siginfo_t info;
491
492 /* Based on the 32 bit code in do_kernel_trap */
493
494 /* XXX: This only works between threads, not between processes.
495 It's probably possible to implement this with native host
496 operations. However things like ldrex/strex are much harder so
497 there's not much point trying. */
498 start_exclusive();
499 cpsr = cpsr_read(env);
500 addr = env->regs[2];
501
502 if (get_user_u64(oldval, env->regs[0])) {
503 env->exception.vaddress = env->regs[0];
504 goto segv;
505 };
506
507 if (get_user_u64(newval, env->regs[1])) {
508 env->exception.vaddress = env->regs[1];
509 goto segv;
510 };
511
512 if (get_user_u64(val, addr)) {
513 env->exception.vaddress = addr;
514 goto segv;
515 }
516
517 if (val == oldval) {
518 val = newval;
519
520 if (put_user_u64(val, addr)) {
521 env->exception.vaddress = addr;
522 goto segv;
523 };
524
525 env->regs[0] = 0;
526 cpsr |= CPSR_C;
527 } else {
528 env->regs[0] = -1;
529 cpsr &= ~CPSR_C;
530 }
531 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
532 end_exclusive();
533 return;
534
535 segv:
536 end_exclusive();
537 /* We get the PC of the entry address - which is as good as anything,
538 on a real kernel what you get depends on which mode it uses. */
539 info.si_signo = TARGET_SIGSEGV;
540 info.si_errno = 0;
541 /* XXX: check env->error_code */
542 info.si_code = TARGET_SEGV_MAPERR;
543 info._sifields._sigfault._addr = env->exception.vaddress;
544 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
545 }
546
547 /* Handle a jump to the kernel code page. */
548 static int
549 do_kernel_trap(CPUARMState *env)
550 {
551 uint32_t addr;
552 uint32_t cpsr;
553 uint32_t val;
554
555 switch (env->regs[15]) {
556 case 0xffff0fa0: /* __kernel_memory_barrier */
557 /* ??? No-op. Will need to do better for SMP. */
558 break;
559 case 0xffff0fc0: /* __kernel_cmpxchg */
560 /* XXX: This only works between threads, not between processes.
561 It's probably possible to implement this with native host
562 operations. However things like ldrex/strex are much harder so
563 there's not much point trying. */
564 start_exclusive();
565 cpsr = cpsr_read(env);
566 addr = env->regs[2];
567 /* FIXME: This should SEGV if the access fails. */
568 if (get_user_u32(val, addr))
569 val = ~env->regs[0];
570 if (val == env->regs[0]) {
571 val = env->regs[1];
572 /* FIXME: Check for segfaults. */
573 put_user_u32(val, addr);
574 env->regs[0] = 0;
575 cpsr |= CPSR_C;
576 } else {
577 env->regs[0] = -1;
578 cpsr &= ~CPSR_C;
579 }
580 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
581 end_exclusive();
582 break;
583 case 0xffff0fe0: /* __kernel_get_tls */
584 env->regs[0] = cpu_get_tls(env);
585 break;
586 case 0xffff0f60: /* __kernel_cmpxchg64 */
587 arm_kernel_cmpxchg64_helper(env);
588 break;
589
590 default:
591 return 1;
592 }
593 /* Jump back to the caller. */
594 addr = env->regs[14];
595 if (addr & 1) {
596 env->thumb = 1;
597 addr &= ~1;
598 }
599 env->regs[15] = addr;
600
601 return 0;
602 }
603
604 void cpu_loop(CPUARMState *env)
605 {
606 CPUState *cs = CPU(arm_env_get_cpu(env));
607 int trapnr;
608 unsigned int n, insn;
609 target_siginfo_t info;
610 uint32_t addr;
611 abi_ulong ret;
612
613 for(;;) {
614 cpu_exec_start(cs);
615 trapnr = cpu_exec(cs);
616 cpu_exec_end(cs);
617 process_queued_cpu_work(cs);
618
619 switch(trapnr) {
620 case EXCP_UDEF:
621 case EXCP_NOCP:
622 case EXCP_INVSTATE:
623 {
624 TaskState *ts = cs->opaque;
625 uint32_t opcode;
626 int rc;
627
628 /* we handle the FPU emulation here, as Linux */
629 /* we get the opcode */
630 /* FIXME - what to do if get_user() fails? */
631 get_user_code_u32(opcode, env->regs[15], env);
632
633 rc = EmulateAll(opcode, &ts->fpa, env);
634 if (rc == 0) { /* illegal instruction */
635 info.si_signo = TARGET_SIGILL;
636 info.si_errno = 0;
637 info.si_code = TARGET_ILL_ILLOPN;
638 info._sifields._sigfault._addr = env->regs[15];
639 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
640 } else if (rc < 0) { /* FP exception */
641 int arm_fpe=0;
642
643 /* translate softfloat flags to FPSR flags */
644 if (-rc & float_flag_invalid)
645 arm_fpe |= BIT_IOC;
646 if (-rc & float_flag_divbyzero)
647 arm_fpe |= BIT_DZC;
648 if (-rc & float_flag_overflow)
649 arm_fpe |= BIT_OFC;
650 if (-rc & float_flag_underflow)
651 arm_fpe |= BIT_UFC;
652 if (-rc & float_flag_inexact)
653 arm_fpe |= BIT_IXC;
654
655 FPSR fpsr = ts->fpa.fpsr;
656 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
657
658 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
659 info.si_signo = TARGET_SIGFPE;
660 info.si_errno = 0;
661
662 /* ordered by priority, least first */
663 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
664 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
665 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
666 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
667 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
668
669 info._sifields._sigfault._addr = env->regs[15];
670 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
671 } else {
672 env->regs[15] += 4;
673 }
674
675 /* accumulate unenabled exceptions */
676 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
677 fpsr |= BIT_IXC;
678 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
679 fpsr |= BIT_UFC;
680 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
681 fpsr |= BIT_OFC;
682 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
683 fpsr |= BIT_DZC;
684 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
685 fpsr |= BIT_IOC;
686 ts->fpa.fpsr=fpsr;
687 } else { /* everything OK */
688 /* increment PC */
689 env->regs[15] += 4;
690 }
691 }
692 break;
693 case EXCP_SWI:
694 case EXCP_BKPT:
695 {
696 env->eabi = 1;
697 /* system call */
698 if (trapnr == EXCP_BKPT) {
699 if (env->thumb) {
700 /* FIXME - what to do if get_user() fails? */
701 get_user_code_u16(insn, env->regs[15], env);
702 n = insn & 0xff;
703 env->regs[15] += 2;
704 } else {
705 /* FIXME - what to do if get_user() fails? */
706 get_user_code_u32(insn, env->regs[15], env);
707 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
708 env->regs[15] += 4;
709 }
710 } else {
711 if (env->thumb) {
712 /* FIXME - what to do if get_user() fails? */
713 get_user_code_u16(insn, env->regs[15] - 2, env);
714 n = insn & 0xff;
715 } else {
716 /* FIXME - what to do if get_user() fails? */
717 get_user_code_u32(insn, env->regs[15] - 4, env);
718 n = insn & 0xffffff;
719 }
720 }
721
722 if (n == ARM_NR_cacheflush) {
723 /* nop */
724 } else if (n == ARM_NR_semihosting
725 || n == ARM_NR_thumb_semihosting) {
726 env->regs[0] = do_arm_semihosting (env);
727 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
728 /* linux syscall */
729 if (env->thumb || n == 0) {
730 n = env->regs[7];
731 } else {
732 n -= ARM_SYSCALL_BASE;
733 env->eabi = 0;
734 }
735 if ( n > ARM_NR_BASE) {
736 switch (n) {
737 case ARM_NR_cacheflush:
738 /* nop */
739 break;
740 case ARM_NR_set_tls:
741 cpu_set_tls(env, env->regs[0]);
742 env->regs[0] = 0;
743 break;
744 case ARM_NR_breakpoint:
745 env->regs[15] -= env->thumb ? 2 : 4;
746 goto excp_debug;
747 default:
748 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
749 n);
750 env->regs[0] = -TARGET_ENOSYS;
751 break;
752 }
753 } else {
754 ret = do_syscall(env,
755 n,
756 env->regs[0],
757 env->regs[1],
758 env->regs[2],
759 env->regs[3],
760 env->regs[4],
761 env->regs[5],
762 0, 0);
763 if (ret == -TARGET_ERESTARTSYS) {
764 env->regs[15] -= env->thumb ? 2 : 4;
765 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
766 env->regs[0] = ret;
767 }
768 }
769 } else {
770 goto error;
771 }
772 }
773 break;
774 case EXCP_SEMIHOST:
775 env->regs[0] = do_arm_semihosting(env);
776 break;
777 case EXCP_INTERRUPT:
778 /* just indicate that signals should be handled asap */
779 break;
780 case EXCP_PREFETCH_ABORT:
781 case EXCP_DATA_ABORT:
782 addr = env->exception.vaddress;
783 {
784 info.si_signo = TARGET_SIGSEGV;
785 info.si_errno = 0;
786 /* XXX: check env->error_code */
787 info.si_code = TARGET_SEGV_MAPERR;
788 info._sifields._sigfault._addr = addr;
789 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
790 }
791 break;
792 case EXCP_DEBUG:
793 excp_debug:
794 {
795 int sig;
796
797 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
798 if (sig)
799 {
800 info.si_signo = sig;
801 info.si_errno = 0;
802 info.si_code = TARGET_TRAP_BRKPT;
803 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
804 }
805 }
806 break;
807 case EXCP_KERNEL_TRAP:
808 if (do_kernel_trap(env))
809 goto error;
810 break;
811 case EXCP_YIELD:
812 /* nothing to do here for user-mode, just resume guest code */
813 break;
814 case EXCP_ATOMIC:
815 cpu_exec_step_atomic(cs);
816 break;
817 default:
818 error:
819 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
820 abort();
821 }
822 process_pending_signals(env);
823 }
824 }
825
826 #else
827
828 /* AArch64 main loop */
829 void cpu_loop(CPUARMState *env)
830 {
831 CPUState *cs = CPU(arm_env_get_cpu(env));
832 int trapnr, sig;
833 abi_long ret;
834 target_siginfo_t info;
835
836 for (;;) {
837 cpu_exec_start(cs);
838 trapnr = cpu_exec(cs);
839 cpu_exec_end(cs);
840 process_queued_cpu_work(cs);
841
842 switch (trapnr) {
843 case EXCP_SWI:
844 ret = do_syscall(env,
845 env->xregs[8],
846 env->xregs[0],
847 env->xregs[1],
848 env->xregs[2],
849 env->xregs[3],
850 env->xregs[4],
851 env->xregs[5],
852 0, 0);
853 if (ret == -TARGET_ERESTARTSYS) {
854 env->pc -= 4;
855 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
856 env->xregs[0] = ret;
857 }
858 break;
859 case EXCP_INTERRUPT:
860 /* just indicate that signals should be handled asap */
861 break;
862 case EXCP_UDEF:
863 info.si_signo = TARGET_SIGILL;
864 info.si_errno = 0;
865 info.si_code = TARGET_ILL_ILLOPN;
866 info._sifields._sigfault._addr = env->pc;
867 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
868 break;
869 case EXCP_PREFETCH_ABORT:
870 case EXCP_DATA_ABORT:
871 info.si_signo = TARGET_SIGSEGV;
872 info.si_errno = 0;
873 /* XXX: check env->error_code */
874 info.si_code = TARGET_SEGV_MAPERR;
875 info._sifields._sigfault._addr = env->exception.vaddress;
876 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
877 break;
878 case EXCP_DEBUG:
879 case EXCP_BKPT:
880 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
881 if (sig) {
882 info.si_signo = sig;
883 info.si_errno = 0;
884 info.si_code = TARGET_TRAP_BRKPT;
885 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
886 }
887 break;
888 case EXCP_SEMIHOST:
889 env->xregs[0] = do_arm_semihosting(env);
890 break;
891 case EXCP_YIELD:
892 /* nothing to do here for user-mode, just resume guest code */
893 break;
894 case EXCP_ATOMIC:
895 cpu_exec_step_atomic(cs);
896 break;
897 default:
898 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
899 abort();
900 }
901 process_pending_signals(env);
902 /* Exception return on AArch64 always clears the exclusive monitor,
903 * so any return to running guest code implies this.
904 */
905 env->exclusive_addr = -1;
906 }
907 }
908 #endif /* ndef TARGET_ABI32 */
909
910 #endif
911
912 #ifdef TARGET_UNICORE32
913
914 void cpu_loop(CPUUniCore32State *env)
915 {
916 CPUState *cs = CPU(uc32_env_get_cpu(env));
917 int trapnr;
918 unsigned int n, insn;
919 target_siginfo_t info;
920
921 for (;;) {
922 cpu_exec_start(cs);
923 trapnr = cpu_exec(cs);
924 cpu_exec_end(cs);
925 process_queued_cpu_work(cs);
926
927 switch (trapnr) {
928 case UC32_EXCP_PRIV:
929 {
930 /* system call */
931 get_user_u32(insn, env->regs[31] - 4);
932 n = insn & 0xffffff;
933
934 if (n >= UC32_SYSCALL_BASE) {
935 /* linux syscall */
936 n -= UC32_SYSCALL_BASE;
937 if (n == UC32_SYSCALL_NR_set_tls) {
938 cpu_set_tls(env, env->regs[0]);
939 env->regs[0] = 0;
940 } else {
941 abi_long ret = do_syscall(env,
942 n,
943 env->regs[0],
944 env->regs[1],
945 env->regs[2],
946 env->regs[3],
947 env->regs[4],
948 env->regs[5],
949 0, 0);
950 if (ret == -TARGET_ERESTARTSYS) {
951 env->regs[31] -= 4;
952 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
953 env->regs[0] = ret;
954 }
955 }
956 } else {
957 goto error;
958 }
959 }
960 break;
961 case UC32_EXCP_DTRAP:
962 case UC32_EXCP_ITRAP:
963 info.si_signo = TARGET_SIGSEGV;
964 info.si_errno = 0;
965 /* XXX: check env->error_code */
966 info.si_code = TARGET_SEGV_MAPERR;
967 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
968 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
969 break;
970 case EXCP_INTERRUPT:
971 /* just indicate that signals should be handled asap */
972 break;
973 case EXCP_DEBUG:
974 {
975 int sig;
976
977 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
978 if (sig) {
979 info.si_signo = sig;
980 info.si_errno = 0;
981 info.si_code = TARGET_TRAP_BRKPT;
982 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
983 }
984 }
985 break;
986 case EXCP_ATOMIC:
987 cpu_exec_step_atomic(cs);
988 break;
989 default:
990 goto error;
991 }
992 process_pending_signals(env);
993 }
994
995 error:
996 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
997 abort();
998 }
999 #endif
1000
1001 #ifdef TARGET_SPARC
1002 #define SPARC64_STACK_BIAS 2047
1003
1004 //#define DEBUG_WIN
1005
1006 /* WARNING: dealing with register windows _is_ complicated. More info
1007 can be found at http://www.sics.se/~psm/sparcstack.html */
1008 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1009 {
1010 index = (index + cwp * 16) % (16 * env->nwindows);
1011 /* wrap handling : if cwp is on the last window, then we use the
1012 registers 'after' the end */
1013 if (index < 8 && env->cwp == env->nwindows - 1)
1014 index += 16 * env->nwindows;
1015 return index;
1016 }
1017
1018 /* save the register window 'cwp1' */
1019 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
1020 {
1021 unsigned int i;
1022 abi_ulong sp_ptr;
1023
1024 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1025 #ifdef TARGET_SPARC64
1026 if (sp_ptr & 3)
1027 sp_ptr += SPARC64_STACK_BIAS;
1028 #endif
1029 #if defined(DEBUG_WIN)
1030 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1031 sp_ptr, cwp1);
1032 #endif
1033 for(i = 0; i < 16; i++) {
1034 /* FIXME - what to do if put_user() fails? */
1035 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1036 sp_ptr += sizeof(abi_ulong);
1037 }
1038 }
1039
1040 static void save_window(CPUSPARCState *env)
1041 {
1042 #ifndef TARGET_SPARC64
1043 unsigned int new_wim;
1044 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1045 ((1LL << env->nwindows) - 1);
1046 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1047 env->wim = new_wim;
1048 #else
1049 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1050 env->cansave++;
1051 env->canrestore--;
1052 #endif
1053 }
1054
1055 static void restore_window(CPUSPARCState *env)
1056 {
1057 #ifndef TARGET_SPARC64
1058 unsigned int new_wim;
1059 #endif
1060 unsigned int i, cwp1;
1061 abi_ulong sp_ptr;
1062
1063 #ifndef TARGET_SPARC64
1064 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1065 ((1LL << env->nwindows) - 1);
1066 #endif
1067
1068 /* restore the invalid window */
1069 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1070 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1071 #ifdef TARGET_SPARC64
1072 if (sp_ptr & 3)
1073 sp_ptr += SPARC64_STACK_BIAS;
1074 #endif
1075 #if defined(DEBUG_WIN)
1076 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1077 sp_ptr, cwp1);
1078 #endif
1079 for(i = 0; i < 16; i++) {
1080 /* FIXME - what to do if get_user() fails? */
1081 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1082 sp_ptr += sizeof(abi_ulong);
1083 }
1084 #ifdef TARGET_SPARC64
1085 env->canrestore++;
1086 if (env->cleanwin < env->nwindows - 1)
1087 env->cleanwin++;
1088 env->cansave--;
1089 #else
1090 env->wim = new_wim;
1091 #endif
1092 }
1093
1094 static void flush_windows(CPUSPARCState *env)
1095 {
1096 int offset, cwp1;
1097
1098 offset = 1;
1099 for(;;) {
1100 /* if restore would invoke restore_window(), then we can stop */
1101 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1102 #ifndef TARGET_SPARC64
1103 if (env->wim & (1 << cwp1))
1104 break;
1105 #else
1106 if (env->canrestore == 0)
1107 break;
1108 env->cansave++;
1109 env->canrestore--;
1110 #endif
1111 save_window_offset(env, cwp1);
1112 offset++;
1113 }
1114 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1115 #ifndef TARGET_SPARC64
1116 /* set wim so that restore will reload the registers */
1117 env->wim = 1 << cwp1;
1118 #endif
1119 #if defined(DEBUG_WIN)
1120 printf("flush_windows: nb=%d\n", offset - 1);
1121 #endif
1122 }
1123
1124 void cpu_loop (CPUSPARCState *env)
1125 {
1126 CPUState *cs = CPU(sparc_env_get_cpu(env));
1127 int trapnr;
1128 abi_long ret;
1129 target_siginfo_t info;
1130
1131 while (1) {
1132 cpu_exec_start(cs);
1133 trapnr = cpu_exec(cs);
1134 cpu_exec_end(cs);
1135 process_queued_cpu_work(cs);
1136
1137 /* Compute PSR before exposing state. */
1138 if (env->cc_op != CC_OP_FLAGS) {
1139 cpu_get_psr(env);
1140 }
1141
1142 switch (trapnr) {
1143 #ifndef TARGET_SPARC64
1144 case 0x88:
1145 case 0x90:
1146 #else
1147 case 0x110:
1148 case 0x16d:
1149 #endif
1150 ret = do_syscall (env, env->gregs[1],
1151 env->regwptr[0], env->regwptr[1],
1152 env->regwptr[2], env->regwptr[3],
1153 env->regwptr[4], env->regwptr[5],
1154 0, 0);
1155 if (ret == -TARGET_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) {
1156 break;
1157 }
1158 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1159 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1160 env->xcc |= PSR_CARRY;
1161 #else
1162 env->psr |= PSR_CARRY;
1163 #endif
1164 ret = -ret;
1165 } else {
1166 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1167 env->xcc &= ~PSR_CARRY;
1168 #else
1169 env->psr &= ~PSR_CARRY;
1170 #endif
1171 }
1172 env->regwptr[0] = ret;
1173 /* next instruction */
1174 env->pc = env->npc;
1175 env->npc = env->npc + 4;
1176 break;
1177 case 0x83: /* flush windows */
1178 #ifdef TARGET_ABI32
1179 case 0x103:
1180 #endif
1181 flush_windows(env);
1182 /* next instruction */
1183 env->pc = env->npc;
1184 env->npc = env->npc + 4;
1185 break;
1186 #ifndef TARGET_SPARC64
1187 case TT_WIN_OVF: /* window overflow */
1188 save_window(env);
1189 break;
1190 case TT_WIN_UNF: /* window underflow */
1191 restore_window(env);
1192 break;
1193 case TT_TFAULT:
1194 case TT_DFAULT:
1195 {
1196 info.si_signo = TARGET_SIGSEGV;
1197 info.si_errno = 0;
1198 /* XXX: check env->error_code */
1199 info.si_code = TARGET_SEGV_MAPERR;
1200 info._sifields._sigfault._addr = env->mmuregs[4];
1201 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1202 }
1203 break;
1204 #else
1205 case TT_SPILL: /* window overflow */
1206 save_window(env);
1207 break;
1208 case TT_FILL: /* window underflow */
1209 restore_window(env);
1210 break;
1211 case TT_TFAULT:
1212 case TT_DFAULT:
1213 {
1214 info.si_signo = TARGET_SIGSEGV;
1215 info.si_errno = 0;
1216 /* XXX: check env->error_code */
1217 info.si_code = TARGET_SEGV_MAPERR;
1218 if (trapnr == TT_DFAULT)
1219 info._sifields._sigfault._addr = env->dmmu.mmuregs[4];
1220 else
1221 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1222 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1223 }
1224 break;
1225 #ifndef TARGET_ABI32
1226 case 0x16e:
1227 flush_windows(env);
1228 sparc64_get_context(env);
1229 break;
1230 case 0x16f:
1231 flush_windows(env);
1232 sparc64_set_context(env);
1233 break;
1234 #endif
1235 #endif
1236 case EXCP_INTERRUPT:
1237 /* just indicate that signals should be handled asap */
1238 break;
1239 case TT_ILL_INSN:
1240 {
1241 info.si_signo = TARGET_SIGILL;
1242 info.si_errno = 0;
1243 info.si_code = TARGET_ILL_ILLOPC;
1244 info._sifields._sigfault._addr = env->pc;
1245 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1246 }
1247 break;
1248 case EXCP_DEBUG:
1249 {
1250 int sig;
1251
1252 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1253 if (sig)
1254 {
1255 info.si_signo = sig;
1256 info.si_errno = 0;
1257 info.si_code = TARGET_TRAP_BRKPT;
1258 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1259 }
1260 }
1261 break;
1262 case EXCP_ATOMIC:
1263 cpu_exec_step_atomic(cs);
1264 break;
1265 default:
1266 printf ("Unhandled trap: 0x%x\n", trapnr);
1267 cpu_dump_state(cs, stderr, fprintf, 0);
1268 exit(EXIT_FAILURE);
1269 }
1270 process_pending_signals (env);
1271 }
1272 }
1273
1274 #endif
1275
1276 #ifdef TARGET_PPC
1277 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1278 {
1279 return cpu_get_host_ticks();
1280 }
1281
1282 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1283 {
1284 return cpu_ppc_get_tb(env);
1285 }
1286
1287 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1288 {
1289 return cpu_ppc_get_tb(env) >> 32;
1290 }
1291
1292 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1293 {
1294 return cpu_ppc_get_tb(env);
1295 }
1296
1297 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1298 {
1299 return cpu_ppc_get_tb(env) >> 32;
1300 }
1301
1302 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1303 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1304
1305 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1306 {
1307 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1308 }
1309
1310 /* XXX: to be fixed */
1311 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1312 {
1313 return -1;
1314 }
1315
1316 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1317 {
1318 return -1;
1319 }
1320
1321 static int do_store_exclusive(CPUPPCState *env)
1322 {
1323 target_ulong addr;
1324 target_ulong page_addr;
1325 target_ulong val, val2 __attribute__((unused)) = 0;
1326 int flags;
1327 int segv = 0;
1328
1329 addr = env->reserve_ea;
1330 page_addr = addr & TARGET_PAGE_MASK;
1331 start_exclusive();
1332 mmap_lock();
1333 flags = page_get_flags(page_addr);
1334 if ((flags & PAGE_READ) == 0) {
1335 segv = 1;
1336 } else {
1337 int reg = env->reserve_info & 0x1f;
1338 int size = env->reserve_info >> 5;
1339 int stored = 0;
1340
1341 if (addr == env->reserve_addr) {
1342 switch (size) {
1343 case 1: segv = get_user_u8(val, addr); break;
1344 case 2: segv = get_user_u16(val, addr); break;
1345 case 4: segv = get_user_u32(val, addr); break;
1346 #if defined(TARGET_PPC64)
1347 case 8: segv = get_user_u64(val, addr); break;
1348 case 16: {
1349 segv = get_user_u64(val, addr);
1350 if (!segv) {
1351 segv = get_user_u64(val2, addr + 8);
1352 }
1353 break;
1354 }
1355 #endif
1356 default: abort();
1357 }
1358 if (!segv && val == env->reserve_val) {
1359 val = env->gpr[reg];
1360 switch (size) {
1361 case 1: segv = put_user_u8(val, addr); break;
1362 case 2: segv = put_user_u16(val, addr); break;
1363 case 4: segv = put_user_u32(val, addr); break;
1364 #if defined(TARGET_PPC64)
1365 case 8: segv = put_user_u64(val, addr); break;
1366 case 16: {
1367 if (val2 == env->reserve_val2) {
1368 if (msr_le) {
1369 val2 = val;
1370 val = env->gpr[reg+1];
1371 } else {
1372 val2 = env->gpr[reg+1];
1373 }
1374 segv = put_user_u64(val, addr);
1375 if (!segv) {
1376 segv = put_user_u64(val2, addr + 8);
1377 }
1378 }
1379 break;
1380 }
1381 #endif
1382 default: abort();
1383 }
1384 if (!segv) {
1385 stored = 1;
1386 }
1387 }
1388 }
1389 env->crf[0] = (stored << 1) | xer_so;
1390 env->reserve_addr = (target_ulong)-1;
1391 }
1392 if (!segv) {
1393 env->nip += 4;
1394 }
1395 mmap_unlock();
1396 end_exclusive();
1397 return segv;
1398 }
1399
1400 void cpu_loop(CPUPPCState *env)
1401 {
1402 CPUState *cs = CPU(ppc_env_get_cpu(env));
1403 target_siginfo_t info;
1404 int trapnr;
1405 target_ulong ret;
1406
1407 for(;;) {
1408 cpu_exec_start(cs);
1409 trapnr = cpu_exec(cs);
1410 cpu_exec_end(cs);
1411 process_queued_cpu_work(cs);
1412
1413 switch(trapnr) {
1414 case POWERPC_EXCP_NONE:
1415 /* Just go on */
1416 break;
1417 case POWERPC_EXCP_CRITICAL: /* Critical input */
1418 cpu_abort(cs, "Critical interrupt while in user mode. "
1419 "Aborting\n");
1420 break;
1421 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1422 cpu_abort(cs, "Machine check exception while in user mode. "
1423 "Aborting\n");
1424 break;
1425 case POWERPC_EXCP_DSI: /* Data storage exception */
1426 /* XXX: check this. Seems bugged */
1427 switch (env->error_code & 0xFF000000) {
1428 case 0x40000000:
1429 case 0x42000000:
1430 info.si_signo = TARGET_SIGSEGV;
1431 info.si_errno = 0;
1432 info.si_code = TARGET_SEGV_MAPERR;
1433 break;
1434 case 0x04000000:
1435 info.si_signo = TARGET_SIGILL;
1436 info.si_errno = 0;
1437 info.si_code = TARGET_ILL_ILLADR;
1438 break;
1439 case 0x08000000:
1440 info.si_signo = TARGET_SIGSEGV;
1441 info.si_errno = 0;
1442 info.si_code = TARGET_SEGV_ACCERR;
1443 break;
1444 default:
1445 /* Let's send a regular segfault... */
1446 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1447 env->error_code);
1448 info.si_signo = TARGET_SIGSEGV;
1449 info.si_errno = 0;
1450 info.si_code = TARGET_SEGV_MAPERR;
1451 break;
1452 }
1453 info._sifields._sigfault._addr = env->nip;
1454 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1455 break;
1456 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1457 /* XXX: check this */
1458 switch (env->error_code & 0xFF000000) {
1459 case 0x40000000:
1460 info.si_signo = TARGET_SIGSEGV;
1461 info.si_errno = 0;
1462 info.si_code = TARGET_SEGV_MAPERR;
1463 break;
1464 case 0x10000000:
1465 case 0x08000000:
1466 info.si_signo = TARGET_SIGSEGV;
1467 info.si_errno = 0;
1468 info.si_code = TARGET_SEGV_ACCERR;
1469 break;
1470 default:
1471 /* Let's send a regular segfault... */
1472 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1473 env->error_code);
1474 info.si_signo = TARGET_SIGSEGV;
1475 info.si_errno = 0;
1476 info.si_code = TARGET_SEGV_MAPERR;
1477 break;
1478 }
1479 info._sifields._sigfault._addr = env->nip - 4;
1480 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1481 break;
1482 case POWERPC_EXCP_EXTERNAL: /* External input */
1483 cpu_abort(cs, "External interrupt while in user mode. "
1484 "Aborting\n");
1485 break;
1486 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1487 /* XXX: check this */
1488 info.si_signo = TARGET_SIGBUS;
1489 info.si_errno = 0;
1490 info.si_code = TARGET_BUS_ADRALN;
1491 info._sifields._sigfault._addr = env->nip;
1492 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1493 break;
1494 case POWERPC_EXCP_PROGRAM: /* Program exception */
1495 case POWERPC_EXCP_HV_EMU: /* HV emulation */
1496 /* XXX: check this */
1497 switch (env->error_code & ~0xF) {
1498 case POWERPC_EXCP_FP:
1499 info.si_signo = TARGET_SIGFPE;
1500 info.si_errno = 0;
1501 switch (env->error_code & 0xF) {
1502 case POWERPC_EXCP_FP_OX:
1503 info.si_code = TARGET_FPE_FLTOVF;
1504 break;
1505 case POWERPC_EXCP_FP_UX:
1506 info.si_code = TARGET_FPE_FLTUND;
1507 break;
1508 case POWERPC_EXCP_FP_ZX:
1509 case POWERPC_EXCP_FP_VXZDZ:
1510 info.si_code = TARGET_FPE_FLTDIV;
1511 break;
1512 case POWERPC_EXCP_FP_XX:
1513 info.si_code = TARGET_FPE_FLTRES;
1514 break;
1515 case POWERPC_EXCP_FP_VXSOFT:
1516 info.si_code = TARGET_FPE_FLTINV;
1517 break;
1518 case POWERPC_EXCP_FP_VXSNAN:
1519 case POWERPC_EXCP_FP_VXISI:
1520 case POWERPC_EXCP_FP_VXIDI:
1521 case POWERPC_EXCP_FP_VXIMZ:
1522 case POWERPC_EXCP_FP_VXVC:
1523 case POWERPC_EXCP_FP_VXSQRT:
1524 case POWERPC_EXCP_FP_VXCVI:
1525 info.si_code = TARGET_FPE_FLTSUB;
1526 break;
1527 default:
1528 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1529 env->error_code);
1530 break;
1531 }
1532 break;
1533 case POWERPC_EXCP_INVAL:
1534 info.si_signo = TARGET_SIGILL;
1535 info.si_errno = 0;
1536 switch (env->error_code & 0xF) {
1537 case POWERPC_EXCP_INVAL_INVAL:
1538 info.si_code = TARGET_ILL_ILLOPC;
1539 break;
1540 case POWERPC_EXCP_INVAL_LSWX:
1541 info.si_code = TARGET_ILL_ILLOPN;
1542 break;
1543 case POWERPC_EXCP_INVAL_SPR:
1544 info.si_code = TARGET_ILL_PRVREG;
1545 break;
1546 case POWERPC_EXCP_INVAL_FP:
1547 info.si_code = TARGET_ILL_COPROC;
1548 break;
1549 default:
1550 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1551 env->error_code & 0xF);
1552 info.si_code = TARGET_ILL_ILLADR;
1553 break;
1554 }
1555 break;
1556 case POWERPC_EXCP_PRIV:
1557 info.si_signo = TARGET_SIGILL;
1558 info.si_errno = 0;
1559 switch (env->error_code & 0xF) {
1560 case POWERPC_EXCP_PRIV_OPC:
1561 info.si_code = TARGET_ILL_PRVOPC;
1562 break;
1563 case POWERPC_EXCP_PRIV_REG:
1564 info.si_code = TARGET_ILL_PRVREG;
1565 break;
1566 default:
1567 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1568 env->error_code & 0xF);
1569 info.si_code = TARGET_ILL_PRVOPC;
1570 break;
1571 }
1572 break;
1573 case POWERPC_EXCP_TRAP:
1574 cpu_abort(cs, "Tried to call a TRAP\n");
1575 break;
1576 default:
1577 /* Should not happen ! */
1578 cpu_abort(cs, "Unknown program exception (%02x)\n",
1579 env->error_code);
1580 break;
1581 }
1582 info._sifields._sigfault._addr = env->nip;
1583 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1584 break;
1585 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1586 info.si_signo = TARGET_SIGILL;
1587 info.si_errno = 0;
1588 info.si_code = TARGET_ILL_COPROC;
1589 info._sifields._sigfault._addr = env->nip;
1590 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1591 break;
1592 case POWERPC_EXCP_SYSCALL: /* System call exception */
1593 cpu_abort(cs, "Syscall exception while in user mode. "
1594 "Aborting\n");
1595 break;
1596 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1597 info.si_signo = TARGET_SIGILL;
1598 info.si_errno = 0;
1599 info.si_code = TARGET_ILL_COPROC;
1600 info._sifields._sigfault._addr = env->nip;
1601 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1602 break;
1603 case POWERPC_EXCP_DECR: /* Decrementer exception */
1604 cpu_abort(cs, "Decrementer interrupt while in user mode. "
1605 "Aborting\n");
1606 break;
1607 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1608 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
1609 "Aborting\n");
1610 break;
1611 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1612 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
1613 "Aborting\n");
1614 break;
1615 case POWERPC_EXCP_DTLB: /* Data TLB error */
1616 cpu_abort(cs, "Data TLB exception while in user mode. "
1617 "Aborting\n");
1618 break;
1619 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1620 cpu_abort(cs, "Instruction TLB exception while in user mode. "
1621 "Aborting\n");
1622 break;
1623 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1624 info.si_signo = TARGET_SIGILL;
1625 info.si_errno = 0;
1626 info.si_code = TARGET_ILL_COPROC;
1627 info._sifields._sigfault._addr = env->nip;
1628 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1629 break;
1630 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1631 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
1632 break;
1633 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1634 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
1635 break;
1636 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1637 cpu_abort(cs, "Performance monitor exception not handled\n");
1638 break;
1639 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1640 cpu_abort(cs, "Doorbell interrupt while in user mode. "
1641 "Aborting\n");
1642 break;
1643 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1644 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
1645 "Aborting\n");
1646 break;
1647 case POWERPC_EXCP_RESET: /* System reset exception */
1648 cpu_abort(cs, "Reset interrupt while in user mode. "
1649 "Aborting\n");
1650 break;
1651 case POWERPC_EXCP_DSEG: /* Data segment exception */
1652 cpu_abort(cs, "Data segment exception while in user mode. "
1653 "Aborting\n");
1654 break;
1655 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1656 cpu_abort(cs, "Instruction segment exception "
1657 "while in user mode. Aborting\n");
1658 break;
1659 /* PowerPC 64 with hypervisor mode support */
1660 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1661 cpu_abort(cs, "Hypervisor decrementer interrupt "
1662 "while in user mode. Aborting\n");
1663 break;
1664 case POWERPC_EXCP_TRACE: /* Trace exception */
1665 /* Nothing to do:
1666 * we use this exception to emulate step-by-step execution mode.
1667 */
1668 break;
1669 /* PowerPC 64 with hypervisor mode support */
1670 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1671 cpu_abort(cs, "Hypervisor data storage exception "
1672 "while in user mode. Aborting\n");
1673 break;
1674 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1675 cpu_abort(cs, "Hypervisor instruction storage exception "
1676 "while in user mode. Aborting\n");
1677 break;
1678 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1679 cpu_abort(cs, "Hypervisor data segment exception "
1680 "while in user mode. Aborting\n");
1681 break;
1682 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1683 cpu_abort(cs, "Hypervisor instruction segment exception "
1684 "while in user mode. Aborting\n");
1685 break;
1686 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1687 info.si_signo = TARGET_SIGILL;
1688 info.si_errno = 0;
1689 info.si_code = TARGET_ILL_COPROC;
1690 info._sifields._sigfault._addr = env->nip;
1691 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1692 break;
1693 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1694 cpu_abort(cs, "Programmable interval timer interrupt "
1695 "while in user mode. Aborting\n");
1696 break;
1697 case POWERPC_EXCP_IO: /* IO error exception */
1698 cpu_abort(cs, "IO error exception while in user mode. "
1699 "Aborting\n");
1700 break;
1701 case POWERPC_EXCP_RUNM: /* Run mode exception */
1702 cpu_abort(cs, "Run mode exception while in user mode. "
1703 "Aborting\n");
1704 break;
1705 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1706 cpu_abort(cs, "Emulation trap exception not handled\n");
1707 break;
1708 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1709 cpu_abort(cs, "Instruction fetch TLB exception "
1710 "while in user-mode. Aborting");
1711 break;
1712 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1713 cpu_abort(cs, "Data load TLB exception while in user-mode. "
1714 "Aborting");
1715 break;
1716 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1717 cpu_abort(cs, "Data store TLB exception while in user-mode. "
1718 "Aborting");
1719 break;
1720 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1721 cpu_abort(cs, "Floating-point assist exception not handled\n");
1722 break;
1723 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1724 cpu_abort(cs, "Instruction address breakpoint exception "
1725 "not handled\n");
1726 break;
1727 case POWERPC_EXCP_SMI: /* System management interrupt */
1728 cpu_abort(cs, "System management interrupt while in user mode. "
1729 "Aborting\n");
1730 break;
1731 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1732 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
1733 "Aborting\n");
1734 break;
1735 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1736 cpu_abort(cs, "Performance monitor exception not handled\n");
1737 break;
1738 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1739 cpu_abort(cs, "Vector assist exception not handled\n");
1740 break;
1741 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1742 cpu_abort(cs, "Soft patch exception not handled\n");
1743 break;
1744 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1745 cpu_abort(cs, "Maintenance exception while in user mode. "
1746 "Aborting\n");
1747 break;
1748 case POWERPC_EXCP_STOP: /* stop translation */
1749 /* We did invalidate the instruction cache. Go on */
1750 break;
1751 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1752 /* We just stopped because of a branch. Go on */
1753 break;
1754 case POWERPC_EXCP_SYSCALL_USER:
1755 /* system call in user-mode emulation */
1756 /* WARNING:
1757 * PPC ABI uses overflow flag in cr0 to signal an error
1758 * in syscalls.
1759 */
1760 env->crf[0] &= ~0x1;
1761 env->nip += 4;
1762 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1763 env->gpr[5], env->gpr[6], env->gpr[7],
1764 env->gpr[8], 0, 0);
1765 if (ret == -TARGET_ERESTARTSYS) {
1766 env->nip -= 4;
1767 break;
1768 }
1769 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
1770 /* Returning from a successful sigreturn syscall.
1771 Avoid corrupting register state. */
1772 break;
1773 }
1774 if (ret > (target_ulong)(-515)) {
1775 env->crf[0] |= 0x1;
1776 ret = -ret;
1777 }
1778 env->gpr[3] = ret;
1779 break;
1780 case POWERPC_EXCP_STCX:
1781 if (do_store_exclusive(env)) {
1782 info.si_signo = TARGET_SIGSEGV;
1783 info.si_errno = 0;
1784 info.si_code = TARGET_SEGV_MAPERR;
1785 info._sifields._sigfault._addr = env->nip;
1786 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1787 }
1788 break;
1789 case EXCP_DEBUG:
1790 {
1791 int sig;
1792
1793 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1794 if (sig) {
1795 info.si_signo = sig;
1796 info.si_errno = 0;
1797 info.si_code = TARGET_TRAP_BRKPT;
1798 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1799 }
1800 }
1801 break;
1802 case EXCP_INTERRUPT:
1803 /* just indicate that signals should be handled asap */
1804 break;
1805 case EXCP_ATOMIC:
1806 cpu_exec_step_atomic(cs);
1807 break;
1808 default:
1809 cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr);
1810 break;
1811 }
1812 process_pending_signals(env);
1813 }
1814 }
1815 #endif
1816
1817 #ifdef TARGET_MIPS
1818
1819 # ifdef TARGET_ABI_MIPSO32
1820 # define MIPS_SYS(name, args) args,
1821 static const uint8_t mips_syscall_args[] = {
1822 MIPS_SYS(sys_syscall , 8) /* 4000 */
1823 MIPS_SYS(sys_exit , 1)
1824 MIPS_SYS(sys_fork , 0)
1825 MIPS_SYS(sys_read , 3)
1826 MIPS_SYS(sys_write , 3)
1827 MIPS_SYS(sys_open , 3) /* 4005 */
1828 MIPS_SYS(sys_close , 1)
1829 MIPS_SYS(sys_waitpid , 3)
1830 MIPS_SYS(sys_creat , 2)
1831 MIPS_SYS(sys_link , 2)
1832 MIPS_SYS(sys_unlink , 1) /* 4010 */
1833 MIPS_SYS(sys_execve , 0)
1834 MIPS_SYS(sys_chdir , 1)
1835 MIPS_SYS(sys_time , 1)
1836 MIPS_SYS(sys_mknod , 3)
1837 MIPS_SYS(sys_chmod , 2) /* 4015 */
1838 MIPS_SYS(sys_lchown , 3)
1839 MIPS_SYS(sys_ni_syscall , 0)
1840 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1841 MIPS_SYS(sys_lseek , 3)
1842 MIPS_SYS(sys_getpid , 0) /* 4020 */
1843 MIPS_SYS(sys_mount , 5)
1844 MIPS_SYS(sys_umount , 1)
1845 MIPS_SYS(sys_setuid , 1)
1846 MIPS_SYS(sys_getuid , 0)
1847 MIPS_SYS(sys_stime , 1) /* 4025 */
1848 MIPS_SYS(sys_ptrace , 4)
1849 MIPS_SYS(sys_alarm , 1)
1850 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1851 MIPS_SYS(sys_pause , 0)
1852 MIPS_SYS(sys_utime , 2) /* 4030 */
1853 MIPS_SYS(sys_ni_syscall , 0)
1854 MIPS_SYS(sys_ni_syscall , 0)
1855 MIPS_SYS(sys_access , 2)
1856 MIPS_SYS(sys_nice , 1)
1857 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1858 MIPS_SYS(sys_sync , 0)
1859 MIPS_SYS(sys_kill , 2)
1860 MIPS_SYS(sys_rename , 2)
1861 MIPS_SYS(sys_mkdir , 2)
1862 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1863 MIPS_SYS(sys_dup , 1)
1864 MIPS_SYS(sys_pipe , 0)
1865 MIPS_SYS(sys_times , 1)
1866 MIPS_SYS(sys_ni_syscall , 0)
1867 MIPS_SYS(sys_brk , 1) /* 4045 */
1868 MIPS_SYS(sys_setgid , 1)
1869 MIPS_SYS(sys_getgid , 0)
1870 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1871 MIPS_SYS(sys_geteuid , 0)
1872 MIPS_SYS(sys_getegid , 0) /* 4050 */
1873 MIPS_SYS(sys_acct , 0)
1874 MIPS_SYS(sys_umount2 , 2)
1875 MIPS_SYS(sys_ni_syscall , 0)
1876 MIPS_SYS(sys_ioctl , 3)
1877 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1878 MIPS_SYS(sys_ni_syscall , 2)
1879 MIPS_SYS(sys_setpgid , 2)
1880 MIPS_SYS(sys_ni_syscall , 0)
1881 MIPS_SYS(sys_olduname , 1)
1882 MIPS_SYS(sys_umask , 1) /* 4060 */
1883 MIPS_SYS(sys_chroot , 1)
1884 MIPS_SYS(sys_ustat , 2)
1885 MIPS_SYS(sys_dup2 , 2)
1886 MIPS_SYS(sys_getppid , 0)
1887 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1888 MIPS_SYS(sys_setsid , 0)
1889 MIPS_SYS(sys_sigaction , 3)
1890 MIPS_SYS(sys_sgetmask , 0)
1891 MIPS_SYS(sys_ssetmask , 1)
1892 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1893 MIPS_SYS(sys_setregid , 2)
1894 MIPS_SYS(sys_sigsuspend , 0)
1895 MIPS_SYS(sys_sigpending , 1)
1896 MIPS_SYS(sys_sethostname , 2)
1897 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1898 MIPS_SYS(sys_getrlimit , 2)
1899 MIPS_SYS(sys_getrusage , 2)
1900 MIPS_SYS(sys_gettimeofday, 2)
1901 MIPS_SYS(sys_settimeofday, 2)
1902 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1903 MIPS_SYS(sys_setgroups , 2)
1904 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1905 MIPS_SYS(sys_symlink , 2)
1906 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1907 MIPS_SYS(sys_readlink , 3) /* 4085 */
1908 MIPS_SYS(sys_uselib , 1)
1909 MIPS_SYS(sys_swapon , 2)
1910 MIPS_SYS(sys_reboot , 3)
1911 MIPS_SYS(old_readdir , 3)
1912 MIPS_SYS(old_mmap , 6) /* 4090 */
1913 MIPS_SYS(sys_munmap , 2)
1914 MIPS_SYS(sys_truncate , 2)
1915 MIPS_SYS(sys_ftruncate , 2)
1916 MIPS_SYS(sys_fchmod , 2)
1917 MIPS_SYS(sys_fchown , 3) /* 4095 */
1918 MIPS_SYS(sys_getpriority , 2)
1919 MIPS_SYS(sys_setpriority , 3)
1920 MIPS_SYS(sys_ni_syscall , 0)
1921 MIPS_SYS(sys_statfs , 2)
1922 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1923 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1924 MIPS_SYS(sys_socketcall , 2)
1925 MIPS_SYS(sys_syslog , 3)
1926 MIPS_SYS(sys_setitimer , 3)
1927 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1928 MIPS_SYS(sys_newstat , 2)
1929 MIPS_SYS(sys_newlstat , 2)
1930 MIPS_SYS(sys_newfstat , 2)
1931 MIPS_SYS(sys_uname , 1)
1932 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1933 MIPS_SYS(sys_vhangup , 0)
1934 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1935 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1936 MIPS_SYS(sys_wait4 , 4)
1937 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1938 MIPS_SYS(sys_sysinfo , 1)
1939 MIPS_SYS(sys_ipc , 6)
1940 MIPS_SYS(sys_fsync , 1)
1941 MIPS_SYS(sys_sigreturn , 0)
1942 MIPS_SYS(sys_clone , 6) /* 4120 */
1943 MIPS_SYS(sys_setdomainname, 2)
1944 MIPS_SYS(sys_newuname , 1)
1945 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1946 MIPS_SYS(sys_adjtimex , 1)
1947 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1948 MIPS_SYS(sys_sigprocmask , 3)
1949 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1950 MIPS_SYS(sys_init_module , 5)
1951 MIPS_SYS(sys_delete_module, 1)
1952 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1953 MIPS_SYS(sys_quotactl , 0)
1954 MIPS_SYS(sys_getpgid , 1)
1955 MIPS_SYS(sys_fchdir , 1)
1956 MIPS_SYS(sys_bdflush , 2)
1957 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1958 MIPS_SYS(sys_personality , 1)
1959 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1960 MIPS_SYS(sys_setfsuid , 1)
1961 MIPS_SYS(sys_setfsgid , 1)
1962 MIPS_SYS(sys_llseek , 5) /* 4140 */
1963 MIPS_SYS(sys_getdents , 3)
1964 MIPS_SYS(sys_select , 5)
1965 MIPS_SYS(sys_flock , 2)
1966 MIPS_SYS(sys_msync , 3)
1967 MIPS_SYS(sys_readv , 3) /* 4145 */
1968 MIPS_SYS(sys_writev , 3)
1969 MIPS_SYS(sys_cacheflush , 3)
1970 MIPS_SYS(sys_cachectl , 3)
1971 MIPS_SYS(sys_sysmips , 4)
1972 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1973 MIPS_SYS(sys_getsid , 1)
1974 MIPS_SYS(sys_fdatasync , 0)
1975 MIPS_SYS(sys_sysctl , 1)
1976 MIPS_SYS(sys_mlock , 2)
1977 MIPS_SYS(sys_munlock , 2) /* 4155 */
1978 MIPS_SYS(sys_mlockall , 1)
1979 MIPS_SYS(sys_munlockall , 0)
1980 MIPS_SYS(sys_sched_setparam, 2)
1981 MIPS_SYS(sys_sched_getparam, 2)
1982 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1983 MIPS_SYS(sys_sched_getscheduler, 1)
1984 MIPS_SYS(sys_sched_yield , 0)
1985 MIPS_SYS(sys_sched_get_priority_max, 1)
1986 MIPS_SYS(sys_sched_get_priority_min, 1)
1987 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1988 MIPS_SYS(sys_nanosleep, 2)
1989 MIPS_SYS(sys_mremap , 5)
1990 MIPS_SYS(sys_accept , 3)
1991 MIPS_SYS(sys_bind , 3)
1992 MIPS_SYS(sys_connect , 3) /* 4170 */
1993 MIPS_SYS(sys_getpeername , 3)
1994 MIPS_SYS(sys_getsockname , 3)
1995 MIPS_SYS(sys_getsockopt , 5)
1996 MIPS_SYS(sys_listen , 2)
1997 MIPS_SYS(sys_recv , 4) /* 4175 */
1998 MIPS_SYS(sys_recvfrom , 6)
1999 MIPS_SYS(sys_recvmsg , 3)
2000 MIPS_SYS(sys_send , 4)
2001 MIPS_SYS(sys_sendmsg , 3)
2002 MIPS_SYS(sys_sendto , 6) /* 4180 */
2003 MIPS_SYS(sys_setsockopt , 5)
2004 MIPS_SYS(sys_shutdown , 2)
2005 MIPS_SYS(sys_socket , 3)
2006 MIPS_SYS(sys_socketpair , 4)
2007 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2008 MIPS_SYS(sys_getresuid , 3)
2009 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2010 MIPS_SYS(sys_poll , 3)
2011 MIPS_SYS(sys_nfsservctl , 3)
2012 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2013 MIPS_SYS(sys_getresgid , 3)
2014 MIPS_SYS(sys_prctl , 5)
2015 MIPS_SYS(sys_rt_sigreturn, 0)
2016 MIPS_SYS(sys_rt_sigaction, 4)
2017 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2018 MIPS_SYS(sys_rt_sigpending, 2)
2019 MIPS_SYS(sys_rt_sigtimedwait, 4)
2020 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2021 MIPS_SYS(sys_rt_sigsuspend, 0)
2022 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2023 MIPS_SYS(sys_pwrite64 , 6)
2024 MIPS_SYS(sys_chown , 3)
2025 MIPS_SYS(sys_getcwd , 2)
2026 MIPS_SYS(sys_capget , 2)
2027 MIPS_SYS(sys_capset , 2) /* 4205 */
2028 MIPS_SYS(sys_sigaltstack , 2)
2029 MIPS_SYS(sys_sendfile , 4)
2030 MIPS_SYS(sys_ni_syscall , 0)
2031 MIPS_SYS(sys_ni_syscall , 0)
2032 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2033 MIPS_SYS(sys_truncate64 , 4)
2034 MIPS_SYS(sys_ftruncate64 , 4)
2035 MIPS_SYS(sys_stat64 , 2)
2036 MIPS_SYS(sys_lstat64 , 2)
2037 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2038 MIPS_SYS(sys_pivot_root , 2)
2039 MIPS_SYS(sys_mincore , 3)
2040 MIPS_SYS(sys_madvise , 3)
2041 MIPS_SYS(sys_getdents64 , 3)
2042 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2043 MIPS_SYS(sys_ni_syscall , 0)
2044 MIPS_SYS(sys_gettid , 0)
2045 MIPS_SYS(sys_readahead , 5)
2046 MIPS_SYS(sys_setxattr , 5)
2047 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2048 MIPS_SYS(sys_fsetxattr , 5)
2049 MIPS_SYS(sys_getxattr , 4)
2050 MIPS_SYS(sys_lgetxattr , 4)
2051 MIPS_SYS(sys_fgetxattr , 4)
2052 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2053 MIPS_SYS(sys_llistxattr , 3)
2054 MIPS_SYS(sys_flistxattr , 3)
2055 MIPS_SYS(sys_removexattr , 2)
2056 MIPS_SYS(sys_lremovexattr, 2)
2057 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2058 MIPS_SYS(sys_tkill , 2)
2059 MIPS_SYS(sys_sendfile64 , 5)
2060 MIPS_SYS(sys_futex , 6)
2061 MIPS_SYS(sys_sched_setaffinity, 3)
2062 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2063 MIPS_SYS(sys_io_setup , 2)
2064 MIPS_SYS(sys_io_destroy , 1)
2065 MIPS_SYS(sys_io_getevents, 5)
2066 MIPS_SYS(sys_io_submit , 3)
2067 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2068 MIPS_SYS(sys_exit_group , 1)
2069 MIPS_SYS(sys_lookup_dcookie, 3)
2070 MIPS_SYS(sys_epoll_create, 1)
2071 MIPS_SYS(sys_epoll_ctl , 4)
2072 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2073 MIPS_SYS(sys_remap_file_pages, 5)
2074 MIPS_SYS(sys_set_tid_address, 1)
2075 MIPS_SYS(sys_restart_syscall, 0)
2076 MIPS_SYS(sys_fadvise64_64, 7)
2077 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2078 MIPS_SYS(sys_fstatfs64 , 2)
2079 MIPS_SYS(sys_timer_create, 3)
2080 MIPS_SYS(sys_timer_settime, 4)
2081 MIPS_SYS(sys_timer_gettime, 2)
2082 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2083 MIPS_SYS(sys_timer_delete, 1)
2084 MIPS_SYS(sys_clock_settime, 2)
2085 MIPS_SYS(sys_clock_gettime, 2)
2086 MIPS_SYS(sys_clock_getres, 2)
2087 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2088 MIPS_SYS(sys_tgkill , 3)
2089 MIPS_SYS(sys_utimes , 2)
2090 MIPS_SYS(sys_mbind , 4)
2091 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2092 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2093 MIPS_SYS(sys_mq_open , 4)
2094 MIPS_SYS(sys_mq_unlink , 1)
2095 MIPS_SYS(sys_mq_timedsend, 5)
2096 MIPS_SYS(sys_mq_timedreceive, 5)
2097 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2098 MIPS_SYS(sys_mq_getsetattr, 3)
2099 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2100 MIPS_SYS(sys_waitid , 4)
2101 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2102 MIPS_SYS(sys_add_key , 5)
2103 MIPS_SYS(sys_request_key, 4)
2104 MIPS_SYS(sys_keyctl , 5)
2105 MIPS_SYS(sys_set_thread_area, 1)
2106 MIPS_SYS(sys_inotify_init, 0)
2107 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2108 MIPS_SYS(sys_inotify_rm_watch, 2)
2109 MIPS_SYS(sys_migrate_pages, 4)
2110 MIPS_SYS(sys_openat, 4)
2111 MIPS_SYS(sys_mkdirat, 3)
2112 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2113 MIPS_SYS(sys_fchownat, 5)
2114 MIPS_SYS(sys_futimesat, 3)
2115 MIPS_SYS(sys_fstatat64, 4)
2116 MIPS_SYS(sys_unlinkat, 3)
2117 MIPS_SYS(sys_renameat, 4) /* 4295 */
2118 MIPS_SYS(sys_linkat, 5)
2119 MIPS_SYS(sys_symlinkat, 3)
2120 MIPS_SYS(sys_readlinkat, 4)
2121 MIPS_SYS(sys_fchmodat, 3)
2122 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2123 MIPS_SYS(sys_pselect6, 6)
2124 MIPS_SYS(sys_ppoll, 5)
2125 MIPS_SYS(sys_unshare, 1)
2126 MIPS_SYS(sys_splice, 6)
2127 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2128 MIPS_SYS(sys_tee, 4)
2129 MIPS_SYS(sys_vmsplice, 4)
2130 MIPS_SYS(sys_move_pages, 6)
2131 MIPS_SYS(sys_set_robust_list, 2)
2132 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2133 MIPS_SYS(sys_kexec_load, 4)
2134 MIPS_SYS(sys_getcpu, 3)
2135 MIPS_SYS(sys_epoll_pwait, 6)
2136 MIPS_SYS(sys_ioprio_set, 3)
2137 MIPS_SYS(sys_ioprio_get, 2)
2138 MIPS_SYS(sys_utimensat, 4)
2139 MIPS_SYS(sys_signalfd, 3)
2140 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2141 MIPS_SYS(sys_eventfd, 1)
2142 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2143 MIPS_SYS(sys_timerfd_create, 2)
2144 MIPS_SYS(sys_timerfd_gettime, 2)
2145 MIPS_SYS(sys_timerfd_settime, 4)
2146 MIPS_SYS(sys_signalfd4, 4)
2147 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2148 MIPS_SYS(sys_epoll_create1, 1)
2149 MIPS_SYS(sys_dup3, 3)
2150 MIPS_SYS(sys_pipe2, 2)
2151 MIPS_SYS(sys_inotify_init1, 1)
2152 MIPS_SYS(sys_preadv, 5) /* 4330 */
2153 MIPS_SYS(sys_pwritev, 5)
2154 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2155 MIPS_SYS(sys_perf_event_open, 5)
2156 MIPS_SYS(sys_accept4, 4)
2157 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2158 MIPS_SYS(sys_fanotify_init, 2)
2159 MIPS_SYS(sys_fanotify_mark, 6)
2160 MIPS_SYS(sys_prlimit64, 4)
2161 MIPS_SYS(sys_name_to_handle_at, 5)
2162 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2163 MIPS_SYS(sys_clock_adjtime, 2)
2164 MIPS_SYS(sys_syncfs, 1)
2165 MIPS_SYS(sys_sendmmsg, 4)
2166 MIPS_SYS(sys_setns, 2)
2167 MIPS_SYS(sys_process_vm_readv, 6) /* 345 */
2168 MIPS_SYS(sys_process_vm_writev, 6)
2169 MIPS_SYS(sys_kcmp, 5)
2170 MIPS_SYS(sys_finit_module, 3)
2171 MIPS_SYS(sys_sched_setattr, 2)
2172 MIPS_SYS(sys_sched_getattr, 3) /* 350 */
2173 MIPS_SYS(sys_renameat2, 5)
2174 MIPS_SYS(sys_seccomp, 3)
2175 MIPS_SYS(sys_getrandom, 3)
2176 MIPS_SYS(sys_memfd_create, 2)
2177 MIPS_SYS(sys_bpf, 3) /* 355 */
2178 MIPS_SYS(sys_execveat, 5)
2179 MIPS_SYS(sys_userfaultfd, 1)
2180 MIPS_SYS(sys_membarrier, 2)
2181 MIPS_SYS(sys_mlock2, 3)
2182 MIPS_SYS(sys_copy_file_range, 6) /* 360 */
2183 MIPS_SYS(sys_preadv2, 6)
2184 MIPS_SYS(sys_pwritev2, 6)
2185 };
2186 # undef MIPS_SYS
2187 # endif /* O32 */
2188
2189 static int do_store_exclusive(CPUMIPSState *env)
2190 {
2191 target_ulong addr;
2192 target_ulong page_addr;
2193 target_ulong val;
2194 int flags;
2195 int segv = 0;
2196 int reg;
2197 int d;
2198
2199 addr = env->lladdr;
2200 page_addr = addr & TARGET_PAGE_MASK;
2201 start_exclusive();
2202 mmap_lock();
2203 flags = page_get_flags(page_addr);
2204 if ((flags & PAGE_READ) == 0) {
2205 segv = 1;
2206 } else {
2207 reg = env->llreg & 0x1f;
2208 d = (env->llreg & 0x20) != 0;
2209 if (d) {
2210 segv = get_user_s64(val, addr);
2211 } else {
2212 segv = get_user_s32(val, addr);
2213 }
2214 if (!segv) {
2215 if (val != env->llval) {
2216 env->active_tc.gpr[reg] = 0;
2217 } else {
2218 if (d) {
2219 segv = put_user_u64(env->llnewval, addr);
2220 } else {
2221 segv = put_user_u32(env->llnewval, addr);
2222 }
2223 if (!segv) {
2224 env->active_tc.gpr[reg] = 1;
2225 }
2226 }
2227 }
2228 }
2229 env->lladdr = -1;
2230 if (!segv) {
2231 env->active_tc.PC += 4;
2232 }
2233 mmap_unlock();
2234 end_exclusive();
2235 return segv;
2236 }
2237
2238 /* Break codes */
2239 enum {
2240 BRK_OVERFLOW = 6,
2241 BRK_DIVZERO = 7
2242 };
2243
2244 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2245 unsigned int code)
2246 {
2247 int ret = -1;
2248
2249 switch (code) {
2250 case BRK_OVERFLOW:
2251 case BRK_DIVZERO:
2252 info->si_signo = TARGET_SIGFPE;
2253 info->si_errno = 0;
2254 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2255 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info);
2256 ret = 0;
2257 break;
2258 default:
2259 info->si_signo = TARGET_SIGTRAP;
2260 info->si_errno = 0;
2261 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info);
2262 ret = 0;
2263 break;
2264 }
2265
2266 return ret;
2267 }
2268
2269 void cpu_loop(CPUMIPSState *env)
2270 {
2271 CPUState *cs = CPU(mips_env_get_cpu(env));
2272 target_siginfo_t info;
2273 int trapnr;
2274 abi_long ret;
2275 # ifdef TARGET_ABI_MIPSO32
2276 unsigned int syscall_num;
2277 # endif
2278
2279 for(;;) {
2280 cpu_exec_start(cs);
2281 trapnr = cpu_exec(cs);
2282 cpu_exec_end(cs);
2283 process_queued_cpu_work(cs);
2284
2285 switch(trapnr) {
2286 case EXCP_SYSCALL:
2287 env->active_tc.PC += 4;
2288 # ifdef TARGET_ABI_MIPSO32
2289 syscall_num = env->active_tc.gpr[2] - 4000;
2290 if (syscall_num >= sizeof(mips_syscall_args)) {
2291 ret = -TARGET_ENOSYS;
2292 } else {
2293 int nb_args;
2294 abi_ulong sp_reg;
2295 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2296
2297 nb_args = mips_syscall_args[syscall_num];
2298 sp_reg = env->active_tc.gpr[29];
2299 switch (nb_args) {
2300 /* these arguments are taken from the stack */
2301 case 8:
2302 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2303 goto done_syscall;
2304 }
2305 case 7:
2306 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2307 goto done_syscall;
2308 }
2309 case 6:
2310 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2311 goto done_syscall;
2312 }
2313 case 5:
2314 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2315 goto done_syscall;
2316 }
2317 default:
2318 break;
2319 }
2320 ret = do_syscall(env, env->active_tc.gpr[2],
2321 env->active_tc.gpr[4],
2322 env->active_tc.gpr[5],
2323 env->active_tc.gpr[6],
2324 env->active_tc.gpr[7],
2325 arg5, arg6, arg7, arg8);
2326 }
2327 done_syscall:
2328 # else
2329 ret = do_syscall(env, env->active_tc.gpr[2],
2330 env->active_tc.gpr[4], env->active_tc.gpr[5],
2331 env->active_tc.gpr[6], env->active_tc.gpr[7],
2332 env->active_tc.gpr[8], env->active_tc.gpr[9],
2333 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2334 # endif /* O32 */
2335 if (ret == -TARGET_ERESTARTSYS) {
2336 env->active_tc.PC -= 4;
2337 break;
2338 }
2339 if (ret == -TARGET_QEMU_ESIGRETURN) {
2340 /* Returning from a successful sigreturn syscall.
2341 Avoid clobbering register state. */
2342 break;
2343 }
2344 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2345 env->active_tc.gpr[7] = 1; /* error flag */
2346 ret = -ret;
2347 } else {
2348 env->active_tc.gpr[7] = 0; /* error flag */
2349 }
2350 env->active_tc.gpr[2] = ret;
2351 break;
2352 case EXCP_TLBL:
2353 case EXCP_TLBS:
2354 case EXCP_AdEL:
2355 case EXCP_AdES:
2356 info.si_signo = TARGET_SIGSEGV;
2357 info.si_errno = 0;
2358 /* XXX: check env->error_code */
2359 info.si_code = TARGET_SEGV_MAPERR;
2360 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2361 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2362 break;
2363 case EXCP_CpU:
2364 case EXCP_RI:
2365 info.si_signo = TARGET_SIGILL;
2366 info.si_errno = 0;
2367 info.si_code = 0;
2368 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2369 break;
2370 case EXCP_INTERRUPT:
2371 /* just indicate that signals should be handled asap */
2372 break;
2373 case EXCP_DEBUG:
2374 {
2375 int sig;
2376
2377 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2378 if (sig)
2379 {
2380 info.si_signo = sig;
2381 info.si_errno = 0;
2382 info.si_code = TARGET_TRAP_BRKPT;
2383 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2384 }
2385 }
2386 break;
2387 case EXCP_SC:
2388 if (do_store_exclusive(env)) {
2389 info.si_signo = TARGET_SIGSEGV;
2390 info.si_errno = 0;
2391 info.si_code = TARGET_SEGV_MAPERR;
2392 info._sifields._sigfault._addr = env->active_tc.PC;
2393 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2394 }
2395 break;
2396 case EXCP_DSPDIS:
2397 info.si_signo = TARGET_SIGILL;
2398 info.si_errno = 0;
2399 info.si_code = TARGET_ILL_ILLOPC;
2400 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2401 break;
2402 /* The code below was inspired by the MIPS Linux kernel trap
2403 * handling code in arch/mips/kernel/traps.c.
2404 */
2405 case EXCP_BREAK:
2406 {
2407 abi_ulong trap_instr;
2408 unsigned int code;
2409
2410 if (env->hflags & MIPS_HFLAG_M16) {
2411 if (env->insn_flags & ASE_MICROMIPS) {
2412 /* microMIPS mode */
2413 ret = get_user_u16(trap_instr, env->active_tc.PC);
2414 if (ret != 0) {
2415 goto error;
2416 }
2417
2418 if ((trap_instr >> 10) == 0x11) {
2419 /* 16-bit instruction */
2420 code = trap_instr & 0xf;
2421 } else {
2422 /* 32-bit instruction */
2423 abi_ulong instr_lo;
2424
2425 ret = get_user_u16(instr_lo,
2426 env->active_tc.PC + 2);
2427 if (ret != 0) {
2428 goto error;
2429 }
2430 trap_instr = (trap_instr << 16) | instr_lo;
2431 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2432 /* Unfortunately, microMIPS also suffers from
2433 the old assembler bug... */
2434 if (code >= (1 << 10)) {
2435 code >>= 10;
2436 }
2437 }
2438 } else {
2439 /* MIPS16e mode */
2440 ret = get_user_u16(trap_instr, env->active_tc.PC);
2441 if (ret != 0) {
2442 goto error;
2443 }
2444 code = (trap_instr >> 6) & 0x3f;
2445 }
2446 } else {
2447 ret = get_user_u32(trap_instr, env->active_tc.PC);
2448 if (ret != 0) {
2449 goto error;
2450 }
2451
2452 /* As described in the original Linux kernel code, the
2453 * below checks on 'code' are to work around an old
2454 * assembly bug.
2455 */
2456 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2457 if (code >= (1 << 10)) {
2458 code >>= 10;
2459 }
2460 }
2461
2462 if (do_break(env, &info, code) != 0) {
2463 goto error;
2464 }
2465 }
2466 break;
2467 case EXCP_TRAP:
2468 {
2469 abi_ulong trap_instr;
2470 unsigned int code = 0;
2471
2472 if (env->hflags & MIPS_HFLAG_M16) {
2473 /* microMIPS mode */
2474 abi_ulong instr[2];
2475
2476 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2477 get_user_u16(instr[1], env->active_tc.PC + 2);
2478
2479 trap_instr = (instr[0] << 16) | instr[1];
2480 } else {
2481 ret = get_user_u32(trap_instr, env->active_tc.PC);
2482 }
2483
2484 if (ret != 0) {
2485 goto error;
2486 }
2487
2488 /* The immediate versions don't provide a code. */
2489 if (!(trap_instr & 0xFC000000)) {
2490 if (env->hflags & MIPS_HFLAG_M16) {
2491 /* microMIPS mode */
2492 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2493 } else {
2494 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2495 }
2496 }
2497
2498 if (do_break(env, &info, code) != 0) {
2499 goto error;
2500 }
2501 }
2502 break;
2503 case EXCP_ATOMIC:
2504 cpu_exec_step_atomic(cs);
2505 break;
2506 default:
2507 error:
2508 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
2509 abort();
2510 }
2511 process_pending_signals(env);
2512 }
2513 }
2514 #endif
2515
2516 #ifdef TARGET_NIOS2
2517
2518 void cpu_loop(CPUNios2State *env)
2519 {
2520 CPUState *cs = ENV_GET_CPU(env);
2521 Nios2CPU *cpu = NIOS2_CPU(cs);
2522 target_siginfo_t info;
2523 int trapnr, gdbsig, ret;
2524
2525 for (;;) {
2526 cpu_exec_start(cs);
2527 trapnr = cpu_exec(cs);
2528 cpu_exec_end(cs);
2529 gdbsig = 0;
2530
2531 switch (trapnr) {
2532 case EXCP_INTERRUPT:
2533 /* just indicate that signals should be handled asap */
2534 break;
2535 case EXCP_TRAP:
2536 if (env->regs[R_AT] == 0) {
2537 abi_long ret;
2538 qemu_log_mask(CPU_LOG_INT, "\nSyscall\n");
2539
2540 ret = do_syscall(env, env->regs[2],
2541 env->regs[4], env->regs[5], env->regs[6],
2542 env->regs[7], env->regs[8], env->regs[9],
2543 0, 0);
2544
2545 if (env->regs[2] == 0) { /* FIXME: syscall 0 workaround */
2546 ret = 0;
2547 }
2548
2549 env->regs[2] = abs(ret);
2550 /* Return value is 0..4096 */
2551 env->regs[7] = (ret > 0xfffffffffffff000ULL);
2552 env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
2553 env->regs[CR_STATUS] &= ~0x3;
2554 env->regs[R_EA] = env->regs[R_PC] + 4;
2555 env->regs[R_PC] += 4;
2556 break;
2557 } else {
2558 qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
2559
2560 env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
2561 env->regs[CR_STATUS] &= ~0x3;
2562 env->regs[R_EA] = env->regs[R_PC] + 4;
2563 env->regs[R_PC] = cpu->exception_addr;
2564
2565 gdbsig = TARGET_SIGTRAP;
2566 break;
2567 }
2568 case 0xaa:
2569 switch (env->regs[R_PC]) {
2570 /*case 0x1000:*/ /* TODO:__kuser_helper_version */
2571 case 0x1004: /* __kuser_cmpxchg */
2572 start_exclusive();
2573 if (env->regs[4] & 0x3) {
2574 goto kuser_fail;
2575 }
2576 ret = get_user_u32(env->regs[2], env->regs[4]);
2577 if (ret) {
2578 end_exclusive();
2579 goto kuser_fail;
2580 }
2581 env->regs[2] -= env->regs[5];
2582 if (env->regs[2] == 0) {
2583 put_user_u32(env->regs[6], env->regs[4]);
2584 }
2585 end_exclusive();
2586 env->regs[R_PC] = env->regs[R_RA];
2587 break;
2588 /*case 0x1040:*/ /* TODO:__kuser_sigtramp */
2589 default:
2590 ;
2591 kuser_fail:
2592 info.si_signo = TARGET_SIGSEGV;
2593 info.si_errno = 0;
2594 /* TODO: check env->error_code */
2595 info.si_code = TARGET_SEGV_MAPERR;
2596 info._sifields._sigfault._addr = env->regs[R_PC];
2597 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2598 }
2599 break;
2600 default:
2601 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
2602 trapnr);
2603 gdbsig = TARGET_SIGILL;
2604 break;
2605 }
2606 if (gdbsig) {
2607 gdb_handlesig(cs, gdbsig);
2608 if (gdbsig != TARGET_SIGTRAP) {
2609 exit(EXIT_FAILURE);
2610 }
2611 }
2612
2613 process_pending_signals(env);
2614 }
2615 }
2616
2617 #endif /* TARGET_NIOS2 */
2618
2619 #ifdef TARGET_OPENRISC
2620
2621 void cpu_loop(CPUOpenRISCState *env)
2622 {
2623 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2624 int trapnr;
2625 abi_long ret;
2626 target_siginfo_t info;
2627
2628 for (;;) {
2629 cpu_exec_start(cs);
2630 trapnr = cpu_exec(cs);
2631 cpu_exec_end(cs);
2632 process_queued_cpu_work(cs);
2633
2634 switch (trapnr) {
2635 case EXCP_SYSCALL:
2636 env->pc += 4; /* 0xc00; */
2637 ret = do_syscall(env,
2638 cpu_get_gpr(env, 11), /* return value */
2639 cpu_get_gpr(env, 3), /* r3 - r7 are params */
2640 cpu_get_gpr(env, 4),
2641 cpu_get_gpr(env, 5),
2642 cpu_get_gpr(env, 6),
2643 cpu_get_gpr(env, 7),
2644 cpu_get_gpr(env, 8), 0, 0);
2645 if (ret == -TARGET_ERESTARTSYS) {
2646 env->pc -= 4;
2647 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2648 cpu_set_gpr(env, 11, ret);
2649 }
2650 break;
2651 case EXCP_DPF:
2652 case EXCP_IPF:
2653 case EXCP_RANGE:
2654 info.si_signo = TARGET_SIGSEGV;
2655 info.si_errno = 0;
2656 info.si_code = TARGET_SEGV_MAPERR;
2657 info._sifields._sigfault._addr = env->pc;
2658 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2659 break;
2660 case EXCP_ALIGN:
2661 info.si_signo = TARGET_SIGBUS;
2662 info.si_errno = 0;
2663 info.si_code = TARGET_BUS_ADRALN;
2664 info._sifields._sigfault._addr = env->pc;
2665 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2666 break;
2667 case EXCP_ILLEGAL:
2668 info.si_signo = TARGET_SIGILL;
2669 info.si_errno = 0;
2670 info.si_code = TARGET_ILL_ILLOPC;
2671 info._sifields._sigfault._addr = env->pc;
2672 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2673 break;
2674 case EXCP_FPE:
2675 info.si_signo = TARGET_SIGFPE;
2676 info.si_errno = 0;
2677 info.si_code = 0;
2678 info._sifields._sigfault._addr = env->pc;
2679 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2680 break;
2681 case EXCP_INTERRUPT:
2682 /* We processed the pending cpu work above. */
2683 break;
2684 case EXCP_DEBUG:
2685 trapnr = gdb_handlesig(cs, TARGET_SIGTRAP);
2686 if (trapnr) {
2687 info.si_signo = trapnr;
2688 info.si_errno = 0;
2689 info.si_code = TARGET_TRAP_BRKPT;
2690 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2691 }
2692 break;
2693 case EXCP_ATOMIC:
2694 cpu_exec_step_atomic(cs);
2695 break;
2696 default:
2697 g_assert_not_reached();
2698 }
2699 process_pending_signals(env);
2700 }
2701 }
2702
2703 #endif /* TARGET_OPENRISC */
2704
2705 #ifdef TARGET_SH4
2706 void cpu_loop(CPUSH4State *env)
2707 {
2708 CPUState *cs = CPU(sh_env_get_cpu(env));
2709 int trapnr, ret;
2710 target_siginfo_t info;
2711
2712 while (1) {
2713 cpu_exec_start(cs);
2714 trapnr = cpu_exec(cs);
2715 cpu_exec_end(cs);
2716 process_queued_cpu_work(cs);
2717
2718 switch (trapnr) {
2719 case 0x160:
2720 env->pc += 2;
2721 ret = do_syscall(env,
2722 env->gregs[3],
2723 env->gregs[4],
2724 env->gregs[5],
2725 env->gregs[6],
2726 env->gregs[7],
2727 env->gregs[0],
2728 env->gregs[1],
2729 0, 0);
2730 if (ret == -TARGET_ERESTARTSYS) {
2731 env->pc -= 2;
2732 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2733 env->gregs[0] = ret;
2734 }
2735 break;
2736 case EXCP_INTERRUPT:
2737 /* just indicate that signals should be handled asap */
2738 break;
2739 case EXCP_DEBUG:
2740 {
2741 int sig;
2742
2743 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2744 if (sig)
2745 {
2746 info.si_signo = sig;
2747 info.si_errno = 0;
2748 info.si_code = TARGET_TRAP_BRKPT;
2749 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2750 }
2751 }
2752 break;
2753 case 0xa0:
2754 case 0xc0:
2755 info.si_signo = TARGET_SIGSEGV;
2756 info.si_errno = 0;
2757 info.si_code = TARGET_SEGV_MAPERR;
2758 info._sifields._sigfault._addr = env->tea;
2759 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2760 break;
2761
2762 case EXCP_ATOMIC:
2763 cpu_exec_step_atomic(cs);
2764 break;
2765 default:
2766 printf ("Unhandled trap: 0x%x\n", trapnr);
2767 cpu_dump_state(cs, stderr, fprintf, 0);
2768 exit(EXIT_FAILURE);
2769 }
2770 process_pending_signals (env);
2771 }
2772 }
2773 #endif
2774
2775 #ifdef TARGET_CRIS
2776 void cpu_loop(CPUCRISState *env)
2777 {
2778 CPUState *cs = CPU(cris_env_get_cpu(env));
2779 int trapnr, ret;
2780 target_siginfo_t info;
2781
2782 while (1) {
2783 cpu_exec_start(cs);
2784 trapnr = cpu_exec(cs);
2785 cpu_exec_end(cs);
2786 process_queued_cpu_work(cs);
2787
2788 switch (trapnr) {
2789 case 0xaa:
2790 {
2791 info.si_signo = TARGET_SIGSEGV;
2792 info.si_errno = 0;
2793 /* XXX: check env->error_code */
2794 info.si_code = TARGET_SEGV_MAPERR;
2795 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2796 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2797 }
2798 break;
2799 case EXCP_INTERRUPT:
2800 /* just indicate that signals should be handled asap */
2801 break;
2802 case EXCP_BREAK:
2803 ret = do_syscall(env,
2804 env->regs[9],
2805 env->regs[10],
2806 env->regs[11],
2807 env->regs[12],
2808 env->regs[13],
2809 env->pregs[7],
2810 env->pregs[11],
2811 0, 0);
2812 if (ret == -TARGET_ERESTARTSYS) {
2813 env->pc -= 2;
2814 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2815 env->regs[10] = ret;
2816 }
2817 break;
2818 case EXCP_DEBUG:
2819 {
2820 int sig;
2821
2822 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2823 if (sig)
2824 {
2825 info.si_signo = sig;
2826 info.si_errno = 0;
2827 info.si_code = TARGET_TRAP_BRKPT;
2828 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2829 }
2830 }
2831 break;
2832 case EXCP_ATOMIC:
2833 cpu_exec_step_atomic(cs);
2834 break;
2835 default:
2836 printf ("Unhandled trap: 0x%x\n", trapnr);
2837 cpu_dump_state(cs, stderr, fprintf, 0);
2838 exit(EXIT_FAILURE);
2839 }
2840 process_pending_signals (env);
2841 }
2842 }
2843 #endif
2844
2845 #ifdef TARGET_MICROBLAZE
2846 void cpu_loop(CPUMBState *env)
2847 {
2848 CPUState *cs = CPU(mb_env_get_cpu(env));
2849 int trapnr, ret;
2850 target_siginfo_t info;
2851
2852 while (1) {
2853 cpu_exec_start(cs);
2854 trapnr = cpu_exec(cs);
2855 cpu_exec_end(cs);
2856 process_queued_cpu_work(cs);
2857
2858 switch (trapnr) {
2859 case 0xaa:
2860 {
2861 info.si_signo = TARGET_SIGSEGV;
2862 info.si_errno = 0;
2863 /* XXX: check env->error_code */
2864 info.si_code = TARGET_SEGV_MAPERR;
2865 info._sifields._sigfault._addr = 0;
2866 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2867 }
2868 break;
2869 case EXCP_INTERRUPT:
2870 /* just indicate that signals should be handled asap */
2871 break;
2872 case EXCP_BREAK:
2873 /* Return address is 4 bytes after the call. */
2874 env->regs[14] += 4;
2875 env->sregs[SR_PC] = env->regs[14];
2876 ret = do_syscall(env,
2877 env->regs[12],
2878 env->regs[5],
2879 env->regs[6],
2880 env->regs[7],
2881 env->regs[8],
2882 env->regs[9],
2883 env->regs[10],
2884 0, 0);
2885 if (ret == -TARGET_ERESTARTSYS) {
2886 /* Wind back to before the syscall. */
2887 env->sregs[SR_PC] -= 4;
2888 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2889 env->regs[3] = ret;
2890 }
2891 /* All syscall exits result in guest r14 being equal to the
2892 * PC we return to, because the kernel syscall exit "rtbd" does
2893 * this. (This is true even for sigreturn(); note that r14 is
2894 * not a userspace-usable register, as the kernel may clobber it
2895 * at any point.)
2896 */
2897 env->regs[14] = env->sregs[SR_PC];
2898 break;
2899 case EXCP_HW_EXCP:
2900 env->regs[17] = env->sregs[SR_PC] + 4;
2901 if (env->iflags & D_FLAG) {
2902 env->sregs[SR_ESR] |= 1 << 12;
2903 env->sregs[SR_PC] -= 4;
2904 /* FIXME: if branch was immed, replay the imm as well. */
2905 }
2906
2907 env->iflags &= ~(IMM_FLAG | D_FLAG);
2908
2909 switch (env->sregs[SR_ESR] & 31) {
2910 case ESR_EC_DIVZERO:
2911 info.si_signo = TARGET_SIGFPE;
2912 info.si_errno = 0;
2913 info.si_code = TARGET_FPE_FLTDIV;
2914 info._sifields._sigfault._addr = 0;
2915 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2916 break;
2917 case ESR_EC_FPU:
2918 info.si_signo = TARGET_SIGFPE;
2919 info.si_errno = 0;
2920 if (env->sregs[SR_FSR] & FSR_IO) {
2921 info.si_code = TARGET_FPE_FLTINV;
2922 }
2923 if (env->sregs[SR_FSR] & FSR_DZ) {
2924 info.si_code = TARGET_FPE_FLTDIV;
2925 }
2926 info._sifields._sigfault._addr = 0;
2927 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2928 break;
2929 default:
2930 printf ("Unhandled hw-exception: 0x%x\n",
2931 env->sregs[SR_ESR] & ESR_EC_MASK);
2932 cpu_dump_state(cs, stderr, fprintf, 0);
2933 exit(EXIT_FAILURE);
2934 break;
2935 }
2936 break;
2937 case EXCP_DEBUG:
2938 {
2939 int sig;
2940
2941 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2942 if (sig)
2943 {
2944 info.si_signo = sig;
2945 info.si_errno = 0;
2946 info.si_code = TARGET_TRAP_BRKPT;
2947 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2948 }
2949 }
2950 break;
2951 case EXCP_ATOMIC:
2952 cpu_exec_step_atomic(cs);
2953 break;
2954 default:
2955 printf ("Unhandled trap: 0x%x\n", trapnr);
2956 cpu_dump_state(cs, stderr, fprintf, 0);
2957 exit(EXIT_FAILURE);
2958 }
2959 process_pending_signals (env);
2960 }
2961 }
2962 #endif
2963
2964 #ifdef TARGET_M68K
2965
2966 void cpu_loop(CPUM68KState *env)
2967 {
2968 CPUState *cs = CPU(m68k_env_get_cpu(env));
2969 int trapnr;
2970 unsigned int n;
2971 target_siginfo_t info;
2972 TaskState *ts = cs->opaque;
2973
2974 for(;;) {
2975 cpu_exec_start(cs);
2976 trapnr = cpu_exec(cs);
2977 cpu_exec_end(cs);
2978 process_queued_cpu_work(cs);
2979
2980 switch(trapnr) {
2981 case EXCP_ILLEGAL:
2982 {
2983 if (ts->sim_syscalls) {
2984 uint16_t nr;
2985 get_user_u16(nr, env->pc + 2);
2986 env->pc += 4;
2987 do_m68k_simcall(env, nr);
2988 } else {
2989 goto do_sigill;
2990 }
2991 }
2992 break;
2993 case EXCP_HALT_INSN:
2994 /* Semihosing syscall. */
2995 env->pc += 4;
2996 do_m68k_semihosting(env, env->dregs[0]);
2997 break;
2998 case EXCP_LINEA:
2999 case EXCP_LINEF:
3000 case EXCP_UNSUPPORTED:
3001 do_sigill:
3002 info.si_signo = TARGET_SIGILL;
3003 info.si_errno = 0;
3004 info.si_code = TARGET_ILL_ILLOPN;
3005 info._sifields._sigfault._addr = env->pc;
3006 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3007 break;
3008 case EXCP_DIV0:
3009 info.si_signo = TARGET_SIGFPE;
3010 info.si_errno = 0;
3011 info.si_code = TARGET_FPE_INTDIV;
3012 info._sifields._sigfault._addr = env->pc;
3013 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3014 break;
3015 case EXCP_TRAP0:
3016 {
3017 abi_long ret;
3018 ts->sim_syscalls = 0;
3019 n = env->dregs[0];
3020 env->pc += 2;
3021 ret = do_syscall(env,
3022 n,
3023 env->dregs[1],
3024 env->dregs[2],
3025 env->dregs[3],
3026 env->dregs[4],
3027 env->dregs[5],
3028 env->aregs[0],
3029 0, 0);
3030 if (ret == -TARGET_ERESTARTSYS) {
3031 env->pc -= 2;
3032 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3033 env->dregs[0] = ret;
3034 }
3035 }
3036 break;
3037 case EXCP_INTERRUPT:
3038 /* just indicate that signals should be handled asap */
3039 break;
3040 case EXCP_ACCESS:
3041 {
3042 info.si_signo = TARGET_SIGSEGV;
3043 info.si_errno = 0;
3044 /* XXX: check env->error_code */
3045 info.si_code = TARGET_SEGV_MAPERR;
3046 info._sifields._sigfault._addr = env->mmu.ar;
3047 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3048 }
3049 break;
3050 case EXCP_DEBUG:
3051 {
3052 int sig;
3053
3054 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3055 if (sig)
3056 {
3057 info.si_signo = sig;
3058 info.si_errno = 0;
3059 info.si_code = TARGET_TRAP_BRKPT;
3060 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3061 }
3062 }
3063 break;
3064 case EXCP_ATOMIC:
3065 cpu_exec_step_atomic(cs);
3066 break;
3067 default:
3068 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
3069 abort();
3070 }
3071 process_pending_signals(env);
3072 }
3073 }
3074 #endif /* TARGET_M68K */
3075
3076 #ifdef TARGET_ALPHA
3077 void cpu_loop(CPUAlphaState *env)
3078 {
3079 CPUState *cs = CPU(alpha_env_get_cpu(env));
3080 int trapnr;
3081 target_siginfo_t info;
3082 abi_long sysret;
3083
3084 while (1) {
3085 cpu_exec_start(cs);
3086 trapnr = cpu_exec(cs);
3087 cpu_exec_end(cs);
3088 process_queued_cpu_work(cs);
3089
3090 /* All of the traps imply a transition through PALcode, which
3091 implies an REI instruction has been executed. Which means
3092 that the intr_flag should be cleared. */
3093 env->intr_flag = 0;
3094
3095 switch (trapnr) {
3096 case EXCP_RESET:
3097 fprintf(stderr, "Reset requested. Exit\n");
3098 exit(EXIT_FAILURE);
3099 break;
3100 case EXCP_MCHK:
3101 fprintf(stderr, "Machine check exception. Exit\n");
3102 exit(EXIT_FAILURE);
3103 break;
3104 case EXCP_SMP_INTERRUPT:
3105 case EXCP_CLK_INTERRUPT:
3106 case EXCP_DEV_INTERRUPT:
3107 fprintf(stderr, "External interrupt. Exit\n");
3108 exit(EXIT_FAILURE);
3109 break;
3110 case EXCP_MMFAULT:
3111 env->lock_addr = -1;
3112 info.si_signo = TARGET_SIGSEGV;
3113 info.si_errno = 0;
3114 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
3115 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
3116 info._sifields._sigfault._addr = env->trap_arg0;
3117 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3118 break;
3119 case EXCP_UNALIGN:
3120 env->lock_addr = -1;
3121 info.si_signo = TARGET_SIGBUS;
3122 info.si_errno = 0;
3123 info.si_code = TARGET_BUS_ADRALN;
3124 info._sifields._sigfault._addr = env->trap_arg0;
3125 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3126 break;
3127 case EXCP_OPCDEC:
3128 do_sigill:
3129 env->lock_addr = -1;
3130 info.si_signo = TARGET_SIGILL;
3131 info.si_errno = 0;
3132 info.si_code = TARGET_ILL_ILLOPC;
3133 info._sifields._sigfault._addr = env->pc;
3134 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3135 break;
3136 case EXCP_ARITH:
3137 env->lock_addr = -1;
3138 info.si_signo = TARGET_SIGFPE;
3139 info.si_errno = 0;
3140 info.si_code = TARGET_FPE_FLTINV;
3141 info._sifields._sigfault._addr = env->pc;
3142 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3143 break;
3144 case EXCP_FEN:
3145 /* No-op. Linux simply re-enables the FPU. */
3146 break;
3147 case EXCP_CALL_PAL:
3148 env->lock_addr = -1;
3149 switch (env->error_code) {
3150 case 0x80:
3151 /* BPT */
3152 info.si_signo = TARGET_SIGTRAP;
3153 info.si_errno = 0;
3154 info.si_code = TARGET_TRAP_BRKPT;
3155 info._sifields._sigfault._addr = env->pc;
3156 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3157 break;
3158 case 0x81:
3159 /* BUGCHK */
3160 info.si_signo = TARGET_SIGTRAP;
3161 info.si_errno = 0;
3162 info.si_code = 0;
3163 info._sifields._sigfault._addr = env->pc;
3164 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3165 break;
3166 case 0x83:
3167 /* CALLSYS */
3168 trapnr = env->ir[IR_V0];
3169 sysret = do_syscall(env, trapnr,
3170 env->ir[IR_A0], env->ir[IR_A1],
3171 env->ir[IR_A2], env->ir[IR_A3],
3172 env->ir[IR_A4], env->ir[IR_A5],
3173 0, 0);
3174 if (sysret == -TARGET_ERESTARTSYS) {
3175 env->pc -= 4;
3176 break;
3177 }
3178 if (sysret == -TARGET_QEMU_ESIGRETURN) {
3179 break;
3180 }
3181 /* Syscall writes 0 to V0 to bypass error check, similar
3182 to how this is handled internal to Linux kernel.
3183 (Ab)use trapnr temporarily as boolean indicating error. */
3184 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3185 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3186 env->ir[IR_A3] = trapnr;
3187 break;
3188 case 0x86:
3189 /* IMB */
3190 /* ??? We can probably elide the code using page_unprotect
3191 that is checking for self-modifying code. Instead we
3192 could simply call tb_flush here. Until we work out the
3193 changes required to turn off the extra write protection,
3194 this can be a no-op. */
3195 break;
3196 case 0x9E:
3197 /* RDUNIQUE */
3198 /* Handled in the translator for usermode. */
3199 abort();
3200 case 0x9F:
3201 /* WRUNIQUE */
3202 /* Handled in the translator for usermode. */
3203 abort();
3204 case 0xAA:
3205 /* GENTRAP */
3206 info.si_signo = TARGET_SIGFPE;
3207 switch (env->ir[IR_A0]) {
3208 case TARGET_GEN_INTOVF:
3209 info.si_code = TARGET_FPE_INTOVF;
3210 break;
3211 case TARGET_GEN_INTDIV:
3212 info.si_code = TARGET_FPE_INTDIV;
3213 break;
3214 case TARGET_GEN_FLTOVF:
3215 info.si_code = TARGET_FPE_FLTOVF;
3216 break;
3217 case TARGET_GEN_FLTUND:
3218 info.si_code = TARGET_FPE_FLTUND;
3219 break;
3220 case TARGET_GEN_FLTINV:
3221 info.si_code = TARGET_FPE_FLTINV;
3222 break;
3223 case TARGET_GEN_FLTINE:
3224 info.si_code = TARGET_FPE_FLTRES;
3225 break;
3226 case TARGET_GEN_ROPRAND:
3227 info.si_code = 0;
3228 break;
3229 default:
3230 info.si_signo = TARGET_SIGTRAP;
3231 info.si_code = 0;
3232 break;
3233 }
3234 info.si_errno = 0;
3235 info._sifields._sigfault._addr = env->pc;
3236 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3237 break;
3238 default:
3239 goto do_sigill;
3240 }
3241 break;
3242 case EXCP_DEBUG:
3243 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
3244 if (info.si_signo) {
3245 env->lock_addr = -1;
3246 info.si_errno = 0;
3247 info.si_code = TARGET_TRAP_BRKPT;
3248 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3249 }
3250 break;
3251 case EXCP_INTERRUPT:
3252 /* Just indicate that signals should be handled asap. */
3253 break;
3254 case EXCP_ATOMIC:
3255 cpu_exec_step_atomic(cs);
3256 break;
3257 default:
3258 printf ("Unhandled trap: 0x%x\n", trapnr);
3259 cpu_dump_state(cs, stderr, fprintf, 0);
3260 exit(EXIT_FAILURE);
3261 }
3262 process_pending_signals (env);
3263 }
3264 }
3265 #endif /* TARGET_ALPHA */
3266
3267 #ifdef TARGET_S390X
3268 void cpu_loop(CPUS390XState *env)
3269 {
3270 CPUState *cs = CPU(s390_env_get_cpu(env));
3271 int trapnr, n, sig;
3272 target_siginfo_t info;
3273 target_ulong addr;
3274 abi_long ret;
3275
3276 while (1) {
3277 cpu_exec_start(cs);
3278 trapnr = cpu_exec(cs);
3279 cpu_exec_end(cs);
3280 process_queued_cpu_work(cs);
3281
3282 switch (trapnr) {
3283 case EXCP_INTERRUPT:
3284 /* Just indicate that signals should be handled asap. */
3285 break;
3286
3287 case EXCP_SVC:
3288 n = env->int_svc_code;
3289 if (!n) {
3290 /* syscalls > 255 */
3291 n = env->regs[1];
3292 }
3293 env->psw.addr += env->int_svc_ilen;
3294 ret = do_syscall(env, n, env->regs[2], env->regs[3],
3295 env->regs[4], env->regs[5],
3296 env->regs[6], env->regs[7], 0, 0);
3297 if (ret == -TARGET_ERESTARTSYS) {
3298 env->psw.addr -= env->int_svc_ilen;
3299 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3300 env->regs[2] = ret;
3301 }
3302 break;
3303
3304 case EXCP_DEBUG:
3305 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3306 if (sig) {
3307 n = TARGET_TRAP_BRKPT;
3308 goto do_signal_pc;
3309 }
3310 break;
3311 case EXCP_PGM:
3312 n = env->int_pgm_code;
3313 switch (n) {
3314 case PGM_OPERATION:
3315 case PGM_PRIVILEGED:
3316 sig = TARGET_SIGILL;
3317 n = TARGET_ILL_ILLOPC;
3318 goto do_signal_pc;
3319 case PGM_PROTECTION:
3320 case PGM_ADDRESSING:
3321 sig = TARGET_SIGSEGV;
3322 /* XXX: check env->error_code */
3323 n = TARGET_SEGV_MAPERR;
3324 addr = env->__excp_addr;
3325 goto do_signal;
3326 case PGM_EXECUTE:
3327 case PGM_SPECIFICATION:
3328 case PGM_SPECIAL_OP:
3329 case PGM_OPERAND:
3330 do_sigill_opn:
3331 sig = TARGET_SIGILL;
3332 n = TARGET_ILL_ILLOPN;
3333 goto do_signal_pc;
3334
3335 case PGM_FIXPT_OVERFLOW:
3336 sig = TARGET_SIGFPE;
3337 n = TARGET_FPE_INTOVF;
3338 goto do_signal_pc;
3339 case PGM_FIXPT_DIVIDE:
3340 sig = TARGET_SIGFPE;
3341 n = TARGET_FPE_INTDIV;
3342 goto do_signal_pc;
3343
3344 case PGM_DATA:
3345 n = (env->fpc >> 8) & 0xff;
3346 if (n == 0xff) {
3347 /* compare-and-trap */
3348 goto do_sigill_opn;
3349 } else {
3350 /* An IEEE exception, simulated or otherwise. */
3351 if (n & 0x80) {
3352 n = TARGET_FPE_FLTINV;
3353 } else if (n & 0x40) {
3354 n = TARGET_FPE_FLTDIV;
3355 } else if (n & 0x20) {
3356 n = TARGET_FPE_FLTOVF;
3357 } else if (n & 0x10) {
3358 n = TARGET_FPE_FLTUND;
3359 } else if (n & 0x08) {
3360 n = TARGET_FPE_FLTRES;
3361 } else {
3362 /* ??? Quantum exception; BFP, DFP error. */
3363 goto do_sigill_opn;
3364 }
3365 sig = TARGET_SIGFPE;
3366 goto do_signal_pc;
3367 }
3368
3369 default:
3370 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3371 cpu_dump_state(cs, stderr, fprintf, 0);
3372 exit(EXIT_FAILURE);
3373 }
3374 break;
3375
3376 do_signal_pc:
3377 addr = env->psw.addr;
3378 do_signal:
3379 info.si_signo = sig;
3380 info.si_errno = 0;
3381 info.si_code = n;
3382 info._sifields._sigfault._addr = addr;
3383 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3384 break;
3385
3386 case EXCP_ATOMIC:
3387 cpu_exec_step_atomic(cs);
3388 break;
3389 default:
3390 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3391 cpu_dump_state(cs, stderr, fprintf, 0);
3392 exit(EXIT_FAILURE);
3393 }
3394 process_pending_signals (env);
3395 }
3396 }
3397
3398 #endif /* TARGET_S390X */
3399
3400 #ifdef TARGET_TILEGX
3401
3402 static void gen_sigill_reg(CPUTLGState *env)
3403 {
3404 target_siginfo_t info;
3405
3406 info.si_signo = TARGET_SIGILL;
3407 info.si_errno = 0;
3408 info.si_code = TARGET_ILL_PRVREG;
3409 info._sifields._sigfault._addr = env->pc;
3410 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3411 }
3412
3413 static void do_signal(CPUTLGState *env, int signo, int sigcode)
3414 {
3415 target_siginfo_t info;
3416
3417 info.si_signo = signo;
3418 info.si_errno = 0;
3419 info._sifields._sigfault._addr = env->pc;
3420
3421 if (signo == TARGET_SIGSEGV) {
3422 /* The passed in sigcode is a dummy; check for a page mapping
3423 and pass either MAPERR or ACCERR. */
3424 target_ulong addr = env->excaddr;
3425 info._sifields._sigfault._addr = addr;
3426 if (page_check_range(addr, 1, PAGE_VALID) < 0) {
3427 sigcode = TARGET_SEGV_MAPERR;
3428 } else {
3429 sigcode = TARGET_SEGV_ACCERR;
3430 }
3431 }
3432 info.si_code = sigcode;
3433
3434 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3435 }
3436
3437 static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
3438 {
3439 env->excaddr = addr;
3440 do_signal(env, TARGET_SIGSEGV, 0);
3441 }
3442
3443 static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
3444 {
3445 if (unlikely(reg >= TILEGX_R_COUNT)) {
3446 switch (reg) {
3447 case TILEGX_R_SN:
3448 case TILEGX_R_ZERO:
3449 return;
3450 case TILEGX_R_IDN0:
3451 case TILEGX_R_IDN1:
3452 case TILEGX_R_UDN0:
3453 case TILEGX_R_UDN1:
3454 case TILEGX_R_UDN2:
3455 case TILEGX_R_UDN3:
3456 gen_sigill_reg(env);
3457 return;
3458 default:
3459 g_assert_not_reached();
3460 }
3461 }
3462 env->regs[reg] = val;
3463 }
3464
3465 /*
3466 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
3467 * memory at the address held in the first source register. If the values are
3468 * not equal, then no memory operation is performed. If the values are equal,
3469 * the 8-byte quantity from the second source register is written into memory
3470 * at the address held in the first source register. In either case, the result
3471 * of the instruction is the value read from memory. The compare and write to
3472 * memory are atomic and thus can be used for synchronization purposes. This
3473 * instruction only operates for addresses aligned to a 8-byte boundary.
3474 * Unaligned memory access causes an Unaligned Data Reference interrupt.
3475 *
3476 * Functional Description (64-bit)
3477 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
3478 * rf[Dest] = memVal;
3479 * if (memVal == SPR[CmpValueSPR])
3480 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
3481 *
3482 * Functional Description (32-bit)
3483 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
3484 * rf[Dest] = memVal;
3485 * if (memVal == signExtend32 (SPR[CmpValueSPR]))
3486 * memoryWriteWord (rf[SrcA], rf[SrcB]);
3487 *
3488 *
3489 * This function also processes exch and exch4 which need not process SPR.
3490 */
3491 static void do_exch(CPUTLGState *env, bool quad, bool cmp)
3492 {
3493 target_ulong addr;
3494 target_long val, sprval;
3495
3496 start_exclusive();
3497
3498 addr = env->atomic_srca;
3499 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3500 goto sigsegv_maperr;
3501 }
3502
3503 if (cmp) {
3504 if (quad) {
3505 sprval = env->spregs[TILEGX_SPR_CMPEXCH];
3506 } else {
3507 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
3508 }
3509 }
3510
3511 if (!cmp || val == sprval) {
3512 target_long valb = env->atomic_srcb;
3513 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3514 goto sigsegv_maperr;
3515 }
3516 }
3517
3518 set_regval(env, env->atomic_dstr, val);
3519 end_exclusive();
3520 return;
3521
3522 sigsegv_maperr:
3523 end_exclusive();
3524 gen_sigsegv_maperr(env, addr);
3525 }
3526
3527 static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
3528 {
3529 int8_t write = 1;
3530 target_ulong addr;
3531 target_long val, valb;
3532
3533 start_exclusive();
3534
3535 addr = env->atomic_srca;
3536 valb = env->atomic_srcb;
3537 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3538 goto sigsegv_maperr;
3539 }
3540
3541 switch (trapnr) {
3542 case TILEGX_EXCP_OPCODE_FETCHADD:
3543 case TILEGX_EXCP_OPCODE_FETCHADD4:
3544 valb += val;
3545 break;
3546 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3547 valb += val;
3548 if (valb < 0) {
3549 write = 0;
3550 }
3551 break;
3552 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3553 valb += val;
3554 if ((int32_t)valb < 0) {
3555 write = 0;
3556 }
3557 break;
3558 case TILEGX_EXCP_OPCODE_FETCHAND:
3559 case TILEGX_EXCP_OPCODE_FETCHAND4:
3560 valb &= val;
3561 break;
3562 case TILEGX_EXCP_OPCODE_FETCHOR:
3563 case TILEGX_EXCP_OPCODE_FETCHOR4:
3564 valb |= val;
3565 break;
3566 default:
3567 g_assert_not_reached();
3568 }
3569
3570 if (write) {
3571 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3572 goto sigsegv_maperr;
3573 }
3574 }
3575
3576 set_regval(env, env->atomic_dstr, val);
3577 end_exclusive();
3578 return;
3579
3580 sigsegv_maperr:
3581 end_exclusive();
3582 gen_sigsegv_maperr(env, addr);
3583 }
3584
3585 void cpu_loop(CPUTLGState *env)
3586 {
3587 CPUState *cs = CPU(tilegx_env_get_cpu(env));
3588 int trapnr;
3589
3590 while (1) {
3591 cpu_exec_start(cs);
3592 trapnr = cpu_exec(cs);
3593 cpu_exec_end(cs);
3594 process_queued_cpu_work(cs);
3595
3596 switch (trapnr) {
3597 case TILEGX_EXCP_SYSCALL:
3598 {
3599 abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR],
3600 env->regs[0], env->regs[1],
3601 env->regs[2], env->regs[3],
3602 env->regs[4], env->regs[5],
3603 env->regs[6], env->regs[7]);
3604 if (ret == -TARGET_ERESTARTSYS) {
3605 env->pc -= 8;
3606 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3607 env->regs[TILEGX_R_RE] = ret;
3608 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0;
3609 }
3610 break;
3611 }
3612 case TILEGX_EXCP_OPCODE_EXCH:
3613 do_exch(env, true, false);
3614 break;
3615 case TILEGX_EXCP_OPCODE_EXCH4:
3616 do_exch(env, false, false);
3617 break;
3618 case TILEGX_EXCP_OPCODE_CMPEXCH:
3619 do_exch(env, true, true);
3620 break;
3621 case TILEGX_EXCP_OPCODE_CMPEXCH4:
3622 do_exch(env, false, true);
3623 break;
3624 case TILEGX_EXCP_OPCODE_FETCHADD:
3625 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3626 case TILEGX_EXCP_OPCODE_FETCHAND:
3627 case TILEGX_EXCP_OPCODE_FETCHOR:
3628 do_fetch(env, trapnr, true);
3629 break;
3630 case TILEGX_EXCP_OPCODE_FETCHADD4:
3631 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3632 case TILEGX_EXCP_OPCODE_FETCHAND4:
3633 case TILEGX_EXCP_OPCODE_FETCHOR4:
3634 do_fetch(env, trapnr, false);
3635 break;
3636 case TILEGX_EXCP_SIGNAL:
3637 do_signal(env, env->signo, env->sigcode);
3638 break;
3639 case TILEGX_EXCP_REG_IDN_ACCESS:
3640 case TILEGX_EXCP_REG_UDN_ACCESS:
3641 gen_sigill_reg(env);
3642 break;
3643 case EXCP_ATOMIC:
3644 cpu_exec_step_atomic(cs);
3645 break;
3646 default:
3647 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
3648 g_assert_not_reached();
3649 }
3650 process_pending_signals(env);
3651 }
3652 }
3653
3654 #endif
3655
3656 #ifdef TARGET_HPPA
3657
3658 static abi_ulong hppa_lws(CPUHPPAState *env)
3659 {
3660 uint32_t which = env->gr[20];
3661 abi_ulong addr = env->gr[26];
3662 abi_ulong old = env->gr[25];
3663 abi_ulong new = env->gr[24];
3664 abi_ulong size, ret;
3665
3666 switch (which) {
3667 default:
3668 return -TARGET_ENOSYS;
3669
3670 case 0: /* elf32 atomic 32bit cmpxchg */
3671 if ((addr & 3) || !access_ok(VERIFY_WRITE, addr, 4)) {
3672 return -TARGET_EFAULT;
3673 }
3674 old = tswap32(old);
3675 new = tswap32(new);
3676 ret = atomic_cmpxchg((uint32_t *)g2h(addr), old, new);
3677 ret = tswap32(ret);
3678 break;
3679
3680 case 2: /* elf32 atomic "new" cmpxchg */
3681 size = env->gr[23];
3682 if (size >= 4) {
3683 return -TARGET_ENOSYS;
3684 }
3685 if (((addr | old | new) & ((1 << size) - 1))
3686 || !access_ok(VERIFY_WRITE, addr, 1 << size)
3687 || !access_ok(VERIFY_READ, old, 1 << size)
3688 || !access_ok(VERIFY_READ, new, 1 << size)) {
3689 return -TARGET_EFAULT;
3690 }
3691 /* Note that below we use host-endian loads so that the cmpxchg
3692 can be host-endian as well. */
3693 switch (size) {
3694 case 0:
3695 old = *(uint8_t *)g2h(old);
3696 new = *(uint8_t *)g2h(new);
3697 ret = atomic_cmpxchg((uint8_t *)g2h(addr), old, new);
3698 ret = ret != old;
3699 break;
3700 case 1:
3701 old = *(uint16_t *)g2h(old);
3702 new = *(uint16_t *)g2h(new);
3703 ret = atomic_cmpxchg((uint16_t *)g2h(addr), old, new);
3704 ret = ret != old;
3705 break;
3706 case 2:
3707 old = *(uint32_t *)g2h(old);
3708 new = *(uint32_t *)g2h(new);
3709 ret = atomic_cmpxchg((uint32_t *)g2h(addr), old, new);
3710 ret = ret != old;
3711 break;
3712 case 3:
3713 {
3714 uint64_t o64, n64, r64;
3715 o64 = *(uint64_t *)g2h(old);
3716 n64 = *(uint64_t *)g2h(new);
3717 #ifdef CONFIG_ATOMIC64
3718 r64 = atomic_cmpxchg__nocheck((uint64_t *)g2h(addr), o64, n64);
3719 ret = r64 != o64;
3720 #else
3721 start_exclusive();
3722 r64 = *(uint64_t *)g2h(addr);
3723 ret = 1;
3724 if (r64 == o64) {
3725 *(uint64_t *)g2h(addr) = n64;
3726 ret = 0;
3727 }
3728 end_exclusive();
3729 #endif
3730 }
3731 break;
3732 }
3733 break;
3734 }
3735
3736 env->gr[28] = ret;
3737 return 0;
3738 }
3739
3740 void cpu_loop(CPUHPPAState *env)
3741 {
3742 CPUState *cs = CPU(hppa_env_get_cpu(env));
3743 target_siginfo_t info;
3744 abi_ulong ret;
3745 int trapnr;
3746
3747 while (1) {
3748 cpu_exec_start(cs);
3749 trapnr = cpu_exec(cs);
3750 cpu_exec_end(cs);
3751 process_queued_cpu_work(cs);
3752
3753 switch (trapnr) {
3754 case EXCP_SYSCALL:
3755 ret = do_syscall(env, env->gr[20],
3756 env->gr[26], env->gr[25],
3757 env->gr[24], env->gr[23],
3758 env->gr[22], env->gr[21], 0, 0);
3759 switch (ret) {
3760 default:
3761 env->gr[28] = ret;
3762 /* We arrived here by faking the gateway page. Return. */
3763 env->iaoq_f = env->gr[31];
3764 env->iaoq_b = env->gr[31] + 4;
3765 break;
3766 case -TARGET_ERESTARTSYS:
3767 case -TARGET_QEMU_ESIGRETURN:
3768 break;
3769 }
3770 break;
3771 case EXCP_SYSCALL_LWS:
3772 env->gr[21] = hppa_lws(env);
3773 /* We arrived here by faking the gateway page. Return. */
3774 env->iaoq_f = env->gr[31];
3775 env->iaoq_b = env->gr[31] + 4;
3776 break;
3777 case EXCP_SIGSEGV:
3778 info.si_signo = TARGET_SIGSEGV;
3779 info.si_errno = 0;
3780 info.si_code = TARGET_SEGV_ACCERR;
3781 info._sifields._sigfault._addr = env->ior;
3782 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3783 break;
3784 case EXCP_SIGILL:
3785 info.si_signo = TARGET_SIGILL;
3786 info.si_errno = 0;
3787 info.si_code = TARGET_ILL_ILLOPN;
3788 info._sifields._sigfault._addr = env->iaoq_f;
3789 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3790 break;
3791 case EXCP_SIGFPE:
3792 info.si_signo = TARGET_SIGFPE;
3793 info.si_errno = 0;
3794 info.si_code = 0;
3795 info._sifields._sigfault._addr = env->iaoq_f;
3796 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3797 break;
3798 case EXCP_DEBUG:
3799 trapnr = gdb_handlesig(cs, TARGET_SIGTRAP);
3800 if (trapnr) {
3801 info.si_signo = trapnr;
3802 info.si_errno = 0;
3803 info.si_code = TARGET_TRAP_BRKPT;
3804 queue_signal(env, trapnr, QEMU_SI_FAULT, &info);
3805 }
3806 break;
3807 case EXCP_INTERRUPT:
3808 /* just indicate that signals should be handled asap */
3809 break;
3810 default:
3811 g_assert_not_reached();
3812 }
3813 process_pending_signals(env);
3814 }
3815 }
3816
3817 #endif /* TARGET_HPPA */
3818
3819 THREAD CPUState *thread_cpu;
3820
3821 bool qemu_cpu_is_self(CPUState *cpu)
3822 {
3823 return thread_cpu == cpu;
3824 }
3825
3826 void qemu_cpu_kick(CPUState *cpu)
3827 {
3828 cpu_exit(cpu);
3829 }
3830
3831 void task_settid(TaskState *ts)
3832 {
3833 if (ts->ts_tid == 0) {
3834 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3835 }
3836 }
3837
3838 void stop_all_tasks(void)
3839 {
3840 /*
3841 * We trust that when using NPTL, start_exclusive()
3842 * handles thread stopping correctly.
3843 */
3844 start_exclusive();
3845 }
3846
3847 /* Assumes contents are already zeroed. */
3848 void init_task_state(TaskState *ts)
3849 {
3850 ts->used = 1;
3851 }
3852
3853 CPUArchState *cpu_copy(CPUArchState *env)
3854 {
3855 CPUState *cpu = ENV_GET_CPU(env);
3856 CPUState *new_cpu = cpu_init(cpu_model);
3857 CPUArchState *new_env = new_cpu->env_ptr;
3858 CPUBreakpoint *bp;
3859 CPUWatchpoint *wp;
3860
3861 /* Reset non arch specific state */
3862 cpu_reset(new_cpu);
3863
3864 memcpy(new_env, env, sizeof(CPUArchState));
3865
3866 /* Clone all break/watchpoints.
3867 Note: Once we support ptrace with hw-debug register access, make sure
3868 BP_CPU break/watchpoints are handled correctly on clone. */
3869 QTAILQ_INIT(&new_cpu->breakpoints);
3870 QTAILQ_INIT(&new_cpu->watchpoints);
3871 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
3872 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
3873 }
3874 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
3875 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
3876 }
3877
3878 return new_env;
3879 }
3880
3881 static void handle_arg_help(const char *arg)
3882 {
3883 usage(EXIT_SUCCESS);
3884 }
3885
3886 static void handle_arg_log(const char *arg)
3887 {
3888 int mask;
3889
3890 mask = qemu_str_to_log_mask(arg);
3891 if (!mask) {
3892 qemu_print_log_usage(stdout);
3893 exit(EXIT_FAILURE);
3894 }
3895 qemu_log_needs_buffers();
3896 qemu_set_log(mask);
3897 }
3898
3899 static void handle_arg_log_filename(const char *arg)
3900 {
3901 qemu_set_log_filename(arg, &error_fatal);
3902 }
3903
3904 static void handle_arg_set_env(const char *arg)
3905 {
3906 char *r, *p, *token;
3907 r = p = strdup(arg);
3908 while ((token = strsep(&p, ",")) != NULL) {
3909 if (envlist_setenv(envlist, token) != 0) {
3910 usage(EXIT_FAILURE);
3911 }
3912 }
3913 free(r);
3914 }
3915
3916 static void handle_arg_unset_env(const char *arg)
3917 {
3918 char *r, *p, *token;
3919 r = p = strdup(arg);
3920 while ((token = strsep(&p, ",")) != NULL) {
3921 if (envlist_unsetenv(envlist, token) != 0) {
3922 usage(EXIT_FAILURE);
3923 }
3924 }
3925 free(r);
3926 }
3927
3928 static void handle_arg_argv0(const char *arg)
3929 {
3930 argv0 = strdup(arg);
3931 }
3932
3933 static void handle_arg_stack_size(const char *arg)
3934 {
3935 char *p;
3936 guest_stack_size = strtoul(arg, &p, 0);
3937 if (guest_stack_size == 0) {
3938 usage(EXIT_FAILURE);
3939 }
3940
3941 if (*p == 'M') {
3942 guest_stack_size *= 1024 * 1024;
3943 } else if (*p == 'k' || *p == 'K') {
3944 guest_stack_size *= 1024;
3945 }
3946 }
3947
3948 static void handle_arg_ld_prefix(const char *arg)
3949 {
3950 interp_prefix = strdup(arg);
3951 }
3952
3953 static void handle_arg_pagesize(const char *arg)
3954 {
3955 qemu_host_page_size = atoi(arg);
3956 if (qemu_host_page_size == 0 ||
3957 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3958 fprintf(stderr, "page size must be a power of two\n");
3959 exit(EXIT_FAILURE);
3960 }
3961 }
3962
3963 static void handle_arg_randseed(const char *arg)
3964 {
3965 unsigned long long seed;
3966
3967 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3968 fprintf(stderr, "Invalid seed number: %s\n", arg);
3969 exit(EXIT_FAILURE);
3970 }
3971 srand(seed);
3972 }
3973
3974 static void handle_arg_gdb(const char *arg)
3975 {
3976 gdbstub_port = atoi(arg);
3977 }
3978
3979 static void handle_arg_uname(const char *arg)
3980 {
3981 qemu_uname_release = strdup(arg);
3982 }
3983
3984 static void handle_arg_cpu(const char *arg)
3985 {
3986 cpu_model = strdup(arg);
3987 if (cpu_model == NULL || is_help_option(cpu_model)) {
3988 /* XXX: implement xxx_cpu_list for targets that still miss it */
3989 #if defined(cpu_list)
3990 cpu_list(stdout, &fprintf); /* deprecated */
3991 #else
3992 /* TODO: add cpu selection for alpha, microblaze, unicore32, s390x. */
3993 printf("Target ignores cpu selection\n");
3994 #endif
3995 exit(EXIT_FAILURE);
3996 }
3997 }
3998
3999 static void handle_arg_guest_base(const char *arg)
4000 {
4001 guest_base = strtol(arg, NULL, 0);
4002 have_guest_base = 1;
4003 }
4004
4005 static void handle_arg_reserved_va(const char *arg)
4006 {
4007 char *p;
4008 int shift = 0;
4009 reserved_va = strtoul(arg, &p, 0);
4010 switch (*p) {
4011 case 'k':
4012 case 'K':
4013 shift = 10;
4014 break;
4015 case 'M':
4016 shift = 20;
4017 break;
4018 case 'G':
4019 shift = 30;
4020 break;
4021 }
4022 if (shift) {
4023 unsigned long unshifted = reserved_va;
4024 p++;
4025 reserved_va <<= shift;
4026 if (((reserved_va >> shift) != unshifted)
4027 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
4028 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
4029 #endif
4030 ) {
4031 fprintf(stderr, "Reserved virtual address too big\n");
4032 exit(EXIT_FAILURE);
4033 }
4034 }
4035 if (*p) {
4036 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
4037 exit(EXIT_FAILURE);
4038 }
4039 }
4040
4041 static void handle_arg_singlestep(const char *arg)
4042 {
4043 singlestep = 1;
4044 }
4045
4046 static void handle_arg_strace(const char *arg)
4047 {
4048 do_strace = 1;
4049 }
4050
4051 static void handle_arg_version(const char *arg)
4052 {
4053 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
4054 "\n" QEMU_COPYRIGHT "\n");
4055 exit(EXIT_SUCCESS);
4056 }
4057
4058 static char *trace_file;
4059 static void handle_arg_trace(const char *arg)
4060 {
4061 g_free(trace_file);
4062 trace_file = trace_opt_parse(arg);
4063 }
4064
4065 struct qemu_argument {
4066 const char *argv;
4067 const char *env;
4068 bool has_arg;
4069 void (*handle_opt)(const char *arg);
4070 const char *example;
4071 const char *help;
4072 };
4073
4074 static const struct qemu_argument arg_table[] = {
4075 {"h", "", false, handle_arg_help,
4076 "", "print this help"},
4077 {"help", "", false, handle_arg_help,
4078 "", ""},
4079 {"g", "QEMU_GDB", true, handle_arg_gdb,
4080 "port", "wait gdb connection to 'port'"},
4081 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
4082 "path", "set the elf interpreter prefix to 'path'"},
4083 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
4084 "size", "set the stack size to 'size' bytes"},
4085 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
4086 "model", "select CPU (-cpu help for list)"},
4087 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
4088 "var=value", "sets targets environment variable (see below)"},
4089 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
4090 "var", "unsets targets environment variable (see below)"},
4091 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
4092 "argv0", "forces target process argv[0] to be 'argv0'"},
4093 {"r", "QEMU_UNAME", true, handle_arg_uname,
4094 "uname", "set qemu uname release string to 'uname'"},
4095 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
4096 "address", "set guest_base address to 'address'"},
4097 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
4098 "size", "reserve 'size' bytes for guest virtual address space"},
4099 {"d", "QEMU_LOG", true, handle_arg_log,
4100 "item[,...]", "enable logging of specified items "
4101 "(use '-d help' for a list of items)"},
4102 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
4103 "logfile", "write logs to 'logfile' (default stderr)"},
4104 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
4105 "pagesize", "set the host page size to 'pagesize'"},
4106 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
4107 "", "run in singlestep mode"},
4108 {"strace", "QEMU_STRACE", false, handle_arg_strace,
4109 "", "log system calls"},
4110 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
4111 "", "Seed for pseudo-random number generator"},
4112 {"trace", "QEMU_TRACE", true, handle_arg_trace,
4113 "", "[[enable=]<pattern>][,events=<file>][,file=<file>]"},
4114 {"version", "QEMU_VERSION", false, handle_arg_version,
4115 "", "display version information and exit"},
4116 {NULL, NULL, false, NULL, NULL, NULL}
4117 };
4118
4119 static void QEMU_NORETURN usage(int exitcode)
4120 {
4121 const struct qemu_argument *arginfo;
4122 int maxarglen;
4123 int maxenvlen;
4124
4125 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
4126 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
4127 "\n"
4128 "Options and associated environment variables:\n"
4129 "\n");
4130
4131 /* Calculate column widths. We must always have at least enough space
4132 * for the column header.
4133 */
4134 maxarglen = strlen("Argument");
4135 maxenvlen = strlen("Env-variable");
4136
4137 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4138 int arglen = strlen(arginfo->argv);
4139 if (arginfo->has_arg) {
4140 arglen += strlen(arginfo->example) + 1;
4141 }
4142 if (strlen(arginfo->env) > maxenvlen) {
4143 maxenvlen = strlen(arginfo->env);
4144 }
4145 if (arglen > maxarglen) {
4146 maxarglen = arglen;
4147 }
4148 }
4149
4150 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
4151 maxenvlen, "Env-variable");
4152
4153 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4154 if (arginfo->has_arg) {
4155 printf("-%s %-*s %-*s %s\n", arginfo->argv,
4156 (int)(maxarglen - strlen(arginfo->argv) - 1),
4157 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
4158 } else {
4159 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
4160 maxenvlen, arginfo->env,
4161 arginfo->help);
4162 }
4163 }
4164
4165 printf("\n"
4166 "Defaults:\n"
4167 "QEMU_LD_PREFIX = %s\n"
4168 "QEMU_STACK_SIZE = %ld byte\n",
4169 interp_prefix,
4170 guest_stack_size);
4171
4172 printf("\n"
4173 "You can use -E and -U options or the QEMU_SET_ENV and\n"
4174 "QEMU_UNSET_ENV environment variables to set and unset\n"
4175 "environment variables for the target process.\n"
4176 "It is possible to provide several variables by separating them\n"
4177 "by commas in getsubopt(3) style. Additionally it is possible to\n"
4178 "provide the -E and -U options multiple times.\n"
4179 "The following lines are equivalent:\n"
4180 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
4181 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
4182 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
4183 "Note that if you provide several changes to a single variable\n"
4184 "the last change will stay in effect.\n");
4185
4186 exit(exitcode);
4187 }
4188
4189 static int parse_args(int argc, char **argv)
4190 {
4191 const char *r;
4192 int optind;
4193 const struct qemu_argument *arginfo;
4194
4195 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4196 if (arginfo->env == NULL) {
4197 continue;
4198 }
4199
4200 r = getenv(arginfo->env);
4201 if (r != NULL) {
4202 arginfo->handle_opt(r);
4203 }
4204 }
4205
4206 optind = 1;
4207 for (;;) {
4208 if (optind >= argc) {
4209 break;
4210 }
4211 r = argv[optind];
4212 if (r[0] != '-') {
4213 break;
4214 }
4215 optind++;
4216 r++;
4217 if (!strcmp(r, "-")) {
4218 break;
4219 }
4220 /* Treat --foo the same as -foo. */
4221 if (r[0] == '-') {
4222 r++;
4223 }
4224
4225 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4226 if (!strcmp(r, arginfo->argv)) {
4227 if (arginfo->has_arg) {
4228 if (optind >= argc) {
4229 (void) fprintf(stderr,
4230 "qemu: missing argument for option '%s'\n", r);
4231 exit(EXIT_FAILURE);
4232 }
4233 arginfo->handle_opt(argv[optind]);
4234 optind++;
4235 } else {
4236 arginfo->handle_opt(NULL);
4237 }
4238 break;
4239 }
4240 }
4241
4242 /* no option matched the current argv */
4243 if (arginfo->handle_opt == NULL) {
4244 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r);
4245 exit(EXIT_FAILURE);
4246 }
4247 }
4248
4249 if (optind >= argc) {
4250 (void) fprintf(stderr, "qemu: no user program specified\n");
4251 exit(EXIT_FAILURE);
4252 }
4253
4254 filename = argv[optind];
4255 exec_path = argv[optind];
4256
4257 return optind;
4258 }
4259
4260 int main(int argc, char **argv)
4261 {
4262 struct target_pt_regs regs1, *regs = &regs1;
4263 struct image_info info1, *info = &info1;
4264 struct linux_binprm bprm;
4265 TaskState *ts;
4266 CPUArchState *env;
4267 CPUState *cpu;
4268 int optind;
4269 char **target_environ, **wrk;
4270 char **target_argv;
4271 int target_argc;
4272 int i;
4273 int ret;
4274 int execfd;
4275
4276 module_call_init(MODULE_INIT_TRACE);
4277 qemu_init_cpu_list();
4278 module_call_init(MODULE_INIT_QOM);
4279
4280 envlist = envlist_create();
4281
4282 /* add current environment into the list */
4283 for (wrk = environ; *wrk != NULL; wrk++) {
4284 (void) envlist_setenv(envlist, *wrk);
4285 }
4286
4287 /* Read the stack limit from the kernel. If it's "unlimited",
4288 then we can do little else besides use the default. */
4289 {
4290 struct rlimit lim;
4291 if (getrlimit(RLIMIT_STACK, &lim) == 0
4292 && lim.rlim_cur != RLIM_INFINITY
4293 && lim.rlim_cur == (target_long)lim.rlim_cur) {
4294 guest_stack_size = lim.rlim_cur;
4295 }
4296 }
4297
4298 cpu_model = NULL;
4299
4300 srand(time(NULL));
4301
4302 qemu_add_opts(&qemu_trace_opts);
4303
4304 optind = parse_args(argc, argv);
4305
4306 if (!trace_init_backends()) {
4307 exit(1);
4308 }
4309 trace_init_file(trace_file);
4310
4311 /* Zero out regs */
4312 memset(regs, 0, sizeof(struct target_pt_regs));
4313
4314 /* Zero out image_info */
4315 memset(info, 0, sizeof(struct image_info));
4316
4317 memset(&bprm, 0, sizeof (bprm));
4318
4319 /* Scan interp_prefix dir for replacement files. */
4320 init_paths(interp_prefix);
4321
4322 init_qemu_uname_release();
4323
4324 if (cpu_model == NULL) {
4325 #if defined(TARGET_I386)
4326 #ifdef TARGET_X86_64
4327 cpu_model = "qemu64";
4328 #else
4329 cpu_model = "qemu32";
4330 #endif
4331 #elif defined(TARGET_ARM)
4332 cpu_model = "any";
4333 #elif defined(TARGET_UNICORE32)
4334 cpu_model = "any";
4335 #elif defined(TARGET_M68K)
4336 cpu_model = "any";
4337 #elif defined(TARGET_SPARC)
4338 #ifdef TARGET_SPARC64
4339 cpu_model = "TI UltraSparc II";
4340 #else
4341 cpu_model = "Fujitsu MB86904";
4342 #endif
4343 #elif defined(TARGET_MIPS)
4344 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
4345 cpu_model = "5KEf";
4346 #else
4347 cpu_model = "24Kf";
4348 #endif
4349 #elif defined TARGET_OPENRISC
4350 cpu_model = "or1200";
4351 #elif defined(TARGET_PPC)
4352 # ifdef TARGET_PPC64
4353 cpu_model = "POWER8";
4354 # else
4355 cpu_model = "750";
4356 # endif
4357 #elif defined TARGET_SH4
4358 cpu_model = TYPE_SH7785_CPU;
4359 #elif defined TARGET_S390X
4360 cpu_model = "qemu";
4361 #else
4362 cpu_model = "any";
4363 #endif
4364 }
4365 tcg_exec_init(0);
4366 /* NOTE: we need to init the CPU at this stage to get
4367 qemu_host_page_size */
4368 cpu = cpu_init(cpu_model);
4369 if (!cpu) {
4370 fprintf(stderr, "Unable to find CPU definition\n");
4371 exit(EXIT_FAILURE);
4372 }
4373 env = cpu->env_ptr;
4374 cpu_reset(cpu);
4375
4376 thread_cpu = cpu;
4377
4378 if (getenv("QEMU_STRACE")) {
4379 do_strace = 1;
4380 }
4381
4382 if (getenv("QEMU_RAND_SEED")) {
4383 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4384 }
4385
4386 target_environ = envlist_to_environ(envlist, NULL);
4387 envlist_free(envlist);
4388
4389 /*
4390 * Now that page sizes are configured in cpu_init() we can do
4391 * proper page alignment for guest_base.
4392 */
4393 guest_base = HOST_PAGE_ALIGN(guest_base);
4394
4395 if (reserved_va || have_guest_base) {
4396 guest_base = init_guest_space(guest_base, reserved_va, 0,
4397 have_guest_base);
4398 if (guest_base == (unsigned long)-1) {
4399 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4400 "space for use as guest address space (check your virtual "
4401 "memory ulimit setting or reserve less using -R option)\n",
4402 reserved_va);
4403 exit(EXIT_FAILURE);
4404 }
4405
4406 if (reserved_va) {
4407 mmap_next_start = reserved_va;
4408 }
4409 }
4410
4411 /*
4412 * Read in mmap_min_addr kernel parameter. This value is used
4413 * When loading the ELF image to determine whether guest_base
4414 * is needed. It is also used in mmap_find_vma.
4415 */
4416 {
4417 FILE *fp;
4418
4419 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4420 unsigned long tmp;
4421 if (fscanf(fp, "%lu", &tmp) == 1) {
4422 mmap_min_addr = tmp;
4423 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr);
4424 }
4425 fclose(fp);
4426 }
4427 }
4428
4429 /*
4430 * Prepare copy of argv vector for target.
4431 */
4432 target_argc = argc - optind;
4433 target_argv = calloc(target_argc + 1, sizeof (char *));
4434 if (target_argv == NULL) {
4435 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4436 exit(EXIT_FAILURE);
4437 }
4438
4439 /*
4440 * If argv0 is specified (using '-0' switch) we replace
4441 * argv[0] pointer with the given one.
4442 */
4443 i = 0;
4444 if (argv0 != NULL) {
4445 target_argv[i++] = strdup(argv0);
4446 }
4447 for (; i < target_argc; i++) {
4448 target_argv[i] = strdup(argv[optind + i]);
4449 }
4450 target_argv[target_argc] = NULL;
4451
4452 ts = g_new0(TaskState, 1);
4453 init_task_state(ts);
4454 /* build Task State */
4455 ts->info = info;
4456 ts->bprm = &bprm;
4457 cpu->opaque = ts;
4458 task_settid(ts);
4459
4460 execfd = qemu_getauxval(AT_EXECFD);
4461 if (execfd == 0) {
4462 execfd = open(filename, O_RDONLY);
4463 if (execfd < 0) {
4464 printf("Error while loading %s: %s\n", filename, strerror(errno));
4465 _exit(EXIT_FAILURE);
4466 }
4467 }
4468
4469 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
4470 info, &bprm);
4471 if (ret != 0) {
4472 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4473 _exit(EXIT_FAILURE);
4474 }
4475
4476 for (wrk = target_environ; *wrk; wrk++) {
4477 g_free(*wrk);
4478 }
4479
4480 g_free(target_environ);
4481
4482 if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
4483 qemu_log("guest_base 0x%" PRIxPTR "\n", guest_base);
4484 log_page_dump();
4485
4486 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4487 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4488 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n", info->start_code);
4489 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n", info->start_data);
4490 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4491 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n", info->start_stack);
4492 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4493 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4494 qemu_log("argv_start 0x" TARGET_ABI_FMT_lx "\n", info->arg_start);
4495 qemu_log("env_start 0x" TARGET_ABI_FMT_lx "\n",
4496 info->arg_end + (abi_ulong)sizeof(abi_ulong));
4497 qemu_log("auxv_start 0x" TARGET_ABI_FMT_lx "\n", info->saved_auxv);
4498 }
4499
4500 target_set_brk(info->brk);
4501 syscall_init();
4502 signal_init();
4503
4504 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4505 generating the prologue until now so that the prologue can take
4506 the real value of GUEST_BASE into account. */
4507 tcg_prologue_init(&tcg_ctx);
4508
4509 #if defined(TARGET_I386)
4510 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
4511 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
4512 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4513 env->cr[4] |= CR4_OSFXSR_MASK;
4514 env->hflags |= HF_OSFXSR_MASK;
4515 }
4516 #ifndef TARGET_ABI32
4517 /* enable 64 bit mode if possible */
4518 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4519 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4520 exit(EXIT_FAILURE);
4521 }
4522 env->cr[4] |= CR4_PAE_MASK;
4523 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
4524 env->hflags |= HF_LMA_MASK;
4525 #endif
4526
4527 /* flags setup : we activate the IRQs by default as in user mode */
4528 env->eflags |= IF_MASK;
4529
4530 /* linux register setup */
4531 #ifndef TARGET_ABI32
4532 env->regs[R_EAX] = regs->rax;
4533 env->regs[R_EBX] = regs->rbx;
4534 env->regs[R_ECX] = regs->rcx;
4535 env->regs[R_EDX] = regs->rdx;
4536 env->regs[R_ESI] = regs->rsi;
4537 env->regs[R_EDI] = regs->rdi;
4538 env->regs[R_EBP] = regs->rbp;
4539 env->regs[R_ESP] = regs->rsp;
4540 env->eip = regs->rip;
4541 #else
4542 env->regs[R_EAX] = regs->eax;
4543 env->regs[R_EBX] = regs->ebx;
4544 env->regs[R_ECX] = regs->ecx;
4545 env->regs[R_EDX] = regs->edx;
4546 env->regs[R_ESI] = regs->esi;
4547 env->regs[R_EDI] = regs->edi;
4548 env->regs[R_EBP] = regs->ebp;
4549 env->regs[R_ESP] = regs->esp;
4550 env->eip = regs->eip;
4551 #endif
4552
4553 /* linux interrupt setup */
4554 #ifndef TARGET_ABI32
4555 env->idt.limit = 511;
4556 #else
4557 env->idt.limit = 255;
4558 #endif
4559 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4560 PROT_READ|PROT_WRITE,
4561 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4562 idt_table = g2h(env->idt.base);
4563 set_idt(0, 0);
4564 set_idt(1, 0);
4565 set_idt(2, 0);
4566 set_idt(3, 3);
4567 set_idt(4, 3);
4568 set_idt(5, 0);
4569 set_idt(6, 0);
4570 set_idt(7, 0);
4571 set_idt(8, 0);
4572 set_idt(9, 0);
4573 set_idt(10, 0);
4574 set_idt(11, 0);
4575 set_idt(12, 0);
4576 set_idt(13, 0);
4577 set_idt(14, 0);
4578 set_idt(15, 0);
4579 set_idt(16, 0);
4580 set_idt(17, 0);
4581 set_idt(18, 0);
4582 set_idt(19, 0);
4583 set_idt(0x80, 3);
4584
4585 /* linux segment setup */
4586 {
4587 uint64_t *gdt_table;
4588 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4589 PROT_READ|PROT_WRITE,
4590 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4591 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
4592 gdt_table = g2h(env->gdt.base);
4593 #ifdef TARGET_ABI32
4594 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4595 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4596 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4597 #else
4598 /* 64 bit code segment */
4599 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4600 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4601 DESC_L_MASK |
4602 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4603 #endif
4604 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4605 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4606 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4607 }
4608 cpu_x86_load_seg(env, R_CS, __USER_CS);
4609 cpu_x86_load_seg(env, R_SS, __USER_DS);
4610 #ifdef TARGET_ABI32
4611 cpu_x86_load_seg(env, R_DS, __USER_DS);
4612 cpu_x86_load_seg(env, R_ES, __USER_DS);
4613 cpu_x86_load_seg(env, R_FS, __USER_DS);
4614 cpu_x86_load_seg(env, R_GS, __USER_DS);
4615 /* This hack makes Wine work... */
4616 env->segs[R_FS].selector = 0;
4617 #else
4618 cpu_x86_load_seg(env, R_DS, 0);
4619 cpu_x86_load_seg(env, R_ES, 0);
4620 cpu_x86_load_seg(env, R_FS, 0);
4621 cpu_x86_load_seg(env, R_GS, 0);
4622 #endif
4623 #elif defined(TARGET_AARCH64)
4624 {
4625 int i;
4626
4627 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4628 fprintf(stderr,
4629 "The selected ARM CPU does not support 64 bit mode\n");
4630 exit(EXIT_FAILURE);
4631 }
4632
4633 for (i = 0; i < 31; i++) {
4634 env->xregs[i] = regs->regs[i];
4635 }
4636 env->pc = regs->pc;
4637 env->xregs[31] = regs->sp;
4638 }
4639 #elif defined(TARGET_ARM)
4640 {
4641 int i;
4642 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
4643 CPSRWriteByInstr);
4644 for(i = 0; i < 16; i++) {
4645 env->regs[i] = regs->uregs[i];
4646 }
4647 #ifdef TARGET_WORDS_BIGENDIAN
4648 /* Enable BE8. */
4649 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4650 && (info->elf_flags & EF_ARM_BE8)) {
4651 env->uncached_cpsr |= CPSR_E;
4652 env->cp15.sctlr_el[1] |= SCTLR_E0E;
4653 } else {
4654 env->cp15.sctlr_el[1] |= SCTLR_B;
4655 }
4656 #endif
4657 }
4658 #elif defined(TARGET_UNICORE32)
4659 {
4660 int i;
4661 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4662 for (i = 0; i < 32; i++) {
4663 env->regs[i] = regs->uregs[i];
4664 }
4665 }
4666 #elif defined(TARGET_SPARC)
4667 {
4668 int i;
4669 env->pc = regs->pc;
4670 env->npc = regs->npc;
4671 env->y = regs->y;
4672 for(i = 0; i < 8; i++)
4673 env->gregs[i] = regs->u_regs[i];
4674 for(i = 0; i < 8; i++)
4675 env->regwptr[i] = regs->u_regs[i + 8];
4676 }
4677 #elif defined(TARGET_PPC)
4678 {
4679 int i;
4680
4681 #if defined(TARGET_PPC64)
4682 int flag = (env->insns_flags2 & PPC2_BOOKE206) ? MSR_CM : MSR_SF;
4683 #if defined(TARGET_ABI32)
4684 env->msr &= ~((target_ulong)1 << flag);
4685 #else
4686 env->msr |= (target_ulong)1 << flag;
4687 #endif
4688 #endif
4689 env->nip = regs->nip;
4690 for(i = 0; i < 32; i++) {
4691 env->gpr[i] = regs->gpr[i];
4692 }
4693 }
4694 #elif defined(TARGET_M68K)
4695 {
4696 env->pc = regs->pc;
4697 env->dregs[0] = regs->d0;
4698 env->dregs[1] = regs->d1;
4699 env->dregs[2] = regs->d2;
4700 env->dregs[3] = regs->d3;
4701 env->dregs[4] = regs->d4;
4702 env->dregs[5] = regs->d5;
4703 env->dregs[6] = regs->d6;
4704 env->dregs[7] = regs->d7;
4705 env->aregs[0] = regs->a0;
4706 env->aregs[1] = regs->a1;
4707 env->aregs[2] = regs->a2;
4708 env->aregs[3] = regs->a3;
4709 env->aregs[4] = regs->a4;
4710 env->aregs[5] = regs->a5;
4711 env->aregs[6] = regs->a6;
4712 env->aregs[7] = regs->usp;
4713 env->sr = regs->sr;
4714 ts->sim_syscalls = 1;
4715 }
4716 #elif defined(TARGET_MICROBLAZE)
4717 {
4718 env->regs[0] = regs->r0;
4719 env->regs[1] = regs->r1;
4720 env->regs[2] = regs->r2;
4721 env->regs[3] = regs->r3;
4722 env->regs[4] = regs->r4;
4723 env->regs[5] = regs->r5;
4724 env->regs[6] = regs->r6;
4725 env->regs[7] = regs->r7;
4726 env->regs[8] = regs->r8;
4727 env->regs[9] = regs->r9;
4728 env->regs[10] = regs->r10;
4729 env->regs[11] = regs->r11;
4730 env->regs[12] = regs->r12;
4731 env->regs[13] = regs->r13;
4732 env->regs[14] = regs->r14;
4733 env->regs[15] = regs->r15;
4734 env->regs[16] = regs->r16;
4735 env->regs[17] = regs->r17;
4736 env->regs[18] = regs->r18;
4737 env->regs[19] = regs->r19;
4738 env->regs[20] = regs->r20;
4739 env->regs[21] = regs->r21;
4740 env->regs[22] = regs->r22;
4741 env->regs[23] = regs->r23;
4742 env->regs[24] = regs->r24;
4743 env->regs[25] = regs->r25;
4744 env->regs[26] = regs->r26;
4745 env->regs[27] = regs->r27;
4746 env->regs[28] = regs->r28;
4747 env->regs[29] = regs->r29;
4748 env->regs[30] = regs->r30;
4749 env->regs[31] = regs->r31;
4750 env->sregs[SR_PC] = regs->pc;
4751 }
4752 #elif defined(TARGET_MIPS)
4753 {
4754 int i;
4755
4756 for(i = 0; i < 32; i++) {
4757 env->active_tc.gpr[i] = regs->regs[i];
4758 }
4759 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4760 if (regs->cp0_epc & 1) {
4761 env->hflags |= MIPS_HFLAG_M16;
4762 }
4763 if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
4764 ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
4765 if ((env->active_fpu.fcr31_rw_bitmask &
4766 (1 << FCR31_NAN2008)) == 0) {
4767 fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n");
4768 exit(1);
4769 }
4770 if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
4771 env->active_fpu.fcr31 |= (1 << FCR31_NAN2008);
4772 } else {
4773 env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
4774 }
4775 restore_snan_bit_mode(env);
4776 }
4777 }
4778 #elif defined(TARGET_NIOS2)
4779 {
4780 env->regs[0] = 0;
4781 env->regs[1] = regs->r1;
4782 env->regs[2] = regs->r2;
4783 env->regs[3] = regs->r3;
4784 env->regs[4] = regs->r4;
4785 env->regs[5] = regs->r5;
4786 env->regs[6] = regs->r6;
4787 env->regs[7] = regs->r7;
4788 env->regs[8] = regs->r8;
4789 env->regs[9] = regs->r9;
4790 env->regs[10] = regs->r10;
4791 env->regs[11] = regs->r11;
4792 env->regs[12] = regs->r12;
4793 env->regs[13] = regs->r13;
4794 env->regs[14] = regs->r14;
4795 env->regs[15] = regs->r15;
4796 /* TODO: unsigned long orig_r2; */
4797 env->regs[R_RA] = regs->ra;
4798 env->regs[R_FP] = regs->fp;
4799 env->regs[R_SP] = regs->sp;
4800 env->regs[R_GP] = regs->gp;
4801 env->regs[CR_ESTATUS] = regs->estatus;
4802 env->regs[R_EA] = regs->ea;
4803 /* TODO: unsigned long orig_r7; */
4804
4805 /* Emulate eret when starting thread. */
4806 env->regs[R_PC] = regs->ea;
4807 }
4808 #elif defined(TARGET_OPENRISC)
4809 {
4810 int i;
4811
4812 for (i = 0; i < 32; i++) {
4813 cpu_set_gpr(env, i, regs->gpr[i]);
4814 }
4815 env->pc = regs->pc;
4816 cpu_set_sr(env, regs->sr);
4817 }
4818 #elif defined(TARGET_SH4)
4819 {
4820 int i;
4821
4822 for(i = 0; i < 16; i++) {
4823 env->gregs[i] = regs->regs[i];
4824 }
4825 env->pc = regs->pc;
4826 }
4827 #elif defined(TARGET_ALPHA)
4828 {
4829 int i;
4830
4831 for(i = 0; i < 28; i++) {
4832 env->ir[i] = ((abi_ulong *)regs)[i];
4833 }
4834 env->ir[IR_SP] = regs->usp;
4835 env->pc = regs->pc;
4836 }
4837 #elif defined(TARGET_CRIS)
4838 {
4839 env->regs[0] = regs->r0;
4840 env->regs[1] = regs->r1;
4841 env->regs[2] = regs->r2;
4842 env->regs[3] = regs->r3;
4843 env->regs[4] = regs->r4;
4844 env->regs[5] = regs->r5;
4845 env->regs[6] = regs->r6;
4846 env->regs[7] = regs->r7;
4847 env->regs[8] = regs->r8;
4848 env->regs[9] = regs->r9;
4849 env->regs[10] = regs->r10;
4850 env->regs[11] = regs->r11;
4851 env->regs[12] = regs->r12;
4852 env->regs[13] = regs->r13;
4853 env->regs[14] = info->start_stack;
4854 env->regs[15] = regs->acr;
4855 env->pc = regs->erp;
4856 }
4857 #elif defined(TARGET_S390X)
4858 {
4859 int i;
4860 for (i = 0; i < 16; i++) {
4861 env->regs[i] = regs->gprs[i];
4862 }
4863 env->psw.mask = regs->psw.mask;
4864 env->psw.addr = regs->psw.addr;
4865 }
4866 #elif defined(TARGET_TILEGX)
4867 {
4868 int i;
4869 for (i = 0; i < TILEGX_R_COUNT; i++) {
4870 env->regs[i] = regs->regs[i];
4871 }
4872 for (i = 0; i < TILEGX_SPR_COUNT; i++) {
4873 env->spregs[i] = 0;
4874 }
4875 env->pc = regs->pc;
4876 }
4877 #elif defined(TARGET_HPPA)
4878 {
4879 int i;
4880 for (i = 1; i < 32; i++) {
4881 env->gr[i] = regs->gr[i];
4882 }
4883 env->iaoq_f = regs->iaoq[0];
4884 env->iaoq_b = regs->iaoq[1];
4885 }
4886 #else
4887 #error unsupported target CPU
4888 #endif
4889
4890 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4891 ts->stack_base = info->start_stack;
4892 ts->heap_base = info->brk;
4893 /* This will be filled in on the first SYS_HEAPINFO call. */
4894 ts->heap_limit = 0;
4895 #endif
4896
4897 if (gdbstub_port) {
4898 if (gdbserver_start(gdbstub_port) < 0) {
4899 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4900 gdbstub_port);
4901 exit(EXIT_FAILURE);
4902 }
4903 gdb_handlesig(cpu, 0);
4904 }
4905 cpu_loop(env);
4906 /* never exits */
4907 return 0;
4908 }
AR7 emulation for QEMU