hw/arm/stellaris.c

   1 /*
   2  * Luminary Micro Stellaris peripherals
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qapi/error.h"
  12 #include "hw/sysbus.h"
  13 #include "hw/ssi/ssi.h"
  14 #include "hw/arm/arm.h"
  15 #include "hw/devices.h"
  16 #include "qemu/timer.h"
  17 #include "hw/i2c/i2c.h"
  18 #include "net/net.h"
  19 #include "hw/boards.h"
  20 #include "qemu/log.h"
  21 #include "exec/address-spaces.h"
  22 #include "sysemu/sysemu.h"
  23 #include "hw/char/pl011.h"
  24 #include "hw/misc/unimp.h"
  25
  26 #define GPIO_A 0
  27 #define GPIO_B 1
  28 #define GPIO_C 2
  29 #define GPIO_D 3
  30 #define GPIO_E 4
  31 #define GPIO_F 5
  32 #define GPIO_G 6
  33
  34 #define BP_OLED_I2C  0x01
  35 #define BP_OLED_SSI  0x02
  36 #define BP_GAMEPAD   0x04
  37
  38 #define NUM_IRQ_LINES 64
  39
  40 typedef const struct {
  41     const char *name;
  42     uint32_t did0;
  43     uint32_t did1;
  44     uint32_t dc0;
  45     uint32_t dc1;
  46     uint32_t dc2;
  47     uint32_t dc3;
  48     uint32_t dc4;
  49     uint32_t peripherals;
  50 } stellaris_board_info;
  51
  52 /* General purpose timer module.  */
  53
  54 #define TYPE_STELLARIS_GPTM "stellaris-gptm"
  55 #define STELLARIS_GPTM(obj) \
  56     OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM)
  57
  58 typedef struct gptm_state {
  59     SysBusDevice parent_obj;
  60
  61     MemoryRegion iomem;
  62     uint32_t config;
  63     uint32_t mode[2];
  64     uint32_t control;
  65     uint32_t state;
  66     uint32_t mask;
  67     uint32_t load[2];
  68     uint32_t match[2];
  69     uint32_t prescale[2];
  70     uint32_t match_prescale[2];
  71     uint32_t rtc;
  72     int64_t tick[2];
  73     struct gptm_state *opaque[2];
  74     QEMUTimer *timer[2];
  75     /* The timers have an alternate output used to trigger the ADC.  */
  76     qemu_irq trigger;
  77     qemu_irq irq;
  78 } gptm_state;
  79
  80 static void gptm_update_irq(gptm_state *s)
  81 {
  82     int level;
  83     level = (s->state & s->mask) != 0;
  84     qemu_set_irq(s->irq, level);
  85 }
  86
  87 static void gptm_stop(gptm_state *s, int n)
  88 {
  89     timer_del(s->timer[n]);
  90 }
  91
  92 static void gptm_reload(gptm_state *s, int n, int reset)
  93 {
  94     int64_t tick;
  95     if (reset)
  96         tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  97     else
  98         tick = s->tick[n];
  99
 100     if (s->config == 0) {
 101         /* 32-bit CountDown.  */
 102         uint32_t count;
 103         count = s->load[0] | (s->load[1] << 16);
 104         tick += (int64_t)count * system_clock_scale;
 105     } else if (s->config == 1) {
 106         /* 32-bit RTC.  1Hz tick.  */
 107         tick += NANOSECONDS_PER_SECOND;
 108     } else if (s->mode[n] == 0xa) {
 109         /* PWM mode.  Not implemented.  */
 110     } else {
 111         qemu_log_mask(LOG_UNIMP,
 112                       "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
 113                       s->mode[n]);
 114         return;
 115     }
 116     s->tick[n] = tick;
 117     timer_mod(s->timer[n], tick);
 118 }
 119
 120 static void gptm_tick(void *opaque)
 121 {
 122     gptm_state **p = (gptm_state **)opaque;
 123     gptm_state *s;
 124     int n;
 125
 126     s = *p;
 127     n = p - s->opaque;
 128     if (s->config == 0) {
 129         s->state |= 1;
 130         if ((s->control & 0x20)) {
 131             /* Output trigger.  */
 132             qemu_irq_pulse(s->trigger);
 133         }
 134         if (s->mode[0] & 1) {
 135             /* One-shot.  */
 136             s->control &= ~1;
 137         } else {
 138             /* Periodic.  */
 139             gptm_reload(s, 0, 0);
 140         }
 141     } else if (s->config == 1) {
 142         /* RTC.  */
 143         uint32_t match;
 144         s->rtc++;
 145         match = s->match[0] | (s->match[1] << 16);
 146         if (s->rtc > match)
 147             s->rtc = 0;
 148         if (s->rtc == 0) {
 149             s->state |= 8;
 150         }
 151         gptm_reload(s, 0, 0);
 152     } else if (s->mode[n] == 0xa) {
 153         /* PWM mode.  Not implemented.  */
 154     } else {
 155         qemu_log_mask(LOG_UNIMP,
 156                       "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
 157                       s->mode[n]);
 158     }
 159     gptm_update_irq(s);
 160 }
 161
 162 static uint64_t gptm_read(void *opaque, hwaddr offset,
 163                           unsigned size)
 164 {
 165     gptm_state *s = (gptm_state *)opaque;
 166
 167     switch (offset) {
 168     case 0x00: /* CFG */
 169         return s->config;
 170     case 0x04: /* TAMR */
 171         return s->mode[0];
 172     case 0x08: /* TBMR */
 173         return s->mode[1];
 174     case 0x0c: /* CTL */
 175         return s->control;
 176     case 0x18: /* IMR */
 177         return s->mask;
 178     case 0x1c: /* RIS */
 179         return s->state;
 180     case 0x20: /* MIS */
 181         return s->state & s->mask;
 182     case 0x24: /* CR */
 183         return 0;
 184     case 0x28: /* TAILR */
 185         return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
 186     case 0x2c: /* TBILR */
 187         return s->load[1];
 188     case 0x30: /* TAMARCHR */
 189         return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
 190     case 0x34: /* TBMATCHR */
 191         return s->match[1];
 192     case 0x38: /* TAPR */
 193         return s->prescale[0];
 194     case 0x3c: /* TBPR */
 195         return s->prescale[1];
 196     case 0x40: /* TAPMR */
 197         return s->match_prescale[0];
 198     case 0x44: /* TBPMR */
 199         return s->match_prescale[1];
 200     case 0x48: /* TAR */
 201         if (s->config == 1) {
 202             return s->rtc;
 203         }
 204         qemu_log_mask(LOG_UNIMP,
 205                       "GPTM: read of TAR but timer read not supported");
 206         return 0;
 207     case 0x4c: /* TBR */
 208         qemu_log_mask(LOG_UNIMP,
 209                       "GPTM: read of TBR but timer read not supported");
 210         return 0;
 211     default:
 212         qemu_log_mask(LOG_GUEST_ERROR,
 213                       "GPTM: read at bad offset 0x%x\n", (int)offset);
 214         return 0;
 215     }
 216 }
 217
 218 static void gptm_write(void *opaque, hwaddr offset,
 219                        uint64_t value, unsigned size)
 220 {
 221     gptm_state *s = (gptm_state *)opaque;
 222     uint32_t oldval;
 223
 224     /* The timers should be disabled before changing the configuration.
 225        We take advantage of this and defer everything until the timer
 226        is enabled.  */
 227     switch (offset) {
 228     case 0x00: /* CFG */
 229         s->config = value;
 230         break;
 231     case 0x04: /* TAMR */
 232         s->mode[0] = value;
 233         break;
 234     case 0x08: /* TBMR */
 235         s->mode[1] = value;
 236         break;
 237     case 0x0c: /* CTL */
 238         oldval = s->control;
 239         s->control = value;
 240         /* TODO: Implement pause.  */
 241         if ((oldval ^ value) & 1) {
 242             if (value & 1) {
 243                 gptm_reload(s, 0, 1);
 244             } else {
 245                 gptm_stop(s, 0);
 246             }
 247         }
 248         if (((oldval ^ value) & 0x100) && s->config >= 4) {
 249             if (value & 0x100) {
 250                 gptm_reload(s, 1, 1);
 251             } else {
 252                 gptm_stop(s, 1);
 253             }
 254         }
 255         break;
 256     case 0x18: /* IMR */
 257         s->mask = value & 0x77;
 258         gptm_update_irq(s);
 259         break;
 260     case 0x24: /* CR */
 261         s->state &= ~value;
 262         break;
 263     case 0x28: /* TAILR */
 264         s->load[0] = value & 0xffff;
 265         if (s->config < 4) {
 266             s->load[1] = value >> 16;
 267         }
 268         break;
 269     case 0x2c: /* TBILR */
 270         s->load[1] = value & 0xffff;
 271         break;
 272     case 0x30: /* TAMARCHR */
 273         s->match[0] = value & 0xffff;
 274         if (s->config < 4) {
 275             s->match[1] = value >> 16;
 276         }
 277         break;
 278     case 0x34: /* TBMATCHR */
 279         s->match[1] = value >> 16;
 280         break;
 281     case 0x38: /* TAPR */
 282         s->prescale[0] = value;
 283         break;
 284     case 0x3c: /* TBPR */
 285         s->prescale[1] = value;
 286         break;
 287     case 0x40: /* TAPMR */
 288         s->match_prescale[0] = value;
 289         break;
 290     case 0x44: /* TBPMR */
 291         s->match_prescale[0] = value;
 292         break;
 293     default:
 294         qemu_log_mask(LOG_GUEST_ERROR,
 295                       "GPTM: read at bad offset 0x%x\n", (int)offset);
 296     }
 297     gptm_update_irq(s);
 298 }
 299
 300 static const MemoryRegionOps gptm_ops = {
 301     .read = gptm_read,
 302     .write = gptm_write,
 303     .endianness = DEVICE_NATIVE_ENDIAN,
 304 };
 305
 306 static const VMStateDescription vmstate_stellaris_gptm = {
 307     .name = "stellaris_gptm",
 308     .version_id = 1,
 309     .minimum_version_id = 1,
 310     .fields = (VMStateField[]) {
 311         VMSTATE_UINT32(config, gptm_state),
 312         VMSTATE_UINT32_ARRAY(mode, gptm_state, 2),
 313         VMSTATE_UINT32(control, gptm_state),
 314         VMSTATE_UINT32(state, gptm_state),
 315         VMSTATE_UINT32(mask, gptm_state),
 316         VMSTATE_UNUSED(8),
 317         VMSTATE_UINT32_ARRAY(load, gptm_state, 2),
 318         VMSTATE_UINT32_ARRAY(match, gptm_state, 2),
 319         VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2),
 320         VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2),
 321         VMSTATE_UINT32(rtc, gptm_state),
 322         VMSTATE_INT64_ARRAY(tick, gptm_state, 2),
 323         VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2),
 324         VMSTATE_END_OF_LIST()
 325     }
 326 };
 327
 328 static void stellaris_gptm_init(Object *obj)
 329 {
 330     DeviceState *dev = DEVICE(obj);
 331     gptm_state *s = STELLARIS_GPTM(obj);
 332     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 333
 334     sysbus_init_irq(sbd, &s->irq);
 335     qdev_init_gpio_out(dev, &s->trigger, 1);
 336
 337     memory_region_init_io(&s->iomem, obj, &gptm_ops, s,
 338                           "gptm", 0x1000);
 339     sysbus_init_mmio(sbd, &s->iomem);
 340
 341     s->opaque[0] = s->opaque[1] = s;
 342     s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]);
 343     s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]);
 344 }
 345
 346
 347 /* System controller.  */
 348
 349 typedef struct {
 350     MemoryRegion iomem;
 351     uint32_t pborctl;
 352     uint32_t ldopctl;
 353     uint32_t int_status;
 354     uint32_t int_mask;
 355     uint32_t resc;
 356     uint32_t rcc;
 357     uint32_t rcc2;
 358     uint32_t rcgc[3];
 359     uint32_t scgc[3];
 360     uint32_t dcgc[3];
 361     uint32_t clkvclr;
 362     uint32_t ldoarst;
 363     uint32_t user0;
 364     uint32_t user1;
 365     qemu_irq irq;
 366     stellaris_board_info *board;
 367 } ssys_state;
 368
 369 static void ssys_update(ssys_state *s)
 370 {
 371   qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
 372 }
 373
 374 static uint32_t pllcfg_sandstorm[16] = {
 375     0x31c0, /* 1 Mhz */
 376     0x1ae0, /* 1.8432 Mhz */
 377     0x18c0, /* 2 Mhz */
 378     0xd573, /* 2.4576 Mhz */
 379     0x37a6, /* 3.57954 Mhz */
 380     0x1ae2, /* 3.6864 Mhz */
 381     0x0c40, /* 4 Mhz */
 382     0x98bc, /* 4.906 Mhz */
 383     0x935b, /* 4.9152 Mhz */
 384     0x09c0, /* 5 Mhz */
 385     0x4dee, /* 5.12 Mhz */
 386     0x0c41, /* 6 Mhz */
 387     0x75db, /* 6.144 Mhz */
 388     0x1ae6, /* 7.3728 Mhz */
 389     0x0600, /* 8 Mhz */
 390     0x585b /* 8.192 Mhz */
 391 };
 392
 393 static uint32_t pllcfg_fury[16] = {
 394     0x3200, /* 1 Mhz */
 395     0x1b20, /* 1.8432 Mhz */
 396     0x1900, /* 2 Mhz */
 397     0xf42b, /* 2.4576 Mhz */
 398     0x37e3, /* 3.57954 Mhz */
 399     0x1b21, /* 3.6864 Mhz */
 400     0x0c80, /* 4 Mhz */
 401     0x98ee, /* 4.906 Mhz */
 402     0xd5b4, /* 4.9152 Mhz */
 403     0x0a00, /* 5 Mhz */
 404     0x4e27, /* 5.12 Mhz */
 405     0x1902, /* 6 Mhz */
 406     0xec1c, /* 6.144 Mhz */
 407     0x1b23, /* 7.3728 Mhz */
 408     0x0640, /* 8 Mhz */
 409     0xb11c /* 8.192 Mhz */
 410 };
 411
 412 #define DID0_VER_MASK        0x70000000
 413 #define DID0_VER_0           0x00000000
 414 #define DID0_VER_1           0x10000000
 415
 416 #define DID0_CLASS_MASK      0x00FF0000
 417 #define DID0_CLASS_SANDSTORM 0x00000000
 418 #define DID0_CLASS_FURY      0x00010000
 419
 420 static int ssys_board_class(const ssys_state *s)
 421 {
 422     uint32_t did0 = s->board->did0;
 423     switch (did0 & DID0_VER_MASK) {
 424     case DID0_VER_0:
 425         return DID0_CLASS_SANDSTORM;
 426     case DID0_VER_1:
 427         switch (did0 & DID0_CLASS_MASK) {
 428         case DID0_CLASS_SANDSTORM:
 429         case DID0_CLASS_FURY:
 430             return did0 & DID0_CLASS_MASK;
 431         }
 432         /* for unknown classes, fall through */
 433     default:
 434         /* This can only happen if the hardwired constant did0 value
 435          * in this board's stellaris_board_info struct is wrong.
 436          */
 437         g_assert_not_reached();
 438     }
 439 }
 440
 441 static uint64_t ssys_read(void *opaque, hwaddr offset,
 442                           unsigned size)
 443 {
 444     ssys_state *s = (ssys_state *)opaque;
 445
 446     switch (offset) {
 447     case 0x000: /* DID0 */
 448         return s->board->did0;
 449     case 0x004: /* DID1 */
 450         return s->board->did1;
 451     case 0x008: /* DC0 */
 452         return s->board->dc0;
 453     case 0x010: /* DC1 */
 454         return s->board->dc1;
 455     case 0x014: /* DC2 */
 456         return s->board->dc2;
 457     case 0x018: /* DC3 */
 458         return s->board->dc3;
 459     case 0x01c: /* DC4 */
 460         return s->board->dc4;
 461     case 0x030: /* PBORCTL */
 462         return s->pborctl;
 463     case 0x034: /* LDOPCTL */
 464         return s->ldopctl;
 465     case 0x040: /* SRCR0 */
 466         return 0;
 467     case 0x044: /* SRCR1 */
 468         return 0;
 469     case 0x048: /* SRCR2 */
 470         return 0;
 471     case 0x050: /* RIS */
 472         return s->int_status;
 473     case 0x054: /* IMC */
 474         return s->int_mask;
 475     case 0x058: /* MISC */
 476         return s->int_status & s->int_mask;
 477     case 0x05c: /* RESC */
 478         return s->resc;
 479     case 0x060: /* RCC */
 480         return s->rcc;
 481     case 0x064: /* PLLCFG */
 482         {
 483             int xtal;
 484             xtal = (s->rcc >> 6) & 0xf;
 485             switch (ssys_board_class(s)) {
 486             case DID0_CLASS_FURY:
 487                 return pllcfg_fury[xtal];
 488             case DID0_CLASS_SANDSTORM:
 489                 return pllcfg_sandstorm[xtal];
 490             default:
 491                 g_assert_not_reached();
 492             }
 493         }
 494     case 0x070: /* RCC2 */
 495         return s->rcc2;
 496     case 0x100: /* RCGC0 */
 497         return s->rcgc[0];
 498     case 0x104: /* RCGC1 */
 499         return s->rcgc[1];
 500     case 0x108: /* RCGC2 */
 501         return s->rcgc[2];
 502     case 0x110: /* SCGC0 */
 503         return s->scgc[0];
 504     case 0x114: /* SCGC1 */
 505         return s->scgc[1];
 506     case 0x118: /* SCGC2 */
 507         return s->scgc[2];
 508     case 0x120: /* DCGC0 */
 509         return s->dcgc[0];
 510     case 0x124: /* DCGC1 */
 511         return s->dcgc[1];
 512     case 0x128: /* DCGC2 */
 513         return s->dcgc[2];
 514     case 0x150: /* CLKVCLR */
 515         return s->clkvclr;
 516     case 0x160: /* LDOARST */
 517         return s->ldoarst;
 518     case 0x1e0: /* USER0 */
 519         return s->user0;
 520     case 0x1e4: /* USER1 */
 521         return s->user1;
 522     default:
 523         qemu_log_mask(LOG_GUEST_ERROR,
 524                       "SSYS: read at bad offset 0x%x\n", (int)offset);
 525         return 0;
 526     }
 527 }
 528
 529 static bool ssys_use_rcc2(ssys_state *s)
 530 {
 531     return (s->rcc2 >> 31) & 0x1;
 532 }
 533
 534 /*
 535  * Caculate the sys. clock period in ms.
 536  */
 537 static void ssys_calculate_system_clock(ssys_state *s)
 538 {
 539     if (ssys_use_rcc2(s)) {
 540         system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
 541     } else {
 542         system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
 543     }
 544 }
 545
 546 static void ssys_write(void *opaque, hwaddr offset,
 547                        uint64_t value, unsigned size)
 548 {
 549     ssys_state *s = (ssys_state *)opaque;
 550
 551     switch (offset) {
 552     case 0x030: /* PBORCTL */
 553         s->pborctl = value & 0xffff;
 554         break;
 555     case 0x034: /* LDOPCTL */
 556         s->ldopctl = value & 0x1f;
 557         break;
 558     case 0x040: /* SRCR0 */
 559     case 0x044: /* SRCR1 */
 560     case 0x048: /* SRCR2 */
 561         fprintf(stderr, "Peripheral reset not implemented\n");
 562         break;
 563     case 0x054: /* IMC */
 564         s->int_mask = value & 0x7f;
 565         break;
 566     case 0x058: /* MISC */
 567         s->int_status &= ~value;
 568         break;
 569     case 0x05c: /* RESC */
 570         s->resc = value & 0x3f;
 571         break;
 572     case 0x060: /* RCC */
 573         if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 574             /* PLL enable.  */
 575             s->int_status |= (1 << 6);
 576         }
 577         s->rcc = value;
 578         ssys_calculate_system_clock(s);
 579         break;
 580     case 0x070: /* RCC2 */
 581         if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 582             break;
 583         }
 584
 585         if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 586             /* PLL enable.  */
 587             s->int_status |= (1 << 6);
 588         }
 589         s->rcc2 = value;
 590         ssys_calculate_system_clock(s);
 591         break;
 592     case 0x100: /* RCGC0 */
 593         s->rcgc[0] = value;
 594         break;
 595     case 0x104: /* RCGC1 */
 596         s->rcgc[1] = value;
 597         break;
 598     case 0x108: /* RCGC2 */
 599         s->rcgc[2] = value;
 600         break;
 601     case 0x110: /* SCGC0 */
 602         s->scgc[0] = value;
 603         break;
 604     case 0x114: /* SCGC1 */
 605         s->scgc[1] = value;
 606         break;
 607     case 0x118: /* SCGC2 */
 608         s->scgc[2] = value;
 609         break;
 610     case 0x120: /* DCGC0 */
 611         s->dcgc[0] = value;
 612         break;
 613     case 0x124: /* DCGC1 */
 614         s->dcgc[1] = value;
 615         break;
 616     case 0x128: /* DCGC2 */
 617         s->dcgc[2] = value;
 618         break;
 619     case 0x150: /* CLKVCLR */
 620         s->clkvclr = value;
 621         break;
 622     case 0x160: /* LDOARST */
 623         s->ldoarst = value;
 624         break;
 625     default:
 626         qemu_log_mask(LOG_GUEST_ERROR,
 627                       "SSYS: write at bad offset 0x%x\n", (int)offset);
 628     }
 629     ssys_update(s);
 630 }
 631
 632 static const MemoryRegionOps ssys_ops = {
 633     .read = ssys_read,
 634     .write = ssys_write,
 635     .endianness = DEVICE_NATIVE_ENDIAN,
 636 };
 637
 638 static void ssys_reset(void *opaque)
 639 {
 640     ssys_state *s = (ssys_state *)opaque;
 641
 642     s->pborctl = 0x7ffd;
 643     s->rcc = 0x078e3ac0;
 644
 645     if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 646         s->rcc2 = 0;
 647     } else {
 648         s->rcc2 = 0x07802810;
 649     }
 650     s->rcgc[0] = 1;
 651     s->scgc[0] = 1;
 652     s->dcgc[0] = 1;
 653     ssys_calculate_system_clock(s);
 654 }
 655
 656 static int stellaris_sys_post_load(void *opaque, int version_id)
 657 {
 658     ssys_state *s = opaque;
 659
 660     ssys_calculate_system_clock(s);
 661
 662     return 0;
 663 }
 664
 665 static const VMStateDescription vmstate_stellaris_sys = {
 666     .name = "stellaris_sys",
 667     .version_id = 2,
 668     .minimum_version_id = 1,
 669     .post_load = stellaris_sys_post_load,
 670     .fields = (VMStateField[]) {
 671         VMSTATE_UINT32(pborctl, ssys_state),
 672         VMSTATE_UINT32(ldopctl, ssys_state),
 673         VMSTATE_UINT32(int_mask, ssys_state),
 674         VMSTATE_UINT32(int_status, ssys_state),
 675         VMSTATE_UINT32(resc, ssys_state),
 676         VMSTATE_UINT32(rcc, ssys_state),
 677         VMSTATE_UINT32_V(rcc2, ssys_state, 2),
 678         VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
 679         VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
 680         VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
 681         VMSTATE_UINT32(clkvclr, ssys_state),
 682         VMSTATE_UINT32(ldoarst, ssys_state),
 683         VMSTATE_END_OF_LIST()
 684     }
 685 };
 686
 687 static int stellaris_sys_init(uint32_t base, qemu_irq irq,
 688                               stellaris_board_info * board,
 689                               uint8_t *macaddr)
 690 {
 691     ssys_state *s;
 692
 693     s = g_new0(ssys_state, 1);
 694     s->irq = irq;
 695     s->board = board;
 696     /* Most devices come preprogrammed with a MAC address in the user data. */
 697     s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);
 698     s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
 699
 700     memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000);
 701     memory_region_add_subregion(get_system_memory(), base, &s->iomem);
 702     ssys_reset(s);
 703     vmstate_register(NULL, -1, &vmstate_stellaris_sys, s);
 704     return 0;
 705 }
 706
 707
 708 /* I2C controller.  */
 709
 710 #define TYPE_STELLARIS_I2C "stellaris-i2c"
 711 #define STELLARIS_I2C(obj) \
 712     OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C)
 713
 714 typedef struct {
 715     SysBusDevice parent_obj;
 716
 717     I2CBus *bus;
 718     qemu_irq irq;
 719     MemoryRegion iomem;
 720     uint32_t msa;
 721     uint32_t mcs;
 722     uint32_t mdr;
 723     uint32_t mtpr;
 724     uint32_t mimr;
 725     uint32_t mris;
 726     uint32_t mcr;
 727 } stellaris_i2c_state;
 728
 729 #define STELLARIS_I2C_MCS_BUSY    0x01
 730 #define STELLARIS_I2C_MCS_ERROR   0x02
 731 #define STELLARIS_I2C_MCS_ADRACK  0x04
 732 #define STELLARIS_I2C_MCS_DATACK  0x08
 733 #define STELLARIS_I2C_MCS_ARBLST  0x10
 734 #define STELLARIS_I2C_MCS_IDLE    0x20
 735 #define STELLARIS_I2C_MCS_BUSBSY  0x40
 736
 737 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
 738                                    unsigned size)
 739 {
 740     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 741
 742     switch (offset) {
 743     case 0x00: /* MSA */
 744         return s->msa;
 745     case 0x04: /* MCS */
 746         /* We don't emulate timing, so the controller is never busy.  */
 747         return s->mcs | STELLARIS_I2C_MCS_IDLE;
 748     case 0x08: /* MDR */
 749         return s->mdr;
 750     case 0x0c: /* MTPR */
 751         return s->mtpr;
 752     case 0x10: /* MIMR */
 753         return s->mimr;
 754     case 0x14: /* MRIS */
 755         return s->mris;
 756     case 0x18: /* MMIS */
 757         return s->mris & s->mimr;
 758     case 0x20: /* MCR */
 759         return s->mcr;
 760     default:
 761         qemu_log_mask(LOG_GUEST_ERROR,
 762                       "stellaris_i2c: read at bad offset 0x%x\n", (int)offset);
 763         return 0;
 764     }
 765 }
 766
 767 static void stellaris_i2c_update(stellaris_i2c_state *s)
 768 {
 769     int level;
 770
 771     level = (s->mris & s->mimr) != 0;
 772     qemu_set_irq(s->irq, level);
 773 }
 774
 775 static void stellaris_i2c_write(void *opaque, hwaddr offset,
 776                                 uint64_t value, unsigned size)
 777 {
 778     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 779
 780     switch (offset) {
 781     case 0x00: /* MSA */
 782         s->msa = value & 0xff;
 783         break;
 784     case 0x04: /* MCS */
 785         if ((s->mcr & 0x10) == 0) {
 786             /* Disabled.  Do nothing.  */
 787             break;
 788         }
 789         /* Grab the bus if this is starting a transfer.  */
 790         if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 791             if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
 792                 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
 793             } else {
 794                 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
 795                 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
 796             }
 797         }
 798         /* If we don't have the bus then indicate an error.  */
 799         if (!i2c_bus_busy(s->bus)
 800                 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 801             s->mcs |= STELLARIS_I2C_MCS_ERROR;
 802             break;
 803         }
 804         s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
 805         if (value & 1) {
 806             /* Transfer a byte.  */
 807             /* TODO: Handle errors.  */
 808             if (s->msa & 1) {
 809                 /* Recv */
 810                 s->mdr = i2c_recv(s->bus) & 0xff;
 811             } else {
 812                 /* Send */
 813                 i2c_send(s->bus, s->mdr);
 814             }
 815             /* Raise an interrupt.  */
 816             s->mris |= 1;
 817         }
 818         if (value & 4) {
 819             /* Finish transfer.  */
 820             i2c_end_transfer(s->bus);
 821             s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
 822         }
 823         break;
 824     case 0x08: /* MDR */
 825         s->mdr = value & 0xff;
 826         break;
 827     case 0x0c: /* MTPR */
 828         s->mtpr = value & 0xff;
 829         break;
 830     case 0x10: /* MIMR */
 831         s->mimr = 1;
 832         break;
 833     case 0x1c: /* MICR */
 834         s->mris &= ~value;
 835         break;
 836     case 0x20: /* MCR */
 837         if (value & 1) {
 838             qemu_log_mask(LOG_UNIMP, "stellaris_i2c: Loopback not implemented");
 839         }
 840         if (value & 0x20) {
 841             qemu_log_mask(LOG_UNIMP,
 842                           "stellaris_i2c: Slave mode not implemented");
 843         }
 844         s->mcr = value & 0x31;
 845         break;
 846     default:
 847         qemu_log_mask(LOG_GUEST_ERROR,
 848                       "stellaris_i2c: write at bad offset 0x%x\n", (int)offset);
 849     }
 850     stellaris_i2c_update(s);
 851 }
 852
 853 static void stellaris_i2c_reset(stellaris_i2c_state *s)
 854 {
 855     if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
 856         i2c_end_transfer(s->bus);
 857
 858     s->msa = 0;
 859     s->mcs = 0;
 860     s->mdr = 0;
 861     s->mtpr = 1;
 862     s->mimr = 0;
 863     s->mris = 0;
 864     s->mcr = 0;
 865     stellaris_i2c_update(s);
 866 }
 867
 868 static const MemoryRegionOps stellaris_i2c_ops = {
 869     .read = stellaris_i2c_read,
 870     .write = stellaris_i2c_write,
 871     .endianness = DEVICE_NATIVE_ENDIAN,
 872 };
 873
 874 static const VMStateDescription vmstate_stellaris_i2c = {
 875     .name = "stellaris_i2c",
 876     .version_id = 1,
 877     .minimum_version_id = 1,
 878     .fields = (VMStateField[]) {
 879         VMSTATE_UINT32(msa, stellaris_i2c_state),
 880         VMSTATE_UINT32(mcs, stellaris_i2c_state),
 881         VMSTATE_UINT32(mdr, stellaris_i2c_state),
 882         VMSTATE_UINT32(mtpr, stellaris_i2c_state),
 883         VMSTATE_UINT32(mimr, stellaris_i2c_state),
 884         VMSTATE_UINT32(mris, stellaris_i2c_state),
 885         VMSTATE_UINT32(mcr, stellaris_i2c_state),
 886         VMSTATE_END_OF_LIST()
 887     }
 888 };
 889
 890 static void stellaris_i2c_init(Object *obj)
 891 {
 892     DeviceState *dev = DEVICE(obj);
 893     stellaris_i2c_state *s = STELLARIS_I2C(obj);
 894     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 895     I2CBus *bus;
 896
 897     sysbus_init_irq(sbd, &s->irq);
 898     bus = i2c_init_bus(dev, "i2c");
 899     s->bus = bus;
 900
 901     memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
 902                           "i2c", 0x1000);
 903     sysbus_init_mmio(sbd, &s->iomem);
 904     /* ??? For now we only implement the master interface.  */
 905     stellaris_i2c_reset(s);
 906 }
 907
 908 /* Analogue to Digital Converter.  This is only partially implemented,
 909    enough for applications that use a combined ADC and timer tick.  */
 910
 911 #define STELLARIS_ADC_EM_CONTROLLER 0
 912 #define STELLARIS_ADC_EM_COMP       1
 913 #define STELLARIS_ADC_EM_EXTERNAL   4
 914 #define STELLARIS_ADC_EM_TIMER      5
 915 #define STELLARIS_ADC_EM_PWM0       6
 916 #define STELLARIS_ADC_EM_PWM1       7
 917 #define STELLARIS_ADC_EM_PWM2       8
 918
 919 #define STELLARIS_ADC_FIFO_EMPTY    0x0100
 920 #define STELLARIS_ADC_FIFO_FULL     0x1000
 921
 922 #define TYPE_STELLARIS_ADC "stellaris-adc"
 923 #define STELLARIS_ADC(obj) \
 924     OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC)
 925
 926 typedef struct StellarisADCState {
 927     SysBusDevice parent_obj;
 928
 929     MemoryRegion iomem;
 930     uint32_t actss;
 931     uint32_t ris;
 932     uint32_t im;
 933     uint32_t emux;
 934     uint32_t ostat;
 935     uint32_t ustat;
 936     uint32_t sspri;
 937     uint32_t sac;
 938     struct {
 939         uint32_t state;
 940         uint32_t data[16];
 941     } fifo[4];
 942     uint32_t ssmux[4];
 943     uint32_t ssctl[4];
 944     uint32_t noise;
 945     qemu_irq irq[4];
 946 } stellaris_adc_state;
 947
 948 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
 949 {
 950     int tail;
 951
 952     tail = s->fifo[n].state & 0xf;
 953     if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
 954         s->ustat |= 1 << n;
 955     } else {
 956         s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
 957         s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
 958         if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
 959             s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
 960     }
 961     return s->fifo[n].data[tail];
 962 }
 963
 964 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
 965                                      uint32_t value)
 966 {
 967     int head;
 968
 969     /* TODO: Real hardware has limited size FIFOs.  We have a full 16 entry
 970        FIFO fir each sequencer.  */
 971     head = (s->fifo[n].state >> 4) & 0xf;
 972     if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
 973         s->ostat |= 1 << n;
 974         return;
 975     }
 976     s->fifo[n].data[head] = value;
 977     head = (head + 1) & 0xf;
 978     s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
 979     s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
 980     if ((s->fifo[n].state & 0xf) == head)
 981         s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
 982 }
 983
 984 static void stellaris_adc_update(stellaris_adc_state *s)
 985 {
 986     int level;
 987     int n;
 988
 989     for (n = 0; n < 4; n++) {
 990         level = (s->ris & s->im & (1 << n)) != 0;
 991         qemu_set_irq(s->irq[n], level);
 992     }
 993 }
 994
 995 static void stellaris_adc_trigger(void *opaque, int irq, int level)
 996 {
 997     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
 998     int n;
 999
1000     for (n = 0; n < 4; n++) {
1001         if ((s->actss & (1 << n)) == 0) {
1002             continue;
1003         }
1004
1005         if (((s->emux >> (n * 4)) & 0xff) != 5) {
1006             continue;
1007         }
1008
1009         /* Some applications use the ADC as a random number source, so introduce
1010            some variation into the signal.  */
1011         s->noise = s->noise * 314159 + 1;
1012         /* ??? actual inputs not implemented.  Return an arbitrary value.  */
1013         stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
1014         s->ris |= (1 << n);
1015         stellaris_adc_update(s);
1016     }
1017 }
1018
1019 static void stellaris_adc_reset(stellaris_adc_state *s)
1020 {
1021     int n;
1022
1023     for (n = 0; n < 4; n++) {
1024         s->ssmux[n] = 0;
1025         s->ssctl[n] = 0;
1026         s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
1027     }
1028 }
1029
1030 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
1031                                    unsigned size)
1032 {
1033     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1034
1035     /* TODO: Implement this.  */
1036     if (offset >= 0x40 && offset < 0xc0) {
1037         int n;
1038         n = (offset - 0x40) >> 5;
1039         switch (offset & 0x1f) {
1040         case 0x00: /* SSMUX */
1041             return s->ssmux[n];
1042         case 0x04: /* SSCTL */
1043             return s->ssctl[n];
1044         case 0x08: /* SSFIFO */
1045             return stellaris_adc_fifo_read(s, n);
1046         case 0x0c: /* SSFSTAT */
1047             return s->fifo[n].state;
1048         default:
1049             break;
1050         }
1051     }
1052     switch (offset) {
1053     case 0x00: /* ACTSS */
1054         return s->actss;
1055     case 0x04: /* RIS */
1056         return s->ris;
1057     case 0x08: /* IM */
1058         return s->im;
1059     case 0x0c: /* ISC */
1060         return s->ris & s->im;
1061     case 0x10: /* OSTAT */
1062         return s->ostat;
1063     case 0x14: /* EMUX */
1064         return s->emux;
1065     case 0x18: /* USTAT */
1066         return s->ustat;
1067     case 0x20: /* SSPRI */
1068         return s->sspri;
1069     case 0x30: /* SAC */
1070         return s->sac;
1071     default:
1072         qemu_log_mask(LOG_GUEST_ERROR,
1073                       "stellaris_adc: read at bad offset 0x%x\n", (int)offset);
1074         return 0;
1075     }
1076 }
1077
1078 static void stellaris_adc_write(void *opaque, hwaddr offset,
1079                                 uint64_t value, unsigned size)
1080 {
1081     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1082
1083     /* TODO: Implement this.  */
1084     if (offset >= 0x40 && offset < 0xc0) {
1085         int n;
1086         n = (offset - 0x40) >> 5;
1087         switch (offset & 0x1f) {
1088         case 0x00: /* SSMUX */
1089             s->ssmux[n] = value & 0x33333333;
1090             return;
1091         case 0x04: /* SSCTL */
1092             if (value != 6) {
1093                 qemu_log_mask(LOG_UNIMP,
1094                               "ADC: Unimplemented sequence %" PRIx64 "\n",
1095                               value);
1096             }
1097             s->ssctl[n] = value;
1098             return;
1099         default:
1100             break;
1101         }
1102     }
1103     switch (offset) {
1104     case 0x00: /* ACTSS */
1105         s->actss = value & 0xf;
1106         break;
1107     case 0x08: /* IM */
1108         s->im = value;
1109         break;
1110     case 0x0c: /* ISC */
1111         s->ris &= ~value;
1112         break;
1113     case 0x10: /* OSTAT */
1114         s->ostat &= ~value;
1115         break;
1116     case 0x14: /* EMUX */
1117         s->emux = value;
1118         break;
1119     case 0x18: /* USTAT */
1120         s->ustat &= ~value;
1121         break;
1122     case 0x20: /* SSPRI */
1123         s->sspri = value;
1124         break;
1125     case 0x28: /* PSSI */
1126         qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented");
1127         break;
1128     case 0x30: /* SAC */
1129         s->sac = value;
1130         break;
1131     default:
1132         qemu_log_mask(LOG_GUEST_ERROR,
1133                       "stellaris_adc: write at bad offset 0x%x\n", (int)offset);
1134     }
1135     stellaris_adc_update(s);
1136 }
1137
1138 static const MemoryRegionOps stellaris_adc_ops = {
1139     .read = stellaris_adc_read,
1140     .write = stellaris_adc_write,
1141     .endianness = DEVICE_NATIVE_ENDIAN,
1142 };
1143
1144 static const VMStateDescription vmstate_stellaris_adc = {
1145     .name = "stellaris_adc",
1146     .version_id = 1,
1147     .minimum_version_id = 1,
1148     .fields = (VMStateField[]) {
1149         VMSTATE_UINT32(actss, stellaris_adc_state),
1150         VMSTATE_UINT32(ris, stellaris_adc_state),
1151         VMSTATE_UINT32(im, stellaris_adc_state),
1152         VMSTATE_UINT32(emux, stellaris_adc_state),
1153         VMSTATE_UINT32(ostat, stellaris_adc_state),
1154         VMSTATE_UINT32(ustat, stellaris_adc_state),
1155         VMSTATE_UINT32(sspri, stellaris_adc_state),
1156         VMSTATE_UINT32(sac, stellaris_adc_state),
1157         VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
1158         VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
1159         VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
1160         VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
1161         VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
1162         VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
1163         VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
1164         VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
1165         VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
1166         VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
1167         VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
1168         VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
1169         VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
1170         VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
1171         VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
1172         VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
1173         VMSTATE_UINT32(noise, stellaris_adc_state),
1174         VMSTATE_END_OF_LIST()
1175     }
1176 };
1177
1178 static void stellaris_adc_init(Object *obj)
1179 {
1180     DeviceState *dev = DEVICE(obj);
1181     stellaris_adc_state *s = STELLARIS_ADC(obj);
1182     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1183     int n;
1184
1185     for (n = 0; n < 4; n++) {
1186         sysbus_init_irq(sbd, &s->irq[n]);
1187     }
1188
1189     memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
1190                           "adc", 0x1000);
1191     sysbus_init_mmio(sbd, &s->iomem);
1192     stellaris_adc_reset(s);
1193     qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
1194 }
1195
1196 static
1197 void do_sys_reset(void *opaque, int n, int level)
1198 {
1199     if (level) {
1200         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
1201     }
1202 }
1203
1204 /* Board init.  */
1205 static stellaris_board_info stellaris_boards[] = {
1206   { "LM3S811EVB",
1207     0,
1208     0x0032000e,
1209     0x001f001f, /* dc0 */
1210     0x001132bf,
1211     0x01071013,
1212     0x3f0f01ff,
1213     0x0000001f,
1214     BP_OLED_I2C
1215   },
1216   { "LM3S6965EVB",
1217     0x10010002,
1218     0x1073402e,
1219     0x00ff007f, /* dc0 */
1220     0x001133ff,
1221     0x030f5317,
1222     0x0f0f87ff,
1223     0x5000007f,
1224     BP_OLED_SSI | BP_GAMEPAD
1225   }
1226 };
1227
1228 static void stellaris_init(const char *kernel_filename, const char *cpu_model,
1229                            stellaris_board_info *board)
1230 {
1231     static const int uart_irq[] = {5, 6, 33, 34};
1232     static const int timer_irq[] = {19, 21, 23, 35};
1233     static const uint32_t gpio_addr[7] =
1234       { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1235         0x40024000, 0x40025000, 0x40026000};
1236     static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
1237
1238     /* Memory map of SoC devices, from
1239      * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
1240      * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
1241      *
1242      * 40000000 wdtimer (unimplemented)
1243      * 40002000 i2c (unimplemented)
1244      * 40004000 GPIO
1245      * 40005000 GPIO
1246      * 40006000 GPIO
1247      * 40007000 GPIO
1248      * 40008000 SSI
1249      * 4000c000 UART
1250      * 4000d000 UART
1251      * 4000e000 UART
1252      * 40020000 i2c
1253      * 40021000 i2c (unimplemented)
1254      * 40024000 GPIO
1255      * 40025000 GPIO
1256      * 40026000 GPIO
1257      * 40028000 PWM (unimplemented)
1258      * 4002c000 QEI (unimplemented)
1259      * 4002d000 QEI (unimplemented)
1260      * 40030000 gptimer
1261      * 40031000 gptimer
1262      * 40032000 gptimer
1263      * 40033000 gptimer
1264      * 40038000 ADC
1265      * 4003c000 analogue comparator (unimplemented)
1266      * 40048000 ethernet
1267      * 400fc000 hibernation module (unimplemented)
1268      * 400fd000 flash memory control (unimplemented)
1269      * 400fe000 system control
1270      */
1271
1272     DeviceState *gpio_dev[7], *nvic;
1273     qemu_irq gpio_in[7][8];
1274     qemu_irq gpio_out[7][8];
1275     qemu_irq adc;
1276     int sram_size;
1277     int flash_size;
1278     I2CBus *i2c;
1279     DeviceState *dev;
1280     int i;
1281     int j;
1282
1283     MemoryRegion *sram = g_new(MemoryRegion, 1);
1284     MemoryRegion *flash = g_new(MemoryRegion, 1);
1285     MemoryRegion *system_memory = get_system_memory();
1286
1287     flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
1288     sram_size = ((board->dc0 >> 18) + 1) * 1024;
1289
1290     /* Flash programming is done via the SCU, so pretend it is ROM.  */
1291     memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size,
1292                            &error_fatal);
1293     vmstate_register_ram_global(flash);
1294     memory_region_set_readonly(flash, true);
1295     memory_region_add_subregion(system_memory, 0, flash);
1296
1297     memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size,
1298                            &error_fatal);
1299     vmstate_register_ram_global(sram);
1300     memory_region_add_subregion(system_memory, 0x20000000, sram);
1301
1302     nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES,
1303                       kernel_filename, cpu_model);
1304
1305     qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0,
1306                                 qemu_allocate_irq(&do_sys_reset, NULL, 0));
1307
1308     if (board->dc1 & (1 << 16)) {
1309         dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
1310                                     qdev_get_gpio_in(nvic, 14),
1311                                     qdev_get_gpio_in(nvic, 15),
1312                                     qdev_get_gpio_in(nvic, 16),
1313                                     qdev_get_gpio_in(nvic, 17),
1314                                     NULL);
1315         adc = qdev_get_gpio_in(dev, 0);
1316     } else {
1317         adc = NULL;
1318     }
1319     for (i = 0; i < 4; i++) {
1320         if (board->dc2 & (0x10000 << i)) {
1321             dev = sysbus_create_simple(TYPE_STELLARIS_GPTM,
1322                                        0x40030000 + i * 0x1000,
1323                                        qdev_get_gpio_in(nvic, timer_irq[i]));
1324             /* TODO: This is incorrect, but we get away with it because
1325                the ADC output is only ever pulsed.  */
1326             qdev_connect_gpio_out(dev, 0, adc);
1327         }
1328     }
1329
1330     stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
1331                        board, nd_table[0].macaddr.a);
1332
1333     for (i = 0; i < 7; i++) {
1334         if (board->dc4 & (1 << i)) {
1335             gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
1336                                                qdev_get_gpio_in(nvic,
1337                                                                 gpio_irq[i]));
1338             for (j = 0; j < 8; j++) {
1339                 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
1340                 gpio_out[i][j] = NULL;
1341             }
1342         }
1343     }
1344
1345     if (board->dc2 & (1 << 12)) {
1346         dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000,
1347                                    qdev_get_gpio_in(nvic, 8));
1348         i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
1349         if (board->peripherals & BP_OLED_I2C) {
1350             i2c_create_slave(i2c, "ssd0303", 0x3d);
1351         }
1352     }
1353
1354     for (i = 0; i < 4; i++) {
1355         if (board->dc2 & (1 << i)) {
1356             pl011_luminary_create(0x4000c000 + i * 0x1000,
1357                                   qdev_get_gpio_in(nvic, uart_irq[i]),
1358                                   serial_hds[i]);
1359         }
1360     }
1361     if (board->dc2 & (1 << 4)) {
1362         dev = sysbus_create_simple("pl022", 0x40008000,
1363                                    qdev_get_gpio_in(nvic, 7));
1364         if (board->peripherals & BP_OLED_SSI) {
1365             void *bus;
1366             DeviceState *sddev;
1367             DeviceState *ssddev;
1368
1369             /* Some boards have both an OLED controller and SD card connected to
1370              * the same SSI port, with the SD card chip select connected to a
1371              * GPIO pin.  Technically the OLED chip select is connected to the
1372              * SSI Fss pin.  We do not bother emulating that as both devices
1373              * should never be selected simultaneously, and our OLED controller
1374              * ignores stray 0xff commands that occur when deselecting the SD
1375              * card.
1376              */
1377             bus = qdev_get_child_bus(dev, "ssi");
1378
1379             sddev = ssi_create_slave(bus, "ssi-sd");
1380             ssddev = ssi_create_slave(bus, "ssd0323");
1381             gpio_out[GPIO_D][0] = qemu_irq_split(
1382                     qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
1383                     qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
1384             gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
1385
1386             /* Make sure the select pin is high.  */
1387             qemu_irq_raise(gpio_out[GPIO_D][0]);
1388         }
1389     }
1390     if (board->dc4 & (1 << 28)) {
1391         DeviceState *enet;
1392
1393         qemu_check_nic_model(&nd_table[0], "stellaris");
1394
1395         enet = qdev_create(NULL, "stellaris_enet");
1396         qdev_set_nic_properties(enet, &nd_table[0]);
1397         qdev_init_nofail(enet);
1398         sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
1399         sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
1400     }
1401     if (board->peripherals & BP_GAMEPAD) {
1402         qemu_irq gpad_irq[5];
1403         static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1404
1405         gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
1406         gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
1407         gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
1408         gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
1409         gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
1410
1411         stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
1412     }
1413     for (i = 0; i < 7; i++) {
1414         if (board->dc4 & (1 << i)) {
1415             for (j = 0; j < 8; j++) {
1416                 if (gpio_out[i][j]) {
1417                     qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
1418                 }
1419             }
1420         }
1421     }
1422
1423     /* Add dummy regions for the devices we don't implement yet,
1424      * so guest accesses don't cause unlogged crashes.
1425      */
1426     create_unimplemented_device("wdtimer", 0x40000000, 0x1000);
1427     create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
1428     create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
1429     create_unimplemented_device("PWM", 0x40028000, 0x1000);
1430     create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
1431     create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
1432     create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
1433     create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
1434     create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
1435 }
1436
1437 /* FIXME: Figure out how to generate these from stellaris_boards.  */
1438 static void lm3s811evb_init(MachineState *machine)
1439 {
1440     const char *cpu_model = machine->cpu_model;
1441     const char *kernel_filename = machine->kernel_filename;
1442     stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]);
1443 }
1444
1445 static void lm3s6965evb_init(MachineState *machine)
1446 {
1447     const char *cpu_model = machine->cpu_model;
1448     const char *kernel_filename = machine->kernel_filename;
1449     stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]);
1450 }
1451
1452 static void lm3s811evb_class_init(ObjectClass *oc, void *data)
1453 {
1454     MachineClass *mc = MACHINE_CLASS(oc);
1455
1456     mc->desc = "Stellaris LM3S811EVB";
1457     mc->init = lm3s811evb_init;
1458 }
1459
1460 static const TypeInfo lm3s811evb_type = {
1461     .name = MACHINE_TYPE_NAME("lm3s811evb"),
1462     .parent = TYPE_MACHINE,
1463     .class_init = lm3s811evb_class_init,
1464 };
1465
1466 static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
1467 {
1468     MachineClass *mc = MACHINE_CLASS(oc);
1469
1470     mc->desc = "Stellaris LM3S6965EVB";
1471     mc->init = lm3s6965evb_init;
1472 }
1473
1474 static const TypeInfo lm3s6965evb_type = {
1475     .name = MACHINE_TYPE_NAME("lm3s6965evb"),
1476     .parent = TYPE_MACHINE,
1477     .class_init = lm3s6965evb_class_init,
1478 };
1479
1480 static void stellaris_machine_init(void)
1481 {
1482     type_register_static(&lm3s811evb_type);
1483     type_register_static(&lm3s6965evb_type);
1484 }
1485
1486 type_init(stellaris_machine_init)
1487
1488 static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
1489 {
1490     DeviceClass *dc = DEVICE_CLASS(klass);
1491
1492     dc->vmsd = &vmstate_stellaris_i2c;
1493 }
1494
1495 static const TypeInfo stellaris_i2c_info = {
1496     .name          = TYPE_STELLARIS_I2C,
1497     .parent        = TYPE_SYS_BUS_DEVICE,
1498     .instance_size = sizeof(stellaris_i2c_state),
1499     .instance_init = stellaris_i2c_init,
1500     .class_init    = stellaris_i2c_class_init,
1501 };
1502
1503 static void stellaris_gptm_class_init(ObjectClass *klass, void *data)
1504 {
1505     DeviceClass *dc = DEVICE_CLASS(klass);
1506
1507     dc->vmsd = &vmstate_stellaris_gptm;
1508 }
1509
1510 static const TypeInfo stellaris_gptm_info = {
1511     .name          = TYPE_STELLARIS_GPTM,
1512     .parent        = TYPE_SYS_BUS_DEVICE,
1513     .instance_size = sizeof(gptm_state),
1514     .instance_init = stellaris_gptm_init,
1515     .class_init    = stellaris_gptm_class_init,
1516 };
1517
1518 static void stellaris_adc_class_init(ObjectClass *klass, void *data)
1519 {
1520     DeviceClass *dc = DEVICE_CLASS(klass);
1521
1522     dc->vmsd = &vmstate_stellaris_adc;
1523 }
1524
1525 static const TypeInfo stellaris_adc_info = {
1526     .name          = TYPE_STELLARIS_ADC,
1527     .parent        = TYPE_SYS_BUS_DEVICE,
1528     .instance_size = sizeof(stellaris_adc_state),
1529     .instance_init = stellaris_adc_init,
1530     .class_init    = stellaris_adc_class_init,
1531 };
1532
1533 static void stellaris_register_types(void)
1534 {
1535     type_register_static(&stellaris_i2c_info);
1536     type_register_static(&stellaris_gptm_info);
1537     type_register_static(&stellaris_adc_info);
1538 }
1539
1540 type_init(stellaris_register_types)