hw/arm/stcpmu.h

   1 /* pmuregs.h
   2  *
   3  * Register definitions for the Simtec PMU.
   4  *
   5  * Copyright 2006 Simtec Electronics.
   6  */
   7
   8 #ifndef PMUREGS_H
   9 #define PMUREGS_H
  10
  11 /* Versions of the Simtec Power management interface. */
  12 /* Version 1.0 interfcae */
  13 #define STCPMU_V1_02             2
  14
  15 /* Version 1.2 interface never existed */
  16
  17 /* Version 1.3 interface */
  18 #define STCPMU_V1_30            30
  19 #define STCPMU_V1_31            31
  20 #define STCPMU_V1_32            32
  21 #define STCPMU_V1_33            33
  22 #define STCPMU_V1_34            34
  23
  24 #define STCPMU_VCURR STCPMU_V1_34 /**< Current revision of the PMU interface. */
  25
  26 /* IIC registers */
  27
  28 /* Version 1.20 regs */
  29 #define IICREG_IDENT            0       /**< PMU ident (SBPM) */
  30 #define IICREG_VER              1       /**< PMU version information. */
  31 #define IICREG_DDCEN            2       /**< Enables/disables the DDC_EN pin */
  32 #define IICREG_PWR              3       /**< Soft power switch */
  33 #define IICREG_RST              4       /**< Press the reset button */
  34 #define IICREG_GWO              5       /**< Global Wake On ... */
  35 #define IICREG_WOL              6       /**< Wake On LAN */
  36 #define IICREG_WOR              7       /**< Wake On Ring */
  37 #define IICREG_SND              8       /**< Play note */
  38 #define IICREG_UNQID            9       /**< Unique ID */
  39 #define IICREG_SLEEP            10      /**< Enter Sleep mode */
  40
  41 /* Version 1.30 regs */
  42 #define IICREG_IRQEN            5       /**< Non zero to enable irqs */
  43
  44 #define IICREG_STATUS           11      /**< (0x0b) status of last operation */
  45
  46 #define IICREG_GPIO_PRESENT     20      /**< (0x14) Pullup enables */
  47 #define IICREG_GPIO_PULLUP      21      /**< (0x15) Pullup enables */
  48 #define IICREG_GPIO_DDR         22      /**< (0x16) Direction, 1=out, 0=in */
  49 #define IICREG_GPIO_STATUS      23      /**< (0x17) GPIO current status (rd) */
  50 #define IICREG_GPIO_SET         23      /**< (0x17) GPIO output bit set */
  51 #define IICREG_GPIO_CLEAR       24      /**< (0x18) GPIO output bit clear */
  52 #define IICREG_GPIO_IRQSOURCE   25      /**< (0x19) Source IRQ mask */
  53 #define IICREG_GPIO_IRQEDGE     26      /**< (0x1a) IRQ Edge/Level select  */
  54 #define IICREG_GPIO_IRQPOLARITY 27      /**< (0x1b) IRQ polarity */
  55 #define IICREG_GPIO_IRQSTATUS   28      /**< (0x1c) IRQs pending, write clears*/
  56 #define IICREG_GPIO_IRQDELAY    29      /**< (0x1d) IRQ delay mask */
  57 #define IICREG_GPIO_DELAY       30      /**< (0x1e) delay time in deciseconds */
  58 #define IICREG_GPIO_IRQBOTHEDGE 31      /**< (0x1f) IRQs on either edge */
  59 #define IICREG_GPIO_IRQFIRST    32      /**< (0x20) First IRQ detected */
  60 #define IICREG_GPIO_IRQRAW      33      /**< (0x21) IRQ raw status */
  61
  62 #define IICREG_ADC_INFO         39      /**< Information about the ADC. */
  63 #define IICREG_ADC_PRESENT      40      /**< ADC presence indicators. */
  64 #define IICREG_ADC_IRQSOURCE    41      /**< ADC IRQ source enables. */
  65 #define IICREG_ADC_IRQSTATUS    42      /**< ADC IRQ status. */
  66 #define IICREG_ADC_POLARITY     43      /**< ADC IRQ polarity. */
  67 #define IICREG_ADC_0            44      /**< ADC 0 value. */
  68 #define IICREG_ADC_1            45      /**< ADC 1 value. */
  69 #define IICREG_ADC_2            46      /**< ADC 2 value. */
  70 #define IICREG_ADC_3            47      /**< ADC 3 value. */
  71 #define IICREG_ADC_4            48      /**< ADC 4 value. */
  72 #define IICREG_ADC_5            49      /**< ADC 5 value. */
  73 #define IICREG_ADC_6            50      /**< ADC 6 value. */
  74 #define IICREG_ADC_7            51      /**< ADC 7 value. */
  75 #define IICREG_ADC_0_THRESHOLD  52      /**< ADC 0 threshold. */
  76 #define IICREG_ADC_1_THRESHOLD  53      /**< ADC 1 threshold. */
  77 #define IICREG_ADC_2_THRESHOLD  54      /**< ADC 2 threshold. */
  78 #define IICREG_ADC_3_THRESHOLD  55      /**< ADC 3 threshold. */
  79 #define IICREG_ADC_4_THRESHOLD  56      /**< ADC 4 threshold. */
  80 #define IICREG_ADC_5_THRESHOLD  57      /**< ADC 5 threshold. */
  81 #define IICREG_ADC_6_THRESHOLD  58      /**< ADC 6 threshold. */
  82 #define IICREG_ADC_7_THRESHOLD  59      /**< ADC 7 threshold. */
  83
  84 /* Version 1.32 registers */
  85
  86 #define IICREG_HWINFO           12      /**< (0x0C) Hardware specific information. */
  87
  88 /* Version 1.33 registers */
  89 #define IICREG_IMPSPEC          13      /**< (0x0D) Implementation specific. */
  90
  91 /* Version 1.34 registers */
  92 #define IICREG_WDG_POR          64      /**< (0x40) Power-On / Reset watchdog. */
  93 #define IICREG_WDG_BUSBEAT      65      /**< (0x41) Bus heartbeat watchdog. */
  94
  95 /* DEBUG registers - only present in debug builds */
  96 #define IICREG_SCRATCH          128
  97
  98
  99 #define IICREG_EEBASE 0xC0
 100
 101 /* eeprom area */
 102 #define EEPROT 0x08     /* number of write once protected bytes */
 103 #define EELNGH 0x40
 104 #define IICREG_EE0   (IICREG_EEBASE + EEPROT) /* EEPROM location 0 (allowing for uniqueID) */
 105 #define IICREG_EEMAX ((IICREG_EE0 + (EELNGH - EEPROT))-1)
 106
 107 /* EEPROM config byte locations */
 108 #define EELOC_WOL (EEPROT + 0)
 109 #define EELOC_WOR (EEPROT + 1)
 110
 111 /* ident bytes */
 112 #define IICIDENT_0      0x53    /* S */
 113 #define IICIDENT_1      0x42    /* B */
 114 #define IICIDENT_2      0x50    /* P */
 115 #define IICIDENT_3      0x4d    /* M */
 116
 117
 118 /* Guard value for potentially hazardous operations (reset, sleep and power off) */
 119 #define IIC_GUARD 0x55
 120
 121 /* status codes - pmu status of last request */
 122 #define PMUSTATUS_OK            (0)
 123 #define PMUSTATUS_ERROR         (1)     /* general failed operation */
 124 #define PMUSTATUS_ACCESS        (2)     /* no writable register here */
 125 #define PMUSTATUS_REGISTER      (3)     /* no readable register here */
 126 #define PMUSTATUS_SHORT         (4)     /* not enough data for operation */
 127 #define PMUSTATUS_INVALID       (5)     /* guard invalid */
 128
 129 #endif