hw/arm/s3c24xx_iic.c

   1 /* hw/s3c24xx_iic.c
   2  *
   3  * Samsung S3C24XX i2c peripheral emulation
   4  *
   5  * Copyright 2006, 2007, 2008 Daniel Silverstone, Ben Dooks
   6  *  and Vincent Sanders
   7  *
   8  * Copyright 2010, 2013 Stefan Weil
   9  *
  10  * This file is under the terms of the GNU General Public License Version 2.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "cpu.h"
  15 #include "hw/hw.h"
  16 #include "exec/address-spaces.h" /* get_system_memory */
  17 #include "hw/i2c/i2c.h"
  18
  19 #include "s3c24xx.h"
  20
  21 /* i2c controller registers */
  22 #define S3C_IICCON  (0x00)
  23 #define S3C_IICSTAT (0x04)
  24 #define S3C_IICADD  (0x08)
  25 #define S3C_IICDS   (0x0C)
  26 #define S3C_IICLC   (0x10)
  27
  28 #define S3C_IICCON_ACKEN        (1<<7)
  29 #define S3C_IICCON_TXDIV_16     (0<<6)
  30 #define S3C_IICCON_TXDIV_512    (1<<6)
  31 #define S3C_IICCON_IRQEN        (1<<5)
  32 #define S3C_IICCON_IRQPEND      (1<<4)
  33 #define S3C_IICCON_SCALE(x)     ((x)&15)
  34 #define S3C_IICCON_SCALEMASK    (0xf)
  35
  36 #define S3C_IICSTAT_MASTER_RX   (2<<6)
  37 #define S3C_IICSTAT_MASTER_TX   (3<<6)
  38 #define S3C_IICSTAT_SLAVE_RX    (0<<6)
  39 #define S3C_IICSTAT_SLAVE_TX    (1<<6)
  40 #define S3C_IICSTAT_MODEMASK    (3<<6)
  41
  42 #define S3C_IICSTAT_START       (1<<5)
  43 #define S3C_IICSTAT_BUSBUSY     (1<<5)
  44 #define S3C_IICSTAT_TXRXEN      (1<<4)
  45 #define S3C_IICSTAT_ARBITR      (1<<3)
  46 #define S3C_IICSTAT_ASSLAVE     (1<<2)
  47 #define S3C_IICSTAT_ADDR0        (1<<1)
  48 #define S3C_IICSTAT_LASTBIT      (1<<0)
  49
  50 #define S3C_IICLC_SDA_DELAY0     (0 << 0)
  51 #define S3C_IICLC_SDA_DELAY5     (1 << 0)
  52 #define S3C_IICLC_SDA_DELAY10    (2 << 0)
  53 #define S3C_IICLC_SDA_DELAY15    (3 << 0)
  54 #define S3C_IICLC_SDA_DELAY_MASK (3 << 0)
  55
  56 #define S3C_IICLC_FILTER_ON      (1<<2)
  57
  58 /* IIC-bus serial interface */
  59 struct s3c24xx_i2c_state_s {
  60     MemoryRegion mmio;
  61     I2CBus *bus;
  62     qemu_irq irq;
  63
  64     uint8_t control;
  65     uint8_t status;
  66     uint8_t data;
  67     uint8_t addy;
  68     int busy;
  69     int newstart;
  70 };
  71
  72 static void s3c24xx_i2c_irq(struct s3c24xx_i2c_state_s *s)
  73 {
  74     s->control |= 1 << 4;
  75
  76     if (s->control & (1 << 5)) {
  77         qemu_irq_raise(s->irq);
  78     }
  79 }
  80
  81 static void s3c24xx_i2c_reset(struct s3c24xx_i2c_state_s *s)
  82 {
  83     s->control = 0x00;
  84     s->status = 0x00;
  85     s->busy = 0;
  86     s->newstart = 0;
  87 }
  88
  89
  90 static void s3c_master_work(void *opaque)
  91 {
  92     struct s3c24xx_i2c_state_s *s = opaque;
  93     int start = 0, stop = 0, ack = 1;
  94
  95     if (s->control & (1 << 4))                          /* Interrupt pending */
  96         return;
  97     if ((s->status & 0x90) != 0x90)                     /* Master */
  98         return;
  99
 100     stop = ~s->status & (1 << 5);
 101     if (s->newstart && s->status & (1 << 5)) {          /* START */
 102         s->busy = 1;
 103         start = 1;
 104     }
 105     s->newstart = 0;
 106
 107     if (!s->busy) {
 108         return;
 109     }
 110
 111     if (start) {
 112         ack = !i2c_start_transfer(s->bus, s->data >> 1, (~s->status >> 6) & 1);
 113     } else if (stop) {
 114         i2c_end_transfer(s->bus);
 115     } else if (s->status & (1 << 6)) {
 116         ack = !i2c_send(s->bus, s->data);
 117     } else {
 118         s->data = i2c_recv(s->bus);
 119
 120         if (!(s->control & (1 << 7)))                   /* ACK */
 121             i2c_nack(s->bus);
 122     }
 123
 124     if (!(s->status & (1 << 5))) {
 125         s->busy = 0;
 126         return;
 127     }
 128
 129     s->status &= ~1;
 130     s->status |= !ack;
 131
 132     if (!ack) {
 133         s->busy = 0;
 134     }
 135     s3c24xx_i2c_irq(s);
 136 }
 137
 138 static uint64_t s3c24xx_i2c_read(void *opaque, hwaddr addr,
 139                                  unsigned size)
 140 {
 141     struct s3c24xx_i2c_state_s *s = opaque;
 142
 143     switch (addr) {
 144     case S3C_IICCON:
 145         return s->control;
 146
 147     case S3C_IICSTAT:
 148         return s->status & ~(1 << 5);                   /* Busy signal */
 149
 150     case S3C_IICADD:
 151         return s->addy;
 152
 153     case S3C_IICDS:
 154         return s->data;
 155
 156     default:
 157         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
 158         break;
 159     }
 160     return 0;
 161 }
 162
 163 static void s3c24xx_i2c_write(void *opaque, hwaddr addr,
 164                               uint64_t value, unsigned size)
 165 {
 166     struct s3c24xx_i2c_state_s *s = opaque;
 167
 168     switch (addr) {
 169     case S3C_IICCON:
 170         s->control = (s->control | 0xef) & value;
 171         if (s->busy || ((s->control & (1<<4)) == 0))
 172             s3c_master_work(s);
 173         break;
 174
 175     case S3C_IICSTAT:
 176         s->status &= 0x0f;
 177         s->status |= value & 0xf0;
 178         if (s->status & (1 << 5))
 179             s->newstart = 1;
 180         s3c_master_work(s);
 181         break;
 182
 183     case S3C_IICADD:
 184         s->addy = value & 0x7f;
 185         break;
 186
 187     case S3C_IICDS:
 188         s->data = value & 0xff;
 189         s->busy = 1;
 190         break;
 191
 192     default:
 193         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
 194         break;
 195     }
 196 }
 197
 198 static const MemoryRegionOps s3c24xx_i2c_ops = {
 199     .read = s3c24xx_i2c_read,
 200     .write = s3c24xx_i2c_write,
 201     .endianness = DEVICE_NATIVE_ENDIAN,
 202     .valid = {
 203         .min_access_size = 1,
 204         .max_access_size = 4
 205     }
 206 };
 207
 208 static void s3c24xx_i2c_save(QEMUFile *f, void *opaque)
 209 {
 210     struct s3c24xx_i2c_state_s *s = opaque;
 211     qemu_put_8s(f, &s->control);
 212     qemu_put_8s(f, &s->status);
 213     qemu_put_8s(f, &s->data);
 214     qemu_put_8s(f, &s->addy);
 215
 216     qemu_put_be32(f, s->busy);
 217     qemu_put_be32(f, s->newstart);
 218
 219 }
 220
 221 static int s3c24xx_i2c_load(QEMUFile *f, void *opaque, int version_id)
 222 {
 223     struct s3c24xx_i2c_state_s *s = opaque;
 224     qemu_get_8s(f, &s->control);
 225     qemu_get_8s(f, &s->status);
 226     qemu_get_8s(f, &s->data);
 227     qemu_get_8s(f, &s->addy);
 228
 229     s->busy = qemu_get_be32(f);
 230     s->newstart = qemu_get_be32(f);
 231
 232     return 0;
 233 }
 234
 235
 236 struct s3c24xx_i2c_state_s *s3c24xx_iic_init(qemu_irq irq,
 237                                              hwaddr base_addr)
 238 {
 239     MemoryRegion *system_memory = get_system_memory();
 240     struct s3c24xx_i2c_state_s *s = g_malloc0(sizeof(struct s3c24xx_i2c_state_s));
 241
 242     s->irq = irq;
 243     s->bus = i2c_init_bus(NULL, "i2c");
 244
 245     s3c24xx_i2c_reset(s);
 246
 247     memory_region_init_io(&s->mmio, OBJECT(s),
 248                           &s3c24xx_i2c_ops, s, "s3c24xx-i2c", 0x1000000);
 249     memory_region_add_subregion(system_memory, base_addr, &s->mmio);
 250
 251     register_savevm(NULL, "s3c24xx_i2c", 0, 0, s3c24xx_i2c_save, s3c24xx_i2c_load, s);
 252
 253     return s;
 254 }
 255
 256 I2CBus *s3c24xx_i2c_bus(struct s3c24xx_i2c_state_s *s)
 257 {
 258     return s->bus;
 259 }