hw/nvram/ds1225y.c

   1 /*
   2  * QEMU NVRAM emulation for DS1225Y chip
   3  *
   4  * Copyright (c) 2007-2008 Hervé Poussineau
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/sysbus.h"
  27 #include "trace.h"
  28 #include "qemu/error-report.h"
  29 #include "qemu/module.h"
  30
  31 typedef struct {
  32     MemoryRegion iomem;
  33     uint32_t chip_size;
  34     char *filename;
  35     FILE *file;
  36     uint8_t *contents;
  37 } NvRamState;
  38
  39 static uint64_t nvram_read(void *opaque, hwaddr addr, unsigned size)
  40 {
  41     NvRamState *s = opaque;
  42     uint32_t val;
  43
  44     val = s->contents[addr];
  45     trace_nvram_read(addr, val);
  46     return val;
  47 }
  48
  49 static void nvram_write(void *opaque, hwaddr addr, uint64_t val,
  50                         unsigned size)
  51 {
  52     NvRamState *s = opaque;
  53
  54     val &= 0xff;
  55     trace_nvram_write(addr, s->contents[addr], val);
  56
  57     s->contents[addr] = val;
  58     if (s->file) {
  59         fseek(s->file, addr, SEEK_SET);
  60         fputc(val, s->file);
  61         fflush(s->file);
  62     }
  63 }
  64
  65 static const MemoryRegionOps nvram_ops = {
  66     .read = nvram_read,
  67     .write = nvram_write,
  68     .impl = {
  69         .min_access_size = 1,
  70         .max_access_size = 1,
  71     },
  72     .endianness = DEVICE_LITTLE_ENDIAN,
  73 };
  74
  75 static int nvram_post_load(void *opaque, int version_id)
  76 {
  77     NvRamState *s = opaque;
  78
  79     /* Close file, as filename may has changed in load/store process */
  80     if (s->file) {
  81         fclose(s->file);
  82     }
  83
  84     /* Write back nvram contents */
  85     s->file = s->filename ? fopen(s->filename, "wb") : NULL;
  86     if (s->file) {
  87         /* Write back contents, as 'wb' mode cleaned the file */
  88         if (fwrite(s->contents, s->chip_size, 1, s->file) != 1) {
  89             printf("nvram_post_load: short write\n");
  90         }
  91         fflush(s->file);
  92     }
  93
  94     return 0;
  95 }
  96
  97 static const VMStateDescription vmstate_nvram = {
  98     .name = "nvram",
  99     .version_id = 0,
 100     .minimum_version_id = 0,
 101     .post_load = nvram_post_load,
 102     .fields = (VMStateField[]) {
 103         VMSTATE_VARRAY_UINT32(contents, NvRamState, chip_size, 0,
 104                               vmstate_info_uint8, uint8_t),
 105         VMSTATE_END_OF_LIST()
 106     }
 107 };
 108
 109 #define TYPE_DS1225Y "ds1225y"
 110 #define DS1225Y(obj) OBJECT_CHECK(SysBusNvRamState, (obj), TYPE_DS1225Y)
 111
 112 typedef struct {
 113     SysBusDevice parent_obj;
 114
 115     NvRamState nvram;
 116 } SysBusNvRamState;
 117
 118 static void nvram_sysbus_realize(DeviceState *dev, Error **errp)
 119 {
 120     SysBusNvRamState *sys = DS1225Y(dev);
 121     NvRamState *s = &sys->nvram;
 122     FILE *file;
 123
 124     s->contents = g_malloc0(s->chip_size);
 125
 126     memory_region_init_io(&s->iomem, OBJECT(s), &nvram_ops, s,
 127                           "nvram", s->chip_size);
 128     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 129
 130     /* Read current file */
 131     file = s->filename ? fopen(s->filename, "rb") : NULL;
 132     if (file) {
 133         /* Read nvram contents */
 134         if (fread(s->contents, s->chip_size, 1, file) != 1) {
 135             error_report("nvram_sysbus_realize: short read");
 136         }
 137         fclose(file);
 138     }
 139     nvram_post_load(s, 0);
 140 }
 141
 142 static Property nvram_sysbus_properties[] = {
 143     DEFINE_PROP_UINT32("size", SysBusNvRamState, nvram.chip_size, 0x2000),
 144     DEFINE_PROP_STRING("filename", SysBusNvRamState, nvram.filename),
 145     DEFINE_PROP_END_OF_LIST(),
 146 };
 147
 148 static void nvram_sysbus_class_init(ObjectClass *klass, void *data)
 149 {
 150     DeviceClass *dc = DEVICE_CLASS(klass);
 151
 152     dc->realize = nvram_sysbus_realize;
 153     dc->vmsd = &vmstate_nvram;
 154     dc->props = nvram_sysbus_properties;
 155 }
 156
 157 static const TypeInfo nvram_sysbus_info = {
 158     .name          = TYPE_DS1225Y,
 159     .parent        = TYPE_SYS_BUS_DEVICE,
 160     .instance_size = sizeof(SysBusNvRamState),
 161     .class_init    = nvram_sysbus_class_init,
 162 };
 163
 164 static void nvram_register_types(void)
 165 {
 166     type_register_static(&nvram_sysbus_info);
 167 }
 168
 169 type_init(nvram_register_types)