hw/misc/zynq_slcr.c

   1 /*
   2  * Status and system control registers for Xilinx Zynq Platform
   3  *
   4  * Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
   5  * Copyright (c) 2012 PetaLogix Pty Ltd.
   6  * Based on hw/arm_sysctl.c, written by Paul Brook
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or (at your option) any later version.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include "qemu/osdep.h"
  18 #include "hw/hw.h"
  19 #include "qemu/timer.h"
  20 #include "hw/sysbus.h"
  21 #include "sysemu/sysemu.h"
  22 #include "qemu/log.h"
  23 #include "qemu/module.h"
  24
  25 #ifndef ZYNQ_SLCR_ERR_DEBUG
  26 #define ZYNQ_SLCR_ERR_DEBUG 0
  27 #endif
  28
  29 #define DB_PRINT(...) do { \
  30         if (ZYNQ_SLCR_ERR_DEBUG) { \
  31             fprintf(stderr,  ": %s: ", __func__); \
  32             fprintf(stderr, ## __VA_ARGS__); \
  33         } \
  34     } while (0)
  35
  36 #define XILINX_LOCK_KEY 0x767b
  37 #define XILINX_UNLOCK_KEY 0xdf0d
  38
  39 #define R_PSS_RST_CTRL_SOFT_RST 0x1
  40
  41 enum {
  42     SCL             = 0x000 / 4,
  43     LOCK,
  44     UNLOCK,
  45     LOCKSTA,
  46
  47     ARM_PLL_CTRL    = 0x100 / 4,
  48     DDR_PLL_CTRL,
  49     IO_PLL_CTRL,
  50     PLL_STATUS,
  51     ARM_PLL_CFG,
  52     DDR_PLL_CFG,
  53     IO_PLL_CFG,
  54
  55     ARM_CLK_CTRL    = 0x120 / 4,
  56     DDR_CLK_CTRL,
  57     DCI_CLK_CTRL,
  58     APER_CLK_CTRL,
  59     USB0_CLK_CTRL,
  60     USB1_CLK_CTRL,
  61     GEM0_RCLK_CTRL,
  62     GEM1_RCLK_CTRL,
  63     GEM0_CLK_CTRL,
  64     GEM1_CLK_CTRL,
  65     SMC_CLK_CTRL,
  66     LQSPI_CLK_CTRL,
  67     SDIO_CLK_CTRL,
  68     UART_CLK_CTRL,
  69     SPI_CLK_CTRL,
  70     CAN_CLK_CTRL,
  71     CAN_MIOCLK_CTRL,
  72     DBG_CLK_CTRL,
  73     PCAP_CLK_CTRL,
  74     TOPSW_CLK_CTRL,
  75
  76 #define FPGA_CTRL_REGS(n, start) \
  77     FPGA ## n ## _CLK_CTRL = (start) / 4, \
  78     FPGA ## n ## _THR_CTRL, \
  79     FPGA ## n ## _THR_CNT, \
  80     FPGA ## n ## _THR_STA,
  81     FPGA_CTRL_REGS(0, 0x170)
  82     FPGA_CTRL_REGS(1, 0x180)
  83     FPGA_CTRL_REGS(2, 0x190)
  84     FPGA_CTRL_REGS(3, 0x1a0)
  85
  86     BANDGAP_TRIP    = 0x1b8 / 4,
  87     PLL_PREDIVISOR  = 0x1c0 / 4,
  88     CLK_621_TRUE,
  89
  90     PSS_RST_CTRL    = 0x200 / 4,
  91     DDR_RST_CTRL,
  92     TOPSW_RESET_CTRL,
  93     DMAC_RST_CTRL,
  94     USB_RST_CTRL,
  95     GEM_RST_CTRL,
  96     SDIO_RST_CTRL,
  97     SPI_RST_CTRL,
  98     CAN_RST_CTRL,
  99     I2C_RST_CTRL,
 100     UART_RST_CTRL,
 101     GPIO_RST_CTRL,
 102     LQSPI_RST_CTRL,
 103     SMC_RST_CTRL,
 104     OCM_RST_CTRL,
 105     FPGA_RST_CTRL   = 0x240 / 4,
 106     A9_CPU_RST_CTRL,
 107
 108     RS_AWDT_CTRL    = 0x24c / 4,
 109     RST_REASON,
 110
 111     REBOOT_STATUS   = 0x258 / 4,
 112     BOOT_MODE,
 113
 114     APU_CTRL        = 0x300 / 4,
 115     WDT_CLK_SEL,
 116
 117     TZ_DMA_NS       = 0x440 / 4,
 118     TZ_DMA_IRQ_NS,
 119     TZ_DMA_PERIPH_NS,
 120
 121     PSS_IDCODE      = 0x530 / 4,
 122
 123     DDR_URGENT      = 0x600 / 4,
 124     DDR_CAL_START   = 0x60c / 4,
 125     DDR_REF_START   = 0x614 / 4,
 126     DDR_CMD_STA,
 127     DDR_URGENT_SEL,
 128     DDR_DFI_STATUS,
 129
 130     MIO             = 0x700 / 4,
 131 #define MIO_LENGTH 54
 132
 133     MIO_LOOPBACK    = 0x804 / 4,
 134     MIO_MST_TRI0,
 135     MIO_MST_TRI1,
 136
 137     SD0_WP_CD_SEL   = 0x830 / 4,
 138     SD1_WP_CD_SEL,
 139
 140     LVL_SHFTR_EN    = 0x900 / 4,
 141     OCM_CFG         = 0x910 / 4,
 142
 143     CPU_RAM         = 0xa00 / 4,
 144
 145     IOU             = 0xa30 / 4,
 146
 147     DMAC_RAM        = 0xa50 / 4,
 148
 149     AFI0            = 0xa60 / 4,
 150     AFI1 = AFI0 + 3,
 151     AFI2 = AFI1 + 3,
 152     AFI3 = AFI2 + 3,
 153 #define AFI_LENGTH 3
 154
 155     OCM             = 0xa90 / 4,
 156
 157     DEVCI_RAM       = 0xaa0 / 4,
 158
 159     CSG_RAM         = 0xab0 / 4,
 160
 161     GPIOB_CTRL      = 0xb00 / 4,
 162     GPIOB_CFG_CMOS18,
 163     GPIOB_CFG_CMOS25,
 164     GPIOB_CFG_CMOS33,
 165     GPIOB_CFG_HSTL  = 0xb14 / 4,
 166     GPIOB_DRVR_BIAS_CTRL,
 167
 168     DDRIOB          = 0xb40 / 4,
 169 #define DDRIOB_LENGTH 14
 170 };
 171
 172 #define ZYNQ_SLCR_MMIO_SIZE     0x1000
 173 #define ZYNQ_SLCR_NUM_REGS      (ZYNQ_SLCR_MMIO_SIZE / 4)
 174
 175 #define TYPE_ZYNQ_SLCR "xilinx,zynq_slcr"
 176 #define ZYNQ_SLCR(obj) OBJECT_CHECK(ZynqSLCRState, (obj), TYPE_ZYNQ_SLCR)
 177
 178 typedef struct ZynqSLCRState {
 179     SysBusDevice parent_obj;
 180
 181     MemoryRegion iomem;
 182
 183     uint32_t regs[ZYNQ_SLCR_NUM_REGS];
 184 } ZynqSLCRState;
 185
 186 static void zynq_slcr_reset(DeviceState *d)
 187 {
 188     ZynqSLCRState *s = ZYNQ_SLCR(d);
 189     int i;
 190
 191     DB_PRINT("RESET\n");
 192
 193     s->regs[LOCKSTA] = 1;
 194     /* 0x100 - 0x11C */
 195     s->regs[ARM_PLL_CTRL]   = 0x0001A008;
 196     s->regs[DDR_PLL_CTRL]   = 0x0001A008;
 197     s->regs[IO_PLL_CTRL]    = 0x0001A008;
 198     s->regs[PLL_STATUS]     = 0x0000003F;
 199     s->regs[ARM_PLL_CFG]    = 0x00014000;
 200     s->regs[DDR_PLL_CFG]    = 0x00014000;
 201     s->regs[IO_PLL_CFG]     = 0x00014000;
 202
 203     /* 0x120 - 0x16C */
 204     s->regs[ARM_CLK_CTRL]   = 0x1F000400;
 205     s->regs[DDR_CLK_CTRL]   = 0x18400003;
 206     s->regs[DCI_CLK_CTRL]   = 0x01E03201;
 207     s->regs[APER_CLK_CTRL]  = 0x01FFCCCD;
 208     s->regs[USB0_CLK_CTRL]  = s->regs[USB1_CLK_CTRL]    = 0x00101941;
 209     s->regs[GEM0_RCLK_CTRL] = s->regs[GEM1_RCLK_CTRL]   = 0x00000001;
 210     s->regs[GEM0_CLK_CTRL]  = s->regs[GEM1_CLK_CTRL]    = 0x00003C01;
 211     s->regs[SMC_CLK_CTRL]   = 0x00003C01;
 212     s->regs[LQSPI_CLK_CTRL] = 0x00002821;
 213     s->regs[SDIO_CLK_CTRL]  = 0x00001E03;
 214     s->regs[UART_CLK_CTRL]  = 0x00003F03;
 215     s->regs[SPI_CLK_CTRL]   = 0x00003F03;
 216     s->regs[CAN_CLK_CTRL]   = 0x00501903;
 217     s->regs[DBG_CLK_CTRL]   = 0x00000F03;
 218     s->regs[PCAP_CLK_CTRL]  = 0x00000F01;
 219
 220     /* 0x170 - 0x1AC */
 221     s->regs[FPGA0_CLK_CTRL] = s->regs[FPGA1_CLK_CTRL] = s->regs[FPGA2_CLK_CTRL]
 222                             = s->regs[FPGA3_CLK_CTRL] = 0x00101800;
 223     s->regs[FPGA0_THR_STA] = s->regs[FPGA1_THR_STA] = s->regs[FPGA2_THR_STA]
 224                            = s->regs[FPGA3_THR_STA] = 0x00010000;
 225
 226     /* 0x1B0 - 0x1D8 */
 227     s->regs[BANDGAP_TRIP]   = 0x0000001F;
 228     s->regs[PLL_PREDIVISOR] = 0x00000001;
 229     s->regs[CLK_621_TRUE]   = 0x00000001;
 230
 231     /* 0x200 - 0x25C */
 232     s->regs[FPGA_RST_CTRL]  = 0x01F33F0F;
 233     s->regs[RST_REASON]     = 0x00000040;
 234
 235     s->regs[BOOT_MODE]      = 0x00000001;
 236
 237     /* 0x700 - 0x7D4 */
 238     for (i = 0; i < 54; i++) {
 239         s->regs[MIO + i] = 0x00001601;
 240     }
 241     for (i = 2; i <= 8; i++) {
 242         s->regs[MIO + i] = 0x00000601;
 243     }
 244
 245     s->regs[MIO_MST_TRI0] = s->regs[MIO_MST_TRI1] = 0xFFFFFFFF;
 246
 247     s->regs[CPU_RAM + 0] = s->regs[CPU_RAM + 1] = s->regs[CPU_RAM + 3]
 248                          = s->regs[CPU_RAM + 4] = s->regs[CPU_RAM + 7]
 249                          = 0x00010101;
 250     s->regs[CPU_RAM + 2] = s->regs[CPU_RAM + 5] = 0x01010101;
 251     s->regs[CPU_RAM + 6] = 0x00000001;
 252
 253     s->regs[IOU + 0] = s->regs[IOU + 1] = s->regs[IOU + 2] = s->regs[IOU + 3]
 254                      = 0x09090909;
 255     s->regs[IOU + 4] = s->regs[IOU + 5] = 0x00090909;
 256     s->regs[IOU + 6] = 0x00000909;
 257
 258     s->regs[DMAC_RAM] = 0x00000009;
 259
 260     s->regs[AFI0 + 0] = s->regs[AFI0 + 1] = 0x09090909;
 261     s->regs[AFI1 + 0] = s->regs[AFI1 + 1] = 0x09090909;
 262     s->regs[AFI2 + 0] = s->regs[AFI2 + 1] = 0x09090909;
 263     s->regs[AFI3 + 0] = s->regs[AFI3 + 1] = 0x09090909;
 264     s->regs[AFI0 + 2] = s->regs[AFI1 + 2] = s->regs[AFI2 + 2]
 265                       = s->regs[AFI3 + 2] = 0x00000909;
 266
 267     s->regs[OCM + 0]    = 0x01010101;
 268     s->regs[OCM + 1]    = s->regs[OCM + 2] = 0x09090909;
 269
 270     s->regs[DEVCI_RAM]  = 0x00000909;
 271     s->regs[CSG_RAM]    = 0x00000001;
 272
 273     s->regs[DDRIOB + 0] = s->regs[DDRIOB + 1] = s->regs[DDRIOB + 2]
 274                         = s->regs[DDRIOB + 3] = 0x00000e00;
 275     s->regs[DDRIOB + 4] = s->regs[DDRIOB + 5] = s->regs[DDRIOB + 6]
 276                         = 0x00000e00;
 277     s->regs[DDRIOB + 12] = 0x00000021;
 278 }
 279
 280
 281 static bool zynq_slcr_check_offset(hwaddr offset, bool rnw)
 282 {
 283     switch (offset) {
 284     case LOCK:
 285     case UNLOCK:
 286     case DDR_CAL_START:
 287     case DDR_REF_START:
 288         return !rnw; /* Write only */
 289     case LOCKSTA:
 290     case FPGA0_THR_STA:
 291     case FPGA1_THR_STA:
 292     case FPGA2_THR_STA:
 293     case FPGA3_THR_STA:
 294     case BOOT_MODE:
 295     case PSS_IDCODE:
 296     case DDR_CMD_STA:
 297     case DDR_DFI_STATUS:
 298     case PLL_STATUS:
 299         return rnw;/* read only */
 300     case SCL:
 301     case ARM_PLL_CTRL ... IO_PLL_CTRL:
 302     case ARM_PLL_CFG ... IO_PLL_CFG:
 303     case ARM_CLK_CTRL ... TOPSW_CLK_CTRL:
 304     case FPGA0_CLK_CTRL ... FPGA0_THR_CNT:
 305     case FPGA1_CLK_CTRL ... FPGA1_THR_CNT:
 306     case FPGA2_CLK_CTRL ... FPGA2_THR_CNT:
 307     case FPGA3_CLK_CTRL ... FPGA3_THR_CNT:
 308     case BANDGAP_TRIP:
 309     case PLL_PREDIVISOR:
 310     case CLK_621_TRUE:
 311     case PSS_RST_CTRL ... A9_CPU_RST_CTRL:
 312     case RS_AWDT_CTRL:
 313     case RST_REASON:
 314     case REBOOT_STATUS:
 315     case APU_CTRL:
 316     case WDT_CLK_SEL:
 317     case TZ_DMA_NS ... TZ_DMA_PERIPH_NS:
 318     case DDR_URGENT:
 319     case DDR_URGENT_SEL:
 320     case MIO ... MIO + MIO_LENGTH - 1:
 321     case MIO_LOOPBACK ... MIO_MST_TRI1:
 322     case SD0_WP_CD_SEL:
 323     case SD1_WP_CD_SEL:
 324     case LVL_SHFTR_EN:
 325     case OCM_CFG:
 326     case CPU_RAM:
 327     case IOU:
 328     case DMAC_RAM:
 329     case AFI0 ... AFI3 + AFI_LENGTH - 1:
 330     case OCM:
 331     case DEVCI_RAM:
 332     case CSG_RAM:
 333     case GPIOB_CTRL ... GPIOB_CFG_CMOS33:
 334     case GPIOB_CFG_HSTL:
 335     case GPIOB_DRVR_BIAS_CTRL:
 336     case DDRIOB ... DDRIOB + DDRIOB_LENGTH - 1:
 337         return true;
 338     default:
 339         return false;
 340     }
 341 }
 342
 343 static uint64_t zynq_slcr_read(void *opaque, hwaddr offset,
 344     unsigned size)
 345 {
 346     ZynqSLCRState *s = opaque;
 347     offset /= 4;
 348     uint32_t ret = s->regs[offset];
 349
 350     if (!zynq_slcr_check_offset(offset, true)) {
 351         qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid read access to "
 352                       " addr %" HWADDR_PRIx "\n", offset * 4);
 353     }
 354
 355     DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx32 "\n", offset * 4, ret);
 356     return ret;
 357 }
 358
 359 static void zynq_slcr_write(void *opaque, hwaddr offset,
 360                           uint64_t val, unsigned size)
 361 {
 362     ZynqSLCRState *s = (ZynqSLCRState *)opaque;
 363     offset /= 4;
 364
 365     DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset * 4, val);
 366
 367     if (!zynq_slcr_check_offset(offset, false)) {
 368         qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid write access to "
 369                       "addr %" HWADDR_PRIx "\n", offset * 4);
 370         return;
 371     }
 372
 373     switch (offset) {
 374     case SCL:
 375         s->regs[SCL] = val & 0x1;
 376         return;
 377     case LOCK:
 378         if ((val & 0xFFFF) == XILINX_LOCK_KEY) {
 379             DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
 380                 (unsigned)val & 0xFFFF);
 381             s->regs[LOCKSTA] = 1;
 382         } else {
 383             DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
 384                 (int)offset, (unsigned)val & 0xFFFF);
 385         }
 386         return;
 387     case UNLOCK:
 388         if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) {
 389             DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
 390                 (unsigned)val & 0xFFFF);
 391             s->regs[LOCKSTA] = 0;
 392         } else {
 393             DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
 394                 (int)offset, (unsigned)val & 0xFFFF);
 395         }
 396         return;
 397     }
 398
 399     if (s->regs[LOCKSTA]) {
 400         qemu_log_mask(LOG_GUEST_ERROR,
 401                       "SCLR registers are locked. Unlock them first\n");
 402         return;
 403     }
 404     s->regs[offset] = val;
 405
 406     switch (offset) {
 407     case PSS_RST_CTRL:
 408         if (val & R_PSS_RST_CTRL_SOFT_RST) {
 409             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 410         }
 411         break;
 412     }
 413 }
 414
 415 static const MemoryRegionOps slcr_ops = {
 416     .read = zynq_slcr_read,
 417     .write = zynq_slcr_write,
 418     .endianness = DEVICE_NATIVE_ENDIAN,
 419 };
 420
 421 static void zynq_slcr_init(Object *obj)
 422 {
 423     ZynqSLCRState *s = ZYNQ_SLCR(obj);
 424
 425     memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr",
 426                           ZYNQ_SLCR_MMIO_SIZE);
 427     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
 428 }
 429
 430 static const VMStateDescription vmstate_zynq_slcr = {
 431     .name = "zynq_slcr",
 432     .version_id = 2,
 433     .minimum_version_id = 2,
 434     .fields = (VMStateField[]) {
 435         VMSTATE_UINT32_ARRAY(regs, ZynqSLCRState, ZYNQ_SLCR_NUM_REGS),
 436         VMSTATE_END_OF_LIST()
 437     }
 438 };
 439
 440 static void zynq_slcr_class_init(ObjectClass *klass, void *data)
 441 {
 442     DeviceClass *dc = DEVICE_CLASS(klass);
 443
 444     dc->vmsd = &vmstate_zynq_slcr;
 445     dc->reset = zynq_slcr_reset;
 446 }
 447
 448 static const TypeInfo zynq_slcr_info = {
 449     .class_init = zynq_slcr_class_init,
 450     .name  = TYPE_ZYNQ_SLCR,
 451     .parent = TYPE_SYS_BUS_DEVICE,
 452     .instance_size  = sizeof(ZynqSLCRState),
 453     .instance_init = zynq_slcr_init,
 454 };
 455
 456 static void zynq_slcr_register_types(void)
 457 {
 458     type_register_static(&zynq_slcr_info);
 459 }
 460
 461 type_init(zynq_slcr_register_types)