hw/isa/pc87312.c

   1 /*
   2  * QEMU National Semiconductor PC87312 (Super I/O)
   3  *
   4  * Copyright (c) 2010-2012 Herve Poussineau
   5  * Copyright (c) 2011-2012 Andreas Färber
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/isa/pc87312.h"
  28 #include "qapi/error.h"
  29 #include "qemu/error-report.h"
  30 #include "qemu/module.h"
  31 #include "trace.h"
  32
  33
  34 #define REG_FER 0
  35 #define REG_FAR 1
  36 #define REG_PTR 2
  37
  38 #define FER_PARALLEL_EN   0x01
  39 #define FER_UART1_EN      0x02
  40 #define FER_UART2_EN      0x04
  41 #define FER_FDC_EN        0x08
  42 #define FER_FDC_4         0x10
  43 #define FER_FDC_ADDR      0x20
  44 #define FER_IDE_EN        0x40
  45 #define FER_IDE_ADDR      0x80
  46
  47 #define FAR_PARALLEL_ADDR 0x03
  48 #define FAR_UART1_ADDR    0x0C
  49 #define FAR_UART2_ADDR    0x30
  50 #define FAR_UART_3_4      0xC0
  51
  52 #define PTR_POWER_DOWN    0x01
  53 #define PTR_CLOCK_DOWN    0x02
  54 #define PTR_PWDN          0x04
  55 #define PTR_IRQ_5_7       0x08
  56 #define PTR_UART1_TEST    0x10
  57 #define PTR_UART2_TEST    0x20
  58 #define PTR_LOCK_CONF     0x40
  59 #define PTR_EPP_MODE      0x80
  60
  61
  62 /* Parallel port */
  63
  64 static bool is_parallel_enabled(ISASuperIODevice *sio, uint8_t index)
  65 {
  66     PC87312State *s = PC87312(sio);
  67     return index ? false : s->regs[REG_FER] & FER_PARALLEL_EN;
  68 }
  69
  70 static const uint16_t parallel_base[] = { 0x378, 0x3bc, 0x278, 0x00 };
  71
  72 static uint16_t get_parallel_iobase(ISASuperIODevice *sio, uint8_t index)
  73 {
  74     PC87312State *s = PC87312(sio);
  75     return parallel_base[s->regs[REG_FAR] & FAR_PARALLEL_ADDR];
  76 }
  77
  78 static const unsigned int parallel_irq[] = { 5, 7, 5, 0 };
  79
  80 static unsigned int get_parallel_irq(ISASuperIODevice *sio, uint8_t index)
  81 {
  82     PC87312State *s = PC87312(sio);
  83     int idx;
  84     idx = (s->regs[REG_FAR] & FAR_PARALLEL_ADDR);
  85     if (idx == 0) {
  86         return (s->regs[REG_PTR] & PTR_IRQ_5_7) ? 7 : 5;
  87     } else {
  88         return parallel_irq[idx];
  89     }
  90 }
  91
  92
  93 /* UARTs */
  94
  95 static const uint16_t uart_base[2][4] = {
  96     { 0x3e8, 0x338, 0x2e8, 0x220 },
  97     { 0x2e8, 0x238, 0x2e0, 0x228 }
  98 };
  99
 100 static uint16_t get_uart_iobase(ISASuperIODevice *sio, uint8_t i)
 101 {
 102     PC87312State *s = PC87312(sio);
 103     int idx;
 104     idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3;
 105     if (idx == 0) {
 106         return 0x3f8;
 107     } else if (idx == 1) {
 108         return 0x2f8;
 109     } else {
 110         return uart_base[idx & 1][(s->regs[REG_FAR] & FAR_UART_3_4) >> 6];
 111     }
 112 }
 113
 114 static unsigned int get_uart_irq(ISASuperIODevice *sio, uint8_t i)
 115 {
 116     PC87312State *s = PC87312(sio);
 117     int idx;
 118     idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3;
 119     return (idx & 1) ? 3 : 4;
 120 }
 121
 122 static bool is_uart_enabled(ISASuperIODevice *sio, uint8_t i)
 123 {
 124     PC87312State *s = PC87312(sio);
 125     return s->regs[REG_FER] & (FER_UART1_EN << i);
 126 }
 127
 128
 129 /* Floppy controller */
 130
 131 static bool is_fdc_enabled(ISASuperIODevice *sio, uint8_t index)
 132 {
 133     PC87312State *s = PC87312(sio);
 134     assert(!index);
 135     return s->regs[REG_FER] & FER_FDC_EN;
 136 }
 137
 138 static uint16_t get_fdc_iobase(ISASuperIODevice *sio, uint8_t index)
 139 {
 140     PC87312State *s = PC87312(sio);
 141     assert(!index);
 142     return (s->regs[REG_FER] & FER_FDC_ADDR) ? 0x370 : 0x3f0;
 143 }
 144
 145 static unsigned int get_fdc_irq(ISASuperIODevice *sio, uint8_t index)
 146 {
 147     assert(!index);
 148     return 6;
 149 }
 150
 151
 152 /* IDE controller */
 153
 154 static bool is_ide_enabled(ISASuperIODevice *sio, uint8_t index)
 155 {
 156     PC87312State *s = PC87312(sio);
 157
 158     return s->regs[REG_FER] & FER_IDE_EN;
 159 }
 160
 161 static uint16_t get_ide_iobase(ISASuperIODevice *sio, uint8_t index)
 162 {
 163     PC87312State *s = PC87312(sio);
 164
 165     if (index == 1) {
 166         return get_ide_iobase(sio, 0) + 0x206;
 167     }
 168     return (s->regs[REG_FER] & FER_IDE_ADDR) ? 0x170 : 0x1f0;
 169 }
 170
 171 static unsigned int get_ide_irq(ISASuperIODevice *sio, uint8_t index)
 172 {
 173     assert(index == 0);
 174     return 14;
 175 }
 176
 177 static void reconfigure_devices(PC87312State *s)
 178 {
 179     error_report("pc87312: unsupported device reconfiguration (%02x %02x %02x)",
 180                  s->regs[REG_FER], s->regs[REG_FAR], s->regs[REG_PTR]);
 181 }
 182
 183 static void pc87312_soft_reset(PC87312State *s)
 184 {
 185     static const uint8_t fer_init[] = {
 186         0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4b, 0x4b,
 187         0x4b, 0x4b, 0x4b, 0x4b, 0x0f, 0x0f, 0x0f, 0x0f,
 188         0x49, 0x49, 0x49, 0x49, 0x07, 0x07, 0x07, 0x07,
 189         0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x08, 0x00,
 190     };
 191     static const uint8_t far_init[] = {
 192         0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x00, 0x01,
 193         0x01, 0x09, 0x08, 0x08, 0x10, 0x11, 0x39, 0x24,
 194         0x00, 0x01, 0x01, 0x00, 0x10, 0x11, 0x39, 0x24,
 195         0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x10, 0x10,
 196     };
 197     static const uint8_t ptr_init[] = {
 198         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 199         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 200         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 201         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
 202     };
 203
 204     s->read_id_step = 0;
 205     s->selected_index = REG_FER;
 206
 207     s->regs[REG_FER] = fer_init[s->config & 0x1f];
 208     s->regs[REG_FAR] = far_init[s->config & 0x1f];
 209     s->regs[REG_PTR] = ptr_init[s->config & 0x1f];
 210 }
 211
 212 static void pc87312_hard_reset(PC87312State *s)
 213 {
 214     pc87312_soft_reset(s);
 215 }
 216
 217 static void pc87312_io_write(void *opaque, hwaddr addr, uint64_t val,
 218                              unsigned int size)
 219 {
 220     PC87312State *s = opaque;
 221
 222     trace_pc87312_io_write(addr, val);
 223
 224     if ((addr & 1) == 0) {
 225         /* Index register */
 226         s->read_id_step = 2;
 227         s->selected_index = val;
 228     } else {
 229         /* Data register */
 230         if (s->selected_index < 3) {
 231             s->regs[s->selected_index] = val;
 232             reconfigure_devices(s);
 233         }
 234     }
 235 }
 236
 237 static uint64_t pc87312_io_read(void *opaque, hwaddr addr, unsigned int size)
 238 {
 239     PC87312State *s = opaque;
 240     uint32_t val;
 241
 242     if ((addr & 1) == 0) {
 243         /* Index register */
 244         if (s->read_id_step++ == 0) {
 245             val = 0x88;
 246         } else if (s->read_id_step++ == 1) {
 247             val = 0;
 248         } else {
 249             val = s->selected_index;
 250         }
 251     } else {
 252         /* Data register */
 253         if (s->selected_index < 3) {
 254             val = s->regs[s->selected_index];
 255         } else {
 256             /* Invalid selected index */
 257             val = 0;
 258         }
 259     }
 260
 261     trace_pc87312_io_read(addr, val);
 262     return val;
 263 }
 264
 265 static const MemoryRegionOps pc87312_io_ops = {
 266     .read  = pc87312_io_read,
 267     .write = pc87312_io_write,
 268     .endianness = DEVICE_LITTLE_ENDIAN,
 269     .valid = {
 270         .min_access_size = 1,
 271         .max_access_size = 1,
 272     },
 273 };
 274
 275 static int pc87312_post_load(void *opaque, int version_id)
 276 {
 277     PC87312State *s = opaque;
 278
 279     reconfigure_devices(s);
 280     return 0;
 281 }
 282
 283 static void pc87312_reset(DeviceState *d)
 284 {
 285     PC87312State *s = PC87312(d);
 286
 287     pc87312_soft_reset(s);
 288 }
 289
 290 static void pc87312_realize(DeviceState *dev, Error **errp)
 291 {
 292     PC87312State *s;
 293     ISADevice *isa;
 294     Error *local_err = NULL;
 295
 296     s = PC87312(dev);
 297     isa = ISA_DEVICE(dev);
 298     isa_register_ioport(isa, &s->io, s->iobase);
 299     pc87312_hard_reset(s);
 300
 301     ISA_SUPERIO_GET_CLASS(dev)->parent_realize(dev, &local_err);
 302     if (local_err) {
 303         error_propagate(errp, local_err);
 304         return;
 305     }
 306 }
 307
 308 static void pc87312_initfn(Object *obj)
 309 {
 310     PC87312State *s = PC87312(obj);
 311
 312     memory_region_init_io(&s->io, obj, &pc87312_io_ops, s, "pc87312", 2);
 313 }
 314
 315 static const VMStateDescription vmstate_pc87312 = {
 316     .name = "pc87312",
 317     .version_id = 1,
 318     .minimum_version_id = 1,
 319     .post_load = pc87312_post_load,
 320     .fields = (VMStateField[]) {
 321         VMSTATE_UINT8(read_id_step, PC87312State),
 322         VMSTATE_UINT8(selected_index, PC87312State),
 323         VMSTATE_UINT8_ARRAY(regs, PC87312State, 3),
 324         VMSTATE_END_OF_LIST()
 325     }
 326 };
 327
 328 static Property pc87312_properties[] = {
 329     DEFINE_PROP_UINT16("iobase", PC87312State, iobase, 0x398),
 330     DEFINE_PROP_UINT8("config", PC87312State, config, 1),
 331     DEFINE_PROP_END_OF_LIST()
 332 };
 333
 334 static void pc87312_class_init(ObjectClass *klass, void *data)
 335 {
 336     DeviceClass *dc = DEVICE_CLASS(klass);
 337     ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
 338
 339     sc->parent_realize = dc->realize;
 340     dc->realize = pc87312_realize;
 341     dc->reset = pc87312_reset;
 342     dc->vmsd = &vmstate_pc87312;
 343     dc->props = pc87312_properties;
 344
 345     sc->parallel = (ISASuperIOFuncs){
 346         .count = 1,
 347         .is_enabled = is_parallel_enabled,
 348         .get_iobase = get_parallel_iobase,
 349         .get_irq    = get_parallel_irq,
 350     };
 351     sc->serial = (ISASuperIOFuncs){
 352         .count = 2,
 353         .is_enabled = is_uart_enabled,
 354         .get_iobase = get_uart_iobase,
 355         .get_irq    = get_uart_irq,
 356     };
 357     sc->floppy = (ISASuperIOFuncs){
 358         .count = 1,
 359         .is_enabled = is_fdc_enabled,
 360         .get_iobase = get_fdc_iobase,
 361         .get_irq    = get_fdc_irq,
 362     };
 363     sc->ide = (ISASuperIOFuncs){
 364         .count = 1,
 365         .is_enabled = is_ide_enabled,
 366         .get_iobase = get_ide_iobase,
 367         .get_irq    = get_ide_irq,
 368     };
 369 }
 370
 371 static const TypeInfo pc87312_type_info = {
 372     .name          = TYPE_PC87312_SUPERIO,
 373     .parent        = TYPE_ISA_SUPERIO,
 374     .instance_size = sizeof(PC87312State),
 375     .instance_init = pc87312_initfn,
 376     .class_init    = pc87312_class_init,
 377     /* FIXME use a qdev drive property instead of drive_get() */
 378 };
 379
 380 static void pc87312_register_types(void)
 381 {
 382     type_register_static(&pc87312_type_info);
 383 }
 384
 385 type_init(pc87312_register_types)