hw/char/serial-pci-multi.c

   1 /*
   2  * QEMU 16550A multi UART emulation
   3  *
   4  * SPDX-License-Identifier: MIT
   5  *
   6  * Copyright (c) 2003-2004 Fabrice Bellard
   7  * Copyright (c) 2008 Citrix Systems, Inc.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27
  28 /* see docs/specs/pci-serial.txt */
  29
  30 #include "qemu/osdep.h"
  31 #include "qapi/error.h"
  32 #include "hw/char/serial.h"
  33 #include "hw/pci/pci.h"
  34
  35 #define PCI_SERIAL_MAX_PORTS 4
  36
  37 typedef struct PCIMultiSerialState {
  38     PCIDevice    dev;
  39     MemoryRegion iobar;
  40     uint32_t     ports;
  41     char         *name[PCI_SERIAL_MAX_PORTS];
  42     SerialState  state[PCI_SERIAL_MAX_PORTS];
  43     uint32_t     level[PCI_SERIAL_MAX_PORTS];
  44     qemu_irq     *irqs;
  45     uint8_t      prog_if;
  46 } PCIMultiSerialState;
  47
  48 static void multi_serial_pci_exit(PCIDevice *dev)
  49 {
  50     PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
  51     SerialState *s;
  52     int i;
  53
  54     for (i = 0; i < pci->ports; i++) {
  55         s = pci->state + i;
  56         serial_exit_core(s);
  57         memory_region_del_subregion(&pci->iobar, &s->io);
  58         g_free(pci->name[i]);
  59     }
  60     qemu_free_irqs(pci->irqs, pci->ports);
  61 }
  62
  63 static void multi_serial_irq_mux(void *opaque, int n, int level)
  64 {
  65     PCIMultiSerialState *pci = opaque;
  66     int i, pending = 0;
  67
  68     pci->level[n] = level;
  69     for (i = 0; i < pci->ports; i++) {
  70         if (pci->level[i]) {
  71             pending = 1;
  72         }
  73     }
  74     pci_set_irq(&pci->dev, pending);
  75 }
  76
  77 static void multi_serial_pci_realize(PCIDevice *dev, Error **errp)
  78 {
  79     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
  80     PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
  81     SerialState *s;
  82     Error *err = NULL;
  83     int i, nr_ports = 0;
  84
  85     switch (pc->device_id) {
  86     case 0x0003:
  87         nr_ports = 2;
  88         break;
  89     case 0x0004:
  90         nr_ports = 4;
  91         break;
  92     }
  93     assert(nr_ports > 0);
  94     assert(nr_ports <= PCI_SERIAL_MAX_PORTS);
  95
  96     pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
  97     pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
  98     memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nr_ports);
  99     pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
 100     pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci,
 101                                    nr_ports);
 102
 103     for (i = 0; i < nr_ports; i++) {
 104         s = pci->state + i;
 105         s->baudbase = 115200;
 106         serial_realize_core(s, &err);
 107         if (err != NULL) {
 108             error_propagate(errp, err);
 109             multi_serial_pci_exit(dev);
 110             return;
 111         }
 112         s->irq = pci->irqs[i];
 113         pci->name[i] = g_strdup_printf("uart #%d", i + 1);
 114         memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
 115                               pci->name[i], 8);
 116         memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
 117         pci->ports++;
 118     }
 119 }
 120
 121 static const VMStateDescription vmstate_pci_multi_serial = {
 122     .name = "pci-serial-multi",
 123     .version_id = 1,
 124     .minimum_version_id = 1,
 125     .fields = (VMStateField[]) {
 126         VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState),
 127         VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS,
 128                              0, vmstate_serial, SerialState),
 129         VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS),
 130         VMSTATE_END_OF_LIST()
 131     }
 132 };
 133
 134 static Property multi_2x_serial_pci_properties[] = {
 135     DEFINE_PROP_CHR("chardev1",  PCIMultiSerialState, state[0].chr),
 136     DEFINE_PROP_CHR("chardev2",  PCIMultiSerialState, state[1].chr),
 137     DEFINE_PROP_UINT8("prog_if",  PCIMultiSerialState, prog_if, 0x02),
 138     DEFINE_PROP_END_OF_LIST(),
 139 };
 140
 141 static Property multi_4x_serial_pci_properties[] = {
 142     DEFINE_PROP_CHR("chardev1",  PCIMultiSerialState, state[0].chr),
 143     DEFINE_PROP_CHR("chardev2",  PCIMultiSerialState, state[1].chr),
 144     DEFINE_PROP_CHR("chardev3",  PCIMultiSerialState, state[2].chr),
 145     DEFINE_PROP_CHR("chardev4",  PCIMultiSerialState, state[3].chr),
 146     DEFINE_PROP_UINT8("prog_if",  PCIMultiSerialState, prog_if, 0x02),
 147     DEFINE_PROP_END_OF_LIST(),
 148 };
 149
 150 static void multi_2x_serial_pci_class_initfn(ObjectClass *klass, void *data)
 151 {
 152     DeviceClass *dc = DEVICE_CLASS(klass);
 153     PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
 154     pc->realize = multi_serial_pci_realize;
 155     pc->exit = multi_serial_pci_exit;
 156     pc->vendor_id = PCI_VENDOR_ID_REDHAT;
 157     pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2;
 158     pc->revision = 1;
 159     pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
 160     dc->vmsd = &vmstate_pci_multi_serial;
 161     dc->props = multi_2x_serial_pci_properties;
 162     set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 163 }
 164
 165 static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, void *data)
 166 {
 167     DeviceClass *dc = DEVICE_CLASS(klass);
 168     PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
 169     pc->realize = multi_serial_pci_realize;
 170     pc->exit = multi_serial_pci_exit;
 171     pc->vendor_id = PCI_VENDOR_ID_REDHAT;
 172     pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4;
 173     pc->revision = 1;
 174     pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
 175     dc->vmsd = &vmstate_pci_multi_serial;
 176     dc->props = multi_4x_serial_pci_properties;
 177     set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 178 }
 179
 180 static const TypeInfo multi_2x_serial_pci_info = {
 181     .name          = "pci-serial-2x",
 182     .parent        = TYPE_PCI_DEVICE,
 183     .instance_size = sizeof(PCIMultiSerialState),
 184     .class_init    = multi_2x_serial_pci_class_initfn,
 185     .interfaces = (InterfaceInfo[]) {
 186         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 187         { },
 188     },
 189 };
 190
 191 static const TypeInfo multi_4x_serial_pci_info = {
 192     .name          = "pci-serial-4x",
 193     .parent        = TYPE_PCI_DEVICE,
 194     .instance_size = sizeof(PCIMultiSerialState),
 195     .class_init    = multi_4x_serial_pci_class_initfn,
 196     .interfaces = (InterfaceInfo[]) {
 197         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 198         { },
 199     },
 200 };
 201
 202 static void multi_serial_pci_register_types(void)
 203 {
 204     type_register_static(&multi_2x_serial_pci_info);
 205     type_register_static(&multi_4x_serial_pci_info);
 206 }
 207
 208 type_init(multi_serial_pci_register_types)