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xics/spapr: Rename xics_kvm_init()
[qemu/ar7.git] / hw / arm / omap2.c
blob87ced7f3a27a3d06be6a41a8e36f192b8f5995ce
1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2007-2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/error-report.h"
23 #include "qapi/error.h"
24 #include "cpu.h"
25 #include "sysemu/qtest.h"
26 #include "hw/boards.h"
27 #include "hw/hw.h"
28 #include "hw/arm/boot.h"
29 #include "hw/arm/omap.h"
30 #include "sysemu/sysemu.h"
31 #include "qemu/timer.h"
32 #include "chardev/char-fe.h"
33 #include "hw/block/flash.h"
34 #include "hw/arm/soc_dma.h"
35 #include "hw/sysbus.h"
36 #include "audio/audio.h"
37
38 /* Enhanced Audio Controller (CODEC only) */
39 struct omap_eac_s {
40 qemu_irq irq;
41 MemoryRegion iomem;
42
43 uint16_t sysconfig;
44 uint8_t config[4];
45 uint8_t control;
46 uint8_t address;
47 uint16_t data;
48 uint8_t vtol;
49 uint8_t vtsl;
50 uint16_t mixer;
51 uint16_t gain[4];
52 uint8_t att;
53 uint16_t max[7];
54
55 struct {
56 qemu_irq txdrq;
57 qemu_irq rxdrq;
58 uint32_t (*txrx)(void *opaque, uint32_t, int);
59 void *opaque;
60
61 #define EAC_BUF_LEN 1024
62 uint32_t rxbuf[EAC_BUF_LEN];
63 int rxoff;
64 int rxlen;
65 int rxavail;
66 uint32_t txbuf[EAC_BUF_LEN];
67 int txlen;
68 int txavail;
69
70 int enable;
71 int rate;
72
73 uint16_t config[4];
74
75 /* These need to be moved to the actual codec */
76 QEMUSoundCard card;
77 SWVoiceIn *in_voice;
78 SWVoiceOut *out_voice;
79 int hw_enable;
80 } codec;
81
82 struct {
83 uint8_t control;
84 uint16_t config;
85 } modem, bt;
86 };
87
88 static inline void omap_eac_interrupt_update(struct omap_eac_s *s)
89 {
90 qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */
91 }
92
93 static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s)
94 {
95 qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) &&
96 ((s->codec.config[1] >> 12) & 1)); /* DMAREN */
97 }
98
99 static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s)
100 {
101 qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail &&
102 ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */
103 }
104
105 static inline void omap_eac_in_refill(struct omap_eac_s *s)
106 {
107 int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2;
108 int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2;
109 int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start);
110 int recv = 1;
111 uint8_t *buf = (uint8_t *) s->codec.rxbuf + start;
112
113 left -= leftwrap;
114 start = 0;
115 while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start,
116 leftwrap)) > 0) { /* Be defensive */
117 start += recv;
118 leftwrap -= recv;
119 }
120 if (recv <= 0)
121 s->codec.rxavail = 0;
122 else
123 s->codec.rxavail -= start >> 2;
124 s->codec.rxlen += start >> 2;
125
126 if (recv > 0 && left > 0) {
127 start = 0;
128 while (left && (recv = AUD_read(s->codec.in_voice,
129 (uint8_t *) s->codec.rxbuf + start,
130 left)) > 0) { /* Be defensive */
131 start += recv;
132 left -= recv;
133 }
134 if (recv <= 0)
135 s->codec.rxavail = 0;
136 else
137 s->codec.rxavail -= start >> 2;
138 s->codec.rxlen += start >> 2;
139 }
140 }
141
142 static inline void omap_eac_out_empty(struct omap_eac_s *s)
143 {
144 int left = s->codec.txlen << 2;
145 int start = 0;
146 int sent = 1;
147
148 while (left && (sent = AUD_write(s->codec.out_voice,
149 (uint8_t *) s->codec.txbuf + start,
150 left)) > 0) { /* Be defensive */
151 start += sent;
152 left -= sent;
153 }
154
155 if (!sent) {
156 s->codec.txavail = 0;
157 omap_eac_out_dmarequest_update(s);
158 }
159
160 if (start)
161 s->codec.txlen = 0;
162 }
163
164 static void omap_eac_in_cb(void *opaque, int avail_b)
165 {
166 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
167
168 s->codec.rxavail = avail_b >> 2;
169 omap_eac_in_refill(s);
170 /* TODO: possibly discard current buffer if overrun */
171 omap_eac_in_dmarequest_update(s);
172 }
173
174 static void omap_eac_out_cb(void *opaque, int free_b)
175 {
176 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
177
178 s->codec.txavail = free_b >> 2;
179 if (s->codec.txlen)
180 omap_eac_out_empty(s);
181 else
182 omap_eac_out_dmarequest_update(s);
183 }
184
185 static void omap_eac_enable_update(struct omap_eac_s *s)
186 {
187 s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */
188 (s->codec.config[1] & 2) && /* AUDEN */
189 s->codec.hw_enable;
190 }
191
192 static const int omap_eac_fsint[4] = {
193 8000,
194 11025,
195 22050,
196 44100,
197 };
198
199 static const int omap_eac_fsint2[8] = {
200 8000,
201 11025,
202 22050,
203 44100,
204 48000,
205 0, 0, 0,
206 };
207
208 static const int omap_eac_fsint3[16] = {
209 8000,
210 11025,
211 16000,
212 22050,
213 24000,
214 32000,
215 44100,
216 48000,
217 0, 0, 0, 0, 0, 0, 0, 0,
218 };
219
220 static void omap_eac_rate_update(struct omap_eac_s *s)
221 {
222 int fsint[3];
223
224 fsint[2] = (s->codec.config[3] >> 9) & 0xf;
225 fsint[1] = (s->codec.config[2] >> 0) & 0x7;
226 fsint[0] = (s->codec.config[0] >> 6) & 0x3;
227 if (fsint[2] < 0xf)
228 s->codec.rate = omap_eac_fsint3[fsint[2]];
229 else if (fsint[1] < 0x7)
230 s->codec.rate = omap_eac_fsint2[fsint[1]];
231 else
232 s->codec.rate = omap_eac_fsint[fsint[0]];
233 }
234
235 static void omap_eac_volume_update(struct omap_eac_s *s)
236 {
237 /* TODO */
238 }
239
240 static void omap_eac_format_update(struct omap_eac_s *s)
241 {
242 struct audsettings fmt;
243
244 /* The hardware buffers at most one sample */
245 if (s->codec.rxlen)
246 s->codec.rxlen = 1;
247
248 if (s->codec.in_voice) {
249 AUD_set_active_in(s->codec.in_voice, 0);
250 AUD_close_in(&s->codec.card, s->codec.in_voice);
251 s->codec.in_voice = NULL;
252 }
253 if (s->codec.out_voice) {
254 omap_eac_out_empty(s);
255 AUD_set_active_out(s->codec.out_voice, 0);
256 AUD_close_out(&s->codec.card, s->codec.out_voice);
257 s->codec.out_voice = NULL;
258 s->codec.txavail = 0;
259 }
260 /* Discard what couldn't be written */
261 s->codec.txlen = 0;
262
263 omap_eac_enable_update(s);
264 if (!s->codec.enable)
265 return;
266
267 omap_eac_rate_update(s);
268 fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */
269 fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */
270 fmt.freq = s->codec.rate;
271 /* TODO: signedness possibly depends on the CODEC hardware - or
272 * does I2S specify it? */
273 /* All register writes are 16 bits so we we store 16-bit samples
274 * in the buffers regardless of AGCFR[B8_16] value. */
275 fmt.fmt = AUDIO_FORMAT_U16;
276
277 s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice,
278 "eac.codec.in", s, omap_eac_in_cb, &fmt);
279 s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice,
280 "eac.codec.out", s, omap_eac_out_cb, &fmt);
281
282 omap_eac_volume_update(s);
283
284 AUD_set_active_in(s->codec.in_voice, 1);
285 AUD_set_active_out(s->codec.out_voice, 1);
286 }
287
288 static void omap_eac_reset(struct omap_eac_s *s)
289 {
290 s->sysconfig = 0;
291 s->config[0] = 0x0c;
292 s->config[1] = 0x09;
293 s->config[2] = 0xab;
294 s->config[3] = 0x03;
295 s->control = 0x00;
296 s->address = 0x00;
297 s->data = 0x0000;
298 s->vtol = 0x00;
299 s->vtsl = 0x00;
300 s->mixer = 0x0000;
301 s->gain[0] = 0xe7e7;
302 s->gain[1] = 0x6767;
303 s->gain[2] = 0x6767;
304 s->gain[3] = 0x6767;
305 s->att = 0xce;
306 s->max[0] = 0;
307 s->max[1] = 0;
308 s->max[2] = 0;
309 s->max[3] = 0;
310 s->max[4] = 0;
311 s->max[5] = 0;
312 s->max[6] = 0;
313
314 s->modem.control = 0x00;
315 s->modem.config = 0x0000;
316 s->bt.control = 0x00;
317 s->bt.config = 0x0000;
318 s->codec.config[0] = 0x0649;
319 s->codec.config[1] = 0x0000;
320 s->codec.config[2] = 0x0007;
321 s->codec.config[3] = 0x1ffc;
322 s->codec.rxoff = 0;
323 s->codec.rxlen = 0;
324 s->codec.txlen = 0;
325 s->codec.rxavail = 0;
326 s->codec.txavail = 0;
327
328 omap_eac_format_update(s);
329 omap_eac_interrupt_update(s);
330 }
331
332 static uint64_t omap_eac_read(void *opaque, hwaddr addr,
333 unsigned size)
334 {
335 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
336 uint32_t ret;
337
338 if (size != 2) {
339 return omap_badwidth_read16(opaque, addr);
340 }
341
342 switch (addr) {
343 case 0x000: /* CPCFR1 */
344 return s->config[0];
345 case 0x004: /* CPCFR2 */
346 return s->config[1];
347 case 0x008: /* CPCFR3 */
348 return s->config[2];
349 case 0x00c: /* CPCFR4 */
350 return s->config[3];
351
352 case 0x010: /* CPTCTL */
353 return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) |
354 ((s->codec.txlen < s->codec.txavail) << 5);
355
356 case 0x014: /* CPTTADR */
357 return s->address;
358 case 0x018: /* CPTDATL */
359 return s->data & 0xff;
360 case 0x01c: /* CPTDATH */
361 return s->data >> 8;
362 case 0x020: /* CPTVSLL */
363 return s->vtol;
364 case 0x024: /* CPTVSLH */
365 return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */
366 case 0x040: /* MPCTR */
367 return s->modem.control;
368 case 0x044: /* MPMCCFR */
369 return s->modem.config;
370 case 0x060: /* BPCTR */
371 return s->bt.control;
372 case 0x064: /* BPMCCFR */
373 return s->bt.config;
374 case 0x080: /* AMSCFR */
375 return s->mixer;
376 case 0x084: /* AMVCTR */
377 return s->gain[0];
378 case 0x088: /* AM1VCTR */
379 return s->gain[1];
380 case 0x08c: /* AM2VCTR */
381 return s->gain[2];
382 case 0x090: /* AM3VCTR */
383 return s->gain[3];
384 case 0x094: /* ASTCTR */
385 return s->att;
386 case 0x098: /* APD1LCR */
387 return s->max[0];
388 case 0x09c: /* APD1RCR */
389 return s->max[1];
390 case 0x0a0: /* APD2LCR */
391 return s->max[2];
392 case 0x0a4: /* APD2RCR */
393 return s->max[3];
394 case 0x0a8: /* APD3LCR */
395 return s->max[4];
396 case 0x0ac: /* APD3RCR */
397 return s->max[5];
398 case 0x0b0: /* APD4R */
399 return s->max[6];
400 case 0x0b4: /* ADWR */
401 /* This should be write-only? Docs list it as read-only. */
402 return 0x0000;
403 case 0x0b8: /* ADRDR */
404 if (likely(s->codec.rxlen > 1)) {
405 ret = s->codec.rxbuf[s->codec.rxoff ++];
406 s->codec.rxlen --;
407 s->codec.rxoff &= EAC_BUF_LEN - 1;
408 return ret;
409 } else if (s->codec.rxlen) {
410 ret = s->codec.rxbuf[s->codec.rxoff ++];
411 s->codec.rxlen --;
412 s->codec.rxoff &= EAC_BUF_LEN - 1;
413 if (s->codec.rxavail)
414 omap_eac_in_refill(s);
415 omap_eac_in_dmarequest_update(s);
416 return ret;
417 }
418 return 0x0000;
419 case 0x0bc: /* AGCFR */
420 return s->codec.config[0];
421 case 0x0c0: /* AGCTR */
422 return s->codec.config[1] | ((s->codec.config[1] & 2) << 14);
423 case 0x0c4: /* AGCFR2 */
424 return s->codec.config[2];
425 case 0x0c8: /* AGCFR3 */
426 return s->codec.config[3];
427 case 0x0cc: /* MBPDMACTR */
428 case 0x0d0: /* MPDDMARR */
429 case 0x0d8: /* MPUDMARR */
430 case 0x0e4: /* BPDDMARR */
431 case 0x0ec: /* BPUDMARR */
432 return 0x0000;
433
434 case 0x100: /* VERSION_NUMBER */
435 return 0x0010;
436
437 case 0x104: /* SYSCONFIG */
438 return s->sysconfig;
439
440 case 0x108: /* SYSSTATUS */
441 return 1 | 0xe; /* RESETDONE | stuff */
442 }
443
444 OMAP_BAD_REG(addr);
445 return 0;
446 }
447
448 static void omap_eac_write(void *opaque, hwaddr addr,
449 uint64_t value, unsigned size)
450 {
451 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
452
453 if (size != 2) {
454 omap_badwidth_write16(opaque, addr, value);
455 return;
456 }
457
458 switch (addr) {
459 case 0x098: /* APD1LCR */
460 case 0x09c: /* APD1RCR */
461 case 0x0a0: /* APD2LCR */
462 case 0x0a4: /* APD2RCR */
463 case 0x0a8: /* APD3LCR */
464 case 0x0ac: /* APD3RCR */
465 case 0x0b0: /* APD4R */
466 case 0x0b8: /* ADRDR */
467 case 0x0d0: /* MPDDMARR */
468 case 0x0d8: /* MPUDMARR */
469 case 0x0e4: /* BPDDMARR */
470 case 0x0ec: /* BPUDMARR */
471 case 0x100: /* VERSION_NUMBER */
472 case 0x108: /* SYSSTATUS */
473 OMAP_RO_REG(addr);
474 return;
475
476 case 0x000: /* CPCFR1 */
477 s->config[0] = value & 0xff;
478 omap_eac_format_update(s);
479 break;
480 case 0x004: /* CPCFR2 */
481 s->config[1] = value & 0xff;
482 omap_eac_format_update(s);
483 break;
484 case 0x008: /* CPCFR3 */
485 s->config[2] = value & 0xff;
486 omap_eac_format_update(s);
487 break;
488 case 0x00c: /* CPCFR4 */
489 s->config[3] = value & 0xff;
490 omap_eac_format_update(s);
491 break;
492
493 case 0x010: /* CPTCTL */
494 /* Assuming TXF and TXE bits are read-only... */
495 s->control = value & 0x5f;
496 omap_eac_interrupt_update(s);
497 break;
498
499 case 0x014: /* CPTTADR */
500 s->address = value & 0xff;
501 break;
502 case 0x018: /* CPTDATL */
503 s->data &= 0xff00;
504 s->data |= value & 0xff;
505 break;
506 case 0x01c: /* CPTDATH */
507 s->data &= 0x00ff;
508 s->data |= value << 8;
509 break;
510 case 0x020: /* CPTVSLL */
511 s->vtol = value & 0xf8;
512 break;
513 case 0x024: /* CPTVSLH */
514 s->vtsl = value & 0x9f;
515 break;
516 case 0x040: /* MPCTR */
517 s->modem.control = value & 0x8f;
518 break;
519 case 0x044: /* MPMCCFR */
520 s->modem.config = value & 0x7fff;
521 break;
522 case 0x060: /* BPCTR */
523 s->bt.control = value & 0x8f;
524 break;
525 case 0x064: /* BPMCCFR */
526 s->bt.config = value & 0x7fff;
527 break;
528 case 0x080: /* AMSCFR */
529 s->mixer = value & 0x0fff;
530 break;
531 case 0x084: /* AMVCTR */
532 s->gain[0] = value & 0xffff;
533 break;
534 case 0x088: /* AM1VCTR */
535 s->gain[1] = value & 0xff7f;
536 break;
537 case 0x08c: /* AM2VCTR */
538 s->gain[2] = value & 0xff7f;
539 break;
540 case 0x090: /* AM3VCTR */
541 s->gain[3] = value & 0xff7f;
542 break;
543 case 0x094: /* ASTCTR */
544 s->att = value & 0xff;
545 break;
546
547 case 0x0b4: /* ADWR */
548 s->codec.txbuf[s->codec.txlen ++] = value;
549 if (unlikely(s->codec.txlen == EAC_BUF_LEN ||
550 s->codec.txlen == s->codec.txavail)) {
551 if (s->codec.txavail)
552 omap_eac_out_empty(s);
553 /* Discard what couldn't be written */
554 s->codec.txlen = 0;
555 }
556 break;
557
558 case 0x0bc: /* AGCFR */
559 s->codec.config[0] = value & 0x07ff;
560 omap_eac_format_update(s);
561 break;
562 case 0x0c0: /* AGCTR */
563 s->codec.config[1] = value & 0x780f;
564 omap_eac_format_update(s);
565 break;
566 case 0x0c4: /* AGCFR2 */
567 s->codec.config[2] = value & 0x003f;
568 omap_eac_format_update(s);
569 break;
570 case 0x0c8: /* AGCFR3 */
571 s->codec.config[3] = value & 0xffff;
572 omap_eac_format_update(s);
573 break;
574 case 0x0cc: /* MBPDMACTR */
575 case 0x0d4: /* MPDDMAWR */
576 case 0x0e0: /* MPUDMAWR */
577 case 0x0e8: /* BPDDMAWR */
578 case 0x0f0: /* BPUDMAWR */
579 break;
580
581 case 0x104: /* SYSCONFIG */
582 if (value & (1 << 1)) /* SOFTRESET */
583 omap_eac_reset(s);
584 s->sysconfig = value & 0x31d;
585 break;
586
587 default:
588 OMAP_BAD_REG(addr);
589 return;
590 }
591 }
592
593 static const MemoryRegionOps omap_eac_ops = {
594 .read = omap_eac_read,
595 .write = omap_eac_write,
596 .endianness = DEVICE_NATIVE_ENDIAN,
597 };
598
599 static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
600 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
601 {
602 struct omap_eac_s *s = g_new0(struct omap_eac_s, 1);
603
604 s->irq = irq;
605 s->codec.rxdrq = *drq ++;
606 s->codec.txdrq = *drq;
607 omap_eac_reset(s);
608
609 AUD_register_card("OMAP EAC", &s->codec.card);
610
611 memory_region_init_io(&s->iomem, NULL, &omap_eac_ops, s, "omap.eac",
612 omap_l4_region_size(ta, 0));
613 omap_l4_attach(ta, 0, &s->iomem);
614
615 return s;
616 }
617
618 /* STI/XTI (emulation interface) console - reverse engineered only */
619 struct omap_sti_s {
620 qemu_irq irq;
621 MemoryRegion iomem;
622 MemoryRegion iomem_fifo;
623 CharBackend chr;
624
625 uint32_t sysconfig;
626 uint32_t systest;
627 uint32_t irqst;
628 uint32_t irqen;
629 uint32_t clkcontrol;
630 uint32_t serial_config;
631 };
632
633 #define STI_TRACE_CONSOLE_CHANNEL 239
634 #define STI_TRACE_CONTROL_CHANNEL 253
635
636 static inline void omap_sti_interrupt_update(struct omap_sti_s *s)
637 {
638 qemu_set_irq(s->irq, s->irqst & s->irqen);
639 }
640
641 static void omap_sti_reset(struct omap_sti_s *s)
642 {
643 s->sysconfig = 0;
644 s->irqst = 0;
645 s->irqen = 0;
646 s->clkcontrol = 0;
647 s->serial_config = 0;
648
649 omap_sti_interrupt_update(s);
650 }
651
652 static uint64_t omap_sti_read(void *opaque, hwaddr addr,
653 unsigned size)
654 {
655 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
656
657 if (size != 4) {
658 return omap_badwidth_read32(opaque, addr);
659 }
660
661 switch (addr) {
662 case 0x00: /* STI_REVISION */
663 return 0x10;
664
665 case 0x10: /* STI_SYSCONFIG */
666 return s->sysconfig;
667
668 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
669 return 0x00;
670
671 case 0x18: /* STI_IRQSTATUS */
672 return s->irqst;
673
674 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
675 return s->irqen;
676
677 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
678 case 0x28: /* STI_RX_DR / XTI_RXDATA */
679 /* TODO */
680 return 0;
681
682 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
683 return s->clkcontrol;
684
685 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
686 return s->serial_config;
687 }
688
689 OMAP_BAD_REG(addr);
690 return 0;
691 }
692
693 static void omap_sti_write(void *opaque, hwaddr addr,
694 uint64_t value, unsigned size)
695 {
696 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
697
698 if (size != 4) {
699 omap_badwidth_write32(opaque, addr, value);
700 return;
701 }
702
703 switch (addr) {
704 case 0x00: /* STI_REVISION */
705 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
706 OMAP_RO_REG(addr);
707 return;
708
709 case 0x10: /* STI_SYSCONFIG */
710 if (value & (1 << 1)) /* SOFTRESET */
711 omap_sti_reset(s);
712 s->sysconfig = value & 0xfe;
713 break;
714
715 case 0x18: /* STI_IRQSTATUS */
716 s->irqst &= ~value;
717 omap_sti_interrupt_update(s);
718 break;
719
720 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
721 s->irqen = value & 0xffff;
722 omap_sti_interrupt_update(s);
723 break;
724
725 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
726 s->clkcontrol = value & 0xff;
727 break;
728
729 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
730 s->serial_config = value & 0xff;
731 break;
732
733 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
734 case 0x28: /* STI_RX_DR / XTI_RXDATA */
735 /* TODO */
736 return;
737
738 default:
739 OMAP_BAD_REG(addr);
740 return;
741 }
742 }
743
744 static const MemoryRegionOps omap_sti_ops = {
745 .read = omap_sti_read,
746 .write = omap_sti_write,
747 .endianness = DEVICE_NATIVE_ENDIAN,
748 };
749
750 static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
751 unsigned size)
752 {
753 OMAP_BAD_REG(addr);
754 return 0;
755 }
756
757 static void omap_sti_fifo_write(void *opaque, hwaddr addr,
758 uint64_t value, unsigned size)
759 {
760 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
761 int ch = addr >> 6;
762 uint8_t byte = value;
763
764 if (size != 1) {
765 omap_badwidth_write8(opaque, addr, size);
766 return;
767 }
768
769 if (ch == STI_TRACE_CONTROL_CHANNEL) {
770 /* Flush channel <i>value</i>. */
771 /* XXX this blocks entire thread. Rewrite to use
772 * qemu_chr_fe_write and background I/O callbacks */
773 qemu_chr_fe_write_all(&s->chr, (const uint8_t *) "\r", 1);
774 } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
775 if (value == 0xc0 || value == 0xc3) {
776 /* Open channel <i>ch</i>. */
777 } else if (value == 0x00) {
778 qemu_chr_fe_write_all(&s->chr, (const uint8_t *) "\n", 1);
779 } else {
780 qemu_chr_fe_write_all(&s->chr, &byte, 1);
781 }
782 }
783 }
784
785 static const MemoryRegionOps omap_sti_fifo_ops = {
786 .read = omap_sti_fifo_read,
787 .write = omap_sti_fifo_write,
788 .endianness = DEVICE_NATIVE_ENDIAN,
789 };
790
791 static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
792 MemoryRegion *sysmem,
793 hwaddr channel_base, qemu_irq irq, omap_clk clk,
794 Chardev *chr)
795 {
796 struct omap_sti_s *s = g_new0(struct omap_sti_s, 1);
797
798 s->irq = irq;
799 omap_sti_reset(s);
800
801 qemu_chr_fe_init(&s->chr, chr ?: qemu_chr_new("null", "null", NULL),
802 &error_abort);
803
804 memory_region_init_io(&s->iomem, NULL, &omap_sti_ops, s, "omap.sti",
805 omap_l4_region_size(ta, 0));
806 omap_l4_attach(ta, 0, &s->iomem);
807
808 memory_region_init_io(&s->iomem_fifo, NULL, &omap_sti_fifo_ops, s,
809 "omap.sti.fifo", 0x10000);
810 memory_region_add_subregion(sysmem, channel_base, &s->iomem_fifo);
811
812 return s;
813 }
814
815 /* L4 Interconnect */
816 #define L4TA(n) (n)
817 #define L4TAO(n) ((n) + 39)
818
819 static const struct omap_l4_region_s omap_l4_region[125] = {
820 [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */
821 [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */
822 [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */
823 [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */
824 [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */
825 [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */
826 [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */
827 [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */
828 [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */
829 [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */
830 [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */
831 [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */
832 [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */
833 [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */
834 [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */
835 [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */
836 [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */
837 [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */
838 [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */
839 [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */
840 [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */
841 [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */
842 [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */
843 [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */
844 [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */
845 [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */
846 [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */
847 [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */
848 [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */
849 [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */
850 [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */
851 [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */
852 [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */
853 [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */
854 [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */
855 [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */
856 [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */
857 [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */
858 [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */
859 [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */
860 [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */
861 [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */
862 [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */
863 [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */
864 [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */
865 [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */
866 [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */
867 [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */
868 [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */
869 [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */
870 [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */
871 [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */
872 [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */
873 [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */
874 [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */
875 [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */
876 [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */
877 [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */
878 [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */
879 [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */
880 [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */
881 [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */
882 [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */
883 [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */
884 [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */
885 [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */
886 [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */
887 [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */
888 [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */
889 [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */
890 [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */
891 [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */
892 [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */
893 [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */
894 [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */
895 [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */
896 [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */
897 [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */
898 [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */
899 [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */
900 [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */
901 [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */
902 [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */
903 [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */
904 [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */
905 [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */
906 [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */
907 [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */
908 [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */
909 [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */
910 [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */
911 [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */
912 [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */
913 [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */
914 [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */
915 [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */
916 [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */
917 [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */
918 [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */
919 [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */
920 [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */
921 [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */
922 [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */
923 [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */
924 [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */
925 [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */
926 [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */
927 [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */
928 [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */
929 [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */
930 [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */
931 [111] = { 0xa0000, 0x1000, 32 }, /* RNG */
932 [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */
933 [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */
934 [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */
935 [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */
936 [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */
937 [117] = { 0xa6000, 0x1000, 32 }, /* AES */
938 [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */
939 [119] = { 0xa8000, 0x2000, 32 }, /* PKA */
940 [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */
941 [121] = { 0xb0000, 0x1000, 32 }, /* MG */
942 [122] = { 0xb1000, 0x1000, 32 | 16 | 8 },
943 [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */
944 [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */
945 };
946
947 static const struct omap_l4_agent_info_s omap_l4_agent_info[54] = {
948 { 0, 0, 3, 2 }, /* L4IA initiatior agent */
949 { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */
950 { L4TAO(2), 5, 2, 1 }, /* 32K timer */
951 { L4TAO(3), 7, 3, 2 }, /* PRCM */
952 { L4TA(1), 10, 2, 1 }, /* BCM */
953 { L4TA(2), 12, 2, 1 }, /* Test JTAG */
954 { L4TA(3), 14, 6, 3 }, /* Quad GPIO */
955 { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */
956 { L4TA(7), 24, 2, 1 }, /* GP timer 1 */
957 { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */
958 { L4TA(10), 28, 5, 4 }, /* Display subsystem */
959 { L4TA(11), 33, 5, 4 }, /* Camera subsystem */
960 { L4TA(12), 38, 2, 1 }, /* sDMA */
961 { L4TA(13), 40, 5, 4 }, /* SSI */
962 { L4TAO(4), 45, 2, 1 }, /* USB */
963 { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */
964 { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */
965 { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */
966 { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */
967 { L4TA(18), 55, 2, 1 }, /* XTI */
968 { L4TA(19), 57, 2, 1 }, /* UART1 */
969 { L4TA(20), 59, 2, 1 }, /* UART2 */
970 { L4TA(21), 61, 2, 1 }, /* UART3 */
971 { L4TAO(5), 63, 2, 1 }, /* I2C1 */
972 { L4TAO(6), 65, 2, 1 }, /* I2C2 */
973 { L4TAO(7), 67, 2, 1 }, /* McBSP1 */
974 { L4TAO(8), 69, 2, 1 }, /* McBSP2 */
975 { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */
976 { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */
977 { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */
978 { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */
979 { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */
980 { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */
981 { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */
982 { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */
983 { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */
984 { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */
985 { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */
986 { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */
987 { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */
988 { L4TA(32), 97, 2, 1 }, /* EAC */
989 { L4TA(33), 99, 2, 1 }, /* FAC */
990 { L4TA(34), 101, 2, 1 }, /* IPC */
991 { L4TA(35), 103, 2, 1 }, /* SPI1 */
992 { L4TA(36), 105, 2, 1 }, /* SPI2 */
993 { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */
994 { L4TAO(10), 109, 2, 1 },
995 { L4TAO(11), 111, 2, 1 }, /* RNG */
996 { L4TAO(12), 113, 2, 1 }, /* DES3DES */
997 { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */
998 { L4TA(37), 117, 2, 1 }, /* AES */
999 { L4TA(38), 119, 2, 1 }, /* PKA */
1000 { -1, 121, 2, 1 },
1001 { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */
1002 };
1003
1004 #define omap_l4ta(bus, cs) \
1005 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TA(cs))
1006 #define omap_l4tao(bus, cs) \
1007 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TAO(cs))
1008
1009 /* Power, Reset, and Clock Management */
1010 struct omap_prcm_s {
1011 qemu_irq irq[3];
1012 struct omap_mpu_state_s *mpu;
1013 MemoryRegion iomem0;
1014 MemoryRegion iomem1;
1015
1016 uint32_t irqst[3];
1017 uint32_t irqen[3];
1018
1019 uint32_t sysconfig;
1020 uint32_t voltctrl;
1021 uint32_t scratch[20];
1022
1023 uint32_t clksrc[1];
1024 uint32_t clkout[1];
1025 uint32_t clkemul[1];
1026 uint32_t clkpol[1];
1027 uint32_t clksel[8];
1028 uint32_t clken[12];
1029 uint32_t clkctrl[4];
1030 uint32_t clkidle[7];
1031 uint32_t setuptime[2];
1032
1033 uint32_t wkup[3];
1034 uint32_t wken[3];
1035 uint32_t wkst[3];
1036 uint32_t rst[4];
1037 uint32_t rstctrl[1];
1038 uint32_t power[4];
1039 uint32_t rsttime_wkup;
1040
1041 uint32_t ev;
1042 uint32_t evtime[2];
1043
1044 int dpll_lock, apll_lock[2];
1045 };
1046
1047 static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
1048 {
1049 qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]);
1050 /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
1051 }
1052
1053 static uint64_t omap_prcm_read(void *opaque, hwaddr addr,
1054 unsigned size)
1055 {
1056 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
1057 uint32_t ret;
1058
1059 if (size != 4) {
1060 return omap_badwidth_read32(opaque, addr);
1061 }
1062
1063 switch (addr) {
1064 case 0x000: /* PRCM_REVISION */
1065 return 0x10;
1066
1067 case 0x010: /* PRCM_SYSCONFIG */
1068 return s->sysconfig;
1069
1070 case 0x018: /* PRCM_IRQSTATUS_MPU */
1071 return s->irqst[0];
1072
1073 case 0x01c: /* PRCM_IRQENABLE_MPU */
1074 return s->irqen[0];
1075
1076 case 0x050: /* PRCM_VOLTCTRL */
1077 return s->voltctrl;
1078 case 0x054: /* PRCM_VOLTST */
1079 return s->voltctrl & 3;
1080
1081 case 0x060: /* PRCM_CLKSRC_CTRL */
1082 return s->clksrc[0];
1083 case 0x070: /* PRCM_CLKOUT_CTRL */
1084 return s->clkout[0];
1085 case 0x078: /* PRCM_CLKEMUL_CTRL */
1086 return s->clkemul[0];
1087 case 0x080: /* PRCM_CLKCFG_CTRL */
1088 case 0x084: /* PRCM_CLKCFG_STATUS */
1089 return 0;
1090
1091 case 0x090: /* PRCM_VOLTSETUP */
1092 return s->setuptime[0];
1093
1094 case 0x094: /* PRCM_CLKSSETUP */
1095 return s->setuptime[1];
1096
1097 case 0x098: /* PRCM_POLCTRL */
1098 return s->clkpol[0];
1099
1100 case 0x0b0: /* GENERAL_PURPOSE1 */
1101 case 0x0b4: /* GENERAL_PURPOSE2 */
1102 case 0x0b8: /* GENERAL_PURPOSE3 */
1103 case 0x0bc: /* GENERAL_PURPOSE4 */
1104 case 0x0c0: /* GENERAL_PURPOSE5 */
1105 case 0x0c4: /* GENERAL_PURPOSE6 */
1106 case 0x0c8: /* GENERAL_PURPOSE7 */
1107 case 0x0cc: /* GENERAL_PURPOSE8 */
1108 case 0x0d0: /* GENERAL_PURPOSE9 */
1109 case 0x0d4: /* GENERAL_PURPOSE10 */
1110 case 0x0d8: /* GENERAL_PURPOSE11 */
1111 case 0x0dc: /* GENERAL_PURPOSE12 */
1112 case 0x0e0: /* GENERAL_PURPOSE13 */
1113 case 0x0e4: /* GENERAL_PURPOSE14 */
1114 case 0x0e8: /* GENERAL_PURPOSE15 */
1115 case 0x0ec: /* GENERAL_PURPOSE16 */
1116 case 0x0f0: /* GENERAL_PURPOSE17 */
1117 case 0x0f4: /* GENERAL_PURPOSE18 */
1118 case 0x0f8: /* GENERAL_PURPOSE19 */
1119 case 0x0fc: /* GENERAL_PURPOSE20 */
1120 return s->scratch[(addr - 0xb0) >> 2];
1121
1122 case 0x140: /* CM_CLKSEL_MPU */
1123 return s->clksel[0];
1124 case 0x148: /* CM_CLKSTCTRL_MPU */
1125 return s->clkctrl[0];
1126
1127 case 0x158: /* RM_RSTST_MPU */
1128 return s->rst[0];
1129 case 0x1c8: /* PM_WKDEP_MPU */
1130 return s->wkup[0];
1131 case 0x1d4: /* PM_EVGENCTRL_MPU */
1132 return s->ev;
1133 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1134 return s->evtime[0];
1135 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1136 return s->evtime[1];
1137 case 0x1e0: /* PM_PWSTCTRL_MPU */
1138 return s->power[0];
1139 case 0x1e4: /* PM_PWSTST_MPU */
1140 return 0;
1141
1142 case 0x200: /* CM_FCLKEN1_CORE */
1143 return s->clken[0];
1144 case 0x204: /* CM_FCLKEN2_CORE */
1145 return s->clken[1];
1146 case 0x210: /* CM_ICLKEN1_CORE */
1147 return s->clken[2];
1148 case 0x214: /* CM_ICLKEN2_CORE */
1149 return s->clken[3];
1150 case 0x21c: /* CM_ICLKEN4_CORE */
1151 return s->clken[4];
1152
1153 case 0x220: /* CM_IDLEST1_CORE */
1154 /* TODO: check the actual iclk status */
1155 return 0x7ffffff9;
1156 case 0x224: /* CM_IDLEST2_CORE */
1157 /* TODO: check the actual iclk status */
1158 return 0x00000007;
1159 case 0x22c: /* CM_IDLEST4_CORE */
1160 /* TODO: check the actual iclk status */
1161 return 0x0000001f;
1162
1163 case 0x230: /* CM_AUTOIDLE1_CORE */
1164 return s->clkidle[0];
1165 case 0x234: /* CM_AUTOIDLE2_CORE */
1166 return s->clkidle[1];
1167 case 0x238: /* CM_AUTOIDLE3_CORE */
1168 return s->clkidle[2];
1169 case 0x23c: /* CM_AUTOIDLE4_CORE */
1170 return s->clkidle[3];
1171
1172 case 0x240: /* CM_CLKSEL1_CORE */
1173 return s->clksel[1];
1174 case 0x244: /* CM_CLKSEL2_CORE */
1175 return s->clksel[2];
1176
1177 case 0x248: /* CM_CLKSTCTRL_CORE */
1178 return s->clkctrl[1];
1179
1180 case 0x2a0: /* PM_WKEN1_CORE */
1181 return s->wken[0];
1182 case 0x2a4: /* PM_WKEN2_CORE */
1183 return s->wken[1];
1184
1185 case 0x2b0: /* PM_WKST1_CORE */
1186 return s->wkst[0];
1187 case 0x2b4: /* PM_WKST2_CORE */
1188 return s->wkst[1];
1189 case 0x2c8: /* PM_WKDEP_CORE */
1190 return 0x1e;
1191
1192 case 0x2e0: /* PM_PWSTCTRL_CORE */
1193 return s->power[1];
1194 case 0x2e4: /* PM_PWSTST_CORE */
1195 return 0x000030 | (s->power[1] & 0xfc00);
1196
1197 case 0x300: /* CM_FCLKEN_GFX */
1198 return s->clken[5];
1199 case 0x310: /* CM_ICLKEN_GFX */
1200 return s->clken[6];
1201 case 0x320: /* CM_IDLEST_GFX */
1202 /* TODO: check the actual iclk status */
1203 return 0x00000001;
1204 case 0x340: /* CM_CLKSEL_GFX */
1205 return s->clksel[3];
1206 case 0x348: /* CM_CLKSTCTRL_GFX */
1207 return s->clkctrl[2];
1208 case 0x350: /* RM_RSTCTRL_GFX */
1209 return s->rstctrl[0];
1210 case 0x358: /* RM_RSTST_GFX */
1211 return s->rst[1];
1212 case 0x3c8: /* PM_WKDEP_GFX */
1213 return s->wkup[1];
1214
1215 case 0x3e0: /* PM_PWSTCTRL_GFX */
1216 return s->power[2];
1217 case 0x3e4: /* PM_PWSTST_GFX */
1218 return s->power[2] & 3;
1219
1220 case 0x400: /* CM_FCLKEN_WKUP */
1221 return s->clken[7];
1222 case 0x410: /* CM_ICLKEN_WKUP */
1223 return s->clken[8];
1224 case 0x420: /* CM_IDLEST_WKUP */
1225 /* TODO: check the actual iclk status */
1226 return 0x0000003f;
1227 case 0x430: /* CM_AUTOIDLE_WKUP */
1228 return s->clkidle[4];
1229 case 0x440: /* CM_CLKSEL_WKUP */
1230 return s->clksel[4];
1231 case 0x450: /* RM_RSTCTRL_WKUP */
1232 return 0;
1233 case 0x454: /* RM_RSTTIME_WKUP */
1234 return s->rsttime_wkup;
1235 case 0x458: /* RM_RSTST_WKUP */
1236 return s->rst[2];
1237 case 0x4a0: /* PM_WKEN_WKUP */
1238 return s->wken[2];
1239 case 0x4b0: /* PM_WKST_WKUP */
1240 return s->wkst[2];
1241
1242 case 0x500: /* CM_CLKEN_PLL */
1243 return s->clken[9];
1244 case 0x520: /* CM_IDLEST_CKGEN */
1245 ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8);
1246 if (!(s->clksel[6] & 3))
1247 /* Core uses 32-kHz clock */
1248 ret |= 3 << 0;
1249 else if (!s->dpll_lock)
1250 /* DPLL not locked, core uses ref_clk */
1251 ret |= 1 << 0;
1252 else
1253 /* Core uses DPLL */
1254 ret |= 2 << 0;
1255 return ret;
1256 case 0x530: /* CM_AUTOIDLE_PLL */
1257 return s->clkidle[5];
1258 case 0x540: /* CM_CLKSEL1_PLL */
1259 return s->clksel[5];
1260 case 0x544: /* CM_CLKSEL2_PLL */
1261 return s->clksel[6];
1262
1263 case 0x800: /* CM_FCLKEN_DSP */
1264 return s->clken[10];
1265 case 0x810: /* CM_ICLKEN_DSP */
1266 return s->clken[11];
1267 case 0x820: /* CM_IDLEST_DSP */
1268 /* TODO: check the actual iclk status */
1269 return 0x00000103;
1270 case 0x830: /* CM_AUTOIDLE_DSP */
1271 return s->clkidle[6];
1272 case 0x840: /* CM_CLKSEL_DSP */
1273 return s->clksel[7];
1274 case 0x848: /* CM_CLKSTCTRL_DSP */
1275 return s->clkctrl[3];
1276 case 0x850: /* RM_RSTCTRL_DSP */
1277 return 0;
1278 case 0x858: /* RM_RSTST_DSP */
1279 return s->rst[3];
1280 case 0x8c8: /* PM_WKDEP_DSP */
1281 return s->wkup[2];
1282 case 0x8e0: /* PM_PWSTCTRL_DSP */
1283 return s->power[3];
1284 case 0x8e4: /* PM_PWSTST_DSP */
1285 return 0x008030 | (s->power[3] & 0x3003);
1286
1287 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
1288 return s->irqst[1];
1289 case 0x8f4: /* PRCM_IRQENABLE_DSP */
1290 return s->irqen[1];
1291
1292 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
1293 return s->irqst[2];
1294 case 0x8fc: /* PRCM_IRQENABLE_IVA */
1295 return s->irqen[2];
1296 }
1297
1298 OMAP_BAD_REG(addr);
1299 return 0;
1300 }
1301
1302 static void omap_prcm_apll_update(struct omap_prcm_s *s)
1303 {
1304 int mode[2];
1305
1306 mode[0] = (s->clken[9] >> 6) & 3;
1307 s->apll_lock[0] = (mode[0] == 3);
1308 mode[1] = (s->clken[9] >> 2) & 3;
1309 s->apll_lock[1] = (mode[1] == 3);
1310 /* TODO: update clocks */
1311
1312 if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[1] == 2)
1313 fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n",
1314 __func__);
1315 }
1316
1317 static void omap_prcm_dpll_update(struct omap_prcm_s *s)
1318 {
1319 omap_clk dpll = omap_findclk(s->mpu, "dpll");
1320 omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll");
1321 omap_clk core = omap_findclk(s->mpu, "core_clk");
1322 int mode = (s->clken[9] >> 0) & 3;
1323 int mult, div;
1324
1325 mult = (s->clksel[5] >> 12) & 0x3ff;
1326 div = (s->clksel[5] >> 8) & 0xf;
1327 if (mult == 0 || mult == 1)
1328 mode = 1; /* Bypass */
1329
1330 s->dpll_lock = 0;
1331 switch (mode) {
1332 case 0:
1333 fprintf(stderr, "%s: bad EN_DPLL\n", __func__);
1334 break;
1335 case 1: /* Low-power bypass mode (Default) */
1336 case 2: /* Fast-relock bypass mode */
1337 omap_clk_setrate(dpll, 1, 1);
1338 omap_clk_setrate(dpll_x2, 1, 1);
1339 break;
1340 case 3: /* Lock mode */
1341 s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */
1342
1343 omap_clk_setrate(dpll, div + 1, mult);
1344 omap_clk_setrate(dpll_x2, div + 1, mult * 2);
1345 break;
1346 }
1347
1348 switch ((s->clksel[6] >> 0) & 3) {
1349 case 0:
1350 omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz"));
1351 break;
1352 case 1:
1353 omap_clk_reparent(core, dpll);
1354 break;
1355 case 2:
1356 /* Default */
1357 omap_clk_reparent(core, dpll_x2);
1358 break;
1359 case 3:
1360 fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __func__);
1361 break;
1362 }
1363 }
1364
1365 static void omap_prcm_write(void *opaque, hwaddr addr,
1366 uint64_t value, unsigned size)
1367 {
1368 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
1369
1370 if (size != 4) {
1371 omap_badwidth_write32(opaque, addr, value);
1372 return;
1373 }
1374
1375 switch (addr) {
1376 case 0x000: /* PRCM_REVISION */
1377 case 0x054: /* PRCM_VOLTST */
1378 case 0x084: /* PRCM_CLKCFG_STATUS */
1379 case 0x1e4: /* PM_PWSTST_MPU */
1380 case 0x220: /* CM_IDLEST1_CORE */
1381 case 0x224: /* CM_IDLEST2_CORE */
1382 case 0x22c: /* CM_IDLEST4_CORE */
1383 case 0x2c8: /* PM_WKDEP_CORE */
1384 case 0x2e4: /* PM_PWSTST_CORE */
1385 case 0x320: /* CM_IDLEST_GFX */
1386 case 0x3e4: /* PM_PWSTST_GFX */
1387 case 0x420: /* CM_IDLEST_WKUP */
1388 case 0x520: /* CM_IDLEST_CKGEN */
1389 case 0x820: /* CM_IDLEST_DSP */
1390 case 0x8e4: /* PM_PWSTST_DSP */
1391 OMAP_RO_REG(addr);
1392 return;
1393
1394 case 0x010: /* PRCM_SYSCONFIG */
1395 s->sysconfig = value & 1;
1396 break;
1397
1398 case 0x018: /* PRCM_IRQSTATUS_MPU */
1399 s->irqst[0] &= ~value;
1400 omap_prcm_int_update(s, 0);
1401 break;
1402 case 0x01c: /* PRCM_IRQENABLE_MPU */
1403 s->irqen[0] = value & 0x3f;
1404 omap_prcm_int_update(s, 0);
1405 break;
1406
1407 case 0x050: /* PRCM_VOLTCTRL */
1408 s->voltctrl = value & 0xf1c3;
1409 break;
1410
1411 case 0x060: /* PRCM_CLKSRC_CTRL */
1412 s->clksrc[0] = value & 0xdb;
1413 /* TODO update clocks */
1414 break;
1415
1416 case 0x070: /* PRCM_CLKOUT_CTRL */
1417 s->clkout[0] = value & 0xbbbb;
1418 /* TODO update clocks */
1419 break;
1420
1421 case 0x078: /* PRCM_CLKEMUL_CTRL */
1422 s->clkemul[0] = value & 1;
1423 /* TODO update clocks */
1424 break;
1425
1426 case 0x080: /* PRCM_CLKCFG_CTRL */
1427 break;
1428
1429 case 0x090: /* PRCM_VOLTSETUP */
1430 s->setuptime[0] = value & 0xffff;
1431 break;
1432 case 0x094: /* PRCM_CLKSSETUP */
1433 s->setuptime[1] = value & 0xffff;
1434 break;
1435
1436 case 0x098: /* PRCM_POLCTRL */
1437 s->clkpol[0] = value & 0x701;
1438 break;
1439
1440 case 0x0b0: /* GENERAL_PURPOSE1 */
1441 case 0x0b4: /* GENERAL_PURPOSE2 */
1442 case 0x0b8: /* GENERAL_PURPOSE3 */
1443 case 0x0bc: /* GENERAL_PURPOSE4 */
1444 case 0x0c0: /* GENERAL_PURPOSE5 */
1445 case 0x0c4: /* GENERAL_PURPOSE6 */
1446 case 0x0c8: /* GENERAL_PURPOSE7 */
1447 case 0x0cc: /* GENERAL_PURPOSE8 */
1448 case 0x0d0: /* GENERAL_PURPOSE9 */
1449 case 0x0d4: /* GENERAL_PURPOSE10 */
1450 case 0x0d8: /* GENERAL_PURPOSE11 */
1451 case 0x0dc: /* GENERAL_PURPOSE12 */
1452 case 0x0e0: /* GENERAL_PURPOSE13 */
1453 case 0x0e4: /* GENERAL_PURPOSE14 */
1454 case 0x0e8: /* GENERAL_PURPOSE15 */
1455 case 0x0ec: /* GENERAL_PURPOSE16 */
1456 case 0x0f0: /* GENERAL_PURPOSE17 */
1457 case 0x0f4: /* GENERAL_PURPOSE18 */
1458 case 0x0f8: /* GENERAL_PURPOSE19 */
1459 case 0x0fc: /* GENERAL_PURPOSE20 */
1460 s->scratch[(addr - 0xb0) >> 2] = value;
1461 break;
1462
1463 case 0x140: /* CM_CLKSEL_MPU */
1464 s->clksel[0] = value & 0x1f;
1465 /* TODO update clocks */
1466 break;
1467 case 0x148: /* CM_CLKSTCTRL_MPU */
1468 s->clkctrl[0] = value & 0x1f;
1469 break;
1470
1471 case 0x158: /* RM_RSTST_MPU */
1472 s->rst[0] &= ~value;
1473 break;
1474 case 0x1c8: /* PM_WKDEP_MPU */
1475 s->wkup[0] = value & 0x15;
1476 break;
1477
1478 case 0x1d4: /* PM_EVGENCTRL_MPU */
1479 s->ev = value & 0x1f;
1480 break;
1481 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1482 s->evtime[0] = value;
1483 break;
1484 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1485 s->evtime[1] = value;
1486 break;
1487
1488 case 0x1e0: /* PM_PWSTCTRL_MPU */
1489 s->power[0] = value & 0xc0f;
1490 break;
1491
1492 case 0x200: /* CM_FCLKEN1_CORE */
1493 s->clken[0] = value & 0xbfffffff;
1494 /* TODO update clocks */
1495 /* The EN_EAC bit only gets/puts func_96m_clk. */
1496 break;
1497 case 0x204: /* CM_FCLKEN2_CORE */
1498 s->clken[1] = value & 0x00000007;
1499 /* TODO update clocks */
1500 break;
1501 case 0x210: /* CM_ICLKEN1_CORE */
1502 s->clken[2] = value & 0xfffffff9;
1503 /* TODO update clocks */
1504 /* The EN_EAC bit only gets/puts core_l4_iclk. */
1505 break;
1506 case 0x214: /* CM_ICLKEN2_CORE */
1507 s->clken[3] = value & 0x00000007;
1508 /* TODO update clocks */
1509 break;
1510 case 0x21c: /* CM_ICLKEN4_CORE */
1511 s->clken[4] = value & 0x0000001f;
1512 /* TODO update clocks */
1513 break;
1514
1515 case 0x230: /* CM_AUTOIDLE1_CORE */
1516 s->clkidle[0] = value & 0xfffffff9;
1517 /* TODO update clocks */
1518 break;
1519 case 0x234: /* CM_AUTOIDLE2_CORE */
1520 s->clkidle[1] = value & 0x00000007;
1521 /* TODO update clocks */
1522 break;
1523 case 0x238: /* CM_AUTOIDLE3_CORE */
1524 s->clkidle[2] = value & 0x00000007;
1525 /* TODO update clocks */
1526 break;
1527 case 0x23c: /* CM_AUTOIDLE4_CORE */
1528 s->clkidle[3] = value & 0x0000001f;
1529 /* TODO update clocks */
1530 break;
1531
1532 case 0x240: /* CM_CLKSEL1_CORE */
1533 s->clksel[1] = value & 0x0fffbf7f;
1534 /* TODO update clocks */
1535 break;
1536
1537 case 0x244: /* CM_CLKSEL2_CORE */
1538 s->clksel[2] = value & 0x00fffffc;
1539 /* TODO update clocks */
1540 break;
1541
1542 case 0x248: /* CM_CLKSTCTRL_CORE */
1543 s->clkctrl[1] = value & 0x7;
1544 break;
1545
1546 case 0x2a0: /* PM_WKEN1_CORE */
1547 s->wken[0] = value & 0x04667ff8;
1548 break;
1549 case 0x2a4: /* PM_WKEN2_CORE */
1550 s->wken[1] = value & 0x00000005;
1551 break;
1552
1553 case 0x2b0: /* PM_WKST1_CORE */
1554 s->wkst[0] &= ~value;
1555 break;
1556 case 0x2b4: /* PM_WKST2_CORE */
1557 s->wkst[1] &= ~value;
1558 break;
1559
1560 case 0x2e0: /* PM_PWSTCTRL_CORE */
1561 s->power[1] = (value & 0x00fc3f) | (1 << 2);
1562 break;
1563
1564 case 0x300: /* CM_FCLKEN_GFX */
1565 s->clken[5] = value & 6;
1566 /* TODO update clocks */
1567 break;
1568 case 0x310: /* CM_ICLKEN_GFX */
1569 s->clken[6] = value & 1;
1570 /* TODO update clocks */
1571 break;
1572 case 0x340: /* CM_CLKSEL_GFX */
1573 s->clksel[3] = value & 7;
1574 /* TODO update clocks */
1575 break;
1576 case 0x348: /* CM_CLKSTCTRL_GFX */
1577 s->clkctrl[2] = value & 1;
1578 break;
1579 case 0x350: /* RM_RSTCTRL_GFX */
1580 s->rstctrl[0] = value & 1;
1581 /* TODO: reset */
1582 break;
1583 case 0x358: /* RM_RSTST_GFX */
1584 s->rst[1] &= ~value;
1585 break;
1586 case 0x3c8: /* PM_WKDEP_GFX */
1587 s->wkup[1] = value & 0x13;
1588 break;
1589 case 0x3e0: /* PM_PWSTCTRL_GFX */
1590 s->power[2] = (value & 0x00c0f) | (3 << 2);
1591 break;
1592
1593 case 0x400: /* CM_FCLKEN_WKUP */
1594 s->clken[7] = value & 0xd;
1595 /* TODO update clocks */
1596 break;
1597 case 0x410: /* CM_ICLKEN_WKUP */
1598 s->clken[8] = value & 0x3f;
1599 /* TODO update clocks */
1600 break;
1601 case 0x430: /* CM_AUTOIDLE_WKUP */
1602 s->clkidle[4] = value & 0x0000003f;
1603 /* TODO update clocks */
1604 break;
1605 case 0x440: /* CM_CLKSEL_WKUP */
1606 s->clksel[4] = value & 3;
1607 /* TODO update clocks */
1608 break;
1609 case 0x450: /* RM_RSTCTRL_WKUP */
1610 /* TODO: reset */
1611 if (value & 2)
1612 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
1613 break;
1614 case 0x454: /* RM_RSTTIME_WKUP */
1615 s->rsttime_wkup = value & 0x1fff;
1616 break;
1617 case 0x458: /* RM_RSTST_WKUP */
1618 s->rst[2] &= ~value;
1619 break;
1620 case 0x4a0: /* PM_WKEN_WKUP */
1621 s->wken[2] = value & 0x00000005;
1622 break;
1623 case 0x4b0: /* PM_WKST_WKUP */
1624 s->wkst[2] &= ~value;
1625 break;
1626
1627 case 0x500: /* CM_CLKEN_PLL */
1628 if (value & 0xffffff30)
1629 fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for "
1630 "future compatibility\n", __func__);
1631 if ((s->clken[9] ^ value) & 0xcc) {
1632 s->clken[9] &= ~0xcc;
1633 s->clken[9] |= value & 0xcc;
1634 omap_prcm_apll_update(s);
1635 }
1636 if ((s->clken[9] ^ value) & 3) {
1637 s->clken[9] &= ~3;
1638 s->clken[9] |= value & 3;
1639 omap_prcm_dpll_update(s);
1640 }
1641 break;
1642 case 0x530: /* CM_AUTOIDLE_PLL */
1643 s->clkidle[5] = value & 0x000000cf;
1644 /* TODO update clocks */
1645 break;
1646 case 0x540: /* CM_CLKSEL1_PLL */
1647 if (value & 0xfc4000d7)
1648 fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for "
1649 "future compatibility\n", __func__);
1650 if ((s->clksel[5] ^ value) & 0x003fff00) {
1651 s->clksel[5] = value & 0x03bfff28;
1652 omap_prcm_dpll_update(s);
1653 }
1654 /* TODO update the other clocks */
1655
1656 s->clksel[5] = value & 0x03bfff28;
1657 break;
1658 case 0x544: /* CM_CLKSEL2_PLL */
1659 if (value & ~3)
1660 fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
1661 "future compatibility\n", __func__);
1662 if (s->clksel[6] != (value & 3)) {
1663 s->clksel[6] = value & 3;
1664 omap_prcm_dpll_update(s);
1665 }
1666 break;
1667
1668 case 0x800: /* CM_FCLKEN_DSP */
1669 s->clken[10] = value & 0x501;
1670 /* TODO update clocks */
1671 break;
1672 case 0x810: /* CM_ICLKEN_DSP */
1673 s->clken[11] = value & 0x2;
1674 /* TODO update clocks */
1675 break;
1676 case 0x830: /* CM_AUTOIDLE_DSP */
1677 s->clkidle[6] = value & 0x2;
1678 /* TODO update clocks */
1679 break;
1680 case 0x840: /* CM_CLKSEL_DSP */
1681 s->clksel[7] = value & 0x3fff;
1682 /* TODO update clocks */
1683 break;
1684 case 0x848: /* CM_CLKSTCTRL_DSP */
1685 s->clkctrl[3] = value & 0x101;
1686 break;
1687 case 0x850: /* RM_RSTCTRL_DSP */
1688 /* TODO: reset */
1689 break;
1690 case 0x858: /* RM_RSTST_DSP */
1691 s->rst[3] &= ~value;
1692 break;
1693 case 0x8c8: /* PM_WKDEP_DSP */
1694 s->wkup[2] = value & 0x13;
1695 break;
1696 case 0x8e0: /* PM_PWSTCTRL_DSP */
1697 s->power[3] = (value & 0x03017) | (3 << 2);
1698 break;
1699
1700 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
1701 s->irqst[1] &= ~value;
1702 omap_prcm_int_update(s, 1);
1703 break;
1704 case 0x8f4: /* PRCM_IRQENABLE_DSP */
1705 s->irqen[1] = value & 0x7;
1706 omap_prcm_int_update(s, 1);
1707 break;
1708
1709 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
1710 s->irqst[2] &= ~value;
1711 omap_prcm_int_update(s, 2);
1712 break;
1713 case 0x8fc: /* PRCM_IRQENABLE_IVA */
1714 s->irqen[2] = value & 0x7;
1715 omap_prcm_int_update(s, 2);
1716 break;
1717
1718 default:
1719 OMAP_BAD_REG(addr);
1720 return;
1721 }
1722 }
1723
1724 static const MemoryRegionOps omap_prcm_ops = {
1725 .read = omap_prcm_read,
1726 .write = omap_prcm_write,
1727 .endianness = DEVICE_NATIVE_ENDIAN,
1728 };
1729
1730 static void omap_prcm_reset(struct omap_prcm_s *s)
1731 {
1732 s->sysconfig = 0;
1733 s->irqst[0] = 0;
1734 s->irqst[1] = 0;
1735 s->irqst[2] = 0;
1736 s->irqen[0] = 0;
1737 s->irqen[1] = 0;
1738 s->irqen[2] = 0;
1739 s->voltctrl = 0x1040;
1740 s->ev = 0x14;
1741 s->evtime[0] = 0;
1742 s->evtime[1] = 0;
1743 s->clkctrl[0] = 0;
1744 s->clkctrl[1] = 0;
1745 s->clkctrl[2] = 0;
1746 s->clkctrl[3] = 0;
1747 s->clken[1] = 7;
1748 s->clken[3] = 7;
1749 s->clken[4] = 0;
1750 s->clken[5] = 0;
1751 s->clken[6] = 0;
1752 s->clken[7] = 0xc;
1753 s->clken[8] = 0x3e;
1754 s->clken[9] = 0x0d;
1755 s->clken[10] = 0;
1756 s->clken[11] = 0;
1757 s->clkidle[0] = 0;
1758 s->clkidle[2] = 7;
1759 s->clkidle[3] = 0;
1760 s->clkidle[4] = 0;
1761 s->clkidle[5] = 0x0c;
1762 s->clkidle[6] = 0;
1763 s->clksel[0] = 0x01;
1764 s->clksel[1] = 0x02100121;
1765 s->clksel[2] = 0x00000000;
1766 s->clksel[3] = 0x01;
1767 s->clksel[4] = 0;
1768 s->clksel[7] = 0x0121;
1769 s->wkup[0] = 0x15;
1770 s->wkup[1] = 0x13;
1771 s->wkup[2] = 0x13;
1772 s->wken[0] = 0x04667ff8;
1773 s->wken[1] = 0x00000005;
1774 s->wken[2] = 5;
1775 s->wkst[0] = 0;
1776 s->wkst[1] = 0;
1777 s->wkst[2] = 0;
1778 s->power[0] = 0x00c;
1779 s->power[1] = 4;
1780 s->power[2] = 0x0000c;
1781 s->power[3] = 0x14;
1782 s->rstctrl[0] = 1;
1783 s->rst[3] = 1;
1784 omap_prcm_apll_update(s);
1785 omap_prcm_dpll_update(s);
1786 }
1787
1788 static void omap_prcm_coldreset(struct omap_prcm_s *s)
1789 {
1790 s->setuptime[0] = 0;
1791 s->setuptime[1] = 0;
1792 memset(&s->scratch, 0, sizeof(s->scratch));
1793 s->rst[0] = 0x01;
1794 s->rst[1] = 0x00;
1795 s->rst[2] = 0x01;
1796 s->clken[0] = 0;
1797 s->clken[2] = 0;
1798 s->clkidle[1] = 0;
1799 s->clksel[5] = 0;
1800 s->clksel[6] = 2;
1801 s->clksrc[0] = 0x43;
1802 s->clkout[0] = 0x0303;
1803 s->clkemul[0] = 0;
1804 s->clkpol[0] = 0x100;
1805 s->rsttime_wkup = 0x1002;
1806
1807 omap_prcm_reset(s);
1808 }
1809
1810 static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
1811 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
1812 struct omap_mpu_state_s *mpu)
1813 {
1814 struct omap_prcm_s *s = g_new0(struct omap_prcm_s, 1);
1815
1816 s->irq[0] = mpu_int;
1817 s->irq[1] = dsp_int;
1818 s->irq[2] = iva_int;
1819 s->mpu = mpu;
1820 omap_prcm_coldreset(s);
1821
1822 memory_region_init_io(&s->iomem0, NULL, &omap_prcm_ops, s, "omap.pcrm0",
1823 omap_l4_region_size(ta, 0));
1824 memory_region_init_io(&s->iomem1, NULL, &omap_prcm_ops, s, "omap.pcrm1",
1825 omap_l4_region_size(ta, 1));
1826 omap_l4_attach(ta, 0, &s->iomem0);
1827 omap_l4_attach(ta, 1, &s->iomem1);
1828
1829 return s;
1830 }
1831
1832 /* System and Pinout control */
1833 struct omap_sysctl_s {
1834 struct omap_mpu_state_s *mpu;
1835 MemoryRegion iomem;
1836
1837 uint32_t sysconfig;
1838 uint32_t devconfig;
1839 uint32_t psaconfig;
1840 uint32_t padconf[0x45];
1841 uint8_t obs;
1842 uint32_t msuspendmux[5];
1843 };
1844
1845 static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
1846 {
1847
1848 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1849 int pad_offset, byte_offset;
1850 int value;
1851
1852 switch (addr) {
1853 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1854 pad_offset = (addr - 0x30) >> 2;
1855 byte_offset = (addr - 0x30) & (4 - 1);
1856
1857 value = s->padconf[pad_offset];
1858 value = (value >> (byte_offset * 8)) & 0xff;
1859
1860 return value;
1861
1862 default:
1863 break;
1864 }
1865
1866 OMAP_BAD_REG(addr);
1867 return 0;
1868 }
1869
1870 static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
1871 {
1872 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1873
1874 switch (addr) {
1875 case 0x000: /* CONTROL_REVISION */
1876 return 0x20;
1877
1878 case 0x010: /* CONTROL_SYSCONFIG */
1879 return s->sysconfig;
1880
1881 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1882 return s->padconf[(addr - 0x30) >> 2];
1883
1884 case 0x270: /* CONTROL_DEBOBS */
1885 return s->obs;
1886
1887 case 0x274: /* CONTROL_DEVCONF */
1888 return s->devconfig;
1889
1890 case 0x28c: /* CONTROL_EMU_SUPPORT */
1891 return 0;
1892
1893 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
1894 return s->msuspendmux[0];
1895 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
1896 return s->msuspendmux[1];
1897 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
1898 return s->msuspendmux[2];
1899 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
1900 return s->msuspendmux[3];
1901 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
1902 return s->msuspendmux[4];
1903 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
1904 return 0;
1905
1906 case 0x2b8: /* CONTROL_PSA_CTRL */
1907 return s->psaconfig;
1908 case 0x2bc: /* CONTROL_PSA_CMD */
1909 case 0x2c0: /* CONTROL_PSA_VALUE */
1910 return 0;
1911
1912 case 0x2b0: /* CONTROL_SEC_CTRL */
1913 return 0x800000f1;
1914 case 0x2d0: /* CONTROL_SEC_EMU */
1915 return 0x80000015;
1916 case 0x2d4: /* CONTROL_SEC_TAP */
1917 return 0x8000007f;
1918 case 0x2b4: /* CONTROL_SEC_TEST */
1919 case 0x2f0: /* CONTROL_SEC_STATUS */
1920 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
1921 /* Secure mode is not present on general-pusrpose device. Outside
1922 * secure mode these values cannot be read or written. */
1923 return 0;
1924
1925 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
1926 return 0xff;
1927 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
1928 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
1929 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
1930 /* No secure mode so no Extended Secure RAM present. */
1931 return 0;
1932
1933 case 0x2f8: /* CONTROL_STATUS */
1934 /* Device Type => General-purpose */
1935 return 0x0300;
1936 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
1937
1938 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
1939 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
1940 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
1941 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
1942 return 0xdecafbad;
1943
1944 case 0x310: /* CONTROL_RAND_KEY_0 */
1945 case 0x314: /* CONTROL_RAND_KEY_1 */
1946 case 0x318: /* CONTROL_RAND_KEY_2 */
1947 case 0x31c: /* CONTROL_RAND_KEY_3 */
1948 case 0x320: /* CONTROL_CUST_KEY_0 */
1949 case 0x324: /* CONTROL_CUST_KEY_1 */
1950 case 0x330: /* CONTROL_TEST_KEY_0 */
1951 case 0x334: /* CONTROL_TEST_KEY_1 */
1952 case 0x338: /* CONTROL_TEST_KEY_2 */
1953 case 0x33c: /* CONTROL_TEST_KEY_3 */
1954 case 0x340: /* CONTROL_TEST_KEY_4 */
1955 case 0x344: /* CONTROL_TEST_KEY_5 */
1956 case 0x348: /* CONTROL_TEST_KEY_6 */
1957 case 0x34c: /* CONTROL_TEST_KEY_7 */
1958 case 0x350: /* CONTROL_TEST_KEY_8 */
1959 case 0x354: /* CONTROL_TEST_KEY_9 */
1960 /* Can only be accessed in secure mode and when C_FieldAccEnable
1961 * bit is set in CONTROL_SEC_CTRL.
1962 * TODO: otherwise an interconnect access error is generated. */
1963 return 0;
1964 }
1965
1966 OMAP_BAD_REG(addr);
1967 return 0;
1968 }
1969
1970 static void omap_sysctl_write8(void *opaque, hwaddr addr,
1971 uint32_t value)
1972 {
1973 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1974 int pad_offset, byte_offset;
1975 int prev_value;
1976
1977 switch (addr) {
1978 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1979 pad_offset = (addr - 0x30) >> 2;
1980 byte_offset = (addr - 0x30) & (4 - 1);
1981
1982 prev_value = s->padconf[pad_offset];
1983 prev_value &= ~(0xff << (byte_offset * 8));
1984 prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f;
1985 s->padconf[pad_offset] = prev_value;
1986 break;
1987
1988 default:
1989 OMAP_BAD_REG(addr);
1990 break;
1991 }
1992 }
1993
1994 static void omap_sysctl_write(void *opaque, hwaddr addr,
1995 uint32_t value)
1996 {
1997 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1998
1999 switch (addr) {
2000 case 0x000: /* CONTROL_REVISION */
2001 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
2002 case 0x2c0: /* CONTROL_PSA_VALUE */
2003 case 0x2f8: /* CONTROL_STATUS */
2004 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
2005 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
2006 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
2007 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
2008 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
2009 case 0x310: /* CONTROL_RAND_KEY_0 */
2010 case 0x314: /* CONTROL_RAND_KEY_1 */
2011 case 0x318: /* CONTROL_RAND_KEY_2 */
2012 case 0x31c: /* CONTROL_RAND_KEY_3 */
2013 case 0x320: /* CONTROL_CUST_KEY_0 */
2014 case 0x324: /* CONTROL_CUST_KEY_1 */
2015 case 0x330: /* CONTROL_TEST_KEY_0 */
2016 case 0x334: /* CONTROL_TEST_KEY_1 */
2017 case 0x338: /* CONTROL_TEST_KEY_2 */
2018 case 0x33c: /* CONTROL_TEST_KEY_3 */
2019 case 0x340: /* CONTROL_TEST_KEY_4 */
2020 case 0x344: /* CONTROL_TEST_KEY_5 */
2021 case 0x348: /* CONTROL_TEST_KEY_6 */
2022 case 0x34c: /* CONTROL_TEST_KEY_7 */
2023 case 0x350: /* CONTROL_TEST_KEY_8 */
2024 case 0x354: /* CONTROL_TEST_KEY_9 */
2025 OMAP_RO_REG(addr);
2026 return;
2027
2028 case 0x010: /* CONTROL_SYSCONFIG */
2029 s->sysconfig = value & 0x1e;
2030 break;
2031
2032 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
2033 /* XXX: should check constant bits */
2034 s->padconf[(addr - 0x30) >> 2] = value & 0x1f1f1f1f;
2035 break;
2036
2037 case 0x270: /* CONTROL_DEBOBS */
2038 s->obs = value & 0xff;
2039 break;
2040
2041 case 0x274: /* CONTROL_DEVCONF */
2042 s->devconfig = value & 0xffffc7ff;
2043 break;
2044
2045 case 0x28c: /* CONTROL_EMU_SUPPORT */
2046 break;
2047
2048 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
2049 s->msuspendmux[0] = value & 0x3fffffff;
2050 break;
2051 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
2052 s->msuspendmux[1] = value & 0x3fffffff;
2053 break;
2054 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
2055 s->msuspendmux[2] = value & 0x3fffffff;
2056 break;
2057 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
2058 s->msuspendmux[3] = value & 0x3fffffff;
2059 break;
2060 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
2061 s->msuspendmux[4] = value & 0x3fffffff;
2062 break;
2063
2064 case 0x2b8: /* CONTROL_PSA_CTRL */
2065 s->psaconfig = value & 0x1c;
2066 s->psaconfig |= (value & 0x20) ? 2 : 1;
2067 break;
2068 case 0x2bc: /* CONTROL_PSA_CMD */
2069 break;
2070
2071 case 0x2b0: /* CONTROL_SEC_CTRL */
2072 case 0x2b4: /* CONTROL_SEC_TEST */
2073 case 0x2d0: /* CONTROL_SEC_EMU */
2074 case 0x2d4: /* CONTROL_SEC_TAP */
2075 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
2076 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
2077 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
2078 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
2079 case 0x2f0: /* CONTROL_SEC_STATUS */
2080 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
2081 break;
2082
2083 default:
2084 OMAP_BAD_REG(addr);
2085 return;
2086 }
2087 }
2088
2089 static uint64_t omap_sysctl_readfn(void *opaque, hwaddr addr,
2090 unsigned size)
2091 {
2092 switch (size) {
2093 case 1:
2094 return omap_sysctl_read8(opaque, addr);
2095 case 2:
2096 return omap_badwidth_read32(opaque, addr); /* TODO */
2097 case 4:
2098 return omap_sysctl_read(opaque, addr);
2099 default:
2100 g_assert_not_reached();
2101 }
2102 }
2103
2104 static void omap_sysctl_writefn(void *opaque, hwaddr addr,
2105 uint64_t value, unsigned size)
2106 {
2107 switch (size) {
2108 case 1:
2109 omap_sysctl_write8(opaque, addr, value);
2110 break;
2111 case 2:
2112 omap_badwidth_write32(opaque, addr, value); /* TODO */
2113 break;
2114 case 4:
2115 omap_sysctl_write(opaque, addr, value);
2116 break;
2117 default:
2118 g_assert_not_reached();
2119 }
2120 }
2121
2122 static const MemoryRegionOps omap_sysctl_ops = {
2123 .read = omap_sysctl_readfn,
2124 .write = omap_sysctl_writefn,
2125 .valid.min_access_size = 1,
2126 .valid.max_access_size = 4,
2127 .endianness = DEVICE_NATIVE_ENDIAN,
2128 };
2129
2130 static void omap_sysctl_reset(struct omap_sysctl_s *s)
2131 {
2132 /* (power-on reset) */
2133 s->sysconfig = 0;
2134 s->obs = 0;
2135 s->devconfig = 0x0c000000;
2136 s->msuspendmux[0] = 0x00000000;
2137 s->msuspendmux[1] = 0x00000000;
2138 s->msuspendmux[2] = 0x00000000;
2139 s->msuspendmux[3] = 0x00000000;
2140 s->msuspendmux[4] = 0x00000000;
2141 s->psaconfig = 1;
2142
2143 s->padconf[0x00] = 0x000f0f0f;
2144 s->padconf[0x01] = 0x00000000;
2145 s->padconf[0x02] = 0x00000000;
2146 s->padconf[0x03] = 0x00000000;
2147 s->padconf[0x04] = 0x00000000;
2148 s->padconf[0x05] = 0x00000000;
2149 s->padconf[0x06] = 0x00000000;
2150 s->padconf[0x07] = 0x00000000;
2151 s->padconf[0x08] = 0x08080800;
2152 s->padconf[0x09] = 0x08080808;
2153 s->padconf[0x0a] = 0x08080808;
2154 s->padconf[0x0b] = 0x08080808;
2155 s->padconf[0x0c] = 0x08080808;
2156 s->padconf[0x0d] = 0x08080800;
2157 s->padconf[0x0e] = 0x08080808;
2158 s->padconf[0x0f] = 0x08080808;
2159 s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */
2160 s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */
2161 s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */
2162 s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */
2163 s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */
2164 s->padconf[0x15] = 0x18181818;
2165 s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */
2166 s->padconf[0x17] = 0x1f001f00;
2167 s->padconf[0x18] = 0x1f1f1f1f;
2168 s->padconf[0x19] = 0x00000000;
2169 s->padconf[0x1a] = 0x1f180000;
2170 s->padconf[0x1b] = 0x00001f1f;
2171 s->padconf[0x1c] = 0x1f001f00;
2172 s->padconf[0x1d] = 0x00000000;
2173 s->padconf[0x1e] = 0x00000000;
2174 s->padconf[0x1f] = 0x08000000;
2175 s->padconf[0x20] = 0x08080808;
2176 s->padconf[0x21] = 0x08080808;
2177 s->padconf[0x22] = 0x0f080808;
2178 s->padconf[0x23] = 0x0f0f0f0f;
2179 s->padconf[0x24] = 0x000f0f0f;
2180 s->padconf[0x25] = 0x1f1f1f0f;
2181 s->padconf[0x26] = 0x080f0f1f;
2182 s->padconf[0x27] = 0x070f1808;
2183 s->padconf[0x28] = 0x0f070707;
2184 s->padconf[0x29] = 0x000f0f1f;
2185 s->padconf[0x2a] = 0x0f0f0f1f;
2186 s->padconf[0x2b] = 0x08000000;
2187 s->padconf[0x2c] = 0x0000001f;
2188 s->padconf[0x2d] = 0x0f0f1f00;
2189 s->padconf[0x2e] = 0x1f1f0f0f;
2190 s->padconf[0x2f] = 0x0f1f1f1f;
2191 s->padconf[0x30] = 0x0f0f0f0f;
2192 s->padconf[0x31] = 0x0f1f0f1f;
2193 s->padconf[0x32] = 0x0f0f0f0f;
2194 s->padconf[0x33] = 0x0f1f0f1f;
2195 s->padconf[0x34] = 0x1f1f0f0f;
2196 s->padconf[0x35] = 0x0f0f1f1f;
2197 s->padconf[0x36] = 0x0f0f1f0f;
2198 s->padconf[0x37] = 0x0f0f0f0f;
2199 s->padconf[0x38] = 0x1f18180f;
2200 s->padconf[0x39] = 0x1f1f1f1f;
2201 s->padconf[0x3a] = 0x00001f1f;
2202 s->padconf[0x3b] = 0x00000000;
2203 s->padconf[0x3c] = 0x00000000;
2204 s->padconf[0x3d] = 0x0f0f0f0f;
2205 s->padconf[0x3e] = 0x18000f0f;
2206 s->padconf[0x3f] = 0x00070000;
2207 s->padconf[0x40] = 0x00000707;
2208 s->padconf[0x41] = 0x0f1f0700;
2209 s->padconf[0x42] = 0x1f1f070f;
2210 s->padconf[0x43] = 0x0008081f;
2211 s->padconf[0x44] = 0x00000800;
2212 }
2213
2214 static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
2215 omap_clk iclk, struct omap_mpu_state_s *mpu)
2216 {
2217 struct omap_sysctl_s *s = g_new0(struct omap_sysctl_s, 1);
2218
2219 s->mpu = mpu;
2220 omap_sysctl_reset(s);
2221
2222 memory_region_init_io(&s->iomem, NULL, &omap_sysctl_ops, s, "omap.sysctl",
2223 omap_l4_region_size(ta, 0));
2224 omap_l4_attach(ta, 0, &s->iomem);
2225
2226 return s;
2227 }
2228
2229 /* General chip reset */
2230 static void omap2_mpu_reset(void *opaque)
2231 {
2232 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
2233
2234 omap_dma_reset(mpu->dma);
2235 omap_prcm_reset(mpu->prcm);
2236 omap_sysctl_reset(mpu->sysc);
2237 omap_gp_timer_reset(mpu->gptimer[0]);
2238 omap_gp_timer_reset(mpu->gptimer[1]);
2239 omap_gp_timer_reset(mpu->gptimer[2]);
2240 omap_gp_timer_reset(mpu->gptimer[3]);
2241 omap_gp_timer_reset(mpu->gptimer[4]);
2242 omap_gp_timer_reset(mpu->gptimer[5]);
2243 omap_gp_timer_reset(mpu->gptimer[6]);
2244 omap_gp_timer_reset(mpu->gptimer[7]);
2245 omap_gp_timer_reset(mpu->gptimer[8]);
2246 omap_gp_timer_reset(mpu->gptimer[9]);
2247 omap_gp_timer_reset(mpu->gptimer[10]);
2248 omap_gp_timer_reset(mpu->gptimer[11]);
2249 omap_synctimer_reset(mpu->synctimer);
2250 omap_sdrc_reset(mpu->sdrc);
2251 omap_gpmc_reset(mpu->gpmc);
2252 omap_dss_reset(mpu->dss);
2253 omap_uart_reset(mpu->uart[0]);
2254 omap_uart_reset(mpu->uart[1]);
2255 omap_uart_reset(mpu->uart[2]);
2256 omap_mmc_reset(mpu->mmc);
2257 omap_mcspi_reset(mpu->mcspi[0]);
2258 omap_mcspi_reset(mpu->mcspi[1]);
2259 cpu_reset(CPU(mpu->cpu));
2260 }
2261
2262 static int omap2_validate_addr(struct omap_mpu_state_s *s,
2263 hwaddr addr)
2264 {
2265 return 1;
2266 }
2267
2268 static const struct dma_irq_map omap2_dma_irq_map[] = {
2269 { 0, OMAP_INT_24XX_SDMA_IRQ0 },
2270 { 0, OMAP_INT_24XX_SDMA_IRQ1 },
2271 { 0, OMAP_INT_24XX_SDMA_IRQ2 },
2272 { 0, OMAP_INT_24XX_SDMA_IRQ3 },
2273 };
2274
2275 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
2276 unsigned long sdram_size,
2277 const char *cpu_type)
2278 {
2279 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);
2280 qemu_irq dma_irqs[4];
2281 DriveInfo *dinfo;
2282 int i;
2283 SysBusDevice *busdev;
2284 struct omap_target_agent_s *ta;
2285
2286 /* Core */
2287 s->mpu_model = omap2420;
2288 s->cpu = ARM_CPU(cpu_create(cpu_type));
2289 s->sdram_size = sdram_size;
2290 s->sram_size = OMAP242X_SRAM_SIZE;
2291
2292 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0);
2293
2294 /* Clocks */
2295 omap_clk_init(s);
2296
2297 /* Memory-mapped stuff */
2298 memory_region_allocate_system_memory(&s->sdram, NULL, "omap2.dram",
2299 s->sdram_size);
2300 memory_region_add_subregion(sysmem, OMAP2_Q2_BASE, &s->sdram);
2301 memory_region_init_ram(&s->sram, NULL, "omap2.sram", s->sram_size,
2302 &error_fatal);
2303 memory_region_add_subregion(sysmem, OMAP2_SRAM_BASE, &s->sram);
2304
2305 s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54);
2306
2307 /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
2308 s->ih[0] = qdev_create(NULL, "omap2-intc");
2309 qdev_prop_set_uint8(s->ih[0], "revision", 0x21);
2310 qdev_prop_set_ptr(s->ih[0], "fclk", omap_findclk(s, "mpu_intc_fclk"));
2311 qdev_prop_set_ptr(s->ih[0], "iclk", omap_findclk(s, "mpu_intc_iclk"));
2312 qdev_init_nofail(s->ih[0]);
2313 busdev = SYS_BUS_DEVICE(s->ih[0]);
2314 sysbus_connect_irq(busdev, 0,
2315 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
2316 sysbus_connect_irq(busdev, 1,
2317 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
2318 sysbus_mmio_map(busdev, 0, 0x480fe000);
2319 s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
2320 qdev_get_gpio_in(s->ih[0],
2321 OMAP_INT_24XX_PRCM_MPU_IRQ),
2322 NULL, NULL, s);
2323
2324 s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
2325 omap_findclk(s, "omapctrl_iclk"), s);
2326
2327 for (i = 0; i < 4; i++) {
2328 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap2_dma_irq_map[i].ih],
2329 omap2_dma_irq_map[i].intr);
2330 }
2331 s->dma = omap_dma4_init(0x48056000, dma_irqs, sysmem, s, 256, 32,
2332 omap_findclk(s, "sdma_iclk"),
2333 omap_findclk(s, "sdma_fclk"));
2334 s->port->addr_valid = omap2_validate_addr;
2335
2336 /* Register SDRAM and SRAM ports for fast DMA transfers. */
2337 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sdram),
2338 OMAP2_Q2_BASE, s->sdram_size);
2339 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sram),
2340 OMAP2_SRAM_BASE, s->sram_size);
2341
2342 s->uart[0] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 19),
2343 qdev_get_gpio_in(s->ih[0],
2344 OMAP_INT_24XX_UART1_IRQ),
2345 omap_findclk(s, "uart1_fclk"),
2346 omap_findclk(s, "uart1_iclk"),
2347 s->drq[OMAP24XX_DMA_UART1_TX],
2348 s->drq[OMAP24XX_DMA_UART1_RX],
2349 "uart1",
2350 serial_hd(0));
2351 s->uart[1] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 20),
2352 qdev_get_gpio_in(s->ih[0],
2353 OMAP_INT_24XX_UART2_IRQ),
2354 omap_findclk(s, "uart2_fclk"),
2355 omap_findclk(s, "uart2_iclk"),
2356 s->drq[OMAP24XX_DMA_UART2_TX],
2357 s->drq[OMAP24XX_DMA_UART2_RX],
2358 "uart2",
2359 serial_hd(0) ? serial_hd(1) : NULL);
2360 s->uart[2] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 21),
2361 qdev_get_gpio_in(s->ih[0],
2362 OMAP_INT_24XX_UART3_IRQ),
2363 omap_findclk(s, "uart3_fclk"),
2364 omap_findclk(s, "uart3_iclk"),
2365 s->drq[OMAP24XX_DMA_UART3_TX],
2366 s->drq[OMAP24XX_DMA_UART3_RX],
2367 "uart3",
2368 serial_hd(0) && serial_hd(1) ? serial_hd(2) : NULL);
2369
2370 s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
2371 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER1),
2372 omap_findclk(s, "wu_gpt1_clk"),
2373 omap_findclk(s, "wu_l4_iclk"));
2374 s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8),
2375 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER2),
2376 omap_findclk(s, "core_gpt2_clk"),
2377 omap_findclk(s, "core_l4_iclk"));
2378 s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22),
2379 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER3),
2380 omap_findclk(s, "core_gpt3_clk"),
2381 omap_findclk(s, "core_l4_iclk"));
2382 s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23),
2383 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER4),
2384 omap_findclk(s, "core_gpt4_clk"),
2385 omap_findclk(s, "core_l4_iclk"));
2386 s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24),
2387 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER5),
2388 omap_findclk(s, "core_gpt5_clk"),
2389 omap_findclk(s, "core_l4_iclk"));
2390 s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25),
2391 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER6),
2392 omap_findclk(s, "core_gpt6_clk"),
2393 omap_findclk(s, "core_l4_iclk"));
2394 s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26),
2395 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER7),
2396 omap_findclk(s, "core_gpt7_clk"),
2397 omap_findclk(s, "core_l4_iclk"));
2398 s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27),
2399 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER8),
2400 omap_findclk(s, "core_gpt8_clk"),
2401 omap_findclk(s, "core_l4_iclk"));
2402 s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28),
2403 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER9),
2404 omap_findclk(s, "core_gpt9_clk"),
2405 omap_findclk(s, "core_l4_iclk"));
2406 s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29),
2407 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER10),
2408 omap_findclk(s, "core_gpt10_clk"),
2409 omap_findclk(s, "core_l4_iclk"));
2410 s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30),
2411 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER11),
2412 omap_findclk(s, "core_gpt11_clk"),
2413 omap_findclk(s, "core_l4_iclk"));
2414 s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31),
2415 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER12),
2416 omap_findclk(s, "core_gpt12_clk"),
2417 omap_findclk(s, "core_l4_iclk"));
2418
2419 omap_tap_init(omap_l4ta(s->l4, 2), s);
2420
2421 s->synctimer = omap_synctimer_init(omap_l4tao(s->l4, 2), s,
2422 omap_findclk(s, "clk32-kHz"),
2423 omap_findclk(s, "core_l4_iclk"));
2424
2425 s->i2c[0] = qdev_create(NULL, "omap_i2c");
2426 qdev_prop_set_uint8(s->i2c[0], "revision", 0x34);
2427 qdev_prop_set_ptr(s->i2c[0], "iclk", omap_findclk(s, "i2c1.iclk"));
2428 qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "i2c1.fclk"));
2429 qdev_init_nofail(s->i2c[0]);
2430 busdev = SYS_BUS_DEVICE(s->i2c[0]);
2431 sysbus_connect_irq(busdev, 0,
2432 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ));
2433 sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C1_TX]);
2434 sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C1_RX]);
2435 sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 5), 0));
2436
2437 s->i2c[1] = qdev_create(NULL, "omap_i2c");
2438 qdev_prop_set_uint8(s->i2c[1], "revision", 0x34);
2439 qdev_prop_set_ptr(s->i2c[1], "iclk", omap_findclk(s, "i2c2.iclk"));
2440 qdev_prop_set_ptr(s->i2c[1], "fclk", omap_findclk(s, "i2c2.fclk"));
2441 qdev_init_nofail(s->i2c[1]);
2442 busdev = SYS_BUS_DEVICE(s->i2c[1]);
2443 sysbus_connect_irq(busdev, 0,
2444 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ));
2445 sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C2_TX]);
2446 sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C2_RX]);
2447 sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 6), 0));
2448
2449 s->gpio = qdev_create(NULL, "omap2-gpio");
2450 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
2451 qdev_prop_set_ptr(s->gpio, "iclk", omap_findclk(s, "gpio_iclk"));
2452 qdev_prop_set_ptr(s->gpio, "fclk0", omap_findclk(s, "gpio1_dbclk"));
2453 qdev_prop_set_ptr(s->gpio, "fclk1", omap_findclk(s, "gpio2_dbclk"));
2454 qdev_prop_set_ptr(s->gpio, "fclk2", omap_findclk(s, "gpio3_dbclk"));
2455 qdev_prop_set_ptr(s->gpio, "fclk3", omap_findclk(s, "gpio4_dbclk"));
2456 if (s->mpu_model == omap2430) {
2457 qdev_prop_set_ptr(s->gpio, "fclk4", omap_findclk(s, "gpio5_dbclk"));
2458 }
2459 qdev_init_nofail(s->gpio);
2460 busdev = SYS_BUS_DEVICE(s->gpio);
2461 sysbus_connect_irq(busdev, 0,
2462 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK1));
2463 sysbus_connect_irq(busdev, 3,
2464 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK2));
2465 sysbus_connect_irq(busdev, 6,
2466 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK3));
2467 sysbus_connect_irq(busdev, 9,
2468 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK4));
2469 if (s->mpu_model == omap2430) {
2470 sysbus_connect_irq(busdev, 12,
2471 qdev_get_gpio_in(s->ih[0],
2472 OMAP_INT_243X_GPIO_BANK5));
2473 }
2474 ta = omap_l4ta(s->l4, 3);
2475 sysbus_mmio_map(busdev, 0, omap_l4_region_base(ta, 1));
2476 sysbus_mmio_map(busdev, 1, omap_l4_region_base(ta, 0));
2477 sysbus_mmio_map(busdev, 2, omap_l4_region_base(ta, 2));
2478 sysbus_mmio_map(busdev, 3, omap_l4_region_base(ta, 4));
2479 sysbus_mmio_map(busdev, 4, omap_l4_region_base(ta, 5));
2480
2481 s->sdrc = omap_sdrc_init(sysmem, 0x68009000);
2482 s->gpmc = omap_gpmc_init(s, 0x6800a000,
2483 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPMC_IRQ),
2484 s->drq[OMAP24XX_DMA_GPMC]);
2485
2486 dinfo = drive_get(IF_SD, 0, 0);
2487 if (!dinfo && !qtest_enabled()) {
2488 warn_report("missing SecureDigital device");
2489 }
2490 s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9),
2491 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
2492 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MMC_IRQ),
2493 &s->drq[OMAP24XX_DMA_MMC1_TX],
2494 omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
2495
2496 s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
2497 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI1_IRQ),
2498 &s->drq[OMAP24XX_DMA_SPI1_TX0],
2499 omap_findclk(s, "spi1_fclk"),
2500 omap_findclk(s, "spi1_iclk"));
2501 s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
2502 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI2_IRQ),
2503 &s->drq[OMAP24XX_DMA_SPI2_TX0],
2504 omap_findclk(s, "spi2_fclk"),
2505 omap_findclk(s, "spi2_iclk"));
2506
2507 s->dss = omap_dss_init(omap_l4ta(s->l4, 10), sysmem, 0x68000800,
2508 /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
2509 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_DSS_IRQ),
2510 s->drq[OMAP24XX_DMA_DSS],
2511 omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
2512 omap_findclk(s, "dss_54m_clk"),
2513 omap_findclk(s, "dss_l3_iclk"),
2514 omap_findclk(s, "dss_l4_iclk"));
2515
2516 omap_sti_init(omap_l4ta(s->l4, 18), sysmem, 0x54000000,
2517 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_STI),
2518 omap_findclk(s, "emul_ck"),
2519 serial_hd(0) && serial_hd(1) && serial_hd(2) ?
2520 serial_hd(3) : NULL);
2521
2522 s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
2523 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_EAC_IRQ),
2524 /* Ten consecutive lines */
2525 &s->drq[OMAP24XX_DMA_EAC_AC_RD],
2526 omap_findclk(s, "func_96m_clk"),
2527 omap_findclk(s, "core_l4_iclk"));
2528
2529 /* All register mappings (includin those not currenlty implemented):
2530 * SystemControlMod 48000000 - 48000fff
2531 * SystemControlL4 48001000 - 48001fff
2532 * 32kHz Timer Mod 48004000 - 48004fff
2533 * 32kHz Timer L4 48005000 - 48005fff
2534 * PRCM ModA 48008000 - 480087ff
2535 * PRCM ModB 48008800 - 48008fff
2536 * PRCM L4 48009000 - 48009fff
2537 * TEST-BCM Mod 48012000 - 48012fff
2538 * TEST-BCM L4 48013000 - 48013fff
2539 * TEST-TAP Mod 48014000 - 48014fff
2540 * TEST-TAP L4 48015000 - 48015fff
2541 * GPIO1 Mod 48018000 - 48018fff
2542 * GPIO Top 48019000 - 48019fff
2543 * GPIO2 Mod 4801a000 - 4801afff
2544 * GPIO L4 4801b000 - 4801bfff
2545 * GPIO3 Mod 4801c000 - 4801cfff
2546 * GPIO4 Mod 4801e000 - 4801efff
2547 * WDTIMER1 Mod 48020000 - 48010fff
2548 * WDTIMER Top 48021000 - 48011fff
2549 * WDTIMER2 Mod 48022000 - 48012fff
2550 * WDTIMER L4 48023000 - 48013fff
2551 * WDTIMER3 Mod 48024000 - 48014fff
2552 * WDTIMER3 L4 48025000 - 48015fff
2553 * WDTIMER4 Mod 48026000 - 48016fff
2554 * WDTIMER4 L4 48027000 - 48017fff
2555 * GPTIMER1 Mod 48028000 - 48018fff
2556 * GPTIMER1 L4 48029000 - 48019fff
2557 * GPTIMER2 Mod 4802a000 - 4801afff
2558 * GPTIMER2 L4 4802b000 - 4801bfff
2559 * L4-Config AP 48040000 - 480407ff
2560 * L4-Config IP 48040800 - 48040fff
2561 * L4-Config LA 48041000 - 48041fff
2562 * ARM11ETB Mod 48048000 - 48049fff
2563 * ARM11ETB L4 4804a000 - 4804afff
2564 * DISPLAY Top 48050000 - 480503ff
2565 * DISPLAY DISPC 48050400 - 480507ff
2566 * DISPLAY RFBI 48050800 - 48050bff
2567 * DISPLAY VENC 48050c00 - 48050fff
2568 * DISPLAY L4 48051000 - 48051fff
2569 * CAMERA Top 48052000 - 480523ff
2570 * CAMERA core 48052400 - 480527ff
2571 * CAMERA DMA 48052800 - 48052bff
2572 * CAMERA MMU 48052c00 - 48052fff
2573 * CAMERA L4 48053000 - 48053fff
2574 * SDMA Mod 48056000 - 48056fff
2575 * SDMA L4 48057000 - 48057fff
2576 * SSI Top 48058000 - 48058fff
2577 * SSI GDD 48059000 - 48059fff
2578 * SSI Port1 4805a000 - 4805afff
2579 * SSI Port2 4805b000 - 4805bfff
2580 * SSI L4 4805c000 - 4805cfff
2581 * USB Mod 4805e000 - 480fefff
2582 * USB L4 4805f000 - 480fffff
2583 * WIN_TRACER1 Mod 48060000 - 48060fff
2584 * WIN_TRACER1 L4 48061000 - 48061fff
2585 * WIN_TRACER2 Mod 48062000 - 48062fff
2586 * WIN_TRACER2 L4 48063000 - 48063fff
2587 * WIN_TRACER3 Mod 48064000 - 48064fff
2588 * WIN_TRACER3 L4 48065000 - 48065fff
2589 * WIN_TRACER4 Top 48066000 - 480660ff
2590 * WIN_TRACER4 ETT 48066100 - 480661ff
2591 * WIN_TRACER4 WT 48066200 - 480662ff
2592 * WIN_TRACER4 L4 48067000 - 48067fff
2593 * XTI Mod 48068000 - 48068fff
2594 * XTI L4 48069000 - 48069fff
2595 * UART1 Mod 4806a000 - 4806afff
2596 * UART1 L4 4806b000 - 4806bfff
2597 * UART2 Mod 4806c000 - 4806cfff
2598 * UART2 L4 4806d000 - 4806dfff
2599 * UART3 Mod 4806e000 - 4806efff
2600 * UART3 L4 4806f000 - 4806ffff
2601 * I2C1 Mod 48070000 - 48070fff
2602 * I2C1 L4 48071000 - 48071fff
2603 * I2C2 Mod 48072000 - 48072fff
2604 * I2C2 L4 48073000 - 48073fff
2605 * McBSP1 Mod 48074000 - 48074fff
2606 * McBSP1 L4 48075000 - 48075fff
2607 * McBSP2 Mod 48076000 - 48076fff
2608 * McBSP2 L4 48077000 - 48077fff
2609 * GPTIMER3 Mod 48078000 - 48078fff
2610 * GPTIMER3 L4 48079000 - 48079fff
2611 * GPTIMER4 Mod 4807a000 - 4807afff
2612 * GPTIMER4 L4 4807b000 - 4807bfff
2613 * GPTIMER5 Mod 4807c000 - 4807cfff
2614 * GPTIMER5 L4 4807d000 - 4807dfff
2615 * GPTIMER6 Mod 4807e000 - 4807efff
2616 * GPTIMER6 L4 4807f000 - 4807ffff
2617 * GPTIMER7 Mod 48080000 - 48080fff
2618 * GPTIMER7 L4 48081000 - 48081fff
2619 * GPTIMER8 Mod 48082000 - 48082fff
2620 * GPTIMER8 L4 48083000 - 48083fff
2621 * GPTIMER9 Mod 48084000 - 48084fff
2622 * GPTIMER9 L4 48085000 - 48085fff
2623 * GPTIMER10 Mod 48086000 - 48086fff
2624 * GPTIMER10 L4 48087000 - 48087fff
2625 * GPTIMER11 Mod 48088000 - 48088fff
2626 * GPTIMER11 L4 48089000 - 48089fff
2627 * GPTIMER12 Mod 4808a000 - 4808afff
2628 * GPTIMER12 L4 4808b000 - 4808bfff
2629 * EAC Mod 48090000 - 48090fff
2630 * EAC L4 48091000 - 48091fff
2631 * FAC Mod 48092000 - 48092fff
2632 * FAC L4 48093000 - 48093fff
2633 * MAILBOX Mod 48094000 - 48094fff
2634 * MAILBOX L4 48095000 - 48095fff
2635 * SPI1 Mod 48098000 - 48098fff
2636 * SPI1 L4 48099000 - 48099fff
2637 * SPI2 Mod 4809a000 - 4809afff
2638 * SPI2 L4 4809b000 - 4809bfff
2639 * MMC/SDIO Mod 4809c000 - 4809cfff
2640 * MMC/SDIO L4 4809d000 - 4809dfff
2641 * MS_PRO Mod 4809e000 - 4809efff
2642 * MS_PRO L4 4809f000 - 4809ffff
2643 * RNG Mod 480a0000 - 480a0fff
2644 * RNG L4 480a1000 - 480a1fff
2645 * DES3DES Mod 480a2000 - 480a2fff
2646 * DES3DES L4 480a3000 - 480a3fff
2647 * SHA1MD5 Mod 480a4000 - 480a4fff
2648 * SHA1MD5 L4 480a5000 - 480a5fff
2649 * AES Mod 480a6000 - 480a6fff
2650 * AES L4 480a7000 - 480a7fff
2651 * PKA Mod 480a8000 - 480a9fff
2652 * PKA L4 480aa000 - 480aafff
2653 * MG Mod 480b0000 - 480b0fff
2654 * MG L4 480b1000 - 480b1fff
2655 * HDQ/1-wire Mod 480b2000 - 480b2fff
2656 * HDQ/1-wire L4 480b3000 - 480b3fff
2657 * MPU interrupt 480fe000 - 480fefff
2658 * STI channel base 54000000 - 5400ffff
2659 * IVA RAM 5c000000 - 5c01ffff
2660 * IVA ROM 5c020000 - 5c027fff
2661 * IMG_BUF_A 5c040000 - 5c040fff
2662 * IMG_BUF_B 5c042000 - 5c042fff
2663 * VLCDS 5c048000 - 5c0487ff
2664 * IMX_COEF 5c049000 - 5c04afff
2665 * IMX_CMD 5c051000 - 5c051fff
2666 * VLCDQ 5c053000 - 5c0533ff
2667 * VLCDH 5c054000 - 5c054fff
2668 * SEQ_CMD 5c055000 - 5c055fff
2669 * IMX_REG 5c056000 - 5c0560ff
2670 * VLCD_REG 5c056100 - 5c0561ff
2671 * SEQ_REG 5c056200 - 5c0562ff
2672 * IMG_BUF_REG 5c056300 - 5c0563ff
2673 * SEQIRQ_REG 5c056400 - 5c0564ff
2674 * OCP_REG 5c060000 - 5c060fff
2675 * SYSC_REG 5c070000 - 5c070fff
2676 * MMU_REG 5d000000 - 5d000fff
2677 * sDMA R 68000400 - 680005ff
2678 * sDMA W 68000600 - 680007ff
2679 * Display Control 68000800 - 680009ff
2680 * DSP subsystem 68000a00 - 68000bff
2681 * MPU subsystem 68000c00 - 68000dff
2682 * IVA subsystem 68001000 - 680011ff
2683 * USB 68001200 - 680013ff
2684 * Camera 68001400 - 680015ff
2685 * VLYNQ (firewall) 68001800 - 68001bff
2686 * VLYNQ 68001e00 - 68001fff
2687 * SSI 68002000 - 680021ff
2688 * L4 68002400 - 680025ff
2689 * DSP (firewall) 68002800 - 68002bff
2690 * DSP subsystem 68002e00 - 68002fff
2691 * IVA (firewall) 68003000 - 680033ff
2692 * IVA 68003600 - 680037ff
2693 * GFX 68003a00 - 68003bff
2694 * CMDWR emulation 68003c00 - 68003dff
2695 * SMS 68004000 - 680041ff
2696 * OCM 68004200 - 680043ff
2697 * GPMC 68004400 - 680045ff
2698 * RAM (firewall) 68005000 - 680053ff
2699 * RAM (err login) 68005400 - 680057ff
2700 * ROM (firewall) 68005800 - 68005bff
2701 * ROM (err login) 68005c00 - 68005fff
2702 * GPMC (firewall) 68006000 - 680063ff
2703 * GPMC (err login) 68006400 - 680067ff
2704 * SMS (err login) 68006c00 - 68006fff
2705 * SMS registers 68008000 - 68008fff
2706 * SDRC registers 68009000 - 68009fff
2707 * GPMC registers 6800a000 6800afff
2708 */
2709
2710 qemu_register_reset(omap2_mpu_reset, s);
2711
2712 return s;
2713 }
AR7 emulation for QEMU