target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include <linux/kvm_para.h>
  22
  23 #include "qemu-common.h"
  24 #include "sysemu.h"
  25 #include "kvm.h"
  26 #include "kvm_i386.h"
  27 #include "cpu.h"
  28 #include "gdbstub.h"
  29 #include "host-utils.h"
  30 #include "hw/pc.h"
  31 #include "hw/apic.h"
  32 #include "ioport.h"
  33 #include "hyperv.h"
  34 #include "hw/pci.h"
  35
  36 //#define DEBUG_KVM
  37
  38 #ifdef DEBUG_KVM
  39 #define DPRINTF(fmt, ...) \
  40     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  41 #else
  42 #define DPRINTF(fmt, ...) \
  43     do { } while (0)
  44 #endif
  45
  46 #define MSR_KVM_WALL_CLOCK  0x11
  47 #define MSR_KVM_SYSTEM_TIME 0x12
  48
  49 #ifndef BUS_MCEERR_AR
  50 #define BUS_MCEERR_AR 4
  51 #endif
  52 #ifndef BUS_MCEERR_AO
  53 #define BUS_MCEERR_AO 5
  54 #endif
  55
  56 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  57     KVM_CAP_INFO(SET_TSS_ADDR),
  58     KVM_CAP_INFO(EXT_CPUID),
  59     KVM_CAP_INFO(MP_STATE),
  60     KVM_CAP_LAST_INFO
  61 };
  62
  63 static bool has_msr_star;
  64 static bool has_msr_hsave_pa;
  65 static bool has_msr_tsc_deadline;
  66 static bool has_msr_async_pf_en;
  67 static bool has_msr_pv_eoi_en;
  68 static bool has_msr_misc_enable;
  69 static int lm_capable_kernel;
  70
  71 bool kvm_allows_irq0_override(void)
  72 {
  73     return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
  74 }
  75
  76 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  77 {
  78     struct kvm_cpuid2 *cpuid;
  79     int r, size;
  80
  81     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  82     cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
  83     cpuid->nent = max;
  84     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  85     if (r == 0 && cpuid->nent >= max) {
  86         r = -E2BIG;
  87     }
  88     if (r < 0) {
  89         if (r == -E2BIG) {
  90             g_free(cpuid);
  91             return NULL;
  92         } else {
  93             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  94                     strerror(-r));
  95             exit(1);
  96         }
  97     }
  98     return cpuid;
  99 }
 100
 101 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
 102  * for all entries.
 103  */
 104 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
 105 {
 106     struct kvm_cpuid2 *cpuid;
 107     int max = 1;
 108     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 109         max *= 2;
 110     }
 111     return cpuid;
 112 }
 113
 114 struct kvm_para_features {
 115     int cap;
 116     int feature;
 117 } para_features[] = {
 118     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 119     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 120     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 121     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 122     { -1, -1 }
 123 };
 124
 125 static int get_para_features(KVMState *s)
 126 {
 127     int i, features = 0;
 128
 129     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 130         if (kvm_check_extension(s, para_features[i].cap)) {
 131             features |= (1 << para_features[i].feature);
 132         }
 133     }
 134
 135     return features;
 136 }
 137
 138
 139 /* Returns the value for a specific register on the cpuid entry
 140  */
 141 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
 142 {
 143     uint32_t ret = 0;
 144     switch (reg) {
 145     case R_EAX:
 146         ret = entry->eax;
 147         break;
 148     case R_EBX:
 149         ret = entry->ebx;
 150         break;
 151     case R_ECX:
 152         ret = entry->ecx;
 153         break;
 154     case R_EDX:
 155         ret = entry->edx;
 156         break;
 157     }
 158     return ret;
 159 }
 160
 161 /* Find matching entry for function/index on kvm_cpuid2 struct
 162  */
 163 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
 164                                                  uint32_t function,
 165                                                  uint32_t index)
 166 {
 167     int i;
 168     for (i = 0; i < cpuid->nent; ++i) {
 169         if (cpuid->entries[i].function == function &&
 170             cpuid->entries[i].index == index) {
 171             return &cpuid->entries[i];
 172         }
 173     }
 174     /* not found: */
 175     return NULL;
 176 }
 177
 178 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 179                                       uint32_t index, int reg)
 180 {
 181     struct kvm_cpuid2 *cpuid;
 182     uint32_t ret = 0;
 183     uint32_t cpuid_1_edx;
 184     bool found = false;
 185
 186     cpuid = get_supported_cpuid(s);
 187
 188     struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
 189     if (entry) {
 190         found = true;
 191         ret = cpuid_entry_get_reg(entry, reg);
 192     }
 193
 194     /* Fixups for the data returned by KVM, below */
 195
 196     if (function == 1 && reg == R_EDX) {
 197         /* KVM before 2.6.30 misreports the following features */
 198         ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 199     } else if (function == 1 && reg == R_ECX) {
 200         /* We can set the hypervisor flag, even if KVM does not return it on
 201          * GET_SUPPORTED_CPUID
 202          */
 203         ret |= CPUID_EXT_HYPERVISOR;
 204         /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
 205          * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
 206          * and the irqchip is in the kernel.
 207          */
 208         if (kvm_irqchip_in_kernel() &&
 209                 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
 210             ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
 211         }
 212
 213         /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
 214          * without the in-kernel irqchip
 215          */
 216         if (!kvm_irqchip_in_kernel()) {
 217             ret &= ~CPUID_EXT_X2APIC;
 218         }
 219     } else if (function == 0x80000001 && reg == R_EDX) {
 220         /* On Intel, kvm returns cpuid according to the Intel spec,
 221          * so add missing bits according to the AMD spec:
 222          */
 223         cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 224         ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
 225     }
 226
 227     g_free(cpuid);
 228
 229     /* fallback for older kernels */
 230     if ((function == KVM_CPUID_FEATURES) && !found) {
 231         ret = get_para_features(s);
 232     }
 233
 234     return ret;
 235 }
 236
 237 typedef struct HWPoisonPage {
 238     ram_addr_t ram_addr;
 239     QLIST_ENTRY(HWPoisonPage) list;
 240 } HWPoisonPage;
 241
 242 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 243     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 244
 245 static void kvm_unpoison_all(void *param)
 246 {
 247     HWPoisonPage *page, *next_page;
 248
 249     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 250         QLIST_REMOVE(page, list);
 251         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 252         g_free(page);
 253     }
 254 }
 255
 256 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 257 {
 258     HWPoisonPage *page;
 259
 260     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 261         if (page->ram_addr == ram_addr) {
 262             return;
 263         }
 264     }
 265     page = g_malloc(sizeof(HWPoisonPage));
 266     page->ram_addr = ram_addr;
 267     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 268 }
 269
 270 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 271                                      int *max_banks)
 272 {
 273     int r;
 274
 275     r = kvm_check_extension(s, KVM_CAP_MCE);
 276     if (r > 0) {
 277         *max_banks = r;
 278         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 279     }
 280     return -ENOSYS;
 281 }
 282
 283 static void kvm_mce_inject(CPUX86State *env, hwaddr paddr, int code)
 284 {
 285     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 286                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 287     uint64_t mcg_status = MCG_STATUS_MCIP;
 288
 289     if (code == BUS_MCEERR_AR) {
 290         status |= MCI_STATUS_AR | 0x134;
 291         mcg_status |= MCG_STATUS_EIPV;
 292     } else {
 293         status |= 0xc0;
 294         mcg_status |= MCG_STATUS_RIPV;
 295     }
 296     cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr,
 297                        (MCM_ADDR_PHYS << 6) | 0xc,
 298                        cpu_x86_support_mca_broadcast(env) ?
 299                        MCE_INJECT_BROADCAST : 0);
 300 }
 301
 302 static void hardware_memory_error(void)
 303 {
 304     fprintf(stderr, "Hardware memory error!\n");
 305     exit(1);
 306 }
 307
 308 int kvm_arch_on_sigbus_vcpu(CPUX86State *env, int code, void *addr)
 309 {
 310     ram_addr_t ram_addr;
 311     hwaddr paddr;
 312
 313     if ((env->mcg_cap & MCG_SER_P) && addr
 314         && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
 315         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 316             !kvm_physical_memory_addr_from_host(env->kvm_state, addr, &paddr)) {
 317             fprintf(stderr, "Hardware memory error for memory used by "
 318                     "QEMU itself instead of guest system!\n");
 319             /* Hope we are lucky for AO MCE */
 320             if (code == BUS_MCEERR_AO) {
 321                 return 0;
 322             } else {
 323                 hardware_memory_error();
 324             }
 325         }
 326         kvm_hwpoison_page_add(ram_addr);
 327         kvm_mce_inject(env, paddr, code);
 328     } else {
 329         if (code == BUS_MCEERR_AO) {
 330             return 0;
 331         } else if (code == BUS_MCEERR_AR) {
 332             hardware_memory_error();
 333         } else {
 334             return 1;
 335         }
 336     }
 337     return 0;
 338 }
 339
 340 int kvm_arch_on_sigbus(int code, void *addr)
 341 {
 342     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
 343         ram_addr_t ram_addr;
 344         hwaddr paddr;
 345
 346         /* Hope we are lucky for AO MCE */
 347         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 348             !kvm_physical_memory_addr_from_host(first_cpu->kvm_state, addr,
 349                                                 &paddr)) {
 350             fprintf(stderr, "Hardware memory error for memory used by "
 351                     "QEMU itself instead of guest system!: %p\n", addr);
 352             return 0;
 353         }
 354         kvm_hwpoison_page_add(ram_addr);
 355         kvm_mce_inject(first_cpu, paddr, code);
 356     } else {
 357         if (code == BUS_MCEERR_AO) {
 358             return 0;
 359         } else if (code == BUS_MCEERR_AR) {
 360             hardware_memory_error();
 361         } else {
 362             return 1;
 363         }
 364     }
 365     return 0;
 366 }
 367
 368 static int kvm_inject_mce_oldstyle(CPUX86State *env)
 369 {
 370     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 371         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 372         struct kvm_x86_mce mce;
 373
 374         env->exception_injected = -1;
 375
 376         /*
 377          * There must be at least one bank in use if an MCE is pending.
 378          * Find it and use its values for the event injection.
 379          */
 380         for (bank = 0; bank < bank_num; bank++) {
 381             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 382                 break;
 383             }
 384         }
 385         assert(bank < bank_num);
 386
 387         mce.bank = bank;
 388         mce.status = env->mce_banks[bank * 4 + 1];
 389         mce.mcg_status = env->mcg_status;
 390         mce.addr = env->mce_banks[bank * 4 + 2];
 391         mce.misc = env->mce_banks[bank * 4 + 3];
 392
 393         return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce);
 394     }
 395     return 0;
 396 }
 397
 398 static void cpu_update_state(void *opaque, int running, RunState state)
 399 {
 400     CPUX86State *env = opaque;
 401
 402     if (running) {
 403         env->tsc_valid = false;
 404     }
 405 }
 406
 407 int kvm_arch_init_vcpu(CPUX86State *env)
 408 {
 409     struct {
 410         struct kvm_cpuid2 cpuid;
 411         struct kvm_cpuid_entry2 entries[100];
 412     } QEMU_PACKED cpuid_data;
 413     KVMState *s = env->kvm_state;
 414     uint32_t limit, i, j, cpuid_i;
 415     uint32_t unused;
 416     struct kvm_cpuid_entry2 *c;
 417     uint32_t signature[3];
 418     int r;
 419
 420     env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 421
 422     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
 423
 424     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
 425                                                              0, R_EDX);
 426     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
 427                                                              0, R_ECX);
 428     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(s, 0x8000000A,
 429                                                              0, R_EDX);
 430
 431     env->cpuid_kvm_features &=
 432             kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
 433
 434     cpuid_i = 0;
 435
 436     /* Paravirtualization CPUIDs */
 437     c = &cpuid_data.entries[cpuid_i++];
 438     memset(c, 0, sizeof(*c));
 439     c->function = KVM_CPUID_SIGNATURE;
 440     if (!hyperv_enabled()) {
 441         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 442         c->eax = 0;
 443     } else {
 444         memcpy(signature, "Microsoft Hv", 12);
 445         c->eax = HYPERV_CPUID_MIN;
 446     }
 447     c->ebx = signature[0];
 448     c->ecx = signature[1];
 449     c->edx = signature[2];
 450
 451     c = &cpuid_data.entries[cpuid_i++];
 452     memset(c, 0, sizeof(*c));
 453     c->function = KVM_CPUID_FEATURES;
 454     c->eax = env->cpuid_kvm_features;
 455
 456     if (hyperv_enabled()) {
 457         memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
 458         c->eax = signature[0];
 459
 460         c = &cpuid_data.entries[cpuid_i++];
 461         memset(c, 0, sizeof(*c));
 462         c->function = HYPERV_CPUID_VERSION;
 463         c->eax = 0x00001bbc;
 464         c->ebx = 0x00060001;
 465
 466         c = &cpuid_data.entries[cpuid_i++];
 467         memset(c, 0, sizeof(*c));
 468         c->function = HYPERV_CPUID_FEATURES;
 469         if (hyperv_relaxed_timing_enabled()) {
 470             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 471         }
 472         if (hyperv_vapic_recommended()) {
 473             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 474             c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
 475         }
 476
 477         c = &cpuid_data.entries[cpuid_i++];
 478         memset(c, 0, sizeof(*c));
 479         c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
 480         if (hyperv_relaxed_timing_enabled()) {
 481             c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
 482         }
 483         if (hyperv_vapic_recommended()) {
 484             c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
 485         }
 486         c->ebx = hyperv_get_spinlock_retries();
 487
 488         c = &cpuid_data.entries[cpuid_i++];
 489         memset(c, 0, sizeof(*c));
 490         c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
 491         c->eax = 0x40;
 492         c->ebx = 0x40;
 493
 494         c = &cpuid_data.entries[cpuid_i++];
 495         memset(c, 0, sizeof(*c));
 496         c->function = KVM_CPUID_SIGNATURE_NEXT;
 497         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 498         c->eax = 0;
 499         c->ebx = signature[0];
 500         c->ecx = signature[1];
 501         c->edx = signature[2];
 502     }
 503
 504     has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
 505
 506     has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
 507
 508     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 509
 510     for (i = 0; i <= limit; i++) {
 511         c = &cpuid_data.entries[cpuid_i++];
 512
 513         switch (i) {
 514         case 2: {
 515             /* Keep reading function 2 till all the input is received */
 516             int times;
 517
 518             c->function = i;
 519             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 520                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 521             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 522             times = c->eax & 0xff;
 523
 524             for (j = 1; j < times; ++j) {
 525                 c = &cpuid_data.entries[cpuid_i++];
 526                 c->function = i;
 527                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 528                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 529             }
 530             break;
 531         }
 532         case 4:
 533         case 0xb:
 534         case 0xd:
 535             for (j = 0; ; j++) {
 536                 if (i == 0xd && j == 64) {
 537                     break;
 538                 }
 539                 c->function = i;
 540                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 541                 c->index = j;
 542                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 543
 544                 if (i == 4 && c->eax == 0) {
 545                     break;
 546                 }
 547                 if (i == 0xb && !(c->ecx & 0xff00)) {
 548                     break;
 549                 }
 550                 if (i == 0xd && c->eax == 0) {
 551                     continue;
 552                 }
 553                 c = &cpuid_data.entries[cpuid_i++];
 554             }
 555             break;
 556         default:
 557             c->function = i;
 558             c->flags = 0;
 559             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 560             break;
 561         }
 562     }
 563     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 564
 565     for (i = 0x80000000; i <= limit; i++) {
 566         c = &cpuid_data.entries[cpuid_i++];
 567
 568         c->function = i;
 569         c->flags = 0;
 570         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 571     }
 572
 573     /* Call Centaur's CPUID instructions they are supported. */
 574     if (env->cpuid_xlevel2 > 0) {
 575         env->cpuid_ext4_features &=
 576             kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
 577         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
 578
 579         for (i = 0xC0000000; i <= limit; i++) {
 580             c = &cpuid_data.entries[cpuid_i++];
 581
 582             c->function = i;
 583             c->flags = 0;
 584             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 585         }
 586     }
 587
 588     cpuid_data.cpuid.nent = cpuid_i;
 589
 590     if (((env->cpuid_version >> 8)&0xF) >= 6
 591         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 592         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 593         uint64_t mcg_cap;
 594         int banks;
 595         int ret;
 596
 597         ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks);
 598         if (ret < 0) {
 599             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
 600             return ret;
 601         }
 602
 603         if (banks > MCE_BANKS_DEF) {
 604             banks = MCE_BANKS_DEF;
 605         }
 606         mcg_cap &= MCE_CAP_DEF;
 607         mcg_cap |= banks;
 608         ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap);
 609         if (ret < 0) {
 610             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
 611             return ret;
 612         }
 613
 614         env->mcg_cap = mcg_cap;
 615     }
 616
 617     qemu_add_vm_change_state_handler(cpu_update_state, env);
 618
 619     cpuid_data.cpuid.padding = 0;
 620     r = kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 621     if (r) {
 622         return r;
 623     }
 624
 625     r = kvm_check_extension(env->kvm_state, KVM_CAP_TSC_CONTROL);
 626     if (r && env->tsc_khz) {
 627         r = kvm_vcpu_ioctl(env, KVM_SET_TSC_KHZ, env->tsc_khz);
 628         if (r < 0) {
 629             fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
 630             return r;
 631         }
 632     }
 633
 634     if (kvm_has_xsave()) {
 635         env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
 636     }
 637
 638     return 0;
 639 }
 640
 641 void kvm_arch_reset_vcpu(CPUX86State *env)
 642 {
 643     X86CPU *cpu = x86_env_get_cpu(env);
 644
 645     env->exception_injected = -1;
 646     env->interrupt_injected = -1;
 647     env->xcr0 = 1;
 648     if (kvm_irqchip_in_kernel()) {
 649         env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
 650                                           KVM_MP_STATE_UNINITIALIZED;
 651     } else {
 652         env->mp_state = KVM_MP_STATE_RUNNABLE;
 653     }
 654 }
 655
 656 static int kvm_get_supported_msrs(KVMState *s)
 657 {
 658     static int kvm_supported_msrs;
 659     int ret = 0;
 660
 661     /* first time */
 662     if (kvm_supported_msrs == 0) {
 663         struct kvm_msr_list msr_list, *kvm_msr_list;
 664
 665         kvm_supported_msrs = -1;
 666
 667         /* Obtain MSR list from KVM.  These are the MSRs that we must
 668          * save/restore */
 669         msr_list.nmsrs = 0;
 670         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 671         if (ret < 0 && ret != -E2BIG) {
 672             return ret;
 673         }
 674         /* Old kernel modules had a bug and could write beyond the provided
 675            memory. Allocate at least a safe amount of 1K. */
 676         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
 677                                               msr_list.nmsrs *
 678                                               sizeof(msr_list.indices[0])));
 679
 680         kvm_msr_list->nmsrs = msr_list.nmsrs;
 681         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 682         if (ret >= 0) {
 683             int i;
 684
 685             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 686                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 687                     has_msr_star = true;
 688                     continue;
 689                 }
 690                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 691                     has_msr_hsave_pa = true;
 692                     continue;
 693                 }
 694                 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
 695                     has_msr_tsc_deadline = true;
 696                     continue;
 697                 }
 698                 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
 699                     has_msr_misc_enable = true;
 700                     continue;
 701                 }
 702             }
 703         }
 704
 705         g_free(kvm_msr_list);
 706     }
 707
 708     return ret;
 709 }
 710
 711 int kvm_arch_init(KVMState *s)
 712 {
 713     QemuOptsList *list = qemu_find_opts("machine");
 714     uint64_t identity_base = 0xfffbc000;
 715     uint64_t shadow_mem;
 716     int ret;
 717     struct utsname utsname;
 718
 719     ret = kvm_get_supported_msrs(s);
 720     if (ret < 0) {
 721         return ret;
 722     }
 723
 724     uname(&utsname);
 725     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 726
 727     /*
 728      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 729      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 730      * Since these must be part of guest physical memory, we need to allocate
 731      * them, both by setting their start addresses in the kernel and by
 732      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 733      *
 734      * Older KVM versions may not support setting the identity map base. In
 735      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 736      * size.
 737      */
 738     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 739         /* Allows up to 16M BIOSes. */
 740         identity_base = 0xfeffc000;
 741
 742         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 743         if (ret < 0) {
 744             return ret;
 745         }
 746     }
 747
 748     /* Set TSS base one page after EPT identity map. */
 749     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 750     if (ret < 0) {
 751         return ret;
 752     }
 753
 754     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 755     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 756     if (ret < 0) {
 757         fprintf(stderr, "e820_add_entry() table is full\n");
 758         return ret;
 759     }
 760     qemu_register_reset(kvm_unpoison_all, NULL);
 761
 762     if (!QTAILQ_EMPTY(&list->head)) {
 763         shadow_mem = qemu_opt_get_size(QTAILQ_FIRST(&list->head),
 764                                        "kvm_shadow_mem", -1);
 765         if (shadow_mem != -1) {
 766             shadow_mem /= 4096;
 767             ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
 768             if (ret < 0) {
 769                 return ret;
 770             }
 771         }
 772     }
 773     return 0;
 774 }
 775
 776 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 777 {
 778     lhs->selector = rhs->selector;
 779     lhs->base = rhs->base;
 780     lhs->limit = rhs->limit;
 781     lhs->type = 3;
 782     lhs->present = 1;
 783     lhs->dpl = 3;
 784     lhs->db = 0;
 785     lhs->s = 1;
 786     lhs->l = 0;
 787     lhs->g = 0;
 788     lhs->avl = 0;
 789     lhs->unusable = 0;
 790 }
 791
 792 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 793 {
 794     unsigned flags = rhs->flags;
 795     lhs->selector = rhs->selector;
 796     lhs->base = rhs->base;
 797     lhs->limit = rhs->limit;
 798     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 799     lhs->present = (flags & DESC_P_MASK) != 0;
 800     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 801     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 802     lhs->s = (flags & DESC_S_MASK) != 0;
 803     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 804     lhs->g = (flags & DESC_G_MASK) != 0;
 805     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 806     lhs->unusable = 0;
 807     lhs->padding = 0;
 808 }
 809
 810 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 811 {
 812     lhs->selector = rhs->selector;
 813     lhs->base = rhs->base;
 814     lhs->limit = rhs->limit;
 815     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 816                  (rhs->present * DESC_P_MASK) |
 817                  (rhs->dpl << DESC_DPL_SHIFT) |
 818                  (rhs->db << DESC_B_SHIFT) |
 819                  (rhs->s * DESC_S_MASK) |
 820                  (rhs->l << DESC_L_SHIFT) |
 821                  (rhs->g * DESC_G_MASK) |
 822                  (rhs->avl * DESC_AVL_MASK);
 823 }
 824
 825 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 826 {
 827     if (set) {
 828         *kvm_reg = *qemu_reg;
 829     } else {
 830         *qemu_reg = *kvm_reg;
 831     }
 832 }
 833
 834 static int kvm_getput_regs(CPUX86State *env, int set)
 835 {
 836     struct kvm_regs regs;
 837     int ret = 0;
 838
 839     if (!set) {
 840         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 841         if (ret < 0) {
 842             return ret;
 843         }
 844     }
 845
 846     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 847     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 848     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 849     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 850     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 851     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 852     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 853     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 854 #ifdef TARGET_X86_64
 855     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 856     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 857     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 858     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 859     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 860     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 861     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 862     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 863 #endif
 864
 865     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 866     kvm_getput_reg(&regs.rip, &env->eip, set);
 867
 868     if (set) {
 869         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 870     }
 871
 872     return ret;
 873 }
 874
 875 static int kvm_put_fpu(CPUX86State *env)
 876 {
 877     struct kvm_fpu fpu;
 878     int i;
 879
 880     memset(&fpu, 0, sizeof fpu);
 881     fpu.fsw = env->fpus & ~(7 << 11);
 882     fpu.fsw |= (env->fpstt & 7) << 11;
 883     fpu.fcw = env->fpuc;
 884     fpu.last_opcode = env->fpop;
 885     fpu.last_ip = env->fpip;
 886     fpu.last_dp = env->fpdp;
 887     for (i = 0; i < 8; ++i) {
 888         fpu.ftwx |= (!env->fptags[i]) << i;
 889     }
 890     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 891     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 892     fpu.mxcsr = env->mxcsr;
 893
 894     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 895 }
 896
 897 #define XSAVE_FCW_FSW     0
 898 #define XSAVE_FTW_FOP     1
 899 #define XSAVE_CWD_RIP     2
 900 #define XSAVE_CWD_RDP     4
 901 #define XSAVE_MXCSR       6
 902 #define XSAVE_ST_SPACE    8
 903 #define XSAVE_XMM_SPACE   40
 904 #define XSAVE_XSTATE_BV   128
 905 #define XSAVE_YMMH_SPACE  144
 906
 907 static int kvm_put_xsave(CPUX86State *env)
 908 {
 909     struct kvm_xsave* xsave = env->kvm_xsave_buf;
 910     uint16_t cwd, swd, twd;
 911     int i, r;
 912
 913     if (!kvm_has_xsave()) {
 914         return kvm_put_fpu(env);
 915     }
 916
 917     memset(xsave, 0, sizeof(struct kvm_xsave));
 918     twd = 0;
 919     swd = env->fpus & ~(7 << 11);
 920     swd |= (env->fpstt & 7) << 11;
 921     cwd = env->fpuc;
 922     for (i = 0; i < 8; ++i) {
 923         twd |= (!env->fptags[i]) << i;
 924     }
 925     xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
 926     xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
 927     memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
 928     memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
 929     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 930             sizeof env->fpregs);
 931     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 932             sizeof env->xmm_regs);
 933     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 934     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 935     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 936             sizeof env->ymmh_regs);
 937     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 938     return r;
 939 }
 940
 941 static int kvm_put_xcrs(CPUX86State *env)
 942 {
 943     struct kvm_xcrs xcrs;
 944
 945     if (!kvm_has_xcrs()) {
 946         return 0;
 947     }
 948
 949     xcrs.nr_xcrs = 1;
 950     xcrs.flags = 0;
 951     xcrs.xcrs[0].xcr = 0;
 952     xcrs.xcrs[0].value = env->xcr0;
 953     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 954 }
 955
 956 static int kvm_put_sregs(CPUX86State *env)
 957 {
 958     struct kvm_sregs sregs;
 959
 960     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 961     if (env->interrupt_injected >= 0) {
 962         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 963                 (uint64_t)1 << (env->interrupt_injected % 64);
 964     }
 965
 966     if ((env->eflags & VM_MASK)) {
 967         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 968         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 969         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 970         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 971         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 972         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 973     } else {
 974         set_seg(&sregs.cs, &env->segs[R_CS]);
 975         set_seg(&sregs.ds, &env->segs[R_DS]);
 976         set_seg(&sregs.es, &env->segs[R_ES]);
 977         set_seg(&sregs.fs, &env->segs[R_FS]);
 978         set_seg(&sregs.gs, &env->segs[R_GS]);
 979         set_seg(&sregs.ss, &env->segs[R_SS]);
 980     }
 981
 982     set_seg(&sregs.tr, &env->tr);
 983     set_seg(&sregs.ldt, &env->ldt);
 984
 985     sregs.idt.limit = env->idt.limit;
 986     sregs.idt.base = env->idt.base;
 987     memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
 988     sregs.gdt.limit = env->gdt.limit;
 989     sregs.gdt.base = env->gdt.base;
 990     memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
 991
 992     sregs.cr0 = env->cr[0];
 993     sregs.cr2 = env->cr[2];
 994     sregs.cr3 = env->cr[3];
 995     sregs.cr4 = env->cr[4];
 996
 997     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 998     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 999
1000     sregs.efer = env->efer;
1001
1002     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
1003 }
1004
1005 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1006                               uint32_t index, uint64_t value)
1007 {
1008     entry->index = index;
1009     entry->data = value;
1010 }
1011
1012 static int kvm_put_msrs(CPUX86State *env, int level)
1013 {
1014     struct {
1015         struct kvm_msrs info;
1016         struct kvm_msr_entry entries[100];
1017     } msr_data;
1018     struct kvm_msr_entry *msrs = msr_data.entries;
1019     int n = 0;
1020
1021     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1022     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1023     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1024     kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1025     if (has_msr_star) {
1026         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1027     }
1028     if (has_msr_hsave_pa) {
1029         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1030     }
1031     if (has_msr_tsc_deadline) {
1032         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1033     }
1034     if (has_msr_misc_enable) {
1035         kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1036                           env->msr_ia32_misc_enable);
1037     }
1038 #ifdef TARGET_X86_64
1039     if (lm_capable_kernel) {
1040         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1041         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1042         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1043         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1044     }
1045 #endif
1046     if (level == KVM_PUT_FULL_STATE) {
1047         /*
1048          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
1049          * writeback. Until this is fixed, we only write the offset to SMP
1050          * guests after migration, desynchronizing the VCPUs, but avoiding
1051          * huge jump-backs that would occur without any writeback at all.
1052          */
1053         if (smp_cpus == 1 || env->tsc != 0) {
1054             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1055         }
1056     }
1057     /*
1058      * The following paravirtual MSRs have side effects on the guest or are
1059      * too heavy for normal writeback. Limit them to reset or full state
1060      * updates.
1061      */
1062     if (level >= KVM_PUT_RESET_STATE) {
1063         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1064                           env->system_time_msr);
1065         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1066         if (has_msr_async_pf_en) {
1067             kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1068                               env->async_pf_en_msr);
1069         }
1070         if (has_msr_pv_eoi_en) {
1071             kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1072                               env->pv_eoi_en_msr);
1073         }
1074         if (hyperv_hypercall_available()) {
1075             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0);
1076             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0);
1077         }
1078         if (hyperv_vapic_recommended()) {
1079             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
1080         }
1081     }
1082     if (env->mcg_cap) {
1083         int i;
1084
1085         kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1086         kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1087         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1088             kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1089         }
1090     }
1091
1092     msr_data.info.nmsrs = n;
1093
1094     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
1095
1096 }
1097
1098
1099 static int kvm_get_fpu(CPUX86State *env)
1100 {
1101     struct kvm_fpu fpu;
1102     int i, ret;
1103
1104     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
1105     if (ret < 0) {
1106         return ret;
1107     }
1108
1109     env->fpstt = (fpu.fsw >> 11) & 7;
1110     env->fpus = fpu.fsw;
1111     env->fpuc = fpu.fcw;
1112     env->fpop = fpu.last_opcode;
1113     env->fpip = fpu.last_ip;
1114     env->fpdp = fpu.last_dp;
1115     for (i = 0; i < 8; ++i) {
1116         env->fptags[i] = !((fpu.ftwx >> i) & 1);
1117     }
1118     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1119     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1120     env->mxcsr = fpu.mxcsr;
1121
1122     return 0;
1123 }
1124
1125 static int kvm_get_xsave(CPUX86State *env)
1126 {
1127     struct kvm_xsave* xsave = env->kvm_xsave_buf;
1128     int ret, i;
1129     uint16_t cwd, swd, twd;
1130
1131     if (!kvm_has_xsave()) {
1132         return kvm_get_fpu(env);
1133     }
1134
1135     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
1136     if (ret < 0) {
1137         return ret;
1138     }
1139
1140     cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1141     swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1142     twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1143     env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1144     env->fpstt = (swd >> 11) & 7;
1145     env->fpus = swd;
1146     env->fpuc = cwd;
1147     for (i = 0; i < 8; ++i) {
1148         env->fptags[i] = !((twd >> i) & 1);
1149     }
1150     memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1151     memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1152     env->mxcsr = xsave->region[XSAVE_MXCSR];
1153     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1154             sizeof env->fpregs);
1155     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1156             sizeof env->xmm_regs);
1157     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1158     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1159             sizeof env->ymmh_regs);
1160     return 0;
1161 }
1162
1163 static int kvm_get_xcrs(CPUX86State *env)
1164 {
1165     int i, ret;
1166     struct kvm_xcrs xcrs;
1167
1168     if (!kvm_has_xcrs()) {
1169         return 0;
1170     }
1171
1172     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
1173     if (ret < 0) {
1174         return ret;
1175     }
1176
1177     for (i = 0; i < xcrs.nr_xcrs; i++) {
1178         /* Only support xcr0 now */
1179         if (xcrs.xcrs[0].xcr == 0) {
1180             env->xcr0 = xcrs.xcrs[0].value;
1181             break;
1182         }
1183     }
1184     return 0;
1185 }
1186
1187 static int kvm_get_sregs(CPUX86State *env)
1188 {
1189     struct kvm_sregs sregs;
1190     uint32_t hflags;
1191     int bit, i, ret;
1192
1193     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
1194     if (ret < 0) {
1195         return ret;
1196     }
1197
1198     /* There can only be one pending IRQ set in the bitmap at a time, so try
1199        to find it and save its number instead (-1 for none). */
1200     env->interrupt_injected = -1;
1201     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1202         if (sregs.interrupt_bitmap[i]) {
1203             bit = ctz64(sregs.interrupt_bitmap[i]);
1204             env->interrupt_injected = i * 64 + bit;
1205             break;
1206         }
1207     }
1208
1209     get_seg(&env->segs[R_CS], &sregs.cs);
1210     get_seg(&env->segs[R_DS], &sregs.ds);
1211     get_seg(&env->segs[R_ES], &sregs.es);
1212     get_seg(&env->segs[R_FS], &sregs.fs);
1213     get_seg(&env->segs[R_GS], &sregs.gs);
1214     get_seg(&env->segs[R_SS], &sregs.ss);
1215
1216     get_seg(&env->tr, &sregs.tr);
1217     get_seg(&env->ldt, &sregs.ldt);
1218
1219     env->idt.limit = sregs.idt.limit;
1220     env->idt.base = sregs.idt.base;
1221     env->gdt.limit = sregs.gdt.limit;
1222     env->gdt.base = sregs.gdt.base;
1223
1224     env->cr[0] = sregs.cr0;
1225     env->cr[2] = sregs.cr2;
1226     env->cr[3] = sregs.cr3;
1227     env->cr[4] = sregs.cr4;
1228
1229     env->efer = sregs.efer;
1230
1231     /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1232
1233 #define HFLAG_COPY_MASK \
1234     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1235        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1236        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1237        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1238
1239     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1240     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1241     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1242                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1243     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1244     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1245                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1246
1247     if (env->efer & MSR_EFER_LMA) {
1248         hflags |= HF_LMA_MASK;
1249     }
1250
1251     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1252         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1253     } else {
1254         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1255                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1256         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1257                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1258         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1259             !(hflags & HF_CS32_MASK)) {
1260             hflags |= HF_ADDSEG_MASK;
1261         } else {
1262             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1263                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1264         }
1265     }
1266     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1267
1268     return 0;
1269 }
1270
1271 static int kvm_get_msrs(CPUX86State *env)
1272 {
1273     struct {
1274         struct kvm_msrs info;
1275         struct kvm_msr_entry entries[100];
1276     } msr_data;
1277     struct kvm_msr_entry *msrs = msr_data.entries;
1278     int ret, i, n;
1279
1280     n = 0;
1281     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1282     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1283     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1284     msrs[n++].index = MSR_PAT;
1285     if (has_msr_star) {
1286         msrs[n++].index = MSR_STAR;
1287     }
1288     if (has_msr_hsave_pa) {
1289         msrs[n++].index = MSR_VM_HSAVE_PA;
1290     }
1291     if (has_msr_tsc_deadline) {
1292         msrs[n++].index = MSR_IA32_TSCDEADLINE;
1293     }
1294     if (has_msr_misc_enable) {
1295         msrs[n++].index = MSR_IA32_MISC_ENABLE;
1296     }
1297
1298     if (!env->tsc_valid) {
1299         msrs[n++].index = MSR_IA32_TSC;
1300         env->tsc_valid = !runstate_is_running();
1301     }
1302
1303 #ifdef TARGET_X86_64
1304     if (lm_capable_kernel) {
1305         msrs[n++].index = MSR_CSTAR;
1306         msrs[n++].index = MSR_KERNELGSBASE;
1307         msrs[n++].index = MSR_FMASK;
1308         msrs[n++].index = MSR_LSTAR;
1309     }
1310 #endif
1311     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1312     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1313     if (has_msr_async_pf_en) {
1314         msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1315     }
1316     if (has_msr_pv_eoi_en) {
1317         msrs[n++].index = MSR_KVM_PV_EOI_EN;
1318     }
1319
1320     if (env->mcg_cap) {
1321         msrs[n++].index = MSR_MCG_STATUS;
1322         msrs[n++].index = MSR_MCG_CTL;
1323         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1324             msrs[n++].index = MSR_MC0_CTL + i;
1325         }
1326     }
1327
1328     msr_data.info.nmsrs = n;
1329     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1330     if (ret < 0) {
1331         return ret;
1332     }
1333
1334     for (i = 0; i < ret; i++) {
1335         switch (msrs[i].index) {
1336         case MSR_IA32_SYSENTER_CS:
1337             env->sysenter_cs = msrs[i].data;
1338             break;
1339         case MSR_IA32_SYSENTER_ESP:
1340             env->sysenter_esp = msrs[i].data;
1341             break;
1342         case MSR_IA32_SYSENTER_EIP:
1343             env->sysenter_eip = msrs[i].data;
1344             break;
1345         case MSR_PAT:
1346             env->pat = msrs[i].data;
1347             break;
1348         case MSR_STAR:
1349             env->star = msrs[i].data;
1350             break;
1351 #ifdef TARGET_X86_64
1352         case MSR_CSTAR:
1353             env->cstar = msrs[i].data;
1354             break;
1355         case MSR_KERNELGSBASE:
1356             env->kernelgsbase = msrs[i].data;
1357             break;
1358         case MSR_FMASK:
1359             env->fmask = msrs[i].data;
1360             break;
1361         case MSR_LSTAR:
1362             env->lstar = msrs[i].data;
1363             break;
1364 #endif
1365         case MSR_IA32_TSC:
1366             env->tsc = msrs[i].data;
1367             break;
1368         case MSR_IA32_TSCDEADLINE:
1369             env->tsc_deadline = msrs[i].data;
1370             break;
1371         case MSR_VM_HSAVE_PA:
1372             env->vm_hsave = msrs[i].data;
1373             break;
1374         case MSR_KVM_SYSTEM_TIME:
1375             env->system_time_msr = msrs[i].data;
1376             break;
1377         case MSR_KVM_WALL_CLOCK:
1378             env->wall_clock_msr = msrs[i].data;
1379             break;
1380         case MSR_MCG_STATUS:
1381             env->mcg_status = msrs[i].data;
1382             break;
1383         case MSR_MCG_CTL:
1384             env->mcg_ctl = msrs[i].data;
1385             break;
1386         case MSR_IA32_MISC_ENABLE:
1387             env->msr_ia32_misc_enable = msrs[i].data;
1388             break;
1389         default:
1390             if (msrs[i].index >= MSR_MC0_CTL &&
1391                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1392                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1393             }
1394             break;
1395         case MSR_KVM_ASYNC_PF_EN:
1396             env->async_pf_en_msr = msrs[i].data;
1397             break;
1398         case MSR_KVM_PV_EOI_EN:
1399             env->pv_eoi_en_msr = msrs[i].data;
1400             break;
1401         }
1402     }
1403
1404     return 0;
1405 }
1406
1407 static int kvm_put_mp_state(CPUX86State *env)
1408 {
1409     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1410
1411     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1412 }
1413
1414 static int kvm_get_mp_state(CPUX86State *env)
1415 {
1416     struct kvm_mp_state mp_state;
1417     int ret;
1418
1419     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1420     if (ret < 0) {
1421         return ret;
1422     }
1423     env->mp_state = mp_state.mp_state;
1424     if (kvm_irqchip_in_kernel()) {
1425         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1426     }
1427     return 0;
1428 }
1429
1430 static int kvm_get_apic(CPUX86State *env)
1431 {
1432     DeviceState *apic = env->apic_state;
1433     struct kvm_lapic_state kapic;
1434     int ret;
1435
1436     if (apic && kvm_irqchip_in_kernel()) {
1437         ret = kvm_vcpu_ioctl(env, KVM_GET_LAPIC, &kapic);
1438         if (ret < 0) {
1439             return ret;
1440         }
1441
1442         kvm_get_apic_state(apic, &kapic);
1443     }
1444     return 0;
1445 }
1446
1447 static int kvm_put_apic(CPUX86State *env)
1448 {
1449     DeviceState *apic = env->apic_state;
1450     struct kvm_lapic_state kapic;
1451
1452     if (apic && kvm_irqchip_in_kernel()) {
1453         kvm_put_apic_state(apic, &kapic);
1454
1455         return kvm_vcpu_ioctl(env, KVM_SET_LAPIC, &kapic);
1456     }
1457     return 0;
1458 }
1459
1460 static int kvm_put_vcpu_events(CPUX86State *env, int level)
1461 {
1462     struct kvm_vcpu_events events;
1463
1464     if (!kvm_has_vcpu_events()) {
1465         return 0;
1466     }
1467
1468     events.exception.injected = (env->exception_injected >= 0);
1469     events.exception.nr = env->exception_injected;
1470     events.exception.has_error_code = env->has_error_code;
1471     events.exception.error_code = env->error_code;
1472     events.exception.pad = 0;
1473
1474     events.interrupt.injected = (env->interrupt_injected >= 0);
1475     events.interrupt.nr = env->interrupt_injected;
1476     events.interrupt.soft = env->soft_interrupt;
1477
1478     events.nmi.injected = env->nmi_injected;
1479     events.nmi.pending = env->nmi_pending;
1480     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1481     events.nmi.pad = 0;
1482
1483     events.sipi_vector = env->sipi_vector;
1484
1485     events.flags = 0;
1486     if (level >= KVM_PUT_RESET_STATE) {
1487         events.flags |=
1488             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1489     }
1490
1491     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1492 }
1493
1494 static int kvm_get_vcpu_events(CPUX86State *env)
1495 {
1496     struct kvm_vcpu_events events;
1497     int ret;
1498
1499     if (!kvm_has_vcpu_events()) {
1500         return 0;
1501     }
1502
1503     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1504     if (ret < 0) {
1505        return ret;
1506     }
1507     env->exception_injected =
1508        events.exception.injected ? events.exception.nr : -1;
1509     env->has_error_code = events.exception.has_error_code;
1510     env->error_code = events.exception.error_code;
1511
1512     env->interrupt_injected =
1513         events.interrupt.injected ? events.interrupt.nr : -1;
1514     env->soft_interrupt = events.interrupt.soft;
1515
1516     env->nmi_injected = events.nmi.injected;
1517     env->nmi_pending = events.nmi.pending;
1518     if (events.nmi.masked) {
1519         env->hflags2 |= HF2_NMI_MASK;
1520     } else {
1521         env->hflags2 &= ~HF2_NMI_MASK;
1522     }
1523
1524     env->sipi_vector = events.sipi_vector;
1525
1526     return 0;
1527 }
1528
1529 static int kvm_guest_debug_workarounds(CPUX86State *env)
1530 {
1531     int ret = 0;
1532     unsigned long reinject_trap = 0;
1533
1534     if (!kvm_has_vcpu_events()) {
1535         if (env->exception_injected == 1) {
1536             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1537         } else if (env->exception_injected == 3) {
1538             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1539         }
1540         env->exception_injected = -1;
1541     }
1542
1543     /*
1544      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1545      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1546      * by updating the debug state once again if single-stepping is on.
1547      * Another reason to call kvm_update_guest_debug here is a pending debug
1548      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1549      * reinject them via SET_GUEST_DEBUG.
1550      */
1551     if (reinject_trap ||
1552         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1553         ret = kvm_update_guest_debug(env, reinject_trap);
1554     }
1555     return ret;
1556 }
1557
1558 static int kvm_put_debugregs(CPUX86State *env)
1559 {
1560     struct kvm_debugregs dbgregs;
1561     int i;
1562
1563     if (!kvm_has_debugregs()) {
1564         return 0;
1565     }
1566
1567     for (i = 0; i < 4; i++) {
1568         dbgregs.db[i] = env->dr[i];
1569     }
1570     dbgregs.dr6 = env->dr[6];
1571     dbgregs.dr7 = env->dr[7];
1572     dbgregs.flags = 0;
1573
1574     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1575 }
1576
1577 static int kvm_get_debugregs(CPUX86State *env)
1578 {
1579     struct kvm_debugregs dbgregs;
1580     int i, ret;
1581
1582     if (!kvm_has_debugregs()) {
1583         return 0;
1584     }
1585
1586     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1587     if (ret < 0) {
1588         return ret;
1589     }
1590     for (i = 0; i < 4; i++) {
1591         env->dr[i] = dbgregs.db[i];
1592     }
1593     env->dr[4] = env->dr[6] = dbgregs.dr6;
1594     env->dr[5] = env->dr[7] = dbgregs.dr7;
1595
1596     return 0;
1597 }
1598
1599 int kvm_arch_put_registers(CPUX86State *env, int level)
1600 {
1601     int ret;
1602
1603     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1604
1605     ret = kvm_getput_regs(env, 1);
1606     if (ret < 0) {
1607         return ret;
1608     }
1609     ret = kvm_put_xsave(env);
1610     if (ret < 0) {
1611         return ret;
1612     }
1613     ret = kvm_put_xcrs(env);
1614     if (ret < 0) {
1615         return ret;
1616     }
1617     ret = kvm_put_sregs(env);
1618     if (ret < 0) {
1619         return ret;
1620     }
1621     /* must be before kvm_put_msrs */
1622     ret = kvm_inject_mce_oldstyle(env);
1623     if (ret < 0) {
1624         return ret;
1625     }
1626     ret = kvm_put_msrs(env, level);
1627     if (ret < 0) {
1628         return ret;
1629     }
1630     if (level >= KVM_PUT_RESET_STATE) {
1631         ret = kvm_put_mp_state(env);
1632         if (ret < 0) {
1633             return ret;
1634         }
1635         ret = kvm_put_apic(env);
1636         if (ret < 0) {
1637             return ret;
1638         }
1639     }
1640     ret = kvm_put_vcpu_events(env, level);
1641     if (ret < 0) {
1642         return ret;
1643     }
1644     ret = kvm_put_debugregs(env);
1645     if (ret < 0) {
1646         return ret;
1647     }
1648     /* must be last */
1649     ret = kvm_guest_debug_workarounds(env);
1650     if (ret < 0) {
1651         return ret;
1652     }
1653     return 0;
1654 }
1655
1656 int kvm_arch_get_registers(CPUX86State *env)
1657 {
1658     int ret;
1659
1660     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1661
1662     ret = kvm_getput_regs(env, 0);
1663     if (ret < 0) {
1664         return ret;
1665     }
1666     ret = kvm_get_xsave(env);
1667     if (ret < 0) {
1668         return ret;
1669     }
1670     ret = kvm_get_xcrs(env);
1671     if (ret < 0) {
1672         return ret;
1673     }
1674     ret = kvm_get_sregs(env);
1675     if (ret < 0) {
1676         return ret;
1677     }
1678     ret = kvm_get_msrs(env);
1679     if (ret < 0) {
1680         return ret;
1681     }
1682     ret = kvm_get_mp_state(env);
1683     if (ret < 0) {
1684         return ret;
1685     }
1686     ret = kvm_get_apic(env);
1687     if (ret < 0) {
1688         return ret;
1689     }
1690     ret = kvm_get_vcpu_events(env);
1691     if (ret < 0) {
1692         return ret;
1693     }
1694     ret = kvm_get_debugregs(env);
1695     if (ret < 0) {
1696         return ret;
1697     }
1698     return 0;
1699 }
1700
1701 void kvm_arch_pre_run(CPUX86State *env, struct kvm_run *run)
1702 {
1703     int ret;
1704
1705     /* Inject NMI */
1706     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1707         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1708         DPRINTF("injected NMI\n");
1709         ret = kvm_vcpu_ioctl(env, KVM_NMI);
1710         if (ret < 0) {
1711             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1712                     strerror(-ret));
1713         }
1714     }
1715
1716     if (!kvm_irqchip_in_kernel()) {
1717         /* Force the VCPU out of its inner loop to process any INIT requests
1718          * or pending TPR access reports. */
1719         if (env->interrupt_request &
1720             (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
1721             env->exit_request = 1;
1722         }
1723
1724         /* Try to inject an interrupt if the guest can accept it */
1725         if (run->ready_for_interrupt_injection &&
1726             (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1727             (env->eflags & IF_MASK)) {
1728             int irq;
1729
1730             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1731             irq = cpu_get_pic_interrupt(env);
1732             if (irq >= 0) {
1733                 struct kvm_interrupt intr;
1734
1735                 intr.irq = irq;
1736                 DPRINTF("injected interrupt %d\n", irq);
1737                 ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1738                 if (ret < 0) {
1739                     fprintf(stderr,
1740                             "KVM: injection failed, interrupt lost (%s)\n",
1741                             strerror(-ret));
1742                 }
1743             }
1744         }
1745
1746         /* If we have an interrupt but the guest is not ready to receive an
1747          * interrupt, request an interrupt window exit.  This will
1748          * cause a return to userspace as soon as the guest is ready to
1749          * receive interrupts. */
1750         if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1751             run->request_interrupt_window = 1;
1752         } else {
1753             run->request_interrupt_window = 0;
1754         }
1755
1756         DPRINTF("setting tpr\n");
1757         run->cr8 = cpu_get_apic_tpr(env->apic_state);
1758     }
1759 }
1760
1761 void kvm_arch_post_run(CPUX86State *env, struct kvm_run *run)
1762 {
1763     if (run->if_flag) {
1764         env->eflags |= IF_MASK;
1765     } else {
1766         env->eflags &= ~IF_MASK;
1767     }
1768     cpu_set_apic_tpr(env->apic_state, run->cr8);
1769     cpu_set_apic_base(env->apic_state, run->apic_base);
1770 }
1771
1772 int kvm_arch_process_async_events(CPUX86State *env)
1773 {
1774     X86CPU *cpu = x86_env_get_cpu(env);
1775
1776     if (env->interrupt_request & CPU_INTERRUPT_MCE) {
1777         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1778         assert(env->mcg_cap);
1779
1780         env->interrupt_request &= ~CPU_INTERRUPT_MCE;
1781
1782         kvm_cpu_synchronize_state(env);
1783
1784         if (env->exception_injected == EXCP08_DBLE) {
1785             /* this means triple fault */
1786             qemu_system_reset_request();
1787             env->exit_request = 1;
1788             return 0;
1789         }
1790         env->exception_injected = EXCP12_MCHK;
1791         env->has_error_code = 0;
1792
1793         env->halted = 0;
1794         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1795             env->mp_state = KVM_MP_STATE_RUNNABLE;
1796         }
1797     }
1798
1799     if (kvm_irqchip_in_kernel()) {
1800         return 0;
1801     }
1802
1803     if (env->interrupt_request & CPU_INTERRUPT_POLL) {
1804         env->interrupt_request &= ~CPU_INTERRUPT_POLL;
1805         apic_poll_irq(env->apic_state);
1806     }
1807     if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1808          (env->eflags & IF_MASK)) ||
1809         (env->interrupt_request & CPU_INTERRUPT_NMI)) {
1810         env->halted = 0;
1811     }
1812     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1813         kvm_cpu_synchronize_state(env);
1814         do_cpu_init(cpu);
1815     }
1816     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1817         kvm_cpu_synchronize_state(env);
1818         do_cpu_sipi(cpu);
1819     }
1820     if (env->interrupt_request & CPU_INTERRUPT_TPR) {
1821         env->interrupt_request &= ~CPU_INTERRUPT_TPR;
1822         kvm_cpu_synchronize_state(env);
1823         apic_handle_tpr_access_report(env->apic_state, env->eip,
1824                                       env->tpr_access_type);
1825     }
1826
1827     return env->halted;
1828 }
1829
1830 static int kvm_handle_halt(CPUX86State *env)
1831 {
1832     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1833           (env->eflags & IF_MASK)) &&
1834         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1835         env->halted = 1;
1836         return EXCP_HLT;
1837     }
1838
1839     return 0;
1840 }
1841
1842 static int kvm_handle_tpr_access(CPUX86State *env)
1843 {
1844     struct kvm_run *run = env->kvm_run;
1845
1846     apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip,
1847                                   run->tpr_access.is_write ? TPR_ACCESS_WRITE
1848                                                            : TPR_ACCESS_READ);
1849     return 1;
1850 }
1851
1852 int kvm_arch_insert_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
1853 {
1854     static const uint8_t int3 = 0xcc;
1855
1856     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1857         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1858         return -EINVAL;
1859     }
1860     return 0;
1861 }
1862
1863 int kvm_arch_remove_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
1864 {
1865     uint8_t int3;
1866
1867     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1868         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1869         return -EINVAL;
1870     }
1871     return 0;
1872 }
1873
1874 static struct {
1875     target_ulong addr;
1876     int len;
1877     int type;
1878 } hw_breakpoint[4];
1879
1880 static int nb_hw_breakpoint;
1881
1882 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1883 {
1884     int n;
1885
1886     for (n = 0; n < nb_hw_breakpoint; n++) {
1887         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1888             (hw_breakpoint[n].len == len || len == -1)) {
1889             return n;
1890         }
1891     }
1892     return -1;
1893 }
1894
1895 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1896                                   target_ulong len, int type)
1897 {
1898     switch (type) {
1899     case GDB_BREAKPOINT_HW:
1900         len = 1;
1901         break;
1902     case GDB_WATCHPOINT_WRITE:
1903     case GDB_WATCHPOINT_ACCESS:
1904         switch (len) {
1905         case 1:
1906             break;
1907         case 2:
1908         case 4:
1909         case 8:
1910             if (addr & (len - 1)) {
1911                 return -EINVAL;
1912             }
1913             break;
1914         default:
1915             return -EINVAL;
1916         }
1917         break;
1918     default:
1919         return -ENOSYS;
1920     }
1921
1922     if (nb_hw_breakpoint == 4) {
1923         return -ENOBUFS;
1924     }
1925     if (find_hw_breakpoint(addr, len, type) >= 0) {
1926         return -EEXIST;
1927     }
1928     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1929     hw_breakpoint[nb_hw_breakpoint].len = len;
1930     hw_breakpoint[nb_hw_breakpoint].type = type;
1931     nb_hw_breakpoint++;
1932
1933     return 0;
1934 }
1935
1936 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1937                                   target_ulong len, int type)
1938 {
1939     int n;
1940
1941     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1942     if (n < 0) {
1943         return -ENOENT;
1944     }
1945     nb_hw_breakpoint--;
1946     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1947
1948     return 0;
1949 }
1950
1951 void kvm_arch_remove_all_hw_breakpoints(void)
1952 {
1953     nb_hw_breakpoint = 0;
1954 }
1955
1956 static CPUWatchpoint hw_watchpoint;
1957
1958 static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info)
1959 {
1960     int ret = 0;
1961     int n;
1962
1963     if (arch_info->exception == 1) {
1964         if (arch_info->dr6 & (1 << 14)) {
1965             if (cpu_single_env->singlestep_enabled) {
1966                 ret = EXCP_DEBUG;
1967             }
1968         } else {
1969             for (n = 0; n < 4; n++) {
1970                 if (arch_info->dr6 & (1 << n)) {
1971                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1972                     case 0x0:
1973                         ret = EXCP_DEBUG;
1974                         break;
1975                     case 0x1:
1976                         ret = EXCP_DEBUG;
1977                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1978                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1979                         hw_watchpoint.flags = BP_MEM_WRITE;
1980                         break;
1981                     case 0x3:
1982                         ret = EXCP_DEBUG;
1983                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1984                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1985                         hw_watchpoint.flags = BP_MEM_ACCESS;
1986                         break;
1987                     }
1988                 }
1989             }
1990         }
1991     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1992         ret = EXCP_DEBUG;
1993     }
1994     if (ret == 0) {
1995         cpu_synchronize_state(cpu_single_env);
1996         assert(cpu_single_env->exception_injected == -1);
1997
1998         /* pass to guest */
1999         cpu_single_env->exception_injected = arch_info->exception;
2000         cpu_single_env->has_error_code = 0;
2001     }
2002
2003     return ret;
2004 }
2005
2006 void kvm_arch_update_guest_debug(CPUX86State *env, struct kvm_guest_debug *dbg)
2007 {
2008     const uint8_t type_code[] = {
2009         [GDB_BREAKPOINT_HW] = 0x0,
2010         [GDB_WATCHPOINT_WRITE] = 0x1,
2011         [GDB_WATCHPOINT_ACCESS] = 0x3
2012     };
2013     const uint8_t len_code[] = {
2014         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2015     };
2016     int n;
2017
2018     if (kvm_sw_breakpoints_active(env)) {
2019         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2020     }
2021     if (nb_hw_breakpoint > 0) {
2022         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2023         dbg->arch.debugreg[7] = 0x0600;
2024         for (n = 0; n < nb_hw_breakpoint; n++) {
2025             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2026             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2027                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2028                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2029         }
2030     }
2031 }
2032
2033 static bool host_supports_vmx(void)
2034 {
2035     uint32_t ecx, unused;
2036
2037     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2038     return ecx & CPUID_EXT_VMX;
2039 }
2040
2041 #define VMX_INVALID_GUEST_STATE 0x80000021
2042
2043 int kvm_arch_handle_exit(CPUX86State *env, struct kvm_run *run)
2044 {
2045     uint64_t code;
2046     int ret;
2047
2048     switch (run->exit_reason) {
2049     case KVM_EXIT_HLT:
2050         DPRINTF("handle_hlt\n");
2051         ret = kvm_handle_halt(env);
2052         break;
2053     case KVM_EXIT_SET_TPR:
2054         ret = 0;
2055         break;
2056     case KVM_EXIT_TPR_ACCESS:
2057         ret = kvm_handle_tpr_access(env);
2058         break;
2059     case KVM_EXIT_FAIL_ENTRY:
2060         code = run->fail_entry.hardware_entry_failure_reason;
2061         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2062                 code);
2063         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2064             fprintf(stderr,
2065                     "\nIf you're running a guest on an Intel machine without "
2066                         "unrestricted mode\n"
2067                     "support, the failure can be most likely due to the guest "
2068                         "entering an invalid\n"
2069                     "state for Intel VT. For example, the guest maybe running "
2070                         "in big real mode\n"
2071                     "which is not supported on less recent Intel processors."
2072                         "\n\n");
2073         }
2074         ret = -1;
2075         break;
2076     case KVM_EXIT_EXCEPTION:
2077         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2078                 run->ex.exception, run->ex.error_code);
2079         ret = -1;
2080         break;
2081     case KVM_EXIT_DEBUG:
2082         DPRINTF("kvm_exit_debug\n");
2083         ret = kvm_handle_debug(&run->debug.arch);
2084         break;
2085     default:
2086         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2087         ret = -1;
2088         break;
2089     }
2090
2091     return ret;
2092 }
2093
2094 bool kvm_arch_stop_on_emulation_error(CPUX86State *env)
2095 {
2096     kvm_cpu_synchronize_state(env);
2097     return !(env->cr[0] & CR0_PE_MASK) ||
2098            ((env->segs[R_CS].selector  & 3) != 3);
2099 }
2100
2101 void kvm_arch_init_irq_routing(KVMState *s)
2102 {
2103     if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2104         /* If kernel can't do irq routing, interrupt source
2105          * override 0->2 cannot be set up as required by HPET.
2106          * So we have to disable it.
2107          */
2108         no_hpet = 1;
2109     }
2110     /* We know at this point that we're using the in-kernel
2111      * irqchip, so we can use irqfds, and on x86 we know
2112      * we can use msi via irqfd and GSI routing.
2113      */
2114     kvm_irqfds_allowed = true;
2115     kvm_msi_via_irqfd_allowed = true;
2116     kvm_gsi_routing_allowed = true;
2117 }
2118
2119 /* Classic KVM device assignment interface. Will remain x86 only. */
2120 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2121                           uint32_t flags, uint32_t *dev_id)
2122 {
2123     struct kvm_assigned_pci_dev dev_data = {
2124         .segnr = dev_addr->domain,
2125         .busnr = dev_addr->bus,
2126         .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2127         .flags = flags,
2128     };
2129     int ret;
2130
2131     dev_data.assigned_dev_id =
2132         (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2133
2134     ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2135     if (ret < 0) {
2136         return ret;
2137     }
2138
2139     *dev_id = dev_data.assigned_dev_id;
2140
2141     return 0;
2142 }
2143
2144 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2145 {
2146     struct kvm_assigned_pci_dev dev_data = {
2147         .assigned_dev_id = dev_id,
2148     };
2149
2150     return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2151 }
2152
2153 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2154                                    uint32_t irq_type, uint32_t guest_irq)
2155 {
2156     struct kvm_assigned_irq assigned_irq = {
2157         .assigned_dev_id = dev_id,
2158         .guest_irq = guest_irq,
2159         .flags = irq_type,
2160     };
2161
2162     if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2163         return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2164     } else {
2165         return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2166     }
2167 }
2168
2169 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2170                            uint32_t guest_irq)
2171 {
2172     uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2173         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2174
2175     return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2176 }
2177
2178 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2179 {
2180     struct kvm_assigned_pci_dev dev_data = {
2181         .assigned_dev_id = dev_id,
2182         .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2183     };
2184
2185     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2186 }
2187
2188 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2189                                      uint32_t type)
2190 {
2191     struct kvm_assigned_irq assigned_irq = {
2192         .assigned_dev_id = dev_id,
2193         .flags = type,
2194     };
2195
2196     return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2197 }
2198
2199 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2200 {
2201     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2202         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2203 }
2204
2205 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2206 {
2207     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2208                                               KVM_DEV_IRQ_GUEST_MSI, virq);
2209 }
2210
2211 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2212 {
2213     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2214                                                 KVM_DEV_IRQ_HOST_MSI);
2215 }
2216
2217 bool kvm_device_msix_supported(KVMState *s)
2218 {
2219     /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2220      * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2221     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2222 }
2223
2224 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2225                                  uint32_t nr_vectors)
2226 {
2227     struct kvm_assigned_msix_nr msix_nr = {
2228         .assigned_dev_id = dev_id,
2229         .entry_nr = nr_vectors,
2230     };
2231
2232     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2233 }
2234
2235 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2236                                int virq)
2237 {
2238     struct kvm_assigned_msix_entry msix_entry = {
2239         .assigned_dev_id = dev_id,
2240         .gsi = virq,
2241         .entry = vector,
2242     };
2243
2244     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2245 }
2246
2247 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2248 {
2249     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2250                                               KVM_DEV_IRQ_GUEST_MSIX, 0);
2251 }
2252
2253 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2254 {
2255     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2256                                                 KVM_DEV_IRQ_HOST_MSIX);
2257 }