linux-user/alpha/target_proc.h

   1 /*
   2  * Alpha specific proc functions for linux-user
   3  *
   4  * SPDX-License-Identifier: GPL-2.0-or-later
   5  */
   6 #ifndef ALPHA_TARGET_PROC_H
   7 #define ALPHA_TARGET_PROC_H
   8
   9 static int open_cpuinfo(CPUArchState *cpu_env, int fd)
  10 {
  11     int max_cpus = sysconf(_SC_NPROCESSORS_CONF);
  12     int num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
  13     unsigned long cpu_mask;
  14     char model[32];
  15     const char *p, *q;
  16     int t;
  17
  18     p = object_class_get_name(OBJECT_CLASS(CPU_GET_CLASS(env_cpu(cpu_env))));
  19     q = strchr(p, '-');
  20     t = q - p;
  21     assert(t < sizeof(model));
  22     memcpy(model, p, t);
  23     model[t] = 0;
  24
  25     t = sched_getaffinity(getpid(), sizeof(cpu_mask), (cpu_set_t *)&cpu_mask);
  26     if (t < 0) {
  27         if (num_cpus >= sizeof(cpu_mask) * 8) {
  28             cpu_mask = -1;
  29         } else {
  30             cpu_mask = (1UL << num_cpus) - 1;
  31         }
  32     }
  33
  34     dprintf(fd,
  35             "cpu\t\t\t: Alpha\n"
  36             "cpu model\t\t: %s\n"
  37             "cpu variation\t\t: 0\n"
  38             "cpu revision\t\t: 0\n"
  39             "cpu serial number\t: JA00000000\n"
  40             "system type\t\t: QEMU\n"
  41             "system variation\t: QEMU_v" QEMU_VERSION "\n"
  42             "system revision\t\t: 0\n"
  43             "system serial number\t: AY00000000\n"
  44             "cycle frequency [Hz]\t: 250000000\n"
  45             "timer frequency [Hz]\t: 250.00\n"
  46             "page size [bytes]\t: %d\n"
  47             "phys. address bits\t: %d\n"
  48             "max. addr. space #\t: 255\n"
  49             "BogoMIPS\t\t: 2500.00\n"
  50             "kernel unaligned acc\t: 0 (pc=0,va=0)\n"
  51             "user unaligned acc\t: 0 (pc=0,va=0)\n"
  52             "platform string\t\t: AlphaServer QEMU user-mode VM\n"
  53             "cpus detected\t\t: %d\n"
  54             "cpus active\t\t: %d\n"
  55             "cpu active mask\t\t: %016lx\n"
  56             "L1 Icache\t\t: n/a\n"
  57             "L1 Dcache\t\t: n/a\n"
  58             "L2 cache\t\t: n/a\n"
  59             "L3 cache\t\t: n/a\n",
  60             model, TARGET_PAGE_SIZE, TARGET_PHYS_ADDR_SPACE_BITS,
  61             max_cpus, num_cpus, cpu_mask);
  62
  63     return 0;
  64 }
  65 #define HAVE_ARCH_PROC_CPUINFO
  66
  67 #endif /* ALPHA_TARGET_PROC_H */