user-exec.c

   1 /*
   2  *  User emulator execution
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "disas/disas.h"
  22 #include "exec/exec-all.h"
  23 #include "tcg.h"
  24 #include "qemu/bitops.h"
  25 #include "exec/cpu_ldst.h"
  26 #include "translate-all.h"
  27
  28 #undef EAX
  29 #undef ECX
  30 #undef EDX
  31 #undef EBX
  32 #undef ESP
  33 #undef EBP
  34 #undef ESI
  35 #undef EDI
  36 #undef EIP
  37 #ifdef __linux__
  38 #include <sys/ucontext.h>
  39 #endif
  40
  41 //#define DEBUG_SIGNAL
  42
  43 /* exit the current TB from a signal handler. The host registers are
  44    restored in a state compatible with the CPU emulator
  45  */
  46 static void cpu_exit_tb_from_sighandler(CPUState *cpu, sigset_t *old_set)
  47 {
  48     /* XXX: use siglongjmp ? */
  49     sigprocmask(SIG_SETMASK, old_set, NULL);
  50     cpu_loop_exit_noexc(cpu);
  51 }
  52
  53 /* 'pc' is the host PC at which the exception was raised. 'address' is
  54    the effective address of the memory exception. 'is_write' is 1 if a
  55    write caused the exception and otherwise 0'. 'old_set' is the
  56    signal set which should be restored */
  57 static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
  58                                     int is_write, sigset_t *old_set)
  59 {
  60     CPUState *cpu;
  61     CPUClass *cc;
  62     int ret;
  63
  64 #if defined(DEBUG_SIGNAL)
  65     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
  66            pc, address, is_write, *(unsigned long *)old_set);
  67 #endif
  68     /* XXX: locking issue */
  69     if (is_write && h2g_valid(address)) {
  70         switch (page_unprotect(h2g(address), pc)) {
  71         case 0:
  72             /* Fault not caused by a page marked unwritable to protect
  73              * cached translations, must be the guest binary's problem
  74              */
  75             break;
  76         case 1:
  77             /* Fault caused by protection of cached translation; TBs
  78              * invalidated, so resume execution
  79              */
  80             return 1;
  81         case 2:
  82             /* Fault caused by protection of cached translation, and the
  83              * currently executing TB was modified and must be exited
  84              * immediately.
  85              */
  86             cpu_exit_tb_from_sighandler(current_cpu, old_set);
  87             g_assert_not_reached();
  88         default:
  89             g_assert_not_reached();
  90         }
  91     }
  92
  93     /* Convert forcefully to guest address space, invalid addresses
  94        are still valid segv ones */
  95     address = h2g_nocheck(address);
  96
  97     cpu = current_cpu;
  98     cc = CPU_GET_CLASS(cpu);
  99     /* see if it is an MMU fault */
 100     g_assert(cc->handle_mmu_fault);
 101     ret = cc->handle_mmu_fault(cpu, address, is_write, MMU_USER_IDX);
 102     if (ret < 0) {
 103         return 0; /* not an MMU fault */
 104     }
 105     if (ret == 0) {
 106         return 1; /* the MMU fault was handled without causing real CPU fault */
 107     }
 108
 109     /* Now we have a real cpu fault.  Since this is the exact location of
 110      * the exception, we must undo the adjustment done by cpu_restore_state
 111      * for handling call return addresses.  */
 112     cpu_restore_state(cpu, pc + GETPC_ADJ);
 113
 114     sigprocmask(SIG_SETMASK, old_set, NULL);
 115     cpu_loop_exit(cpu);
 116
 117     /* never comes here */
 118     return 1;
 119 }
 120
 121 #if defined(__i386__)
 122
 123 #if defined(__NetBSD__)
 124 #include <ucontext.h>
 125
 126 #define EIP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_EIP])
 127 #define TRAP_sig(context)    ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 128 #define ERROR_sig(context)   ((context)->uc_mcontext.__gregs[_REG_ERR])
 129 #define MASK_sig(context)    ((context)->uc_sigmask)
 130 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 131 #include <ucontext.h>
 132
 133 #define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
 134 #define TRAP_sig(context)    ((context)->uc_mcontext.mc_trapno)
 135 #define ERROR_sig(context)   ((context)->uc_mcontext.mc_err)
 136 #define MASK_sig(context)    ((context)->uc_sigmask)
 137 #elif defined(__OpenBSD__)
 138 #define EIP_sig(context)     ((context)->sc_eip)
 139 #define TRAP_sig(context)    ((context)->sc_trapno)
 140 #define ERROR_sig(context)   ((context)->sc_err)
 141 #define MASK_sig(context)    ((context)->sc_mask)
 142 #else
 143 #define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])
 144 #define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])
 145 #define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])
 146 #define MASK_sig(context)    ((context)->uc_sigmask)
 147 #endif
 148
 149 int cpu_signal_handler(int host_signum, void *pinfo,
 150                        void *puc)
 151 {
 152     siginfo_t *info = pinfo;
 153 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 154     ucontext_t *uc = puc;
 155 #elif defined(__OpenBSD__)
 156     struct sigcontext *uc = puc;
 157 #else
 158     struct ucontext *uc = puc;
 159 #endif
 160     unsigned long pc;
 161     int trapno;
 162
 163 #ifndef REG_EIP
 164 /* for glibc 2.1 */
 165 #define REG_EIP    EIP
 166 #define REG_ERR    ERR
 167 #define REG_TRAPNO TRAPNO
 168 #endif
 169     pc = EIP_sig(uc);
 170     trapno = TRAP_sig(uc);
 171     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 172                              trapno == 0xe ?
 173                              (ERROR_sig(uc) >> 1) & 1 : 0,
 174                              &MASK_sig(uc));
 175 }
 176
 177 #elif defined(__x86_64__)
 178
 179 #ifdef __NetBSD__
 180 #define PC_sig(context)       _UC_MACHINE_PC(context)
 181 #define TRAP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 182 #define ERROR_sig(context)    ((context)->uc_mcontext.__gregs[_REG_ERR])
 183 #define MASK_sig(context)     ((context)->uc_sigmask)
 184 #elif defined(__OpenBSD__)
 185 #define PC_sig(context)       ((context)->sc_rip)
 186 #define TRAP_sig(context)     ((context)->sc_trapno)
 187 #define ERROR_sig(context)    ((context)->sc_err)
 188 #define MASK_sig(context)     ((context)->sc_mask)
 189 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 190 #include <ucontext.h>
 191
 192 #define PC_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
 193 #define TRAP_sig(context)     ((context)->uc_mcontext.mc_trapno)
 194 #define ERROR_sig(context)    ((context)->uc_mcontext.mc_err)
 195 #define MASK_sig(context)     ((context)->uc_sigmask)
 196 #else
 197 #define PC_sig(context)       ((context)->uc_mcontext.gregs[REG_RIP])
 198 #define TRAP_sig(context)     ((context)->uc_mcontext.gregs[REG_TRAPNO])
 199 #define ERROR_sig(context)    ((context)->uc_mcontext.gregs[REG_ERR])
 200 #define MASK_sig(context)     ((context)->uc_sigmask)
 201 #endif
 202
 203 int cpu_signal_handler(int host_signum, void *pinfo,
 204                        void *puc)
 205 {
 206     siginfo_t *info = pinfo;
 207     unsigned long pc;
 208 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 209     ucontext_t *uc = puc;
 210 #elif defined(__OpenBSD__)
 211     struct sigcontext *uc = puc;
 212 #else
 213     struct ucontext *uc = puc;
 214 #endif
 215
 216     pc = PC_sig(uc);
 217     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 218                              TRAP_sig(uc) == 0xe ?
 219                              (ERROR_sig(uc) >> 1) & 1 : 0,
 220                              &MASK_sig(uc));
 221 }
 222
 223 #elif defined(_ARCH_PPC)
 224
 225 /***********************************************************************
 226  * signal context platform-specific definitions
 227  * From Wine
 228  */
 229 #ifdef linux
 230 /* All Registers access - only for local access */
 231 #define REG_sig(reg_name, context)              \
 232     ((context)->uc_mcontext.regs->reg_name)
 233 /* Gpr Registers access  */
 234 #define GPR_sig(reg_num, context)              REG_sig(gpr[reg_num], context)
 235 /* Program counter */
 236 #define IAR_sig(context)                       REG_sig(nip, context)
 237 /* Machine State Register (Supervisor) */
 238 #define MSR_sig(context)                       REG_sig(msr, context)
 239 /* Count register */
 240 #define CTR_sig(context)                       REG_sig(ctr, context)
 241 /* User's integer exception register */
 242 #define XER_sig(context)                       REG_sig(xer, context)
 243 /* Link register */
 244 #define LR_sig(context)                        REG_sig(link, context)
 245 /* Condition register */
 246 #define CR_sig(context)                        REG_sig(ccr, context)
 247
 248 /* Float Registers access  */
 249 #define FLOAT_sig(reg_num, context)                                     \
 250     (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
 251 #define FPSCR_sig(context) \
 252     (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
 253 /* Exception Registers access */
 254 #define DAR_sig(context)                       REG_sig(dar, context)
 255 #define DSISR_sig(context)                     REG_sig(dsisr, context)
 256 #define TRAP_sig(context)                      REG_sig(trap, context)
 257 #endif /* linux */
 258
 259 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 260 #include <ucontext.h>
 261 #define IAR_sig(context)               ((context)->uc_mcontext.mc_srr0)
 262 #define MSR_sig(context)               ((context)->uc_mcontext.mc_srr1)
 263 #define CTR_sig(context)               ((context)->uc_mcontext.mc_ctr)
 264 #define XER_sig(context)               ((context)->uc_mcontext.mc_xer)
 265 #define LR_sig(context)                ((context)->uc_mcontext.mc_lr)
 266 #define CR_sig(context)                ((context)->uc_mcontext.mc_cr)
 267 /* Exception Registers access */
 268 #define DAR_sig(context)               ((context)->uc_mcontext.mc_dar)
 269 #define DSISR_sig(context)             ((context)->uc_mcontext.mc_dsisr)
 270 #define TRAP_sig(context)              ((context)->uc_mcontext.mc_exc)
 271 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
 272
 273 int cpu_signal_handler(int host_signum, void *pinfo,
 274                        void *puc)
 275 {
 276     siginfo_t *info = pinfo;
 277 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 278     ucontext_t *uc = puc;
 279 #else
 280     struct ucontext *uc = puc;
 281 #endif
 282     unsigned long pc;
 283     int is_write;
 284
 285     pc = IAR_sig(uc);
 286     is_write = 0;
 287 #if 0
 288     /* ppc 4xx case */
 289     if (DSISR_sig(uc) & 0x00800000) {
 290         is_write = 1;
 291     }
 292 #else
 293     if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
 294         is_write = 1;
 295     }
 296 #endif
 297     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 298                              is_write, &uc->uc_sigmask);
 299 }
 300
 301 #elif defined(__alpha__)
 302
 303 int cpu_signal_handler(int host_signum, void *pinfo,
 304                            void *puc)
 305 {
 306     siginfo_t *info = pinfo;
 307     struct ucontext *uc = puc;
 308     uint32_t *pc = uc->uc_mcontext.sc_pc;
 309     uint32_t insn = *pc;
 310     int is_write = 0;
 311
 312     /* XXX: need kernel patch to get write flag faster */
 313     switch (insn >> 26) {
 314     case 0x0d: /* stw */
 315     case 0x0e: /* stb */
 316     case 0x0f: /* stq_u */
 317     case 0x24: /* stf */
 318     case 0x25: /* stg */
 319     case 0x26: /* sts */
 320     case 0x27: /* stt */
 321     case 0x2c: /* stl */
 322     case 0x2d: /* stq */
 323     case 0x2e: /* stl_c */
 324     case 0x2f: /* stq_c */
 325         is_write = 1;
 326     }
 327
 328     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 329                              is_write, &uc->uc_sigmask);
 330 }
 331 #elif defined(__sparc__)
 332
 333 int cpu_signal_handler(int host_signum, void *pinfo,
 334                        void *puc)
 335 {
 336     siginfo_t *info = pinfo;
 337     int is_write;
 338     uint32_t insn;
 339 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
 340     uint32_t *regs = (uint32_t *)(info + 1);
 341     void *sigmask = (regs + 20);
 342     /* XXX: is there a standard glibc define ? */
 343     unsigned long pc = regs[1];
 344 #else
 345 #ifdef __linux__
 346     struct sigcontext *sc = puc;
 347     unsigned long pc = sc->sigc_regs.tpc;
 348     void *sigmask = (void *)sc->sigc_mask;
 349 #elif defined(__OpenBSD__)
 350     struct sigcontext *uc = puc;
 351     unsigned long pc = uc->sc_pc;
 352     void *sigmask = (void *)(long)uc->sc_mask;
 353 #elif defined(__NetBSD__)
 354     ucontext_t *uc = puc;
 355     unsigned long pc = _UC_MACHINE_PC(uc);
 356     void *sigmask = (void *)&uc->uc_sigmask;
 357 #endif
 358 #endif
 359
 360     /* XXX: need kernel patch to get write flag faster */
 361     is_write = 0;
 362     insn = *(uint32_t *)pc;
 363     if ((insn >> 30) == 3) {
 364         switch ((insn >> 19) & 0x3f) {
 365         case 0x05: /* stb */
 366         case 0x15: /* stba */
 367         case 0x06: /* sth */
 368         case 0x16: /* stha */
 369         case 0x04: /* st */
 370         case 0x14: /* sta */
 371         case 0x07: /* std */
 372         case 0x17: /* stda */
 373         case 0x0e: /* stx */
 374         case 0x1e: /* stxa */
 375         case 0x24: /* stf */
 376         case 0x34: /* stfa */
 377         case 0x27: /* stdf */
 378         case 0x37: /* stdfa */
 379         case 0x26: /* stqf */
 380         case 0x36: /* stqfa */
 381         case 0x25: /* stfsr */
 382         case 0x3c: /* casa */
 383         case 0x3e: /* casxa */
 384             is_write = 1;
 385             break;
 386         }
 387     }
 388     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 389                              is_write, sigmask);
 390 }
 391
 392 #elif defined(__arm__)
 393
 394 #if defined(__NetBSD__)
 395 #include <ucontext.h>
 396 #endif
 397
 398 int cpu_signal_handler(int host_signum, void *pinfo,
 399                        void *puc)
 400 {
 401     siginfo_t *info = pinfo;
 402 #if defined(__NetBSD__)
 403     ucontext_t *uc = puc;
 404 #else
 405     struct ucontext *uc = puc;
 406 #endif
 407     unsigned long pc;
 408     int is_write;
 409
 410 #if defined(__NetBSD__)
 411     pc = uc->uc_mcontext.__gregs[_REG_R15];
 412 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
 413     pc = uc->uc_mcontext.gregs[R15];
 414 #else
 415     pc = uc->uc_mcontext.arm_pc;
 416 #endif
 417
 418     /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
 419      * later processor; on v5 we will always report this as a read).
 420      */
 421     is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
 422     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 423                              is_write,
 424                              &uc->uc_sigmask);
 425 }
 426
 427 #elif defined(__aarch64__)
 428
 429 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
 430 {
 431     siginfo_t *info = pinfo;
 432     struct ucontext *uc = puc;
 433     uintptr_t pc = uc->uc_mcontext.pc;
 434     uint32_t insn = *(uint32_t *)pc;
 435     bool is_write;
 436
 437     /* XXX: need kernel patch to get write flag faster.  */
 438     is_write = (   (insn & 0xbfff0000) == 0x0c000000   /* C3.3.1 */
 439                 || (insn & 0xbfe00000) == 0x0c800000   /* C3.3.2 */
 440                 || (insn & 0xbfdf0000) == 0x0d000000   /* C3.3.3 */
 441                 || (insn & 0xbfc00000) == 0x0d800000   /* C3.3.4 */
 442                 || (insn & 0x3f400000) == 0x08000000   /* C3.3.6 */
 443                 || (insn & 0x3bc00000) == 0x39000000   /* C3.3.13 */
 444                 || (insn & 0x3fc00000) == 0x3d800000   /* ... 128bit */
 445                 /* Ingore bits 10, 11 & 21, controlling indexing.  */
 446                 || (insn & 0x3bc00000) == 0x38000000   /* C3.3.8-12 */
 447                 || (insn & 0x3fe00000) == 0x3c800000   /* ... 128bit */
 448                 /* Ignore bits 23 & 24, controlling indexing.  */
 449                 || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
 450
 451     return handle_cpu_signal(pc, (uintptr_t)info->si_addr,
 452                              is_write, &uc->uc_sigmask);
 453 }
 454
 455 #elif defined(__ia64)
 456
 457 #ifndef __ISR_VALID
 458   /* This ought to be in <bits/siginfo.h>... */
 459 # define __ISR_VALID    1
 460 #endif
 461
 462 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
 463 {
 464     siginfo_t *info = pinfo;
 465     struct ucontext *uc = puc;
 466     unsigned long ip;
 467     int is_write = 0;
 468
 469     ip = uc->uc_mcontext.sc_ip;
 470     switch (host_signum) {
 471     case SIGILL:
 472     case SIGFPE:
 473     case SIGSEGV:
 474     case SIGBUS:
 475     case SIGTRAP:
 476         if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
 477             /* ISR.W (write-access) is bit 33:  */
 478             is_write = (info->si_isr >> 33) & 1;
 479         }
 480         break;
 481
 482     default:
 483         break;
 484     }
 485     return handle_cpu_signal(ip, (unsigned long)info->si_addr,
 486                              is_write,
 487                              (sigset_t *)&uc->uc_sigmask);
 488 }
 489
 490 #elif defined(__s390__)
 491
 492 int cpu_signal_handler(int host_signum, void *pinfo,
 493                        void *puc)
 494 {
 495     siginfo_t *info = pinfo;
 496     struct ucontext *uc = puc;
 497     unsigned long pc;
 498     uint16_t *pinsn;
 499     int is_write = 0;
 500
 501     pc = uc->uc_mcontext.psw.addr;
 502
 503     /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
 504        of the normal 2 arguments.  The 3rd argument contains the "int_code"
 505        from the hardware which does in fact contain the is_write value.
 506        The rt signal handler, as far as I can tell, does not give this value
 507        at all.  Not that we could get to it from here even if it were.  */
 508     /* ??? This is not even close to complete, since it ignores all
 509        of the read-modify-write instructions.  */
 510     pinsn = (uint16_t *)pc;
 511     switch (pinsn[0] >> 8) {
 512     case 0x50: /* ST */
 513     case 0x42: /* STC */
 514     case 0x40: /* STH */
 515         is_write = 1;
 516         break;
 517     case 0xc4: /* RIL format insns */
 518         switch (pinsn[0] & 0xf) {
 519         case 0xf: /* STRL */
 520         case 0xb: /* STGRL */
 521         case 0x7: /* STHRL */
 522             is_write = 1;
 523         }
 524         break;
 525     case 0xe3: /* RXY format insns */
 526         switch (pinsn[2] & 0xff) {
 527         case 0x50: /* STY */
 528         case 0x24: /* STG */
 529         case 0x72: /* STCY */
 530         case 0x70: /* STHY */
 531         case 0x8e: /* STPQ */
 532         case 0x3f: /* STRVH */
 533         case 0x3e: /* STRV */
 534         case 0x2f: /* STRVG */
 535             is_write = 1;
 536         }
 537         break;
 538     }
 539     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 540                              is_write, &uc->uc_sigmask);
 541 }
 542
 543 #elif defined(__mips__)
 544
 545 int cpu_signal_handler(int host_signum, void *pinfo,
 546                        void *puc)
 547 {
 548     siginfo_t *info = pinfo;
 549     struct ucontext *uc = puc;
 550     greg_t pc = uc->uc_mcontext.pc;
 551     int is_write;
 552
 553     /* XXX: compute is_write */
 554     is_write = 0;
 555     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 556                              is_write, &uc->uc_sigmask);
 557 }
 558
 559 #else
 560
 561 #error host CPU specific signal handler needed
 562
 563 #endif