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qemu-iotests: Add qemu-img compare test
[qemu/ar7.git] / target-i386 / cpu.c
blobdfcf86e862437a6df1c62cc5ee3eeeef96ae87e9
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
27 #include "topology.h"
28
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32
33 #include "qapi/visitor.h"
34 #include "sysemu/arch_init.h"
35
36 #include "hyperv.h"
37
38 #include "hw/hw.h"
39 #if defined(CONFIG_KVM)
40 #include <linux/kvm_para.h>
41 #endif
42
43 #include "sysemu/sysemu.h"
44 #ifndef CONFIG_USER_ONLY
45 #include "hw/xen.h"
46 #include "hw/sysbus.h"
47 #include "hw/apic_internal.h"
48 #endif
49
50 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
51 uint32_t vendor2, uint32_t vendor3)
52 {
53 int i;
54 for (i = 0; i < 4; i++) {
55 dst[i] = vendor1 >> (8 * i);
56 dst[i + 4] = vendor2 >> (8 * i);
57 dst[i + 8] = vendor3 >> (8 * i);
58 }
59 dst[CPUID_VENDOR_SZ] = '\0';
60 }
61
62 /* feature flags taken from "Intel Processor Identification and the CPUID
63 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
64 * between feature naming conventions, aliases may be added.
65 */
66 static const char *feature_name[] = {
67 "fpu", "vme", "de", "pse",
68 "tsc", "msr", "pae", "mce",
69 "cx8", "apic", NULL, "sep",
70 "mtrr", "pge", "mca", "cmov",
71 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
72 NULL, "ds" /* Intel dts */, "acpi", "mmx",
73 "fxsr", "sse", "sse2", "ss",
74 "ht" /* Intel htt */, "tm", "ia64", "pbe",
75 };
76 static const char *ext_feature_name[] = {
77 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
78 "ds_cpl", "vmx", "smx", "est",
79 "tm2", "ssse3", "cid", NULL,
80 "fma", "cx16", "xtpr", "pdcm",
81 NULL, "pcid", "dca", "sse4.1|sse4_1",
82 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
83 "tsc-deadline", "aes", "xsave", "osxsave",
84 "avx", "f16c", "rdrand", "hypervisor",
85 };
86 /* Feature names that are already defined on feature_name[] but are set on
87 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
88 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
89 * if and only if CPU vendor is AMD.
90 */
91 static const char *ext2_feature_name[] = {
92 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
93 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
94 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
95 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
96 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
97 "nx|xd", NULL, "mmxext", NULL /* mmx */,
98 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
99 NULL, "lm|i64", "3dnowext", "3dnow",
100 };
101 static const char *ext3_feature_name[] = {
102 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
103 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
104 "3dnowprefetch", "osvw", "ibs", "xop",
105 "skinit", "wdt", NULL, "lwp",
106 "fma4", "tce", NULL, "nodeid_msr",
107 NULL, "tbm", "topoext", "perfctr_core",
108 "perfctr_nb", NULL, NULL, NULL,
109 NULL, NULL, NULL, NULL,
110 };
111
112 static const char *ext4_feature_name[] = {
113 NULL, NULL, "xstore", "xstore-en",
114 NULL, NULL, "xcrypt", "xcrypt-en",
115 "ace2", "ace2-en", "phe", "phe-en",
116 "pmm", "pmm-en", NULL, NULL,
117 NULL, NULL, NULL, NULL,
118 NULL, NULL, NULL, NULL,
119 NULL, NULL, NULL, NULL,
120 NULL, NULL, NULL, NULL,
121 };
122
123 static const char *kvm_feature_name[] = {
124 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
125 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
126 NULL, NULL, NULL, NULL,
127 NULL, NULL, NULL, NULL,
128 NULL, NULL, NULL, NULL,
129 NULL, NULL, NULL, NULL,
130 NULL, NULL, NULL, NULL,
131 NULL, NULL, NULL, NULL,
132 };
133
134 static const char *svm_feature_name[] = {
135 "npt", "lbrv", "svm_lock", "nrip_save",
136 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
137 NULL, NULL, "pause_filter", NULL,
138 "pfthreshold", NULL, NULL, NULL,
139 NULL, NULL, NULL, NULL,
140 NULL, NULL, NULL, NULL,
141 NULL, NULL, NULL, NULL,
142 NULL, NULL, NULL, NULL,
143 };
144
145 static const char *cpuid_7_0_ebx_feature_name[] = {
146 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
147 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
148 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
149 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
150 };
151
152 typedef struct FeatureWordInfo {
153 const char **feat_names;
154 uint32_t cpuid_eax; /* Input EAX for CPUID */
155 int cpuid_reg; /* R_* register constant */
156 } FeatureWordInfo;
157
158 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
159 [FEAT_1_EDX] = {
160 .feat_names = feature_name,
161 .cpuid_eax = 1, .cpuid_reg = R_EDX,
162 },
163 [FEAT_1_ECX] = {
164 .feat_names = ext_feature_name,
165 .cpuid_eax = 1, .cpuid_reg = R_ECX,
166 },
167 [FEAT_8000_0001_EDX] = {
168 .feat_names = ext2_feature_name,
169 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
170 },
171 [FEAT_8000_0001_ECX] = {
172 .feat_names = ext3_feature_name,
173 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
174 },
175 [FEAT_C000_0001_EDX] = {
176 .feat_names = ext4_feature_name,
177 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
178 },
179 [FEAT_KVM] = {
180 .feat_names = kvm_feature_name,
181 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
182 },
183 [FEAT_SVM] = {
184 .feat_names = svm_feature_name,
185 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
186 },
187 [FEAT_7_0_EBX] = {
188 .feat_names = cpuid_7_0_ebx_feature_name,
189 .cpuid_eax = 7, .cpuid_reg = R_EBX,
190 },
191 };
192
193 const char *get_register_name_32(unsigned int reg)
194 {
195 static const char *reg_names[CPU_NB_REGS32] = {
196 [R_EAX] = "EAX",
197 [R_ECX] = "ECX",
198 [R_EDX] = "EDX",
199 [R_EBX] = "EBX",
200 [R_ESP] = "ESP",
201 [R_EBP] = "EBP",
202 [R_ESI] = "ESI",
203 [R_EDI] = "EDI",
204 };
205
206 if (reg > CPU_NB_REGS32) {
207 return NULL;
208 }
209 return reg_names[reg];
210 }
211
212 /* collects per-function cpuid data
213 */
214 typedef struct model_features_t {
215 uint32_t *guest_feat;
216 uint32_t *host_feat;
217 FeatureWord feat_word;
218 } model_features_t;
219
220 int check_cpuid = 0;
221 int enforce_cpuid = 0;
222
223 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
224 (1 << KVM_FEATURE_NOP_IO_DELAY) |
225 (1 << KVM_FEATURE_CLOCKSOURCE2) |
226 (1 << KVM_FEATURE_ASYNC_PF) |
227 (1 << KVM_FEATURE_STEAL_TIME) |
228 (1 << KVM_FEATURE_PV_EOI) |
229 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
230
231 void disable_kvm_pv_eoi(void)
232 {
233 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
234 }
235
236 void host_cpuid(uint32_t function, uint32_t count,
237 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
238 {
239 #if defined(CONFIG_KVM)
240 uint32_t vec[4];
241
242 #ifdef __x86_64__
243 asm volatile("cpuid"
244 : "=a"(vec[0]), "=b"(vec[1]),
245 "=c"(vec[2]), "=d"(vec[3])
246 : "0"(function), "c"(count) : "cc");
247 #else
248 asm volatile("pusha \n\t"
249 "cpuid \n\t"
250 "mov %%eax, 0(%2) \n\t"
251 "mov %%ebx, 4(%2) \n\t"
252 "mov %%ecx, 8(%2) \n\t"
253 "mov %%edx, 12(%2) \n\t"
254 "popa"
255 : : "a"(function), "c"(count), "S"(vec)
256 : "memory", "cc");
257 #endif
258
259 if (eax)
260 *eax = vec[0];
261 if (ebx)
262 *ebx = vec[1];
263 if (ecx)
264 *ecx = vec[2];
265 if (edx)
266 *edx = vec[3];
267 #endif
268 }
269
270 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
271
272 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
273 * a substring. ex if !NULL points to the first char after a substring,
274 * otherwise the string is assumed to sized by a terminating nul.
275 * Return lexical ordering of *s1:*s2.
276 */
277 static int sstrcmp(const char *s1, const char *e1, const char *s2,
278 const char *e2)
279 {
280 for (;;) {
281 if (!*s1 || !*s2 || *s1 != *s2)
282 return (*s1 - *s2);
283 ++s1, ++s2;
284 if (s1 == e1 && s2 == e2)
285 return (0);
286 else if (s1 == e1)
287 return (*s2);
288 else if (s2 == e2)
289 return (*s1);
290 }
291 }
292
293 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
294 * '|' delimited (possibly empty) strings in which case search for a match
295 * within the alternatives proceeds left to right. Return 0 for success,
296 * non-zero otherwise.
297 */
298 static int altcmp(const char *s, const char *e, const char *altstr)
299 {
300 const char *p, *q;
301
302 for (q = p = altstr; ; ) {
303 while (*p && *p != '|')
304 ++p;
305 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
306 return (0);
307 if (!*p)
308 return (1);
309 else
310 q = ++p;
311 }
312 }
313
314 /* search featureset for flag *[s..e), if found set corresponding bit in
315 * *pval and return true, otherwise return false
316 */
317 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
318 const char **featureset)
319 {
320 uint32_t mask;
321 const char **ppc;
322 bool found = false;
323
324 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
325 if (*ppc && !altcmp(s, e, *ppc)) {
326 *pval |= mask;
327 found = true;
328 }
329 }
330 return found;
331 }
332
333 static void add_flagname_to_bitmaps(const char *flagname,
334 FeatureWordArray words)
335 {
336 FeatureWord w;
337 for (w = 0; w < FEATURE_WORDS; w++) {
338 FeatureWordInfo *wi = &feature_word_info[w];
339 if (wi->feat_names &&
340 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
341 break;
342 }
343 }
344 if (w == FEATURE_WORDS) {
345 fprintf(stderr, "CPU feature %s not found\n", flagname);
346 }
347 }
348
349 typedef struct x86_def_t {
350 const char *name;
351 uint32_t level;
352 /* vendor is zero-terminated, 12 character ASCII string */
353 char vendor[CPUID_VENDOR_SZ + 1];
354 int family;
355 int model;
356 int stepping;
357 uint32_t features, ext_features, ext2_features, ext3_features;
358 uint32_t kvm_features, svm_features;
359 uint32_t xlevel;
360 char model_id[48];
361 /* Store the results of Centaur's CPUID instructions */
362 uint32_t ext4_features;
363 uint32_t xlevel2;
364 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
365 uint32_t cpuid_7_0_ebx_features;
366 } x86_def_t;
367
368 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
369 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
370 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
371 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
372 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
373 CPUID_PSE36 | CPUID_FXSR)
374 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
375 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
376 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
377 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
378 CPUID_PAE | CPUID_SEP | CPUID_APIC)
379
380 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
381 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
382 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
383 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
384 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
385 /* partly implemented:
386 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
387 CPUID_PSE36 (needed for Solaris) */
388 /* missing:
389 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
390 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
391 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
392 CPUID_EXT_HYPERVISOR)
393 /* missing:
394 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
395 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
396 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
397 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
398 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
399 /* missing:
400 CPUID_EXT2_PDPE1GB */
401 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
402 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
403 #define TCG_SVM_FEATURES 0
404 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
405
406 /* built-in CPU model definitions
407 */
408 static x86_def_t builtin_x86_defs[] = {
409 {
410 .name = "qemu64",
411 .level = 4,
412 .vendor = CPUID_VENDOR_AMD,
413 .family = 6,
414 .model = 2,
415 .stepping = 3,
416 .features = PPRO_FEATURES |
417 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
418 CPUID_PSE36,
419 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
420 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
421 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
422 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
423 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
424 .xlevel = 0x8000000A,
425 },
426 {
427 .name = "phenom",
428 .level = 5,
429 .vendor = CPUID_VENDOR_AMD,
430 .family = 16,
431 .model = 2,
432 .stepping = 3,
433 .features = PPRO_FEATURES |
434 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
435 CPUID_PSE36 | CPUID_VME | CPUID_HT,
436 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
437 CPUID_EXT_POPCNT,
438 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
439 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
440 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
441 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
442 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
443 CPUID_EXT3_CR8LEG,
444 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
445 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
446 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
447 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
448 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
449 .xlevel = 0x8000001A,
450 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
451 },
452 {
453 .name = "core2duo",
454 .level = 10,
455 .vendor = CPUID_VENDOR_INTEL,
456 .family = 6,
457 .model = 15,
458 .stepping = 11,
459 .features = PPRO_FEATURES |
460 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
461 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
462 CPUID_HT | CPUID_TM | CPUID_PBE,
463 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
464 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
465 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
466 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
467 .ext3_features = CPUID_EXT3_LAHF_LM,
468 .xlevel = 0x80000008,
469 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
470 },
471 {
472 .name = "kvm64",
473 .level = 5,
474 .vendor = CPUID_VENDOR_INTEL,
475 .family = 15,
476 .model = 6,
477 .stepping = 1,
478 /* Missing: CPUID_VME, CPUID_HT */
479 .features = PPRO_FEATURES |
480 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
481 CPUID_PSE36,
482 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
483 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
484 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
485 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
486 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
487 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
488 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
489 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
490 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
491 .ext3_features = 0,
492 .xlevel = 0x80000008,
493 .model_id = "Common KVM processor"
494 },
495 {
496 .name = "qemu32",
497 .level = 4,
498 .vendor = CPUID_VENDOR_INTEL,
499 .family = 6,
500 .model = 3,
501 .stepping = 3,
502 .features = PPRO_FEATURES,
503 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
504 .xlevel = 0x80000004,
505 },
506 {
507 .name = "kvm32",
508 .level = 5,
509 .vendor = CPUID_VENDOR_INTEL,
510 .family = 15,
511 .model = 6,
512 .stepping = 1,
513 .features = PPRO_FEATURES |
514 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
515 .ext_features = CPUID_EXT_SSE3,
516 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
517 .ext3_features = 0,
518 .xlevel = 0x80000008,
519 .model_id = "Common 32-bit KVM processor"
520 },
521 {
522 .name = "coreduo",
523 .level = 10,
524 .vendor = CPUID_VENDOR_INTEL,
525 .family = 6,
526 .model = 14,
527 .stepping = 8,
528 .features = PPRO_FEATURES | CPUID_VME |
529 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
530 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
531 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
532 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
533 .ext2_features = CPUID_EXT2_NX,
534 .xlevel = 0x80000008,
535 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
536 },
537 {
538 .name = "486",
539 .level = 1,
540 .vendor = CPUID_VENDOR_INTEL,
541 .family = 4,
542 .model = 0,
543 .stepping = 0,
544 .features = I486_FEATURES,
545 .xlevel = 0,
546 },
547 {
548 .name = "pentium",
549 .level = 1,
550 .vendor = CPUID_VENDOR_INTEL,
551 .family = 5,
552 .model = 4,
553 .stepping = 3,
554 .features = PENTIUM_FEATURES,
555 .xlevel = 0,
556 },
557 {
558 .name = "pentium2",
559 .level = 2,
560 .vendor = CPUID_VENDOR_INTEL,
561 .family = 6,
562 .model = 5,
563 .stepping = 2,
564 .features = PENTIUM2_FEATURES,
565 .xlevel = 0,
566 },
567 {
568 .name = "pentium3",
569 .level = 2,
570 .vendor = CPUID_VENDOR_INTEL,
571 .family = 6,
572 .model = 7,
573 .stepping = 3,
574 .features = PENTIUM3_FEATURES,
575 .xlevel = 0,
576 },
577 {
578 .name = "athlon",
579 .level = 2,
580 .vendor = CPUID_VENDOR_AMD,
581 .family = 6,
582 .model = 2,
583 .stepping = 3,
584 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
585 CPUID_MCA,
586 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
587 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
588 .xlevel = 0x80000008,
589 },
590 {
591 .name = "n270",
592 /* original is on level 10 */
593 .level = 5,
594 .vendor = CPUID_VENDOR_INTEL,
595 .family = 6,
596 .model = 28,
597 .stepping = 2,
598 .features = PPRO_FEATURES |
599 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
600 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
601 /* Some CPUs got no CPUID_SEP */
602 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
603 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
604 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
605 CPUID_EXT2_NX,
606 .ext3_features = CPUID_EXT3_LAHF_LM,
607 .xlevel = 0x8000000A,
608 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
609 },
610 {
611 .name = "Conroe",
612 .level = 2,
613 .vendor = CPUID_VENDOR_INTEL,
614 .family = 6,
615 .model = 2,
616 .stepping = 3,
617 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
618 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
619 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
620 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
621 CPUID_DE | CPUID_FP87,
622 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
623 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
624 .ext3_features = CPUID_EXT3_LAHF_LM,
625 .xlevel = 0x8000000A,
626 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
627 },
628 {
629 .name = "Penryn",
630 .level = 2,
631 .vendor = CPUID_VENDOR_INTEL,
632 .family = 6,
633 .model = 2,
634 .stepping = 3,
635 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
636 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
637 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
638 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
639 CPUID_DE | CPUID_FP87,
640 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
641 CPUID_EXT_SSE3,
642 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
643 .ext3_features = CPUID_EXT3_LAHF_LM,
644 .xlevel = 0x8000000A,
645 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
646 },
647 {
648 .name = "Nehalem",
649 .level = 2,
650 .vendor = CPUID_VENDOR_INTEL,
651 .family = 6,
652 .model = 2,
653 .stepping = 3,
654 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
655 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
656 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
657 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
658 CPUID_DE | CPUID_FP87,
659 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
660 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
661 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
662 .ext3_features = CPUID_EXT3_LAHF_LM,
663 .xlevel = 0x8000000A,
664 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
665 },
666 {
667 .name = "Westmere",
668 .level = 11,
669 .vendor = CPUID_VENDOR_INTEL,
670 .family = 6,
671 .model = 44,
672 .stepping = 1,
673 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
674 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
675 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
676 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
677 CPUID_DE | CPUID_FP87,
678 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
679 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
680 CPUID_EXT_SSE3,
681 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
682 .ext3_features = CPUID_EXT3_LAHF_LM,
683 .xlevel = 0x8000000A,
684 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
685 },
686 {
687 .name = "SandyBridge",
688 .level = 0xd,
689 .vendor = CPUID_VENDOR_INTEL,
690 .family = 6,
691 .model = 42,
692 .stepping = 1,
693 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
694 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
695 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
696 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
697 CPUID_DE | CPUID_FP87,
698 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
699 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
700 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
701 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
702 CPUID_EXT_SSE3,
703 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
704 CPUID_EXT2_SYSCALL,
705 .ext3_features = CPUID_EXT3_LAHF_LM,
706 .xlevel = 0x8000000A,
707 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
708 },
709 {
710 .name = "Haswell",
711 .level = 0xd,
712 .vendor = CPUID_VENDOR_INTEL,
713 .family = 6,
714 .model = 60,
715 .stepping = 1,
716 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
717 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
718 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
719 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
720 CPUID_DE | CPUID_FP87,
721 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
722 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
723 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
724 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
725 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
726 CPUID_EXT_PCID,
727 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
728 CPUID_EXT2_SYSCALL,
729 .ext3_features = CPUID_EXT3_LAHF_LM,
730 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
731 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
732 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
733 CPUID_7_0_EBX_RTM,
734 .xlevel = 0x8000000A,
735 .model_id = "Intel Core Processor (Haswell)",
736 },
737 {
738 .name = "Opteron_G1",
739 .level = 5,
740 .vendor = CPUID_VENDOR_AMD,
741 .family = 15,
742 .model = 6,
743 .stepping = 1,
744 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
745 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
746 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
747 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
748 CPUID_DE | CPUID_FP87,
749 .ext_features = CPUID_EXT_SSE3,
750 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
751 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
752 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
753 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
754 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
755 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
756 .xlevel = 0x80000008,
757 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
758 },
759 {
760 .name = "Opteron_G2",
761 .level = 5,
762 .vendor = CPUID_VENDOR_AMD,
763 .family = 15,
764 .model = 6,
765 .stepping = 1,
766 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
767 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
768 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
769 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
770 CPUID_DE | CPUID_FP87,
771 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
772 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
773 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
774 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
775 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
776 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
777 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
778 CPUID_EXT2_DE | CPUID_EXT2_FPU,
779 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
780 .xlevel = 0x80000008,
781 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
782 },
783 {
784 .name = "Opteron_G3",
785 .level = 5,
786 .vendor = CPUID_VENDOR_AMD,
787 .family = 15,
788 .model = 6,
789 .stepping = 1,
790 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
791 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
792 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
793 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
794 CPUID_DE | CPUID_FP87,
795 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
796 CPUID_EXT_SSE3,
797 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
798 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
799 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
800 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
801 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
802 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
803 CPUID_EXT2_DE | CPUID_EXT2_FPU,
804 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
805 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
806 .xlevel = 0x80000008,
807 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
808 },
809 {
810 .name = "Opteron_G4",
811 .level = 0xd,
812 .vendor = CPUID_VENDOR_AMD,
813 .family = 21,
814 .model = 1,
815 .stepping = 2,
816 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
817 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
818 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
819 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
820 CPUID_DE | CPUID_FP87,
821 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
822 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
823 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
824 CPUID_EXT_SSE3,
825 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
826 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
827 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
828 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
829 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
830 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
831 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
832 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
833 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
834 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
835 CPUID_EXT3_LAHF_LM,
836 .xlevel = 0x8000001A,
837 .model_id = "AMD Opteron 62xx class CPU",
838 },
839 {
840 .name = "Opteron_G5",
841 .level = 0xd,
842 .vendor = CPUID_VENDOR_AMD,
843 .family = 21,
844 .model = 2,
845 .stepping = 0,
846 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
847 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
848 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
849 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
850 CPUID_DE | CPUID_FP87,
851 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
852 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
853 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
854 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
855 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
856 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
857 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
858 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
859 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
860 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
861 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
862 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
863 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
864 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
865 CPUID_EXT3_LAHF_LM,
866 .xlevel = 0x8000001A,
867 .model_id = "AMD Opteron 63xx class CPU",
868 },
869 };
870
871 #ifdef CONFIG_KVM
872 static int cpu_x86_fill_model_id(char *str)
873 {
874 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
875 int i;
876
877 for (i = 0; i < 3; i++) {
878 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
879 memcpy(str + i * 16 + 0, &eax, 4);
880 memcpy(str + i * 16 + 4, &ebx, 4);
881 memcpy(str + i * 16 + 8, &ecx, 4);
882 memcpy(str + i * 16 + 12, &edx, 4);
883 }
884 return 0;
885 }
886 #endif
887
888 /* Fill a x86_def_t struct with information about the host CPU, and
889 * the CPU features supported by the host hardware + host kernel
890 *
891 * This function may be called only if KVM is enabled.
892 */
893 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
894 {
895 #ifdef CONFIG_KVM
896 KVMState *s = kvm_state;
897 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
898
899 assert(kvm_enabled());
900
901 x86_cpu_def->name = "host";
902 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
903 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
904
905 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
906 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
907 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
908 x86_cpu_def->stepping = eax & 0x0F;
909
910 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
911 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
912 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
913
914 if (x86_cpu_def->level >= 7) {
915 x86_cpu_def->cpuid_7_0_ebx_features =
916 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
917 } else {
918 x86_cpu_def->cpuid_7_0_ebx_features = 0;
919 }
920
921 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
922 x86_cpu_def->ext2_features =
923 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
924 x86_cpu_def->ext3_features =
925 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
926
927 cpu_x86_fill_model_id(x86_cpu_def->model_id);
928
929 /* Call Centaur's CPUID instruction. */
930 if (!strcmp(x86_cpu_def->vendor, CPUID_VENDOR_VIA)) {
931 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
932 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
933 if (eax >= 0xC0000001) {
934 /* Support VIA max extended level */
935 x86_cpu_def->xlevel2 = eax;
936 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
937 x86_cpu_def->ext4_features =
938 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
939 }
940 }
941
942 /* Other KVM-specific feature fields: */
943 x86_cpu_def->svm_features =
944 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
945 x86_cpu_def->kvm_features =
946 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
947
948 #endif /* CONFIG_KVM */
949 }
950
951 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
952 {
953 int i;
954
955 for (i = 0; i < 32; ++i)
956 if (1 << i & mask) {
957 const char *reg = get_register_name_32(f->cpuid_reg);
958 assert(reg);
959 fprintf(stderr, "warning: host doesn't support requested feature: "
960 "CPUID.%02XH:%s%s%s [bit %d]\n",
961 f->cpuid_eax, reg,
962 f->feat_names[i] ? "." : "",
963 f->feat_names[i] ? f->feat_names[i] : "", i);
964 break;
965 }
966 return 0;
967 }
968
969 /* Check if all requested cpu flags are making their way to the guest
970 *
971 * Returns 0 if all flags are supported by the host, non-zero otherwise.
972 *
973 * This function may be called only if KVM is enabled.
974 */
975 static int kvm_check_features_against_host(X86CPU *cpu)
976 {
977 CPUX86State *env = &cpu->env;
978 x86_def_t host_def;
979 uint32_t mask;
980 int rv, i;
981 struct model_features_t ft[] = {
982 {&env->cpuid_features, &host_def.features,
983 FEAT_1_EDX },
984 {&env->cpuid_ext_features, &host_def.ext_features,
985 FEAT_1_ECX },
986 {&env->cpuid_ext2_features, &host_def.ext2_features,
987 FEAT_8000_0001_EDX },
988 {&env->cpuid_ext3_features, &host_def.ext3_features,
989 FEAT_8000_0001_ECX },
990 {&env->cpuid_ext4_features, &host_def.ext4_features,
991 FEAT_C000_0001_EDX },
992 {&env->cpuid_7_0_ebx_features, &host_def.cpuid_7_0_ebx_features,
993 FEAT_7_0_EBX },
994 {&env->cpuid_svm_features, &host_def.svm_features,
995 FEAT_SVM },
996 {&env->cpuid_kvm_features, &host_def.kvm_features,
997 FEAT_KVM },
998 };
999
1000 assert(kvm_enabled());
1001
1002 kvm_cpu_fill_host(&host_def);
1003 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1004 FeatureWord w = ft[i].feat_word;
1005 FeatureWordInfo *wi = &feature_word_info[w];
1006 for (mask = 1; mask; mask <<= 1) {
1007 if (*ft[i].guest_feat & mask &&
1008 !(*ft[i].host_feat & mask)) {
1009 unavailable_host_feature(wi, mask);
1010 rv = 1;
1011 }
1012 }
1013 }
1014 return rv;
1015 }
1016
1017 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1018 const char *name, Error **errp)
1019 {
1020 X86CPU *cpu = X86_CPU(obj);
1021 CPUX86State *env = &cpu->env;
1022 int64_t value;
1023
1024 value = (env->cpuid_version >> 8) & 0xf;
1025 if (value == 0xf) {
1026 value += (env->cpuid_version >> 20) & 0xff;
1027 }
1028 visit_type_int(v, &value, name, errp);
1029 }
1030
1031 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1032 const char *name, Error **errp)
1033 {
1034 X86CPU *cpu = X86_CPU(obj);
1035 CPUX86State *env = &cpu->env;
1036 const int64_t min = 0;
1037 const int64_t max = 0xff + 0xf;
1038 int64_t value;
1039
1040 visit_type_int(v, &value, name, errp);
1041 if (error_is_set(errp)) {
1042 return;
1043 }
1044 if (value < min || value > max) {
1045 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1046 name ? name : "null", value, min, max);
1047 return;
1048 }
1049
1050 env->cpuid_version &= ~0xff00f00;
1051 if (value > 0x0f) {
1052 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1053 } else {
1054 env->cpuid_version |= value << 8;
1055 }
1056 }
1057
1058 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1059 const char *name, Error **errp)
1060 {
1061 X86CPU *cpu = X86_CPU(obj);
1062 CPUX86State *env = &cpu->env;
1063 int64_t value;
1064
1065 value = (env->cpuid_version >> 4) & 0xf;
1066 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1067 visit_type_int(v, &value, name, errp);
1068 }
1069
1070 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1071 const char *name, Error **errp)
1072 {
1073 X86CPU *cpu = X86_CPU(obj);
1074 CPUX86State *env = &cpu->env;
1075 const int64_t min = 0;
1076 const int64_t max = 0xff;
1077 int64_t value;
1078
1079 visit_type_int(v, &value, name, errp);
1080 if (error_is_set(errp)) {
1081 return;
1082 }
1083 if (value < min || value > max) {
1084 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1085 name ? name : "null", value, min, max);
1086 return;
1087 }
1088
1089 env->cpuid_version &= ~0xf00f0;
1090 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1091 }
1092
1093 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1094 void *opaque, const char *name,
1095 Error **errp)
1096 {
1097 X86CPU *cpu = X86_CPU(obj);
1098 CPUX86State *env = &cpu->env;
1099 int64_t value;
1100
1101 value = env->cpuid_version & 0xf;
1102 visit_type_int(v, &value, name, errp);
1103 }
1104
1105 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1106 void *opaque, const char *name,
1107 Error **errp)
1108 {
1109 X86CPU *cpu = X86_CPU(obj);
1110 CPUX86State *env = &cpu->env;
1111 const int64_t min = 0;
1112 const int64_t max = 0xf;
1113 int64_t value;
1114
1115 visit_type_int(v, &value, name, errp);
1116 if (error_is_set(errp)) {
1117 return;
1118 }
1119 if (value < min || value > max) {
1120 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1121 name ? name : "null", value, min, max);
1122 return;
1123 }
1124
1125 env->cpuid_version &= ~0xf;
1126 env->cpuid_version |= value & 0xf;
1127 }
1128
1129 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1130 const char *name, Error **errp)
1131 {
1132 X86CPU *cpu = X86_CPU(obj);
1133
1134 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1135 }
1136
1137 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1138 const char *name, Error **errp)
1139 {
1140 X86CPU *cpu = X86_CPU(obj);
1141
1142 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1143 }
1144
1145 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1146 const char *name, Error **errp)
1147 {
1148 X86CPU *cpu = X86_CPU(obj);
1149
1150 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1151 }
1152
1153 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1154 const char *name, Error **errp)
1155 {
1156 X86CPU *cpu = X86_CPU(obj);
1157
1158 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1159 }
1160
1161 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1162 {
1163 X86CPU *cpu = X86_CPU(obj);
1164 CPUX86State *env = &cpu->env;
1165 char *value;
1166
1167 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1168 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1169 env->cpuid_vendor3);
1170 return value;
1171 }
1172
1173 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1174 Error **errp)
1175 {
1176 X86CPU *cpu = X86_CPU(obj);
1177 CPUX86State *env = &cpu->env;
1178 int i;
1179
1180 if (strlen(value) != CPUID_VENDOR_SZ) {
1181 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1182 "vendor", value);
1183 return;
1184 }
1185
1186 env->cpuid_vendor1 = 0;
1187 env->cpuid_vendor2 = 0;
1188 env->cpuid_vendor3 = 0;
1189 for (i = 0; i < 4; i++) {
1190 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1191 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1192 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1193 }
1194 }
1195
1196 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1197 {
1198 X86CPU *cpu = X86_CPU(obj);
1199 CPUX86State *env = &cpu->env;
1200 char *value;
1201 int i;
1202
1203 value = g_malloc(48 + 1);
1204 for (i = 0; i < 48; i++) {
1205 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1206 }
1207 value[48] = '\0';
1208 return value;
1209 }
1210
1211 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1212 Error **errp)
1213 {
1214 X86CPU *cpu = X86_CPU(obj);
1215 CPUX86State *env = &cpu->env;
1216 int c, len, i;
1217
1218 if (model_id == NULL) {
1219 model_id = "";
1220 }
1221 len = strlen(model_id);
1222 memset(env->cpuid_model, 0, 48);
1223 for (i = 0; i < 48; i++) {
1224 if (i >= len) {
1225 c = '\0';
1226 } else {
1227 c = (uint8_t)model_id[i];
1228 }
1229 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1230 }
1231 }
1232
1233 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1234 const char *name, Error **errp)
1235 {
1236 X86CPU *cpu = X86_CPU(obj);
1237 int64_t value;
1238
1239 value = cpu->env.tsc_khz * 1000;
1240 visit_type_int(v, &value, name, errp);
1241 }
1242
1243 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1244 const char *name, Error **errp)
1245 {
1246 X86CPU *cpu = X86_CPU(obj);
1247 const int64_t min = 0;
1248 const int64_t max = INT64_MAX;
1249 int64_t value;
1250
1251 visit_type_int(v, &value, name, errp);
1252 if (error_is_set(errp)) {
1253 return;
1254 }
1255 if (value < min || value > max) {
1256 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1257 name ? name : "null", value, min, max);
1258 return;
1259 }
1260
1261 cpu->env.tsc_khz = value / 1000;
1262 }
1263
1264 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
1265 {
1266 x86_def_t *def;
1267 int i;
1268
1269 if (name == NULL) {
1270 return -1;
1271 }
1272 if (kvm_enabled() && strcmp(name, "host") == 0) {
1273 kvm_cpu_fill_host(x86_cpu_def);
1274 return 0;
1275 }
1276
1277 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1278 def = &builtin_x86_defs[i];
1279 if (strcmp(name, def->name) == 0) {
1280 memcpy(x86_cpu_def, def, sizeof(*def));
1281 /* sysenter isn't supported in compatibility mode on AMD,
1282 * syscall isn't supported in compatibility mode on Intel.
1283 * Normally we advertise the actual CPU vendor, but you can
1284 * override this using the 'vendor' property if you want to use
1285 * KVM's sysenter/syscall emulation in compatibility mode and
1286 * when doing cross vendor migration
1287 */
1288 if (kvm_enabled()) {
1289 uint32_t ebx = 0, ecx = 0, edx = 0;
1290 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1291 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1292 }
1293 return 0;
1294 }
1295 }
1296
1297 return -1;
1298 }
1299
1300 /* Parse "+feature,-feature,feature=foo" CPU feature string
1301 */
1302 static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
1303 {
1304 char *featurestr; /* Single 'key=value" string being parsed */
1305 /* Features to be added */
1306 FeatureWordArray plus_features = { 0 };
1307 /* Features to be removed */
1308 FeatureWordArray minus_features = { 0 };
1309 uint32_t numvalue;
1310 CPUX86State *env = &cpu->env;
1311
1312 featurestr = features ? strtok(features, ",") : NULL;
1313
1314 while (featurestr) {
1315 char *val;
1316 if (featurestr[0] == '+') {
1317 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1318 } else if (featurestr[0] == '-') {
1319 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1320 } else if ((val = strchr(featurestr, '='))) {
1321 *val = 0; val++;
1322 if (!strcmp(featurestr, "family")) {
1323 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1324 } else if (!strcmp(featurestr, "model")) {
1325 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1326 } else if (!strcmp(featurestr, "stepping")) {
1327 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1328 } else if (!strcmp(featurestr, "level")) {
1329 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1330 } else if (!strcmp(featurestr, "xlevel")) {
1331 char *err;
1332 char num[32];
1333
1334 numvalue = strtoul(val, &err, 0);
1335 if (!*val || *err) {
1336 error_setg(errp, "bad numerical value %s", val);
1337 goto out;
1338 }
1339 if (numvalue < 0x80000000) {
1340 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1341 ", fixup will be removed in future versions\n");
1342 numvalue += 0x80000000;
1343 }
1344 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1345 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1346 } else if (!strcmp(featurestr, "vendor")) {
1347 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1348 } else if (!strcmp(featurestr, "model_id")) {
1349 object_property_parse(OBJECT(cpu), val, "model-id", errp);
1350 } else if (!strcmp(featurestr, "tsc_freq")) {
1351 int64_t tsc_freq;
1352 char *err;
1353 char num[32];
1354
1355 tsc_freq = strtosz_suffix_unit(val, &err,
1356 STRTOSZ_DEFSUFFIX_B, 1000);
1357 if (tsc_freq < 0 || *err) {
1358 error_setg(errp, "bad numerical value %s", val);
1359 goto out;
1360 }
1361 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1362 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
1363 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1364 char *err;
1365 numvalue = strtoul(val, &err, 0);
1366 if (!*val || *err) {
1367 error_setg(errp, "bad numerical value %s", val);
1368 goto out;
1369 }
1370 hyperv_set_spinlock_retries(numvalue);
1371 } else {
1372 error_setg(errp, "unrecognized feature %s", featurestr);
1373 goto out;
1374 }
1375 } else if (!strcmp(featurestr, "check")) {
1376 check_cpuid = 1;
1377 } else if (!strcmp(featurestr, "enforce")) {
1378 check_cpuid = enforce_cpuid = 1;
1379 } else if (!strcmp(featurestr, "hv_relaxed")) {
1380 hyperv_enable_relaxed_timing(true);
1381 } else if (!strcmp(featurestr, "hv_vapic")) {
1382 hyperv_enable_vapic_recommended(true);
1383 } else {
1384 error_setg(errp, "feature string `%s' not in format (+feature|"
1385 "-feature|feature=xyz)", featurestr);
1386 goto out;
1387 }
1388 if (error_is_set(errp)) {
1389 goto out;
1390 }
1391 featurestr = strtok(NULL, ",");
1392 }
1393 env->cpuid_features |= plus_features[FEAT_1_EDX];
1394 env->cpuid_ext_features |= plus_features[FEAT_1_ECX];
1395 env->cpuid_ext2_features |= plus_features[FEAT_8000_0001_EDX];
1396 env->cpuid_ext3_features |= plus_features[FEAT_8000_0001_ECX];
1397 env->cpuid_ext4_features |= plus_features[FEAT_C000_0001_EDX];
1398 env->cpuid_kvm_features |= plus_features[FEAT_KVM];
1399 env->cpuid_svm_features |= plus_features[FEAT_SVM];
1400 env->cpuid_7_0_ebx_features |= plus_features[FEAT_7_0_EBX];
1401 env->cpuid_features &= ~minus_features[FEAT_1_EDX];
1402 env->cpuid_ext_features &= ~minus_features[FEAT_1_ECX];
1403 env->cpuid_ext2_features &= ~minus_features[FEAT_8000_0001_EDX];
1404 env->cpuid_ext3_features &= ~minus_features[FEAT_8000_0001_ECX];
1405 env->cpuid_ext4_features &= ~minus_features[FEAT_C000_0001_EDX];
1406 env->cpuid_kvm_features &= ~minus_features[FEAT_KVM];
1407 env->cpuid_svm_features &= ~minus_features[FEAT_SVM];
1408 env->cpuid_7_0_ebx_features &= ~minus_features[FEAT_7_0_EBX];
1409
1410 out:
1411 return;
1412 }
1413
1414 /* generate a composite string into buf of all cpuid names in featureset
1415 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1416 * if flags, suppress names undefined in featureset.
1417 */
1418 static void listflags(char *buf, int bufsize, uint32_t fbits,
1419 const char **featureset, uint32_t flags)
1420 {
1421 const char **p = &featureset[31];
1422 char *q, *b, bit;
1423 int nc;
1424
1425 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1426 *buf = '\0';
1427 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1428 if (fbits & 1 << bit && (*p || !flags)) {
1429 if (*p)
1430 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1431 else
1432 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1433 if (bufsize <= nc) {
1434 if (b) {
1435 memcpy(b, "...", sizeof("..."));
1436 }
1437 return;
1438 }
1439 q += nc;
1440 bufsize -= nc;
1441 }
1442 }
1443
1444 /* generate CPU information. */
1445 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1446 {
1447 x86_def_t *def;
1448 char buf[256];
1449 int i;
1450
1451 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1452 def = &builtin_x86_defs[i];
1453 snprintf(buf, sizeof(buf), "%s", def->name);
1454 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1455 }
1456 if (kvm_enabled()) {
1457 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1458 }
1459 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1460 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1461 (*cpu_fprintf)(f, " %s\n", buf);
1462 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1463 (*cpu_fprintf)(f, " %s\n", buf);
1464 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1465 (*cpu_fprintf)(f, " %s\n", buf);
1466 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1467 (*cpu_fprintf)(f, " %s\n", buf);
1468 }
1469
1470 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1471 {
1472 CpuDefinitionInfoList *cpu_list = NULL;
1473 x86_def_t *def;
1474 int i;
1475
1476 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1477 CpuDefinitionInfoList *entry;
1478 CpuDefinitionInfo *info;
1479
1480 def = &builtin_x86_defs[i];
1481 info = g_malloc0(sizeof(*info));
1482 info->name = g_strdup(def->name);
1483
1484 entry = g_malloc0(sizeof(*entry));
1485 entry->value = info;
1486 entry->next = cpu_list;
1487 cpu_list = entry;
1488 }
1489
1490 return cpu_list;
1491 }
1492
1493 #ifdef CONFIG_KVM
1494 static void filter_features_for_kvm(X86CPU *cpu)
1495 {
1496 CPUX86State *env = &cpu->env;
1497 KVMState *s = kvm_state;
1498
1499 env->cpuid_features &=
1500 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1501 env->cpuid_ext_features &=
1502 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1503 env->cpuid_ext2_features &=
1504 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1505 env->cpuid_ext3_features &=
1506 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1507 env->cpuid_svm_features &=
1508 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1509 env->cpuid_7_0_ebx_features &=
1510 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1511 env->cpuid_kvm_features &=
1512 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1513 env->cpuid_ext4_features &=
1514 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1515
1516 }
1517 #endif
1518
1519 static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp)
1520 {
1521 CPUX86State *env = &cpu->env;
1522 x86_def_t def1, *def = &def1;
1523
1524 memset(def, 0, sizeof(*def));
1525
1526 if (cpu_x86_find_by_name(def, name) < 0) {
1527 error_setg(errp, "Unable to find CPU definition: %s", name);
1528 return;
1529 }
1530
1531 if (kvm_enabled()) {
1532 def->kvm_features |= kvm_default_features;
1533 }
1534 def->ext_features |= CPUID_EXT_HYPERVISOR;
1535
1536 object_property_set_str(OBJECT(cpu), def->vendor, "vendor", errp);
1537 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1538 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1539 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1540 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1541 env->cpuid_features = def->features;
1542 env->cpuid_ext_features = def->ext_features;
1543 env->cpuid_ext2_features = def->ext2_features;
1544 env->cpuid_ext3_features = def->ext3_features;
1545 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1546 env->cpuid_kvm_features = def->kvm_features;
1547 env->cpuid_svm_features = def->svm_features;
1548 env->cpuid_ext4_features = def->ext4_features;
1549 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1550 env->cpuid_xlevel2 = def->xlevel2;
1551
1552 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1553 }
1554
1555 X86CPU *cpu_x86_init(const char *cpu_model)
1556 {
1557 X86CPU *cpu = NULL;
1558 CPUX86State *env;
1559 gchar **model_pieces;
1560 char *name, *features;
1561 Error *error = NULL;
1562
1563 model_pieces = g_strsplit(cpu_model, ",", 2);
1564 if (!model_pieces[0]) {
1565 error_setg(&error, "Invalid/empty CPU model name");
1566 goto out;
1567 }
1568 name = model_pieces[0];
1569 features = model_pieces[1];
1570
1571 cpu = X86_CPU(object_new(TYPE_X86_CPU));
1572 env = &cpu->env;
1573 env->cpu_model_str = cpu_model;
1574
1575 cpu_x86_register(cpu, name, &error);
1576 if (error) {
1577 goto out;
1578 }
1579
1580 cpu_x86_parse_featurestr(cpu, features, &error);
1581 if (error) {
1582 goto out;
1583 }
1584
1585 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1586 if (error) {
1587 goto out;
1588 }
1589
1590 out:
1591 g_strfreev(model_pieces);
1592 if (error) {
1593 fprintf(stderr, "%s\n", error_get_pretty(error));
1594 error_free(error);
1595 if (cpu != NULL) {
1596 object_unref(OBJECT(cpu));
1597 cpu = NULL;
1598 }
1599 }
1600 return cpu;
1601 }
1602
1603 #if !defined(CONFIG_USER_ONLY)
1604
1605 void cpu_clear_apic_feature(CPUX86State *env)
1606 {
1607 env->cpuid_features &= ~CPUID_APIC;
1608 }
1609
1610 #endif /* !CONFIG_USER_ONLY */
1611
1612 /* Initialize list of CPU models, filling some non-static fields if necessary
1613 */
1614 void x86_cpudef_setup(void)
1615 {
1616 int i, j;
1617 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1618
1619 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1620 x86_def_t *def = &builtin_x86_defs[i];
1621
1622 /* Look for specific "cpudef" models that */
1623 /* have the QEMU version in .model_id */
1624 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1625 if (strcmp(model_with_versions[j], def->name) == 0) {
1626 pstrcpy(def->model_id, sizeof(def->model_id),
1627 "QEMU Virtual CPU version ");
1628 pstrcat(def->model_id, sizeof(def->model_id),
1629 qemu_get_version());
1630 break;
1631 }
1632 }
1633 }
1634 }
1635
1636 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1637 uint32_t *ecx, uint32_t *edx)
1638 {
1639 *ebx = env->cpuid_vendor1;
1640 *edx = env->cpuid_vendor2;
1641 *ecx = env->cpuid_vendor3;
1642 }
1643
1644 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1645 uint32_t *eax, uint32_t *ebx,
1646 uint32_t *ecx, uint32_t *edx)
1647 {
1648 X86CPU *cpu = x86_env_get_cpu(env);
1649 CPUState *cs = CPU(cpu);
1650
1651 /* test if maximum index reached */
1652 if (index & 0x80000000) {
1653 if (index > env->cpuid_xlevel) {
1654 if (env->cpuid_xlevel2 > 0) {
1655 /* Handle the Centaur's CPUID instruction. */
1656 if (index > env->cpuid_xlevel2) {
1657 index = env->cpuid_xlevel2;
1658 } else if (index < 0xC0000000) {
1659 index = env->cpuid_xlevel;
1660 }
1661 } else {
1662 /* Intel documentation states that invalid EAX input will
1663 * return the same information as EAX=cpuid_level
1664 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1665 */
1666 index = env->cpuid_level;
1667 }
1668 }
1669 } else {
1670 if (index > env->cpuid_level)
1671 index = env->cpuid_level;
1672 }
1673
1674 switch(index) {
1675 case 0:
1676 *eax = env->cpuid_level;
1677 get_cpuid_vendor(env, ebx, ecx, edx);
1678 break;
1679 case 1:
1680 *eax = env->cpuid_version;
1681 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1682 *ecx = env->cpuid_ext_features;
1683 *edx = env->cpuid_features;
1684 if (cs->nr_cores * cs->nr_threads > 1) {
1685 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
1686 *edx |= 1 << 28; /* HTT bit */
1687 }
1688 break;
1689 case 2:
1690 /* cache info: needed for Pentium Pro compatibility */
1691 *eax = 1;
1692 *ebx = 0;
1693 *ecx = 0;
1694 *edx = 0x2c307d;
1695 break;
1696 case 4:
1697 /* cache info: needed for Core compatibility */
1698 if (cs->nr_cores > 1) {
1699 *eax = (cs->nr_cores - 1) << 26;
1700 } else {
1701 *eax = 0;
1702 }
1703 switch (count) {
1704 case 0: /* L1 dcache info */
1705 *eax |= 0x0000121;
1706 *ebx = 0x1c0003f;
1707 *ecx = 0x000003f;
1708 *edx = 0x0000001;
1709 break;
1710 case 1: /* L1 icache info */
1711 *eax |= 0x0000122;
1712 *ebx = 0x1c0003f;
1713 *ecx = 0x000003f;
1714 *edx = 0x0000001;
1715 break;
1716 case 2: /* L2 cache info */
1717 *eax |= 0x0000143;
1718 if (cs->nr_threads > 1) {
1719 *eax |= (cs->nr_threads - 1) << 14;
1720 }
1721 *ebx = 0x3c0003f;
1722 *ecx = 0x0000fff;
1723 *edx = 0x0000001;
1724 break;
1725 default: /* end of info */
1726 *eax = 0;
1727 *ebx = 0;
1728 *ecx = 0;
1729 *edx = 0;
1730 break;
1731 }
1732 break;
1733 case 5:
1734 /* mwait info: needed for Core compatibility */
1735 *eax = 0; /* Smallest monitor-line size in bytes */
1736 *ebx = 0; /* Largest monitor-line size in bytes */
1737 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1738 *edx = 0;
1739 break;
1740 case 6:
1741 /* Thermal and Power Leaf */
1742 *eax = 0;
1743 *ebx = 0;
1744 *ecx = 0;
1745 *edx = 0;
1746 break;
1747 case 7:
1748 /* Structured Extended Feature Flags Enumeration Leaf */
1749 if (count == 0) {
1750 *eax = 0; /* Maximum ECX value for sub-leaves */
1751 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1752 *ecx = 0; /* Reserved */
1753 *edx = 0; /* Reserved */
1754 } else {
1755 *eax = 0;
1756 *ebx = 0;
1757 *ecx = 0;
1758 *edx = 0;
1759 }
1760 break;
1761 case 9:
1762 /* Direct Cache Access Information Leaf */
1763 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1764 *ebx = 0;
1765 *ecx = 0;
1766 *edx = 0;
1767 break;
1768 case 0xA:
1769 /* Architectural Performance Monitoring Leaf */
1770 if (kvm_enabled()) {
1771 KVMState *s = cs->kvm_state;
1772
1773 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1774 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1775 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1776 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1777 } else {
1778 *eax = 0;
1779 *ebx = 0;
1780 *ecx = 0;
1781 *edx = 0;
1782 }
1783 break;
1784 case 0xD:
1785 /* Processor Extended State */
1786 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1787 *eax = 0;
1788 *ebx = 0;
1789 *ecx = 0;
1790 *edx = 0;
1791 break;
1792 }
1793 if (kvm_enabled()) {
1794 KVMState *s = cs->kvm_state;
1795
1796 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1797 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1798 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1799 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1800 } else {
1801 *eax = 0;
1802 *ebx = 0;
1803 *ecx = 0;
1804 *edx = 0;
1805 }
1806 break;
1807 case 0x80000000:
1808 *eax = env->cpuid_xlevel;
1809 *ebx = env->cpuid_vendor1;
1810 *edx = env->cpuid_vendor2;
1811 *ecx = env->cpuid_vendor3;
1812 break;
1813 case 0x80000001:
1814 *eax = env->cpuid_version;
1815 *ebx = 0;
1816 *ecx = env->cpuid_ext3_features;
1817 *edx = env->cpuid_ext2_features;
1818
1819 /* The Linux kernel checks for the CMPLegacy bit and
1820 * discards multiple thread information if it is set.
1821 * So dont set it here for Intel to make Linux guests happy.
1822 */
1823 if (cs->nr_cores * cs->nr_threads > 1) {
1824 uint32_t tebx, tecx, tedx;
1825 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1826 if (tebx != CPUID_VENDOR_INTEL_1 ||
1827 tedx != CPUID_VENDOR_INTEL_2 ||
1828 tecx != CPUID_VENDOR_INTEL_3) {
1829 *ecx |= 1 << 1; /* CmpLegacy bit */
1830 }
1831 }
1832 break;
1833 case 0x80000002:
1834 case 0x80000003:
1835 case 0x80000004:
1836 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1837 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1838 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1839 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1840 break;
1841 case 0x80000005:
1842 /* cache info (L1 cache) */
1843 *eax = 0x01ff01ff;
1844 *ebx = 0x01ff01ff;
1845 *ecx = 0x40020140;
1846 *edx = 0x40020140;
1847 break;
1848 case 0x80000006:
1849 /* cache info (L2 cache) */
1850 *eax = 0;
1851 *ebx = 0x42004200;
1852 *ecx = 0x02008140;
1853 *edx = 0;
1854 break;
1855 case 0x80000008:
1856 /* virtual & phys address size in low 2 bytes. */
1857 /* XXX: This value must match the one used in the MMU code. */
1858 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1859 /* 64 bit processor */
1860 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1861 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1862 } else {
1863 if (env->cpuid_features & CPUID_PSE36)
1864 *eax = 0x00000024; /* 36 bits physical */
1865 else
1866 *eax = 0x00000020; /* 32 bits physical */
1867 }
1868 *ebx = 0;
1869 *ecx = 0;
1870 *edx = 0;
1871 if (cs->nr_cores * cs->nr_threads > 1) {
1872 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
1873 }
1874 break;
1875 case 0x8000000A:
1876 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1877 *eax = 0x00000001; /* SVM Revision */
1878 *ebx = 0x00000010; /* nr of ASIDs */
1879 *ecx = 0;
1880 *edx = env->cpuid_svm_features; /* optional features */
1881 } else {
1882 *eax = 0;
1883 *ebx = 0;
1884 *ecx = 0;
1885 *edx = 0;
1886 }
1887 break;
1888 case 0xC0000000:
1889 *eax = env->cpuid_xlevel2;
1890 *ebx = 0;
1891 *ecx = 0;
1892 *edx = 0;
1893 break;
1894 case 0xC0000001:
1895 /* Support for VIA CPU's CPUID instruction */
1896 *eax = env->cpuid_version;
1897 *ebx = 0;
1898 *ecx = 0;
1899 *edx = env->cpuid_ext4_features;
1900 break;
1901 case 0xC0000002:
1902 case 0xC0000003:
1903 case 0xC0000004:
1904 /* Reserved for the future, and now filled with zero */
1905 *eax = 0;
1906 *ebx = 0;
1907 *ecx = 0;
1908 *edx = 0;
1909 break;
1910 default:
1911 /* reserved values: zero */
1912 *eax = 0;
1913 *ebx = 0;
1914 *ecx = 0;
1915 *edx = 0;
1916 break;
1917 }
1918 }
1919
1920 /* CPUClass::reset() */
1921 static void x86_cpu_reset(CPUState *s)
1922 {
1923 X86CPU *cpu = X86_CPU(s);
1924 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1925 CPUX86State *env = &cpu->env;
1926 int i;
1927
1928 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1929 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
1930 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1931 }
1932
1933 xcc->parent_reset(s);
1934
1935
1936 memset(env, 0, offsetof(CPUX86State, breakpoints));
1937
1938 tlb_flush(env, 1);
1939
1940 env->old_exception = -1;
1941
1942 /* init to reset state */
1943
1944 #ifdef CONFIG_SOFTMMU
1945 env->hflags |= HF_SOFTMMU_MASK;
1946 #endif
1947 env->hflags2 |= HF2_GIF_MASK;
1948
1949 cpu_x86_update_cr0(env, 0x60000010);
1950 env->a20_mask = ~0x0;
1951 env->smbase = 0x30000;
1952
1953 env->idt.limit = 0xffff;
1954 env->gdt.limit = 0xffff;
1955 env->ldt.limit = 0xffff;
1956 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1957 env->tr.limit = 0xffff;
1958 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1959
1960 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1961 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1962 DESC_R_MASK | DESC_A_MASK);
1963 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1964 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1965 DESC_A_MASK);
1966 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1967 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1968 DESC_A_MASK);
1969 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1970 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1971 DESC_A_MASK);
1972 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1973 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1974 DESC_A_MASK);
1975 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1976 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1977 DESC_A_MASK);
1978
1979 env->eip = 0xfff0;
1980 env->regs[R_EDX] = env->cpuid_version;
1981
1982 env->eflags = 0x2;
1983
1984 /* FPU init */
1985 for (i = 0; i < 8; i++) {
1986 env->fptags[i] = 1;
1987 }
1988 env->fpuc = 0x37f;
1989
1990 env->mxcsr = 0x1f80;
1991
1992 env->pat = 0x0007040600070406ULL;
1993 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1994
1995 memset(env->dr, 0, sizeof(env->dr));
1996 env->dr[6] = DR6_FIXED_1;
1997 env->dr[7] = DR7_FIXED_1;
1998 cpu_breakpoint_remove_all(env, BP_CPU);
1999 cpu_watchpoint_remove_all(env, BP_CPU);
2000
2001 #if !defined(CONFIG_USER_ONLY)
2002 /* We hard-wire the BSP to the first CPU. */
2003 if (s->cpu_index == 0) {
2004 apic_designate_bsp(env->apic_state);
2005 }
2006
2007 env->halted = !cpu_is_bsp(cpu);
2008 #endif
2009 }
2010
2011 #ifndef CONFIG_USER_ONLY
2012 bool cpu_is_bsp(X86CPU *cpu)
2013 {
2014 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2015 }
2016
2017 /* TODO: remove me, when reset over QOM tree is implemented */
2018 static void x86_cpu_machine_reset_cb(void *opaque)
2019 {
2020 X86CPU *cpu = opaque;
2021 cpu_reset(CPU(cpu));
2022 }
2023 #endif
2024
2025 static void mce_init(X86CPU *cpu)
2026 {
2027 CPUX86State *cenv = &cpu->env;
2028 unsigned int bank;
2029
2030 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2031 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2032 (CPUID_MCE | CPUID_MCA)) {
2033 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2034 cenv->mcg_ctl = ~(uint64_t)0;
2035 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2036 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2037 }
2038 }
2039 }
2040
2041 #define MSI_ADDR_BASE 0xfee00000
2042
2043 #ifndef CONFIG_USER_ONLY
2044 static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2045 {
2046 static int apic_mapped;
2047 CPUX86State *env = &cpu->env;
2048 APICCommonState *apic;
2049 const char *apic_type = "apic";
2050
2051 if (kvm_irqchip_in_kernel()) {
2052 apic_type = "kvm-apic";
2053 } else if (xen_enabled()) {
2054 apic_type = "xen-apic";
2055 }
2056
2057 env->apic_state = qdev_try_create(NULL, apic_type);
2058 if (env->apic_state == NULL) {
2059 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2060 return;
2061 }
2062
2063 object_property_add_child(OBJECT(cpu), "apic",
2064 OBJECT(env->apic_state), NULL);
2065 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2066 /* TODO: convert to link<> */
2067 apic = APIC_COMMON(env->apic_state);
2068 apic->cpu = cpu;
2069
2070 if (qdev_init(env->apic_state)) {
2071 error_setg(errp, "APIC device '%s' could not be initialized",
2072 object_get_typename(OBJECT(env->apic_state)));
2073 return;
2074 }
2075
2076 /* XXX: mapping more APICs at the same memory location */
2077 if (apic_mapped == 0) {
2078 /* NOTE: the APIC is directly connected to the CPU - it is not
2079 on the global memory bus. */
2080 /* XXX: what if the base changes? */
2081 sysbus_mmio_map(SYS_BUS_DEVICE(env->apic_state), 0, MSI_ADDR_BASE);
2082 apic_mapped = 1;
2083 }
2084 }
2085 #endif
2086
2087 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2088 {
2089 X86CPU *cpu = X86_CPU(dev);
2090 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2091 CPUX86State *env = &cpu->env;
2092 #ifndef CONFIG_USER_ONLY
2093 Error *local_err = NULL;
2094 #endif
2095
2096 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2097 env->cpuid_level = 7;
2098 }
2099
2100 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2101 * CPUID[1].EDX.
2102 */
2103 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2104 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2105 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2106 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
2107 env->cpuid_ext2_features |= (env->cpuid_features
2108 & CPUID_EXT2_AMD_ALIASES);
2109 }
2110
2111 if (!kvm_enabled()) {
2112 env->cpuid_features &= TCG_FEATURES;
2113 env->cpuid_ext_features &= TCG_EXT_FEATURES;
2114 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2115 #ifdef TARGET_X86_64
2116 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2117 #endif
2118 );
2119 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2120 env->cpuid_svm_features &= TCG_SVM_FEATURES;
2121 } else {
2122 #ifdef CONFIG_KVM
2123 filter_features_for_kvm(cpu);
2124 #endif
2125 if (check_cpuid && kvm_check_features_against_host(cpu)
2126 && enforce_cpuid) {
2127 error_setg(errp, "Host's CPU doesn't support requested features");
2128 return;
2129 }
2130 }
2131
2132 #ifndef CONFIG_USER_ONLY
2133 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2134
2135 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2136 x86_cpu_apic_init(cpu, &local_err);
2137 if (local_err != NULL) {
2138 error_propagate(errp, local_err);
2139 return;
2140 }
2141 }
2142 #endif
2143
2144 mce_init(cpu);
2145 qemu_init_vcpu(&cpu->env);
2146 cpu_reset(CPU(cpu));
2147
2148 xcc->parent_realize(dev, errp);
2149 }
2150
2151 /* Enables contiguous-apic-ID mode, for compatibility */
2152 static bool compat_apic_id_mode;
2153
2154 void enable_compat_apic_id_mode(void)
2155 {
2156 compat_apic_id_mode = true;
2157 }
2158
2159 /* Calculates initial APIC ID for a specific CPU index
2160 *
2161 * Currently we need to be able to calculate the APIC ID from the CPU index
2162 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2163 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2164 * all CPUs up to max_cpus.
2165 */
2166 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2167 {
2168 uint32_t correct_id;
2169 static bool warned;
2170
2171 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2172 if (compat_apic_id_mode) {
2173 if (cpu_index != correct_id && !warned) {
2174 error_report("APIC IDs set in compatibility mode, "
2175 "CPU topology won't match the configuration");
2176 warned = true;
2177 }
2178 return cpu_index;
2179 } else {
2180 return correct_id;
2181 }
2182 }
2183
2184 static void x86_cpu_initfn(Object *obj)
2185 {
2186 CPUState *cs = CPU(obj);
2187 X86CPU *cpu = X86_CPU(obj);
2188 CPUX86State *env = &cpu->env;
2189 static int inited;
2190
2191 cs->env_ptr = env;
2192 cpu_exec_init(env);
2193
2194 object_property_add(obj, "family", "int",
2195 x86_cpuid_version_get_family,
2196 x86_cpuid_version_set_family, NULL, NULL, NULL);
2197 object_property_add(obj, "model", "int",
2198 x86_cpuid_version_get_model,
2199 x86_cpuid_version_set_model, NULL, NULL, NULL);
2200 object_property_add(obj, "stepping", "int",
2201 x86_cpuid_version_get_stepping,
2202 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2203 object_property_add(obj, "level", "int",
2204 x86_cpuid_get_level,
2205 x86_cpuid_set_level, NULL, NULL, NULL);
2206 object_property_add(obj, "xlevel", "int",
2207 x86_cpuid_get_xlevel,
2208 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2209 object_property_add_str(obj, "vendor",
2210 x86_cpuid_get_vendor,
2211 x86_cpuid_set_vendor, NULL);
2212 object_property_add_str(obj, "model-id",
2213 x86_cpuid_get_model_id,
2214 x86_cpuid_set_model_id, NULL);
2215 object_property_add(obj, "tsc-frequency", "int",
2216 x86_cpuid_get_tsc_freq,
2217 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2218
2219 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2220
2221 /* init various static tables used in TCG mode */
2222 if (tcg_enabled() && !inited) {
2223 inited = 1;
2224 optimize_flags_init();
2225 #ifndef CONFIG_USER_ONLY
2226 cpu_set_debug_excp_handler(breakpoint_handler);
2227 #endif
2228 }
2229 }
2230
2231 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2232 {
2233 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2234 CPUClass *cc = CPU_CLASS(oc);
2235 DeviceClass *dc = DEVICE_CLASS(oc);
2236
2237 xcc->parent_realize = dc->realize;
2238 dc->realize = x86_cpu_realizefn;
2239
2240 xcc->parent_reset = cc->reset;
2241 cc->reset = x86_cpu_reset;
2242 }
2243
2244 static const TypeInfo x86_cpu_type_info = {
2245 .name = TYPE_X86_CPU,
2246 .parent = TYPE_CPU,
2247 .instance_size = sizeof(X86CPU),
2248 .instance_init = x86_cpu_initfn,
2249 .abstract = false,
2250 .class_size = sizeof(X86CPUClass),
2251 .class_init = x86_cpu_common_class_init,
2252 };
2253
2254 static void x86_cpu_register_types(void)
2255 {
2256 type_register_static(&x86_cpu_type_info);
2257 }
2258
2259 type_init(x86_cpu_register_types)
AR7 emulation for QEMU