tests/e1000e-test.c

   1  /*
   2  * QTest testcase for e1000e NIC
   3  *
   4  * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
   5  * Developed by Daynix Computing LTD (http://www.daynix.com)
   6  *
   7  * Authors:
   8  * Dmitry Fleytman <dmitry@daynix.com>
   9  * Leonid Bloch <leonid@daynix.com>
  10  * Yan Vugenfirer <yan@daynix.com>
  11  *
  12  * This library is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU Lesser General Public
  14  * License as published by the Free Software Foundation; either
  15  * version 2 of the License, or (at your option) any later version.
  16  *
  17  * This library is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  20  * Lesser General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU Lesser General Public
  23  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  24  */
  25
  26
  27 #include "qemu/osdep.h"
  28 #include "libqtest.h"
  29 #include "qemu-common.h"
  30 #include "libqos/pci-pc.h"
  31 #include "qemu/sockets.h"
  32 #include "qemu/iov.h"
  33 #include "qemu/bitops.h"
  34 #include "libqos/malloc.h"
  35 #include "libqos/malloc-pc.h"
  36 #include "libqos/malloc-generic.h"
  37
  38 #define E1000E_IMS      (0x00d0)
  39
  40 #define E1000E_STATUS   (0x0008)
  41 #define E1000E_STATUS_LU BIT(1)
  42 #define E1000E_STATUS_ASDV1000 BIT(9)
  43
  44 #define E1000E_CTRL     (0x0000)
  45 #define E1000E_CTRL_RESET BIT(26)
  46
  47 #define E1000E_RCTL     (0x0100)
  48 #define E1000E_RCTL_EN  BIT(1)
  49 #define E1000E_RCTL_UPE BIT(3)
  50 #define E1000E_RCTL_MPE BIT(4)
  51
  52 #define E1000E_RFCTL     (0x5008)
  53 #define E1000E_RFCTL_EXTEN  BIT(15)
  54
  55 #define E1000E_TCTL     (0x0400)
  56 #define E1000E_TCTL_EN  BIT(1)
  57
  58 #define E1000E_CTRL_EXT             (0x0018)
  59 #define E1000E_CTRL_EXT_DRV_LOAD    BIT(28)
  60 #define E1000E_CTRL_EXT_TXLSFLOW    BIT(22)
  61
  62 #define E1000E_RX0_MSG_ID           (0)
  63 #define E1000E_TX0_MSG_ID           (1)
  64 #define E1000E_OTHER_MSG_ID         (2)
  65
  66 #define E1000E_IVAR                 (0x00E4)
  67 #define E1000E_IVAR_TEST_CFG        ((E1000E_RX0_MSG_ID << 0)    | BIT(3)  | \
  68                                      (E1000E_TX0_MSG_ID << 8)    | BIT(11) | \
  69                                      (E1000E_OTHER_MSG_ID << 16) | BIT(19) | \
  70                                      BIT(31))
  71
  72 #define E1000E_RING_LEN             (0x1000)
  73 #define E1000E_TXD_LEN              (16)
  74 #define E1000E_RXD_LEN              (16)
  75
  76 #define E1000E_TDBAL    (0x3800)
  77 #define E1000E_TDBAH    (0x3804)
  78 #define E1000E_TDLEN    (0x3808)
  79 #define E1000E_TDH      (0x3810)
  80 #define E1000E_TDT      (0x3818)
  81
  82 #define E1000E_RDBAL    (0x2800)
  83 #define E1000E_RDBAH    (0x2804)
  84 #define E1000E_RDLEN    (0x2808)
  85 #define E1000E_RDH      (0x2810)
  86 #define E1000E_RDT      (0x2818)
  87
  88 typedef struct e1000e_device {
  89     QPCIDevice *pci_dev;
  90     QPCIBar mac_regs;
  91
  92     uint64_t tx_ring;
  93     uint64_t rx_ring;
  94 } e1000e_device;
  95
  96 static int test_sockets[2];
  97 static QGuestAllocator *test_alloc;
  98 static QPCIBus *test_bus;
  99
 100 static void e1000e_pci_foreach_callback(QPCIDevice *dev, int devfn, void *data)
 101 {
 102     QPCIDevice **res = data;
 103
 104     g_assert_null(*res);
 105     *res = dev;
 106 }
 107
 108 static QPCIDevice *e1000e_device_find(QPCIBus *bus)
 109 {
 110     static const int e1000e_vendor_id = 0x8086;
 111     static const int e1000e_dev_id = 0x10D3;
 112
 113     QPCIDevice *e1000e_dev = NULL;
 114
 115     qpci_device_foreach(bus, e1000e_vendor_id, e1000e_dev_id,
 116         e1000e_pci_foreach_callback, &e1000e_dev);
 117
 118     g_assert_nonnull(e1000e_dev);
 119
 120     return e1000e_dev;
 121 }
 122
 123 static void e1000e_macreg_write(e1000e_device *d, uint32_t reg, uint32_t val)
 124 {
 125     qpci_io_writel(d->pci_dev, d->mac_regs, reg, val);
 126 }
 127
 128 static uint32_t e1000e_macreg_read(e1000e_device *d, uint32_t reg)
 129 {
 130     return qpci_io_readl(d->pci_dev, d->mac_regs, reg);
 131 }
 132
 133 static void e1000e_device_init(QPCIBus *bus, e1000e_device *d)
 134 {
 135     uint32_t val;
 136
 137     d->pci_dev = e1000e_device_find(bus);
 138
 139     /* Enable the device */
 140     qpci_device_enable(d->pci_dev);
 141
 142     /* Map BAR0 (mac registers) */
 143     d->mac_regs = qpci_iomap(d->pci_dev, 0, NULL);
 144
 145     /* Reset the device */
 146     val = e1000e_macreg_read(d, E1000E_CTRL);
 147     e1000e_macreg_write(d, E1000E_CTRL, val | E1000E_CTRL_RESET);
 148
 149     /* Enable and configure MSI-X */
 150     qpci_msix_enable(d->pci_dev);
 151     e1000e_macreg_write(d, E1000E_IVAR, E1000E_IVAR_TEST_CFG);
 152
 153     /* Check the device status - link and speed */
 154     val = e1000e_macreg_read(d, E1000E_STATUS);
 155     g_assert_cmphex(val & (E1000E_STATUS_LU | E1000E_STATUS_ASDV1000),
 156         ==, E1000E_STATUS_LU | E1000E_STATUS_ASDV1000);
 157
 158     /* Initialize TX/RX logic */
 159     e1000e_macreg_write(d, E1000E_RCTL, 0);
 160     e1000e_macreg_write(d, E1000E_TCTL, 0);
 161
 162     /* Notify the device that the driver is ready */
 163     val = e1000e_macreg_read(d, E1000E_CTRL_EXT);
 164     e1000e_macreg_write(d, E1000E_CTRL_EXT,
 165         val | E1000E_CTRL_EXT_DRV_LOAD | E1000E_CTRL_EXT_TXLSFLOW);
 166
 167     /* Allocate and setup TX ring */
 168     d->tx_ring = guest_alloc(test_alloc, E1000E_RING_LEN);
 169     g_assert(d->tx_ring != 0);
 170
 171     e1000e_macreg_write(d, E1000E_TDBAL, (uint32_t) d->tx_ring);
 172     e1000e_macreg_write(d, E1000E_TDBAH, (uint32_t) (d->tx_ring >> 32));
 173     e1000e_macreg_write(d, E1000E_TDLEN, E1000E_RING_LEN);
 174     e1000e_macreg_write(d, E1000E_TDT, 0);
 175     e1000e_macreg_write(d, E1000E_TDH, 0);
 176
 177     /* Enable transmit */
 178     e1000e_macreg_write(d, E1000E_TCTL, E1000E_TCTL_EN);
 179
 180     /* Allocate and setup RX ring */
 181     d->rx_ring = guest_alloc(test_alloc, E1000E_RING_LEN);
 182     g_assert(d->rx_ring != 0);
 183
 184     e1000e_macreg_write(d, E1000E_RDBAL, (uint32_t)d->rx_ring);
 185     e1000e_macreg_write(d, E1000E_RDBAH, (uint32_t)(d->rx_ring >> 32));
 186     e1000e_macreg_write(d, E1000E_RDLEN, E1000E_RING_LEN);
 187     e1000e_macreg_write(d, E1000E_RDT, 0);
 188     e1000e_macreg_write(d, E1000E_RDH, 0);
 189
 190     /* Enable receive */
 191     e1000e_macreg_write(d, E1000E_RFCTL, E1000E_RFCTL_EXTEN);
 192     e1000e_macreg_write(d, E1000E_RCTL, E1000E_RCTL_EN  |
 193                                         E1000E_RCTL_UPE |
 194                                         E1000E_RCTL_MPE);
 195
 196     /* Enable all interrupts */
 197     e1000e_macreg_write(d, E1000E_IMS, 0xFFFFFFFF);
 198 }
 199
 200 static void e1000e_tx_ring_push(e1000e_device *d, void *descr)
 201 {
 202     uint32_t tail = e1000e_macreg_read(d, E1000E_TDT);
 203     uint32_t len = e1000e_macreg_read(d, E1000E_TDLEN) / E1000E_TXD_LEN;
 204
 205     memwrite(d->tx_ring + tail * E1000E_TXD_LEN, descr, E1000E_TXD_LEN);
 206     e1000e_macreg_write(d, E1000E_TDT, (tail + 1) % len);
 207
 208     /* Read WB data for the packet transmitted */
 209     memread(d->tx_ring + tail * E1000E_TXD_LEN, descr, E1000E_TXD_LEN);
 210 }
 211
 212 static void e1000e_rx_ring_push(e1000e_device *d, void *descr)
 213 {
 214     uint32_t tail = e1000e_macreg_read(d, E1000E_RDT);
 215     uint32_t len = e1000e_macreg_read(d, E1000E_RDLEN) / E1000E_RXD_LEN;
 216
 217     memwrite(d->rx_ring + tail * E1000E_RXD_LEN, descr, E1000E_RXD_LEN);
 218     e1000e_macreg_write(d, E1000E_RDT, (tail + 1) % len);
 219
 220     /* Read WB data for the packet received */
 221     memread(d->rx_ring + tail * E1000E_RXD_LEN, descr, E1000E_RXD_LEN);
 222 }
 223
 224 static void e1000e_wait_isr(e1000e_device *d, uint16_t msg_id)
 225 {
 226     guint64 end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND;
 227
 228     do {
 229         if (qpci_msix_pending(d->pci_dev, msg_id)) {
 230             return;
 231         }
 232         clock_step(10000);
 233     } while (g_get_monotonic_time() < end_time);
 234
 235     g_error("Timeout expired");
 236 }
 237
 238 static void e1000e_send_verify(e1000e_device *d)
 239 {
 240     struct {
 241         uint64_t buffer_addr;
 242         union {
 243             uint32_t data;
 244             struct {
 245                 uint16_t length;
 246                 uint8_t cso;
 247                 uint8_t cmd;
 248             } flags;
 249         } lower;
 250         union {
 251             uint32_t data;
 252             struct {
 253                 uint8_t status;
 254                 uint8_t css;
 255                 uint16_t special;
 256             } fields;
 257         } upper;
 258     } descr;
 259
 260     static const uint32_t dtyp_data = BIT(20);
 261     static const uint32_t dtyp_ext  = BIT(29);
 262     static const uint32_t dcmd_rs   = BIT(27);
 263     static const uint32_t dcmd_eop  = BIT(24);
 264     static const uint32_t dsta_dd   = BIT(0);
 265     static const int data_len = 64;
 266     char buffer[64];
 267     int ret;
 268     uint32_t recv_len;
 269
 270     /* Prepare test data buffer */
 271     uint64_t data = guest_alloc(test_alloc, data_len);
 272     memwrite(data, "TEST", 5);
 273
 274     /* Prepare TX descriptor */
 275     memset(&descr, 0, sizeof(descr));
 276     descr.buffer_addr = cpu_to_le64(data);
 277     descr.lower.data = cpu_to_le32(dcmd_rs   |
 278                                    dcmd_eop  |
 279                                    dtyp_ext  |
 280                                    dtyp_data |
 281                                    data_len);
 282
 283     /* Put descriptor to the ring */
 284     e1000e_tx_ring_push(d, &descr);
 285
 286     /* Wait for TX WB interrupt */
 287     e1000e_wait_isr(d, E1000E_TX0_MSG_ID);
 288
 289     /* Check DD bit */
 290     g_assert_cmphex(le32_to_cpu(descr.upper.data) & dsta_dd, ==, dsta_dd);
 291
 292     /* Check data sent to the backend */
 293     ret = qemu_recv(test_sockets[0], &recv_len, sizeof(recv_len), 0);
 294     g_assert_cmpint(ret, == , sizeof(recv_len));
 295     qemu_recv(test_sockets[0], buffer, 64, 0);
 296     g_assert_cmpstr(buffer, == , "TEST");
 297
 298     /* Free test data buffer */
 299     guest_free(test_alloc, data);
 300 }
 301
 302 static void e1000e_receive_verify(e1000e_device *d)
 303 {
 304     union {
 305         struct {
 306             uint64_t buffer_addr;
 307             uint64_t reserved;
 308         } read;
 309         struct {
 310             struct {
 311                 uint32_t mrq;
 312                 union {
 313                     uint32_t rss;
 314                     struct {
 315                         uint16_t ip_id;
 316                         uint16_t csum;
 317                     } csum_ip;
 318                 } hi_dword;
 319             } lower;
 320             struct {
 321                 uint32_t status_error;
 322                 uint16_t length;
 323                 uint16_t vlan;
 324             } upper;
 325         } wb;
 326     } descr;
 327
 328     static const uint32_t esta_dd = BIT(0);
 329
 330     char test[] = "TEST";
 331     int len = htonl(sizeof(test));
 332     struct iovec iov[] = {
 333         {
 334             .iov_base = &len,
 335             .iov_len = sizeof(len),
 336         },{
 337             .iov_base = test,
 338             .iov_len = sizeof(test),
 339         },
 340     };
 341
 342     static const int data_len = 64;
 343     char buffer[64];
 344     int ret;
 345
 346     /* Send a dummy packet to device's socket*/
 347     ret = iov_send(test_sockets[0], iov, 2, 0, sizeof(len) + sizeof(test));
 348     g_assert_cmpint(ret, == , sizeof(test) + sizeof(len));
 349
 350     /* Prepare test data buffer */
 351     uint64_t data = guest_alloc(test_alloc, data_len);
 352
 353     /* Prepare RX descriptor */
 354     memset(&descr, 0, sizeof(descr));
 355     descr.read.buffer_addr = cpu_to_le64(data);
 356
 357     /* Put descriptor to the ring */
 358     e1000e_rx_ring_push(d, &descr);
 359
 360     /* Wait for TX WB interrupt */
 361     e1000e_wait_isr(d, E1000E_RX0_MSG_ID);
 362
 363     /* Check DD bit */
 364     g_assert_cmphex(le32_to_cpu(descr.wb.upper.status_error) &
 365         esta_dd, ==, esta_dd);
 366
 367     /* Check data sent to the backend */
 368     memread(data, buffer, sizeof(buffer));
 369     g_assert_cmpstr(buffer, == , "TEST");
 370
 371     /* Free test data buffer */
 372     guest_free(test_alloc, data);
 373 }
 374
 375 static void e1000e_device_clear(QPCIBus *bus, e1000e_device *d)
 376 {
 377     qpci_iounmap(d->pci_dev, d->mac_regs);
 378     qpci_msix_disable(d->pci_dev);
 379 }
 380
 381 static void data_test_init(e1000e_device *d)
 382 {
 383     char *cmdline;
 384
 385     int ret = socketpair(PF_UNIX, SOCK_STREAM, 0, test_sockets);
 386     g_assert_cmpint(ret, != , -1);
 387
 388     cmdline = g_strdup_printf("-netdev socket,fd=%d,id=hs0 "
 389                               "-device e1000e,netdev=hs0", test_sockets[1]);
 390     g_assert_nonnull(cmdline);
 391
 392     qtest_start(cmdline);
 393     g_free(cmdline);
 394
 395     test_alloc = pc_alloc_init(global_qtest);
 396     g_assert_nonnull(test_alloc);
 397
 398     test_bus = qpci_init_pc(global_qtest, test_alloc);
 399     g_assert_nonnull(test_bus);
 400
 401     e1000e_device_init(test_bus, d);
 402 }
 403
 404 static void data_test_clear(e1000e_device *d)
 405 {
 406     e1000e_device_clear(test_bus, d);
 407     close(test_sockets[0]);
 408     pc_alloc_uninit(test_alloc);
 409     g_free(d->pci_dev);
 410     qpci_free_pc(test_bus);
 411     qtest_end();
 412 }
 413
 414 static void test_e1000e_init(gconstpointer data)
 415 {
 416     e1000e_device d;
 417
 418     data_test_init(&d);
 419     data_test_clear(&d);
 420 }
 421
 422 static void test_e1000e_tx(gconstpointer data)
 423 {
 424     e1000e_device d;
 425
 426     data_test_init(&d);
 427     e1000e_send_verify(&d);
 428     data_test_clear(&d);
 429 }
 430
 431 static void test_e1000e_rx(gconstpointer data)
 432 {
 433     e1000e_device d;
 434
 435     data_test_init(&d);
 436     e1000e_receive_verify(&d);
 437     data_test_clear(&d);
 438 }
 439
 440 static void test_e1000e_multiple_transfers(gconstpointer data)
 441 {
 442     static const long iterations = 4 * 1024;
 443     long i;
 444
 445     e1000e_device d;
 446
 447     data_test_init(&d);
 448
 449     for (i = 0; i < iterations; i++) {
 450         e1000e_send_verify(&d);
 451         e1000e_receive_verify(&d);
 452     }
 453
 454     data_test_clear(&d);
 455 }
 456
 457 static void test_e1000e_hotplug(gconstpointer data)
 458 {
 459     qtest_start("-device e1000e");
 460
 461     qtest_qmp_device_add("e1000e", "e1000e_net", "{'addr': '0x06'}");
 462     qpci_unplug_acpi_device_test("e1000e_net", 0x06);
 463
 464     qtest_end();
 465 }
 466
 467 int main(int argc, char **argv)
 468 {
 469     g_test_init(&argc, &argv, NULL);
 470
 471     qtest_add_data_func("e1000e/init", NULL, test_e1000e_init);
 472     qtest_add_data_func("e1000e/tx", NULL, test_e1000e_tx);
 473     qtest_add_data_func("e1000e/rx", NULL, test_e1000e_rx);
 474     qtest_add_data_func("e1000e/multiple_transfers", NULL,
 475         test_e1000e_multiple_transfers);
 476     qtest_add_data_func("e1000e/hotplug", NULL, test_e1000e_hotplug);
 477
 478     return g_test_run();
 479 }