target-unicore32/helper.c

   1 /*
   2  * Copyright (C) 2010-2012 Guan Xuetao
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Contributions from 2012-04-01 on are considered under GPL version 2,
   9  * or (at your option) any later version.
  10  */
  11
  12 #include "cpu.h"
  13 #include "gdbstub.h"
  14 #include "helper.h"
  15 #include "host-utils.h"
  16
  17 #undef DEBUG_UC32
  18
  19 #ifdef DEBUG_UC32
  20 #define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
  21 #else
  22 #define DPRINTF(fmt, ...) do {} while (0)
  23 #endif
  24
  25 CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
  26 {
  27     UniCore32CPU *cpu;
  28     CPUUniCore32State *env;
  29     static int inited = 1;
  30
  31     if (object_class_by_name(cpu_model) == NULL) {
  32         return NULL;
  33     }
  34     cpu = UNICORE32_CPU(object_new(cpu_model));
  35     env = &cpu->env;
  36
  37     if (inited) {
  38         inited = 0;
  39         uc32_translate_init();
  40     }
  41
  42     qemu_init_vcpu(env);
  43     return env;
  44 }
  45
  46 uint32_t HELPER(clo)(uint32_t x)
  47 {
  48     return clo32(x);
  49 }
  50
  51 uint32_t HELPER(clz)(uint32_t x)
  52 {
  53     return clz32(x);
  54 }
  55
  56 #ifndef CONFIG_USER_ONLY
  57 void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
  58         uint32_t cop)
  59 {
  60     /*
  61      * movc pp.nn, rn, #imm9
  62      *      rn: UCOP_REG_D
  63      *      nn: UCOP_REG_N
  64      *          1: sys control reg.
  65      *          2: page table base reg.
  66      *          3: data fault status reg.
  67      *          4: insn fault status reg.
  68      *          5: cache op. reg.
  69      *          6: tlb op. reg.
  70      *      imm9: split UCOP_IMM10 with bit5 is 0
  71      */
  72     switch (creg) {
  73     case 1:
  74         if (cop != 0) {
  75             goto unrecognized;
  76         }
  77         env->cp0.c1_sys = val;
  78         break;
  79     case 2:
  80         if (cop != 0) {
  81             goto unrecognized;
  82         }
  83         env->cp0.c2_base = val;
  84         break;
  85     case 3:
  86         if (cop != 0) {
  87             goto unrecognized;
  88         }
  89         env->cp0.c3_faultstatus = val;
  90         break;
  91     case 4:
  92         if (cop != 0) {
  93             goto unrecognized;
  94         }
  95         env->cp0.c4_faultaddr = val;
  96         break;
  97     case 5:
  98         switch (cop) {
  99         case 28:
 100             DPRINTF("Invalidate Entire I&D cache\n");
 101             return;
 102         case 20:
 103             DPRINTF("Invalidate Entire Icache\n");
 104             return;
 105         case 12:
 106             DPRINTF("Invalidate Entire Dcache\n");
 107             return;
 108         case 10:
 109             DPRINTF("Clean Entire Dcache\n");
 110             return;
 111         case 14:
 112             DPRINTF("Flush Entire Dcache\n");
 113             return;
 114         case 13:
 115             DPRINTF("Invalidate Dcache line\n");
 116             return;
 117         case 11:
 118             DPRINTF("Clean Dcache line\n");
 119             return;
 120         case 15:
 121             DPRINTF("Flush Dcache line\n");
 122             return;
 123         }
 124         break;
 125     case 6:
 126         if ((cop <= 6) && (cop >= 2)) {
 127             /* invalid all tlb */
 128             tlb_flush(env, 1);
 129             return;
 130         }
 131         break;
 132     default:
 133         goto unrecognized;
 134     }
 135     return;
 136 unrecognized:
 137     DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
 138             creg, cop);
 139 }
 140
 141 uint32_t helper_cp0_get(CPUUniCore32State *env, uint32_t creg, uint32_t cop)
 142 {
 143     /*
 144      * movc rd, pp.nn, #imm9
 145      *      rd: UCOP_REG_D
 146      *      nn: UCOP_REG_N
 147      *          0: cpuid and cachetype
 148      *          1: sys control reg.
 149      *          2: page table base reg.
 150      *          3: data fault status reg.
 151      *          4: insn fault status reg.
 152      *      imm9: split UCOP_IMM10 with bit5 is 0
 153      */
 154     switch (creg) {
 155     case 0:
 156         switch (cop) {
 157         case 0:
 158             return env->cp0.c0_cpuid;
 159         case 1:
 160             return env->cp0.c0_cachetype;
 161         }
 162         break;
 163     case 1:
 164         if (cop == 0) {
 165             return env->cp0.c1_sys;
 166         }
 167         break;
 168     case 2:
 169         if (cop == 0) {
 170             return env->cp0.c2_base;
 171         }
 172         break;
 173     case 3:
 174         if (cop == 0) {
 175             return env->cp0.c3_faultstatus;
 176         }
 177         break;
 178     case 4:
 179         if (cop == 0) {
 180             return env->cp0.c4_faultaddr;
 181         }
 182         break;
 183     }
 184     DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
 185             creg, cop);
 186     return 0;
 187 }
 188
 189 void helper_cp1_putc(target_ulong x)
 190 {
 191     /* TODO: curses display should be added here for screen output. */
 192     DPRINTF("%c", x);
 193 }
 194 #endif
 195
 196 #ifdef CONFIG_USER_ONLY
 197 void switch_mode(CPUUniCore32State *env, int mode)
 198 {
 199     if (mode != ASR_MODE_USER) {
 200         cpu_abort(env, "Tried to switch out of user mode\n");
 201     }
 202 }
 203
 204 void do_interrupt(CPUUniCore32State *env)
 205 {
 206     cpu_abort(env, "NO interrupt in user mode\n");
 207 }
 208
 209 int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
 210                               int access_type, int mmu_idx)
 211 {
 212     cpu_abort(env, "NO mmu fault in user mode\n");
 213     return 1;
 214 }
 215 #endif