target/sparc/monitor.c

   1 /*
   2  * QEMU monitor
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "cpu.h"
  26 #include "monitor/monitor.h"
  27 #include "monitor/hmp-target.h"
  28 #include "monitor/hmp.h"
  29
  30
  31 void hmp_info_tlb(Monitor *mon, const QDict *qdict)
  32 {
  33     CPUArchState *env1 = mon_get_cpu_env();
  34
  35     if (!env1) {
  36         monitor_printf(mon, "No CPU available\n");
  37         return;
  38     }
  39     dump_mmu(env1);
  40 }
  41
  42 #ifndef TARGET_SPARC64
  43 static target_long monitor_get_psr (const struct MonitorDef *md, int val)
  44 {
  45     CPUArchState *env = mon_get_cpu_env();
  46
  47     return cpu_get_psr(env);
  48 }
  49 #endif
  50
  51 static target_long monitor_get_reg(const struct MonitorDef *md, int val)
  52 {
  53     CPUArchState *env = mon_get_cpu_env();
  54     return env->regwptr[val];
  55 }
  56
  57 const MonitorDef monitor_defs[] = {
  58     { "g0", offsetof(CPUSPARCState, gregs[0]) },
  59     { "g1", offsetof(CPUSPARCState, gregs[1]) },
  60     { "g2", offsetof(CPUSPARCState, gregs[2]) },
  61     { "g3", offsetof(CPUSPARCState, gregs[3]) },
  62     { "g4", offsetof(CPUSPARCState, gregs[4]) },
  63     { "g5", offsetof(CPUSPARCState, gregs[5]) },
  64     { "g6", offsetof(CPUSPARCState, gregs[6]) },
  65     { "g7", offsetof(CPUSPARCState, gregs[7]) },
  66     { "o0", 0, monitor_get_reg },
  67     { "o1", 1, monitor_get_reg },
  68     { "o2", 2, monitor_get_reg },
  69     { "o3", 3, monitor_get_reg },
  70     { "o4", 4, monitor_get_reg },
  71     { "o5", 5, monitor_get_reg },
  72     { "o6", 6, monitor_get_reg },
  73     { "o7", 7, monitor_get_reg },
  74     { "l0", 8, monitor_get_reg },
  75     { "l1", 9, monitor_get_reg },
  76     { "l2", 10, monitor_get_reg },
  77     { "l3", 11, monitor_get_reg },
  78     { "l4", 12, monitor_get_reg },
  79     { "l5", 13, monitor_get_reg },
  80     { "l6", 14, monitor_get_reg },
  81     { "l7", 15, monitor_get_reg },
  82     { "i0", 16, monitor_get_reg },
  83     { "i1", 17, monitor_get_reg },
  84     { "i2", 18, monitor_get_reg },
  85     { "i3", 19, monitor_get_reg },
  86     { "i4", 20, monitor_get_reg },
  87     { "i5", 21, monitor_get_reg },
  88     { "i6", 22, monitor_get_reg },
  89     { "i7", 23, monitor_get_reg },
  90     { "pc", offsetof(CPUSPARCState, pc) },
  91     { "npc", offsetof(CPUSPARCState, npc) },
  92     { "y", offsetof(CPUSPARCState, y) },
  93 #ifndef TARGET_SPARC64
  94     { "psr", 0, &monitor_get_psr, },
  95     { "wim", offsetof(CPUSPARCState, wim) },
  96 #endif
  97     { "tbr", offsetof(CPUSPARCState, tbr) },
  98     { "fsr", offsetof(CPUSPARCState, fsr) },
  99     { "f0", offsetof(CPUSPARCState, fpr[0].l.upper) },
 100     { "f1", offsetof(CPUSPARCState, fpr[0].l.lower) },
 101     { "f2", offsetof(CPUSPARCState, fpr[1].l.upper) },
 102     { "f3", offsetof(CPUSPARCState, fpr[1].l.lower) },
 103     { "f4", offsetof(CPUSPARCState, fpr[2].l.upper) },
 104     { "f5", offsetof(CPUSPARCState, fpr[2].l.lower) },
 105     { "f6", offsetof(CPUSPARCState, fpr[3].l.upper) },
 106     { "f7", offsetof(CPUSPARCState, fpr[3].l.lower) },
 107     { "f8", offsetof(CPUSPARCState, fpr[4].l.upper) },
 108     { "f9", offsetof(CPUSPARCState, fpr[4].l.lower) },
 109     { "f10", offsetof(CPUSPARCState, fpr[5].l.upper) },
 110     { "f11", offsetof(CPUSPARCState, fpr[5].l.lower) },
 111     { "f12", offsetof(CPUSPARCState, fpr[6].l.upper) },
 112     { "f13", offsetof(CPUSPARCState, fpr[6].l.lower) },
 113     { "f14", offsetof(CPUSPARCState, fpr[7].l.upper) },
 114     { "f15", offsetof(CPUSPARCState, fpr[7].l.lower) },
 115     { "f16", offsetof(CPUSPARCState, fpr[8].l.upper) },
 116     { "f17", offsetof(CPUSPARCState, fpr[8].l.lower) },
 117     { "f18", offsetof(CPUSPARCState, fpr[9].l.upper) },
 118     { "f19", offsetof(CPUSPARCState, fpr[9].l.lower) },
 119     { "f20", offsetof(CPUSPARCState, fpr[10].l.upper) },
 120     { "f21", offsetof(CPUSPARCState, fpr[10].l.lower) },
 121     { "f22", offsetof(CPUSPARCState, fpr[11].l.upper) },
 122     { "f23", offsetof(CPUSPARCState, fpr[11].l.lower) },
 123     { "f24", offsetof(CPUSPARCState, fpr[12].l.upper) },
 124     { "f25", offsetof(CPUSPARCState, fpr[12].l.lower) },
 125     { "f26", offsetof(CPUSPARCState, fpr[13].l.upper) },
 126     { "f27", offsetof(CPUSPARCState, fpr[13].l.lower) },
 127     { "f28", offsetof(CPUSPARCState, fpr[14].l.upper) },
 128     { "f29", offsetof(CPUSPARCState, fpr[14].l.lower) },
 129     { "f30", offsetof(CPUSPARCState, fpr[15].l.upper) },
 130     { "f31", offsetof(CPUSPARCState, fpr[15].l.lower) },
 131 #ifdef TARGET_SPARC64
 132     { "f32", offsetof(CPUSPARCState, fpr[16]) },
 133     { "f34", offsetof(CPUSPARCState, fpr[17]) },
 134     { "f36", offsetof(CPUSPARCState, fpr[18]) },
 135     { "f38", offsetof(CPUSPARCState, fpr[19]) },
 136     { "f40", offsetof(CPUSPARCState, fpr[20]) },
 137     { "f42", offsetof(CPUSPARCState, fpr[21]) },
 138     { "f44", offsetof(CPUSPARCState, fpr[22]) },
 139     { "f46", offsetof(CPUSPARCState, fpr[23]) },
 140     { "f48", offsetof(CPUSPARCState, fpr[24]) },
 141     { "f50", offsetof(CPUSPARCState, fpr[25]) },
 142     { "f52", offsetof(CPUSPARCState, fpr[26]) },
 143     { "f54", offsetof(CPUSPARCState, fpr[27]) },
 144     { "f56", offsetof(CPUSPARCState, fpr[28]) },
 145     { "f58", offsetof(CPUSPARCState, fpr[29]) },
 146     { "f60", offsetof(CPUSPARCState, fpr[30]) },
 147     { "f62", offsetof(CPUSPARCState, fpr[31]) },
 148     { "asi", offsetof(CPUSPARCState, asi) },
 149     { "pstate", offsetof(CPUSPARCState, pstate) },
 150     { "cansave", offsetof(CPUSPARCState, cansave) },
 151     { "canrestore", offsetof(CPUSPARCState, canrestore) },
 152     { "otherwin", offsetof(CPUSPARCState, otherwin) },
 153     { "wstate", offsetof(CPUSPARCState, wstate) },
 154     { "cleanwin", offsetof(CPUSPARCState, cleanwin) },
 155     { "fprs", offsetof(CPUSPARCState, fprs) },
 156 #endif
 157     { NULL },
 158 };
 159
 160 const MonitorDef *target_monitor_defs(void)
 161 {
 162     return monitor_defs;
 163 }