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s390x/css: catch ccw sequence errors
[qemu/ar7.git] / target-ppc / translate.c
blobd03daeaa486768d960961afbf8d2a76841fe07e9
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25 #include "exec/cpu_ldst.h"
26
27 #include "exec/helper-proto.h"
28 #include "exec/helper-gen.h"
29
30 #include "trace-tcg.h"
31
32
33 #define CPU_SINGLE_STEP 0x1
34 #define CPU_BRANCH_STEP 0x2
35 #define GDBSTUB_SINGLE_STEP 0x4
36
37 /* Include definitions for instructions classes and implementations flags */
38 //#define PPC_DEBUG_DISAS
39 //#define DO_PPC_STATISTICS
40
41 #ifdef PPC_DEBUG_DISAS
42 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
43 #else
44 # define LOG_DISAS(...) do { } while (0)
45 #endif
46 /*****************************************************************************/
47 /* Code translation helpers */
48
49 /* global register indexes */
50 static TCGv_ptr cpu_env;
51 static char cpu_reg_names[10*3 + 22*4 /* GPR */
52 + 10*4 + 22*5 /* SPE GPRh */
53 + 10*4 + 22*5 /* FPR */
54 + 2*(10*6 + 22*7) /* AVRh, AVRl */
55 + 10*5 + 22*6 /* VSR */
56 + 8*5 /* CRF */];
57 static TCGv cpu_gpr[32];
58 static TCGv cpu_gprh[32];
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i64 cpu_vsr[32];
62 static TCGv_i32 cpu_crf[8];
63 static TCGv cpu_nip;
64 static TCGv cpu_msr;
65 static TCGv cpu_ctr;
66 static TCGv cpu_lr;
67 #if defined(TARGET_PPC64)
68 static TCGv cpu_cfar;
69 #endif
70 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
71 static TCGv cpu_reserve;
72 static TCGv cpu_fpscr;
73 static TCGv_i32 cpu_access_type;
74
75 #include "exec/gen-icount.h"
76
77 void ppc_translate_init(void)
78 {
79 int i;
80 char* p;
81 size_t cpu_reg_names_size;
82 static int done_init = 0;
83
84 if (done_init)
85 return;
86
87 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
88
89 p = cpu_reg_names;
90 cpu_reg_names_size = sizeof(cpu_reg_names);
91
92 for (i = 0; i < 8; i++) {
93 snprintf(p, cpu_reg_names_size, "crf%d", i);
94 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
95 offsetof(CPUPPCState, crf[i]), p);
96 p += 5;
97 cpu_reg_names_size -= 5;
98 }
99
100 for (i = 0; i < 32; i++) {
101 snprintf(p, cpu_reg_names_size, "r%d", i);
102 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
103 offsetof(CPUPPCState, gpr[i]), p);
104 p += (i < 10) ? 3 : 4;
105 cpu_reg_names_size -= (i < 10) ? 3 : 4;
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111
112 snprintf(p, cpu_reg_names_size, "fp%d", i);
113 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
114 offsetof(CPUPPCState, fpr[i]), p);
115 p += (i < 10) ? 4 : 5;
116 cpu_reg_names_size -= (i < 10) ? 4 : 5;
117
118 snprintf(p, cpu_reg_names_size, "avr%dH", i);
119 #ifdef HOST_WORDS_BIGENDIAN
120 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
121 offsetof(CPUPPCState, avr[i].u64[0]), p);
122 #else
123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
124 offsetof(CPUPPCState, avr[i].u64[1]), p);
125 #endif
126 p += (i < 10) ? 6 : 7;
127 cpu_reg_names_size -= (i < 10) ? 6 : 7;
128
129 snprintf(p, cpu_reg_names_size, "avr%dL", i);
130 #ifdef HOST_WORDS_BIGENDIAN
131 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
132 offsetof(CPUPPCState, avr[i].u64[1]), p);
133 #else
134 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
135 offsetof(CPUPPCState, avr[i].u64[0]), p);
136 #endif
137 p += (i < 10) ? 6 : 7;
138 cpu_reg_names_size -= (i < 10) ? 6 : 7;
139 snprintf(p, cpu_reg_names_size, "vsr%d", i);
140 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
141 offsetof(CPUPPCState, vsr[i]), p);
142 p += (i < 10) ? 5 : 6;
143 cpu_reg_names_size -= (i < 10) ? 5 : 6;
144 }
145
146 cpu_nip = tcg_global_mem_new(TCG_AREG0,
147 offsetof(CPUPPCState, nip), "nip");
148
149 cpu_msr = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUPPCState, msr), "msr");
151
152 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
153 offsetof(CPUPPCState, ctr), "ctr");
154
155 cpu_lr = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, lr), "lr");
157
158 #if defined(TARGET_PPC64)
159 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, cfar), "cfar");
161 #endif
162
163 cpu_xer = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, xer), "xer");
165 cpu_so = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, so), "SO");
167 cpu_ov = tcg_global_mem_new(TCG_AREG0,
168 offsetof(CPUPPCState, ov), "OV");
169 cpu_ca = tcg_global_mem_new(TCG_AREG0,
170 offsetof(CPUPPCState, ca), "CA");
171
172 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, reserve_addr),
174 "reserve_addr");
175
176 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
177 offsetof(CPUPPCState, fpscr), "fpscr");
178
179 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
180 offsetof(CPUPPCState, access_type), "access_type");
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196 TCGMemOp default_tcg_memop_mask;
197 #if defined(TARGET_PPC64)
198 int sf_mode;
199 int has_cfar;
200 #endif
201 int fpu_enabled;
202 int altivec_enabled;
203 int vsx_enabled;
204 int spe_enabled;
205 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
206 int singlestep_enabled;
207 uint64_t insns_flags;
208 uint64_t insns_flags2;
209 } DisasContext;
210
211 /* Return true iff byteswap is needed in a scalar memop */
212 static inline bool need_byteswap(const DisasContext *ctx)
213 {
214 #if defined(TARGET_WORDS_BIGENDIAN)
215 return ctx->le_mode;
216 #else
217 return !ctx->le_mode;
218 #endif
219 }
220
221 /* True when active word size < size of target_long. */
222 #ifdef TARGET_PPC64
223 # define NARROW_MODE(C) (!(C)->sf_mode)
224 #else
225 # define NARROW_MODE(C) 0
226 #endif
227
228 struct opc_handler_t {
229 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
230 uint32_t inval1;
231 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
232 uint32_t inval2;
233 /* instruction type */
234 uint64_t type;
235 /* extended instruction type */
236 uint64_t type2;
237 /* handler */
238 void (*handler)(DisasContext *ctx);
239 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
240 const char *oname;
241 #endif
242 #if defined(DO_PPC_STATISTICS)
243 uint64_t count;
244 #endif
245 };
246
247 static inline void gen_reset_fpstatus(void)
248 {
249 gen_helper_reset_fpstatus(cpu_env);
250 }
251
252 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
253 {
254 TCGv_i32 t0 = tcg_temp_new_i32();
255
256 if (set_fprf != 0) {
257 /* This case might be optimized later */
258 tcg_gen_movi_i32(t0, 1);
259 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
260 if (unlikely(set_rc)) {
261 tcg_gen_mov_i32(cpu_crf[1], t0);
262 }
263 gen_helper_float_check_status(cpu_env);
264 } else if (unlikely(set_rc)) {
265 /* We always need to compute fpcc */
266 tcg_gen_movi_i32(t0, 0);
267 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
268 tcg_gen_mov_i32(cpu_crf[1], t0);
269 }
270
271 tcg_temp_free_i32(t0);
272 }
273
274 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
275 {
276 if (ctx->access_type != access_type) {
277 tcg_gen_movi_i32(cpu_access_type, access_type);
278 ctx->access_type = access_type;
279 }
280 }
281
282 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
283 {
284 if (NARROW_MODE(ctx)) {
285 nip = (uint32_t)nip;
286 }
287 tcg_gen_movi_tl(cpu_nip, nip);
288 }
289
290 void gen_update_current_nip(void *opaque)
291 {
292 DisasContext *ctx = opaque;
293
294 tcg_gen_movi_tl(cpu_nip, ctx->nip);
295 }
296
297 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
298 {
299 TCGv_i32 t0, t1;
300 if (ctx->exception == POWERPC_EXCP_NONE) {
301 gen_update_nip(ctx, ctx->nip);
302 }
303 t0 = tcg_const_i32(excp);
304 t1 = tcg_const_i32(error);
305 gen_helper_raise_exception_err(cpu_env, t0, t1);
306 tcg_temp_free_i32(t0);
307 tcg_temp_free_i32(t1);
308 ctx->exception = (excp);
309 }
310
311 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
312 {
313 TCGv_i32 t0;
314 if (ctx->exception == POWERPC_EXCP_NONE) {
315 gen_update_nip(ctx, ctx->nip);
316 }
317 t0 = tcg_const_i32(excp);
318 gen_helper_raise_exception(cpu_env, t0);
319 tcg_temp_free_i32(t0);
320 ctx->exception = (excp);
321 }
322
323 static inline void gen_debug_exception(DisasContext *ctx)
324 {
325 TCGv_i32 t0;
326
327 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
328 (ctx->exception != POWERPC_EXCP_SYNC)) {
329 gen_update_nip(ctx, ctx->nip);
330 }
331 t0 = tcg_const_i32(EXCP_DEBUG);
332 gen_helper_raise_exception(cpu_env, t0);
333 tcg_temp_free_i32(t0);
334 }
335
336 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
337 {
338 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
339 }
340
341 /* Stop translation */
342 static inline void gen_stop_exception(DisasContext *ctx)
343 {
344 gen_update_nip(ctx, ctx->nip);
345 ctx->exception = POWERPC_EXCP_STOP;
346 }
347
348 /* No need to update nip here, as execution flow will change */
349 static inline void gen_sync_exception(DisasContext *ctx)
350 {
351 ctx->exception = POWERPC_EXCP_SYNC;
352 }
353
354 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
355 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
356
357 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
358 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
359
360 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
361 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
362
363 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
364 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
365
366 typedef struct opcode_t {
367 unsigned char opc1, opc2, opc3;
368 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
369 unsigned char pad[5];
370 #else
371 unsigned char pad[1];
372 #endif
373 opc_handler_t handler;
374 const char *oname;
375 } opcode_t;
376
377 /*****************************************************************************/
378 /*** Instruction decoding ***/
379 #define EXTRACT_HELPER(name, shift, nb) \
380 static inline uint32_t name(uint32_t opcode) \
381 { \
382 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
383 }
384
385 #define EXTRACT_SHELPER(name, shift, nb) \
386 static inline int32_t name(uint32_t opcode) \
387 { \
388 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
389 }
390
391 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
392 static inline uint32_t name(uint32_t opcode) \
393 { \
394 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
395 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
396 }
397 /* Opcode part 1 */
398 EXTRACT_HELPER(opc1, 26, 6);
399 /* Opcode part 2 */
400 EXTRACT_HELPER(opc2, 1, 5);
401 /* Opcode part 3 */
402 EXTRACT_HELPER(opc3, 6, 5);
403 /* Update Cr0 flags */
404 EXTRACT_HELPER(Rc, 0, 1);
405 /* Update Cr6 flags (Altivec) */
406 EXTRACT_HELPER(Rc21, 10, 1);
407 /* Destination */
408 EXTRACT_HELPER(rD, 21, 5);
409 /* Source */
410 EXTRACT_HELPER(rS, 21, 5);
411 /* First operand */
412 EXTRACT_HELPER(rA, 16, 5);
413 /* Second operand */
414 EXTRACT_HELPER(rB, 11, 5);
415 /* Third operand */
416 EXTRACT_HELPER(rC, 6, 5);
417 /*** Get CRn ***/
418 EXTRACT_HELPER(crfD, 23, 3);
419 EXTRACT_HELPER(crfS, 18, 3);
420 EXTRACT_HELPER(crbD, 21, 5);
421 EXTRACT_HELPER(crbA, 16, 5);
422 EXTRACT_HELPER(crbB, 11, 5);
423 /* SPR / TBL */
424 EXTRACT_HELPER(_SPR, 11, 10);
425 static inline uint32_t SPR(uint32_t opcode)
426 {
427 uint32_t sprn = _SPR(opcode);
428
429 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
430 }
431 /*** Get constants ***/
432 /* 16 bits signed immediate value */
433 EXTRACT_SHELPER(SIMM, 0, 16);
434 /* 16 bits unsigned immediate value */
435 EXTRACT_HELPER(UIMM, 0, 16);
436 /* 5 bits signed immediate value */
437 EXTRACT_HELPER(SIMM5, 16, 5);
438 /* 5 bits signed immediate value */
439 EXTRACT_HELPER(UIMM5, 16, 5);
440 /* Bit count */
441 EXTRACT_HELPER(NB, 11, 5);
442 /* Shift count */
443 EXTRACT_HELPER(SH, 11, 5);
444 /* Vector shift count */
445 EXTRACT_HELPER(VSH, 6, 4);
446 /* Mask start */
447 EXTRACT_HELPER(MB, 6, 5);
448 /* Mask end */
449 EXTRACT_HELPER(ME, 1, 5);
450 /* Trap operand */
451 EXTRACT_HELPER(TO, 21, 5);
452
453 EXTRACT_HELPER(CRM, 12, 8);
454 EXTRACT_HELPER(SR, 16, 4);
455
456 /* mtfsf/mtfsfi */
457 EXTRACT_HELPER(FPBF, 23, 3);
458 EXTRACT_HELPER(FPIMM, 12, 4);
459 EXTRACT_HELPER(FPL, 25, 1);
460 EXTRACT_HELPER(FPFLM, 17, 8);
461 EXTRACT_HELPER(FPW, 16, 1);
462
463 /*** Jump target decoding ***/
464 /* Immediate address */
465 static inline target_ulong LI(uint32_t opcode)
466 {
467 return (opcode >> 0) & 0x03FFFFFC;
468 }
469
470 static inline uint32_t BD(uint32_t opcode)
471 {
472 return (opcode >> 0) & 0xFFFC;
473 }
474
475 EXTRACT_HELPER(BO, 21, 5);
476 EXTRACT_HELPER(BI, 16, 5);
477 /* Absolute/relative address */
478 EXTRACT_HELPER(AA, 1, 1);
479 /* Link */
480 EXTRACT_HELPER(LK, 0, 1);
481
482 /* DFP Z22-form */
483 EXTRACT_HELPER(DCM, 10, 6)
484
485 /* DFP Z23-form */
486 EXTRACT_HELPER(RMC, 9, 2)
487
488 /* Create a mask between <start> and <end> bits */
489 static inline target_ulong MASK(uint32_t start, uint32_t end)
490 {
491 target_ulong ret;
492
493 #if defined(TARGET_PPC64)
494 if (likely(start == 0)) {
495 ret = UINT64_MAX << (63 - end);
496 } else if (likely(end == 63)) {
497 ret = UINT64_MAX >> start;
498 }
499 #else
500 if (likely(start == 0)) {
501 ret = UINT32_MAX << (31 - end);
502 } else if (likely(end == 31)) {
503 ret = UINT32_MAX >> start;
504 }
505 #endif
506 else {
507 ret = (((target_ulong)(-1ULL)) >> (start)) ^
508 (((target_ulong)(-1ULL) >> (end)) >> 1);
509 if (unlikely(start > end))
510 return ~ret;
511 }
512
513 return ret;
514 }
515
516 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
517 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
518 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
519 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
520 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
521 EXTRACT_HELPER(DM, 8, 2);
522 EXTRACT_HELPER(UIM, 16, 2);
523 EXTRACT_HELPER(SHW, 8, 2);
524 EXTRACT_HELPER(SP, 19, 2);
525 /*****************************************************************************/
526 /* PowerPC instructions table */
527
528 #if defined(DO_PPC_STATISTICS)
529 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
530 { \
531 .opc1 = op1, \
532 .opc2 = op2, \
533 .opc3 = op3, \
534 .pad = { 0, }, \
535 .handler = { \
536 .inval1 = invl, \
537 .type = _typ, \
538 .type2 = _typ2, \
539 .handler = &gen_##name, \
540 .oname = stringify(name), \
541 }, \
542 .oname = stringify(name), \
543 }
544 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
545 { \
546 .opc1 = op1, \
547 .opc2 = op2, \
548 .opc3 = op3, \
549 .pad = { 0, }, \
550 .handler = { \
551 .inval1 = invl1, \
552 .inval2 = invl2, \
553 .type = _typ, \
554 .type2 = _typ2, \
555 .handler = &gen_##name, \
556 .oname = stringify(name), \
557 }, \
558 .oname = stringify(name), \
559 }
560 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
561 { \
562 .opc1 = op1, \
563 .opc2 = op2, \
564 .opc3 = op3, \
565 .pad = { 0, }, \
566 .handler = { \
567 .inval1 = invl, \
568 .type = _typ, \
569 .type2 = _typ2, \
570 .handler = &gen_##name, \
571 .oname = onam, \
572 }, \
573 .oname = onam, \
574 }
575 #else
576 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
577 { \
578 .opc1 = op1, \
579 .opc2 = op2, \
580 .opc3 = op3, \
581 .pad = { 0, }, \
582 .handler = { \
583 .inval1 = invl, \
584 .type = _typ, \
585 .type2 = _typ2, \
586 .handler = &gen_##name, \
587 }, \
588 .oname = stringify(name), \
589 }
590 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
591 { \
592 .opc1 = op1, \
593 .opc2 = op2, \
594 .opc3 = op3, \
595 .pad = { 0, }, \
596 .handler = { \
597 .inval1 = invl1, \
598 .inval2 = invl2, \
599 .type = _typ, \
600 .type2 = _typ2, \
601 .handler = &gen_##name, \
602 }, \
603 .oname = stringify(name), \
604 }
605 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
606 { \
607 .opc1 = op1, \
608 .opc2 = op2, \
609 .opc3 = op3, \
610 .pad = { 0, }, \
611 .handler = { \
612 .inval1 = invl, \
613 .type = _typ, \
614 .type2 = _typ2, \
615 .handler = &gen_##name, \
616 }, \
617 .oname = onam, \
618 }
619 #endif
620
621 /* SPR load/store helpers */
622 static inline void gen_load_spr(TCGv t, int reg)
623 {
624 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
625 }
626
627 static inline void gen_store_spr(int reg, TCGv t)
628 {
629 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
630 }
631
632 /* Invalid instruction */
633 static void gen_invalid(DisasContext *ctx)
634 {
635 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
636 }
637
638 static opc_handler_t invalid_handler = {
639 .inval1 = 0xFFFFFFFF,
640 .inval2 = 0xFFFFFFFF,
641 .type = PPC_NONE,
642 .type2 = PPC_NONE,
643 .handler = gen_invalid,
644 };
645
646 #if defined(TARGET_PPC64)
647 /* NOTE: as this time, the only use of is_user_mode() is in 64 bit code. And */
648 /* so the function is wrapped in the standard 64-bit ifdef in order to */
649 /* avoid compiler warnings in 32-bit implementations. */
650 static bool is_user_mode(DisasContext *ctx)
651 {
652 #if defined(CONFIG_USER_ONLY)
653 return true;
654 #else
655 return ctx->mem_idx == 0;
656 #endif
657 }
658 #endif
659
660 /*** Integer comparison ***/
661
662 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
663 {
664 TCGv t0 = tcg_temp_new();
665 TCGv_i32 t1 = tcg_temp_new_i32();
666
667 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
668
669 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
670 tcg_gen_trunc_tl_i32(t1, t0);
671 tcg_gen_shli_i32(t1, t1, CRF_LT);
672 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
673
674 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
675 tcg_gen_trunc_tl_i32(t1, t0);
676 tcg_gen_shli_i32(t1, t1, CRF_GT);
677 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
678
679 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
680 tcg_gen_trunc_tl_i32(t1, t0);
681 tcg_gen_shli_i32(t1, t1, CRF_EQ);
682 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
683
684 tcg_temp_free(t0);
685 tcg_temp_free_i32(t1);
686 }
687
688 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
689 {
690 TCGv t0 = tcg_const_tl(arg1);
691 gen_op_cmp(arg0, t0, s, crf);
692 tcg_temp_free(t0);
693 }
694
695 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
696 {
697 TCGv t0, t1;
698 t0 = tcg_temp_new();
699 t1 = tcg_temp_new();
700 if (s) {
701 tcg_gen_ext32s_tl(t0, arg0);
702 tcg_gen_ext32s_tl(t1, arg1);
703 } else {
704 tcg_gen_ext32u_tl(t0, arg0);
705 tcg_gen_ext32u_tl(t1, arg1);
706 }
707 gen_op_cmp(t0, t1, s, crf);
708 tcg_temp_free(t1);
709 tcg_temp_free(t0);
710 }
711
712 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
713 {
714 TCGv t0 = tcg_const_tl(arg1);
715 gen_op_cmp32(arg0, t0, s, crf);
716 tcg_temp_free(t0);
717 }
718
719 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
720 {
721 if (NARROW_MODE(ctx)) {
722 gen_op_cmpi32(reg, 0, 1, 0);
723 } else {
724 gen_op_cmpi(reg, 0, 1, 0);
725 }
726 }
727
728 /* cmp */
729 static void gen_cmp(DisasContext *ctx)
730 {
731 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
732 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
733 1, crfD(ctx->opcode));
734 } else {
735 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
736 1, crfD(ctx->opcode));
737 }
738 }
739
740 /* cmpi */
741 static void gen_cmpi(DisasContext *ctx)
742 {
743 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
744 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
745 1, crfD(ctx->opcode));
746 } else {
747 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
748 1, crfD(ctx->opcode));
749 }
750 }
751
752 /* cmpl */
753 static void gen_cmpl(DisasContext *ctx)
754 {
755 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
756 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
757 0, crfD(ctx->opcode));
758 } else {
759 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
760 0, crfD(ctx->opcode));
761 }
762 }
763
764 /* cmpli */
765 static void gen_cmpli(DisasContext *ctx)
766 {
767 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
768 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
769 0, crfD(ctx->opcode));
770 } else {
771 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
772 0, crfD(ctx->opcode));
773 }
774 }
775
776 /* isel (PowerPC 2.03 specification) */
777 static void gen_isel(DisasContext *ctx)
778 {
779 int l1, l2;
780 uint32_t bi = rC(ctx->opcode);
781 uint32_t mask;
782 TCGv_i32 t0;
783
784 l1 = gen_new_label();
785 l2 = gen_new_label();
786
787 mask = 1 << (3 - (bi & 0x03));
788 t0 = tcg_temp_new_i32();
789 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
790 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
791 if (rA(ctx->opcode) == 0)
792 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
793 else
794 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
795 tcg_gen_br(l2);
796 gen_set_label(l1);
797 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
798 gen_set_label(l2);
799 tcg_temp_free_i32(t0);
800 }
801
802 /* cmpb: PowerPC 2.05 specification */
803 static void gen_cmpb(DisasContext *ctx)
804 {
805 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
806 cpu_gpr[rB(ctx->opcode)]);
807 }
808
809 /*** Integer arithmetic ***/
810
811 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
812 TCGv arg1, TCGv arg2, int sub)
813 {
814 TCGv t0 = tcg_temp_new();
815
816 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
817 tcg_gen_xor_tl(t0, arg1, arg2);
818 if (sub) {
819 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
820 } else {
821 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
822 }
823 tcg_temp_free(t0);
824 if (NARROW_MODE(ctx)) {
825 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
826 }
827 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
828 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
829 }
830
831 /* Common add function */
832 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
833 TCGv arg2, bool add_ca, bool compute_ca,
834 bool compute_ov, bool compute_rc0)
835 {
836 TCGv t0 = ret;
837
838 if (compute_ca || compute_ov) {
839 t0 = tcg_temp_new();
840 }
841
842 if (compute_ca) {
843 if (NARROW_MODE(ctx)) {
844 /* Caution: a non-obvious corner case of the spec is that we
845 must produce the *entire* 64-bit addition, but produce the
846 carry into bit 32. */
847 TCGv t1 = tcg_temp_new();
848 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
849 tcg_gen_add_tl(t0, arg1, arg2);
850 if (add_ca) {
851 tcg_gen_add_tl(t0, t0, cpu_ca);
852 }
853 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
854 tcg_temp_free(t1);
855 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
856 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
857 } else {
858 TCGv zero = tcg_const_tl(0);
859 if (add_ca) {
860 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
861 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
862 } else {
863 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
864 }
865 tcg_temp_free(zero);
866 }
867 } else {
868 tcg_gen_add_tl(t0, arg1, arg2);
869 if (add_ca) {
870 tcg_gen_add_tl(t0, t0, cpu_ca);
871 }
872 }
873
874 if (compute_ov) {
875 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
876 }
877 if (unlikely(compute_rc0)) {
878 gen_set_Rc0(ctx, t0);
879 }
880
881 if (!TCGV_EQUAL(t0, ret)) {
882 tcg_gen_mov_tl(ret, t0);
883 tcg_temp_free(t0);
884 }
885 }
886 /* Add functions with two operands */
887 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
888 static void glue(gen_, name)(DisasContext *ctx) \
889 { \
890 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
891 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
892 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
893 }
894 /* Add functions with one operand and one immediate */
895 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
896 add_ca, compute_ca, compute_ov) \
897 static void glue(gen_, name)(DisasContext *ctx) \
898 { \
899 TCGv t0 = tcg_const_tl(const_val); \
900 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
901 cpu_gpr[rA(ctx->opcode)], t0, \
902 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
903 tcg_temp_free(t0); \
904 }
905
906 /* add add. addo addo. */
907 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
908 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
909 /* addc addc. addco addco. */
910 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
911 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
912 /* adde adde. addeo addeo. */
913 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
914 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
915 /* addme addme. addmeo addmeo. */
916 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
917 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
918 /* addze addze. addzeo addzeo.*/
919 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
920 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
921 /* addi */
922 static void gen_addi(DisasContext *ctx)
923 {
924 target_long simm = SIMM(ctx->opcode);
925
926 if (rA(ctx->opcode) == 0) {
927 /* li case */
928 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
929 } else {
930 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
931 cpu_gpr[rA(ctx->opcode)], simm);
932 }
933 }
934 /* addic addic.*/
935 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
936 {
937 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
938 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
939 c, 0, 1, 0, compute_rc0);
940 tcg_temp_free(c);
941 }
942
943 static void gen_addic(DisasContext *ctx)
944 {
945 gen_op_addic(ctx, 0);
946 }
947
948 static void gen_addic_(DisasContext *ctx)
949 {
950 gen_op_addic(ctx, 1);
951 }
952
953 /* addis */
954 static void gen_addis(DisasContext *ctx)
955 {
956 target_long simm = SIMM(ctx->opcode);
957
958 if (rA(ctx->opcode) == 0) {
959 /* lis case */
960 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
961 } else {
962 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
963 cpu_gpr[rA(ctx->opcode)], simm << 16);
964 }
965 }
966
967 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
968 TCGv arg2, int sign, int compute_ov)
969 {
970 int l1 = gen_new_label();
971 int l2 = gen_new_label();
972 TCGv_i32 t0 = tcg_temp_local_new_i32();
973 TCGv_i32 t1 = tcg_temp_local_new_i32();
974
975 tcg_gen_trunc_tl_i32(t0, arg1);
976 tcg_gen_trunc_tl_i32(t1, arg2);
977 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
978 if (sign) {
979 int l3 = gen_new_label();
980 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
981 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
982 gen_set_label(l3);
983 tcg_gen_div_i32(t0, t0, t1);
984 } else {
985 tcg_gen_divu_i32(t0, t0, t1);
986 }
987 if (compute_ov) {
988 tcg_gen_movi_tl(cpu_ov, 0);
989 }
990 tcg_gen_br(l2);
991 gen_set_label(l1);
992 if (sign) {
993 tcg_gen_sari_i32(t0, t0, 31);
994 } else {
995 tcg_gen_movi_i32(t0, 0);
996 }
997 if (compute_ov) {
998 tcg_gen_movi_tl(cpu_ov, 1);
999 tcg_gen_movi_tl(cpu_so, 1);
1000 }
1001 gen_set_label(l2);
1002 tcg_gen_extu_i32_tl(ret, t0);
1003 tcg_temp_free_i32(t0);
1004 tcg_temp_free_i32(t1);
1005 if (unlikely(Rc(ctx->opcode) != 0))
1006 gen_set_Rc0(ctx, ret);
1007 }
1008 /* Div functions */
1009 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1010 static void glue(gen_, name)(DisasContext *ctx) \
1011 { \
1012 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1013 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1014 sign, compute_ov); \
1015 }
1016 /* divwu divwu. divwuo divwuo. */
1017 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1018 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1019 /* divw divw. divwo divwo. */
1020 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1021 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1022
1023 /* div[wd]eu[o][.] */
1024 #define GEN_DIVE(name, hlpr, compute_ov) \
1025 static void gen_##name(DisasContext *ctx) \
1026 { \
1027 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1028 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1029 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1030 tcg_temp_free_i32(t0); \
1031 if (unlikely(Rc(ctx->opcode) != 0)) { \
1032 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1033 } \
1034 }
1035
1036 GEN_DIVE(divweu, divweu, 0);
1037 GEN_DIVE(divweuo, divweu, 1);
1038 GEN_DIVE(divwe, divwe, 0);
1039 GEN_DIVE(divweo, divwe, 1);
1040
1041 #if defined(TARGET_PPC64)
1042 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1043 TCGv arg2, int sign, int compute_ov)
1044 {
1045 int l1 = gen_new_label();
1046 int l2 = gen_new_label();
1047
1048 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1049 if (sign) {
1050 int l3 = gen_new_label();
1051 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1052 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1053 gen_set_label(l3);
1054 tcg_gen_div_i64(ret, arg1, arg2);
1055 } else {
1056 tcg_gen_divu_i64(ret, arg1, arg2);
1057 }
1058 if (compute_ov) {
1059 tcg_gen_movi_tl(cpu_ov, 0);
1060 }
1061 tcg_gen_br(l2);
1062 gen_set_label(l1);
1063 if (sign) {
1064 tcg_gen_sari_i64(ret, arg1, 63);
1065 } else {
1066 tcg_gen_movi_i64(ret, 0);
1067 }
1068 if (compute_ov) {
1069 tcg_gen_movi_tl(cpu_ov, 1);
1070 tcg_gen_movi_tl(cpu_so, 1);
1071 }
1072 gen_set_label(l2);
1073 if (unlikely(Rc(ctx->opcode) != 0))
1074 gen_set_Rc0(ctx, ret);
1075 }
1076 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1077 static void glue(gen_, name)(DisasContext *ctx) \
1078 { \
1079 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1080 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1081 sign, compute_ov); \
1082 }
1083 /* divwu divwu. divwuo divwuo. */
1084 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1085 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1086 /* divw divw. divwo divwo. */
1087 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1088 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1089
1090 GEN_DIVE(divdeu, divdeu, 0);
1091 GEN_DIVE(divdeuo, divdeu, 1);
1092 GEN_DIVE(divde, divde, 0);
1093 GEN_DIVE(divdeo, divde, 1);
1094 #endif
1095
1096 /* mulhw mulhw. */
1097 static void gen_mulhw(DisasContext *ctx)
1098 {
1099 TCGv_i32 t0 = tcg_temp_new_i32();
1100 TCGv_i32 t1 = tcg_temp_new_i32();
1101
1102 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1103 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1104 tcg_gen_muls2_i32(t0, t1, t0, t1);
1105 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1106 tcg_temp_free_i32(t0);
1107 tcg_temp_free_i32(t1);
1108 if (unlikely(Rc(ctx->opcode) != 0))
1109 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1110 }
1111
1112 /* mulhwu mulhwu. */
1113 static void gen_mulhwu(DisasContext *ctx)
1114 {
1115 TCGv_i32 t0 = tcg_temp_new_i32();
1116 TCGv_i32 t1 = tcg_temp_new_i32();
1117
1118 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1119 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1120 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1121 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1122 tcg_temp_free_i32(t0);
1123 tcg_temp_free_i32(t1);
1124 if (unlikely(Rc(ctx->opcode) != 0))
1125 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1126 }
1127
1128 /* mullw mullw. */
1129 static void gen_mullw(DisasContext *ctx)
1130 {
1131 #if defined(TARGET_PPC64)
1132 TCGv_i64 t0, t1;
1133 t0 = tcg_temp_new_i64();
1134 t1 = tcg_temp_new_i64();
1135 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1136 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1137 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1138 tcg_temp_free(t0);
1139 tcg_temp_free(t1);
1140 #else
1141 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1142 cpu_gpr[rB(ctx->opcode)]);
1143 #endif
1144 if (unlikely(Rc(ctx->opcode) != 0))
1145 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1146 }
1147
1148 /* mullwo mullwo. */
1149 static void gen_mullwo(DisasContext *ctx)
1150 {
1151 TCGv_i32 t0 = tcg_temp_new_i32();
1152 TCGv_i32 t1 = tcg_temp_new_i32();
1153
1154 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1155 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1156 tcg_gen_muls2_i32(t0, t1, t0, t1);
1157 #if defined(TARGET_PPC64)
1158 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1159 #else
1160 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1161 #endif
1162
1163 tcg_gen_sari_i32(t0, t0, 31);
1164 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1165 tcg_gen_extu_i32_tl(cpu_ov, t0);
1166 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1167
1168 tcg_temp_free_i32(t0);
1169 tcg_temp_free_i32(t1);
1170 if (unlikely(Rc(ctx->opcode) != 0))
1171 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1172 }
1173
1174 /* mulli */
1175 static void gen_mulli(DisasContext *ctx)
1176 {
1177 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1178 SIMM(ctx->opcode));
1179 }
1180
1181 #if defined(TARGET_PPC64)
1182 /* mulhd mulhd. */
1183 static void gen_mulhd(DisasContext *ctx)
1184 {
1185 TCGv lo = tcg_temp_new();
1186 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1187 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1188 tcg_temp_free(lo);
1189 if (unlikely(Rc(ctx->opcode) != 0)) {
1190 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1191 }
1192 }
1193
1194 /* mulhdu mulhdu. */
1195 static void gen_mulhdu(DisasContext *ctx)
1196 {
1197 TCGv lo = tcg_temp_new();
1198 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1199 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1200 tcg_temp_free(lo);
1201 if (unlikely(Rc(ctx->opcode) != 0)) {
1202 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1203 }
1204 }
1205
1206 /* mulld mulld. */
1207 static void gen_mulld(DisasContext *ctx)
1208 {
1209 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1210 cpu_gpr[rB(ctx->opcode)]);
1211 if (unlikely(Rc(ctx->opcode) != 0))
1212 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1213 }
1214
1215 /* mulldo mulldo. */
1216 static void gen_mulldo(DisasContext *ctx)
1217 {
1218 TCGv_i64 t0 = tcg_temp_new_i64();
1219 TCGv_i64 t1 = tcg_temp_new_i64();
1220
1221 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1222 cpu_gpr[rB(ctx->opcode)]);
1223 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1224
1225 tcg_gen_sari_i64(t0, t0, 63);
1226 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1227 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1228
1229 tcg_temp_free_i64(t0);
1230 tcg_temp_free_i64(t1);
1231
1232 if (unlikely(Rc(ctx->opcode) != 0)) {
1233 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1234 }
1235 }
1236 #endif
1237
1238 /* Common subf function */
1239 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1240 TCGv arg2, bool add_ca, bool compute_ca,
1241 bool compute_ov, bool compute_rc0)
1242 {
1243 TCGv t0 = ret;
1244
1245 if (compute_ca || compute_ov) {
1246 t0 = tcg_temp_new();
1247 }
1248
1249 if (compute_ca) {
1250 /* dest = ~arg1 + arg2 [+ ca]. */
1251 if (NARROW_MODE(ctx)) {
1252 /* Caution: a non-obvious corner case of the spec is that we
1253 must produce the *entire* 64-bit addition, but produce the
1254 carry into bit 32. */
1255 TCGv inv1 = tcg_temp_new();
1256 TCGv t1 = tcg_temp_new();
1257 tcg_gen_not_tl(inv1, arg1);
1258 if (add_ca) {
1259 tcg_gen_add_tl(t0, arg2, cpu_ca);
1260 } else {
1261 tcg_gen_addi_tl(t0, arg2, 1);
1262 }
1263 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1264 tcg_gen_add_tl(t0, t0, inv1);
1265 tcg_temp_free(inv1);
1266 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1267 tcg_temp_free(t1);
1268 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1269 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1270 } else if (add_ca) {
1271 TCGv zero, inv1 = tcg_temp_new();
1272 tcg_gen_not_tl(inv1, arg1);
1273 zero = tcg_const_tl(0);
1274 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1275 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1276 tcg_temp_free(zero);
1277 tcg_temp_free(inv1);
1278 } else {
1279 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1280 tcg_gen_sub_tl(t0, arg2, arg1);
1281 }
1282 } else if (add_ca) {
1283 /* Since we're ignoring carry-out, we can simplify the
1284 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1285 tcg_gen_sub_tl(t0, arg2, arg1);
1286 tcg_gen_add_tl(t0, t0, cpu_ca);
1287 tcg_gen_subi_tl(t0, t0, 1);
1288 } else {
1289 tcg_gen_sub_tl(t0, arg2, arg1);
1290 }
1291
1292 if (compute_ov) {
1293 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1294 }
1295 if (unlikely(compute_rc0)) {
1296 gen_set_Rc0(ctx, t0);
1297 }
1298
1299 if (!TCGV_EQUAL(t0, ret)) {
1300 tcg_gen_mov_tl(ret, t0);
1301 tcg_temp_free(t0);
1302 }
1303 }
1304 /* Sub functions with Two operands functions */
1305 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1306 static void glue(gen_, name)(DisasContext *ctx) \
1307 { \
1308 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1309 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1310 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1311 }
1312 /* Sub functions with one operand and one immediate */
1313 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1314 add_ca, compute_ca, compute_ov) \
1315 static void glue(gen_, name)(DisasContext *ctx) \
1316 { \
1317 TCGv t0 = tcg_const_tl(const_val); \
1318 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1319 cpu_gpr[rA(ctx->opcode)], t0, \
1320 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1321 tcg_temp_free(t0); \
1322 }
1323 /* subf subf. subfo subfo. */
1324 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1325 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1326 /* subfc subfc. subfco subfco. */
1327 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1328 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1329 /* subfe subfe. subfeo subfo. */
1330 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1331 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1332 /* subfme subfme. subfmeo subfmeo. */
1333 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1334 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1335 /* subfze subfze. subfzeo subfzeo.*/
1336 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1337 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1338
1339 /* subfic */
1340 static void gen_subfic(DisasContext *ctx)
1341 {
1342 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1343 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1344 c, 0, 1, 0, 0);
1345 tcg_temp_free(c);
1346 }
1347
1348 /* neg neg. nego nego. */
1349 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1350 {
1351 TCGv zero = tcg_const_tl(0);
1352 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1353 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1354 tcg_temp_free(zero);
1355 }
1356
1357 static void gen_neg(DisasContext *ctx)
1358 {
1359 gen_op_arith_neg(ctx, 0);
1360 }
1361
1362 static void gen_nego(DisasContext *ctx)
1363 {
1364 gen_op_arith_neg(ctx, 1);
1365 }
1366
1367 /*** Integer logical ***/
1368 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1369 static void glue(gen_, name)(DisasContext *ctx) \
1370 { \
1371 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1372 cpu_gpr[rB(ctx->opcode)]); \
1373 if (unlikely(Rc(ctx->opcode) != 0)) \
1374 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1375 }
1376
1377 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1378 static void glue(gen_, name)(DisasContext *ctx) \
1379 { \
1380 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1381 if (unlikely(Rc(ctx->opcode) != 0)) \
1382 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1383 }
1384
1385 /* and & and. */
1386 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1387 /* andc & andc. */
1388 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1389
1390 /* andi. */
1391 static void gen_andi_(DisasContext *ctx)
1392 {
1393 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1394 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1395 }
1396
1397 /* andis. */
1398 static void gen_andis_(DisasContext *ctx)
1399 {
1400 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1401 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1402 }
1403
1404 /* cntlzw */
1405 static void gen_cntlzw(DisasContext *ctx)
1406 {
1407 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1408 if (unlikely(Rc(ctx->opcode) != 0))
1409 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1410 }
1411 /* eqv & eqv. */
1412 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1413 /* extsb & extsb. */
1414 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1415 /* extsh & extsh. */
1416 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1417 /* nand & nand. */
1418 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1419 /* nor & nor. */
1420 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1421
1422 /* or & or. */
1423 static void gen_or(DisasContext *ctx)
1424 {
1425 int rs, ra, rb;
1426
1427 rs = rS(ctx->opcode);
1428 ra = rA(ctx->opcode);
1429 rb = rB(ctx->opcode);
1430 /* Optimisation for mr. ri case */
1431 if (rs != ra || rs != rb) {
1432 if (rs != rb)
1433 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1434 else
1435 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1436 if (unlikely(Rc(ctx->opcode) != 0))
1437 gen_set_Rc0(ctx, cpu_gpr[ra]);
1438 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1439 gen_set_Rc0(ctx, cpu_gpr[rs]);
1440 #if defined(TARGET_PPC64)
1441 } else {
1442 int prio = 0;
1443
1444 switch (rs) {
1445 case 1:
1446 /* Set process priority to low */
1447 prio = 2;
1448 break;
1449 case 6:
1450 /* Set process priority to medium-low */
1451 prio = 3;
1452 break;
1453 case 2:
1454 /* Set process priority to normal */
1455 prio = 4;
1456 break;
1457 #if !defined(CONFIG_USER_ONLY)
1458 case 31:
1459 if (ctx->mem_idx > 0) {
1460 /* Set process priority to very low */
1461 prio = 1;
1462 }
1463 break;
1464 case 5:
1465 if (ctx->mem_idx > 0) {
1466 /* Set process priority to medium-hight */
1467 prio = 5;
1468 }
1469 break;
1470 case 3:
1471 if (ctx->mem_idx > 0) {
1472 /* Set process priority to high */
1473 prio = 6;
1474 }
1475 break;
1476 case 7:
1477 if (ctx->mem_idx > 1) {
1478 /* Set process priority to very high */
1479 prio = 7;
1480 }
1481 break;
1482 #endif
1483 default:
1484 /* nop */
1485 break;
1486 }
1487 if (prio) {
1488 TCGv t0 = tcg_temp_new();
1489 gen_load_spr(t0, SPR_PPR);
1490 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1491 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1492 gen_store_spr(SPR_PPR, t0);
1493 tcg_temp_free(t0);
1494 }
1495 #endif
1496 }
1497 }
1498 /* orc & orc. */
1499 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1500
1501 /* xor & xor. */
1502 static void gen_xor(DisasContext *ctx)
1503 {
1504 /* Optimisation for "set to zero" case */
1505 if (rS(ctx->opcode) != rB(ctx->opcode))
1506 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1507 else
1508 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1509 if (unlikely(Rc(ctx->opcode) != 0))
1510 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1511 }
1512
1513 /* ori */
1514 static void gen_ori(DisasContext *ctx)
1515 {
1516 target_ulong uimm = UIMM(ctx->opcode);
1517
1518 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1519 /* NOP */
1520 /* XXX: should handle special NOPs for POWER series */
1521 return;
1522 }
1523 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1524 }
1525
1526 /* oris */
1527 static void gen_oris(DisasContext *ctx)
1528 {
1529 target_ulong uimm = UIMM(ctx->opcode);
1530
1531 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1532 /* NOP */
1533 return;
1534 }
1535 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1536 }
1537
1538 /* xori */
1539 static void gen_xori(DisasContext *ctx)
1540 {
1541 target_ulong uimm = UIMM(ctx->opcode);
1542
1543 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1544 /* NOP */
1545 return;
1546 }
1547 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1548 }
1549
1550 /* xoris */
1551 static void gen_xoris(DisasContext *ctx)
1552 {
1553 target_ulong uimm = UIMM(ctx->opcode);
1554
1555 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1556 /* NOP */
1557 return;
1558 }
1559 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1560 }
1561
1562 /* popcntb : PowerPC 2.03 specification */
1563 static void gen_popcntb(DisasContext *ctx)
1564 {
1565 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1566 }
1567
1568 static void gen_popcntw(DisasContext *ctx)
1569 {
1570 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1571 }
1572
1573 #if defined(TARGET_PPC64)
1574 /* popcntd: PowerPC 2.06 specification */
1575 static void gen_popcntd(DisasContext *ctx)
1576 {
1577 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1578 }
1579 #endif
1580
1581 /* prtyw: PowerPC 2.05 specification */
1582 static void gen_prtyw(DisasContext *ctx)
1583 {
1584 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1585 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1586 TCGv t0 = tcg_temp_new();
1587 tcg_gen_shri_tl(t0, rs, 16);
1588 tcg_gen_xor_tl(ra, rs, t0);
1589 tcg_gen_shri_tl(t0, ra, 8);
1590 tcg_gen_xor_tl(ra, ra, t0);
1591 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1592 tcg_temp_free(t0);
1593 }
1594
1595 #if defined(TARGET_PPC64)
1596 /* prtyd: PowerPC 2.05 specification */
1597 static void gen_prtyd(DisasContext *ctx)
1598 {
1599 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1600 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1601 TCGv t0 = tcg_temp_new();
1602 tcg_gen_shri_tl(t0, rs, 32);
1603 tcg_gen_xor_tl(ra, rs, t0);
1604 tcg_gen_shri_tl(t0, ra, 16);
1605 tcg_gen_xor_tl(ra, ra, t0);
1606 tcg_gen_shri_tl(t0, ra, 8);
1607 tcg_gen_xor_tl(ra, ra, t0);
1608 tcg_gen_andi_tl(ra, ra, 1);
1609 tcg_temp_free(t0);
1610 }
1611 #endif
1612
1613 #if defined(TARGET_PPC64)
1614 /* bpermd */
1615 static void gen_bpermd(DisasContext *ctx)
1616 {
1617 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1618 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1619 }
1620 #endif
1621
1622 #if defined(TARGET_PPC64)
1623 /* extsw & extsw. */
1624 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1625
1626 /* cntlzd */
1627 static void gen_cntlzd(DisasContext *ctx)
1628 {
1629 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1630 if (unlikely(Rc(ctx->opcode) != 0))
1631 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1632 }
1633 #endif
1634
1635 /*** Integer rotate ***/
1636
1637 /* rlwimi & rlwimi. */
1638 static void gen_rlwimi(DisasContext *ctx)
1639 {
1640 uint32_t mb, me, sh;
1641
1642 mb = MB(ctx->opcode);
1643 me = ME(ctx->opcode);
1644 sh = SH(ctx->opcode);
1645 if (likely(sh == (31-me) && mb <= me)) {
1646 tcg_gen_deposit_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1647 cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1);
1648 } else {
1649 target_ulong mask;
1650 TCGv t1;
1651 TCGv t0 = tcg_temp_new();
1652 #if defined(TARGET_PPC64)
1653 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1654 cpu_gpr[rS(ctx->opcode)], 32, 32);
1655 tcg_gen_rotli_i64(t0, t0, sh);
1656 #else
1657 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1658 #endif
1659 #if defined(TARGET_PPC64)
1660 mb += 32;
1661 me += 32;
1662 #endif
1663 mask = MASK(mb, me);
1664 t1 = tcg_temp_new();
1665 tcg_gen_andi_tl(t0, t0, mask);
1666 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1667 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1668 tcg_temp_free(t0);
1669 tcg_temp_free(t1);
1670 }
1671 if (unlikely(Rc(ctx->opcode) != 0))
1672 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1673 }
1674
1675 /* rlwinm & rlwinm. */
1676 static void gen_rlwinm(DisasContext *ctx)
1677 {
1678 uint32_t mb, me, sh;
1679
1680 sh = SH(ctx->opcode);
1681 mb = MB(ctx->opcode);
1682 me = ME(ctx->opcode);
1683
1684 if (likely(mb == 0 && me == (31 - sh))) {
1685 if (likely(sh == 0)) {
1686 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1687 } else {
1688 TCGv t0 = tcg_temp_new();
1689 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1690 tcg_gen_shli_tl(t0, t0, sh);
1691 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1692 tcg_temp_free(t0);
1693 }
1694 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1695 TCGv t0 = tcg_temp_new();
1696 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1697 tcg_gen_shri_tl(t0, t0, mb);
1698 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1699 tcg_temp_free(t0);
1700 } else if (likely(mb == 0 && me == 31)) {
1701 TCGv_i32 t0 = tcg_temp_new_i32();
1702 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rS(ctx->opcode)]);
1703 tcg_gen_rotli_i32(t0, t0, sh);
1704 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t0);
1705 tcg_temp_free_i32(t0);
1706 } else {
1707 TCGv t0 = tcg_temp_new();
1708 #if defined(TARGET_PPC64)
1709 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1710 cpu_gpr[rS(ctx->opcode)], 32, 32);
1711 tcg_gen_rotli_i64(t0, t0, sh);
1712 #else
1713 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1714 #endif
1715 #if defined(TARGET_PPC64)
1716 mb += 32;
1717 me += 32;
1718 #endif
1719 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1720 tcg_temp_free(t0);
1721 }
1722 if (unlikely(Rc(ctx->opcode) != 0))
1723 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1724 }
1725
1726 /* rlwnm & rlwnm. */
1727 static void gen_rlwnm(DisasContext *ctx)
1728 {
1729 uint32_t mb, me;
1730 mb = MB(ctx->opcode);
1731 me = ME(ctx->opcode);
1732
1733 if (likely(mb == 0 && me == 31)) {
1734 TCGv_i32 t0, t1;
1735 t0 = tcg_temp_new_i32();
1736 t1 = tcg_temp_new_i32();
1737 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]);
1738 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1739 tcg_gen_andi_i32(t0, t0, 0x1f);
1740 tcg_gen_rotl_i32(t1, t1, t0);
1741 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t1);
1742 tcg_temp_free_i32(t0);
1743 tcg_temp_free_i32(t1);
1744 } else {
1745 TCGv t0;
1746 #if defined(TARGET_PPC64)
1747 TCGv t1;
1748 #endif
1749
1750 t0 = tcg_temp_new();
1751 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1752 #if defined(TARGET_PPC64)
1753 t1 = tcg_temp_new_i64();
1754 tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
1755 cpu_gpr[rS(ctx->opcode)], 32, 32);
1756 tcg_gen_rotl_i64(t0, t1, t0);
1757 tcg_temp_free_i64(t1);
1758 #else
1759 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1760 #endif
1761 if (unlikely(mb != 0 || me != 31)) {
1762 #if defined(TARGET_PPC64)
1763 mb += 32;
1764 me += 32;
1765 #endif
1766 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1767 } else {
1768 tcg_gen_andi_tl(t0, t0, MASK(32, 63));
1769 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1770 }
1771 tcg_temp_free(t0);
1772 }
1773 if (unlikely(Rc(ctx->opcode) != 0))
1774 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1775 }
1776
1777 #if defined(TARGET_PPC64)
1778 #define GEN_PPC64_R2(name, opc1, opc2) \
1779 static void glue(gen_, name##0)(DisasContext *ctx) \
1780 { \
1781 gen_##name(ctx, 0); \
1782 } \
1783 \
1784 static void glue(gen_, name##1)(DisasContext *ctx) \
1785 { \
1786 gen_##name(ctx, 1); \
1787 }
1788 #define GEN_PPC64_R4(name, opc1, opc2) \
1789 static void glue(gen_, name##0)(DisasContext *ctx) \
1790 { \
1791 gen_##name(ctx, 0, 0); \
1792 } \
1793 \
1794 static void glue(gen_, name##1)(DisasContext *ctx) \
1795 { \
1796 gen_##name(ctx, 0, 1); \
1797 } \
1798 \
1799 static void glue(gen_, name##2)(DisasContext *ctx) \
1800 { \
1801 gen_##name(ctx, 1, 0); \
1802 } \
1803 \
1804 static void glue(gen_, name##3)(DisasContext *ctx) \
1805 { \
1806 gen_##name(ctx, 1, 1); \
1807 }
1808
1809 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1810 uint32_t sh)
1811 {
1812 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1813 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1814 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1815 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1816 } else {
1817 TCGv t0 = tcg_temp_new();
1818 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1819 if (likely(mb == 0 && me == 63)) {
1820 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1821 } else {
1822 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1823 }
1824 tcg_temp_free(t0);
1825 }
1826 if (unlikely(Rc(ctx->opcode) != 0))
1827 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1828 }
1829 /* rldicl - rldicl. */
1830 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1831 {
1832 uint32_t sh, mb;
1833
1834 sh = SH(ctx->opcode) | (shn << 5);
1835 mb = MB(ctx->opcode) | (mbn << 5);
1836 gen_rldinm(ctx, mb, 63, sh);
1837 }
1838 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1839 /* rldicr - rldicr. */
1840 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1841 {
1842 uint32_t sh, me;
1843
1844 sh = SH(ctx->opcode) | (shn << 5);
1845 me = MB(ctx->opcode) | (men << 5);
1846 gen_rldinm(ctx, 0, me, sh);
1847 }
1848 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1849 /* rldic - rldic. */
1850 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1851 {
1852 uint32_t sh, mb;
1853
1854 sh = SH(ctx->opcode) | (shn << 5);
1855 mb = MB(ctx->opcode) | (mbn << 5);
1856 gen_rldinm(ctx, mb, 63 - sh, sh);
1857 }
1858 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1859
1860 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1861 {
1862 TCGv t0;
1863
1864 t0 = tcg_temp_new();
1865 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1866 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1867 if (unlikely(mb != 0 || me != 63)) {
1868 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1869 } else {
1870 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1871 }
1872 tcg_temp_free(t0);
1873 if (unlikely(Rc(ctx->opcode) != 0))
1874 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1875 }
1876
1877 /* rldcl - rldcl. */
1878 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1879 {
1880 uint32_t mb;
1881
1882 mb = MB(ctx->opcode) | (mbn << 5);
1883 gen_rldnm(ctx, mb, 63);
1884 }
1885 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1886 /* rldcr - rldcr. */
1887 static inline void gen_rldcr(DisasContext *ctx, int men)
1888 {
1889 uint32_t me;
1890
1891 me = MB(ctx->opcode) | (men << 5);
1892 gen_rldnm(ctx, 0, me);
1893 }
1894 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1895 /* rldimi - rldimi. */
1896 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1897 {
1898 uint32_t sh, mb, me;
1899
1900 sh = SH(ctx->opcode) | (shn << 5);
1901 mb = MB(ctx->opcode) | (mbn << 5);
1902 me = 63 - sh;
1903 if (unlikely(sh == 0 && mb == 0)) {
1904 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1905 } else {
1906 TCGv t0, t1;
1907 target_ulong mask;
1908
1909 t0 = tcg_temp_new();
1910 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1911 t1 = tcg_temp_new();
1912 mask = MASK(mb, me);
1913 tcg_gen_andi_tl(t0, t0, mask);
1914 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1915 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1916 tcg_temp_free(t0);
1917 tcg_temp_free(t1);
1918 }
1919 if (unlikely(Rc(ctx->opcode) != 0))
1920 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1921 }
1922 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1923 #endif
1924
1925 /*** Integer shift ***/
1926
1927 /* slw & slw. */
1928 static void gen_slw(DisasContext *ctx)
1929 {
1930 TCGv t0, t1;
1931
1932 t0 = tcg_temp_new();
1933 /* AND rS with a mask that is 0 when rB >= 0x20 */
1934 #if defined(TARGET_PPC64)
1935 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1936 tcg_gen_sari_tl(t0, t0, 0x3f);
1937 #else
1938 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1939 tcg_gen_sari_tl(t0, t0, 0x1f);
1940 #endif
1941 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1942 t1 = tcg_temp_new();
1943 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1944 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1945 tcg_temp_free(t1);
1946 tcg_temp_free(t0);
1947 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1948 if (unlikely(Rc(ctx->opcode) != 0))
1949 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1950 }
1951
1952 /* sraw & sraw. */
1953 static void gen_sraw(DisasContext *ctx)
1954 {
1955 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1956 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1957 if (unlikely(Rc(ctx->opcode) != 0))
1958 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1959 }
1960
1961 /* srawi & srawi. */
1962 static void gen_srawi(DisasContext *ctx)
1963 {
1964 int sh = SH(ctx->opcode);
1965 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1966 TCGv src = cpu_gpr[rS(ctx->opcode)];
1967 if (sh == 0) {
1968 tcg_gen_ext32s_tl(dst, src);
1969 tcg_gen_movi_tl(cpu_ca, 0);
1970 } else {
1971 TCGv t0;
1972 tcg_gen_ext32s_tl(dst, src);
1973 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1974 t0 = tcg_temp_new();
1975 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1976 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1977 tcg_temp_free(t0);
1978 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1979 tcg_gen_sari_tl(dst, dst, sh);
1980 }
1981 if (unlikely(Rc(ctx->opcode) != 0)) {
1982 gen_set_Rc0(ctx, dst);
1983 }
1984 }
1985
1986 /* srw & srw. */
1987 static void gen_srw(DisasContext *ctx)
1988 {
1989 TCGv t0, t1;
1990
1991 t0 = tcg_temp_new();
1992 /* AND rS with a mask that is 0 when rB >= 0x20 */
1993 #if defined(TARGET_PPC64)
1994 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1995 tcg_gen_sari_tl(t0, t0, 0x3f);
1996 #else
1997 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1998 tcg_gen_sari_tl(t0, t0, 0x1f);
1999 #endif
2000 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2001 tcg_gen_ext32u_tl(t0, t0);
2002 t1 = tcg_temp_new();
2003 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2004 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2005 tcg_temp_free(t1);
2006 tcg_temp_free(t0);
2007 if (unlikely(Rc(ctx->opcode) != 0))
2008 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2009 }
2010
2011 #if defined(TARGET_PPC64)
2012 /* sld & sld. */
2013 static void gen_sld(DisasContext *ctx)
2014 {
2015 TCGv t0, t1;
2016
2017 t0 = tcg_temp_new();
2018 /* AND rS with a mask that is 0 when rB >= 0x40 */
2019 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2020 tcg_gen_sari_tl(t0, t0, 0x3f);
2021 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2022 t1 = tcg_temp_new();
2023 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2024 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2025 tcg_temp_free(t1);
2026 tcg_temp_free(t0);
2027 if (unlikely(Rc(ctx->opcode) != 0))
2028 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2029 }
2030
2031 /* srad & srad. */
2032 static void gen_srad(DisasContext *ctx)
2033 {
2034 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2035 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2036 if (unlikely(Rc(ctx->opcode) != 0))
2037 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2038 }
2039 /* sradi & sradi. */
2040 static inline void gen_sradi(DisasContext *ctx, int n)
2041 {
2042 int sh = SH(ctx->opcode) + (n << 5);
2043 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2044 TCGv src = cpu_gpr[rS(ctx->opcode)];
2045 if (sh == 0) {
2046 tcg_gen_mov_tl(dst, src);
2047 tcg_gen_movi_tl(cpu_ca, 0);
2048 } else {
2049 TCGv t0;
2050 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2051 t0 = tcg_temp_new();
2052 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2053 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2054 tcg_temp_free(t0);
2055 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2056 tcg_gen_sari_tl(dst, src, sh);
2057 }
2058 if (unlikely(Rc(ctx->opcode) != 0)) {
2059 gen_set_Rc0(ctx, dst);
2060 }
2061 }
2062
2063 static void gen_sradi0(DisasContext *ctx)
2064 {
2065 gen_sradi(ctx, 0);
2066 }
2067
2068 static void gen_sradi1(DisasContext *ctx)
2069 {
2070 gen_sradi(ctx, 1);
2071 }
2072
2073 /* srd & srd. */
2074 static void gen_srd(DisasContext *ctx)
2075 {
2076 TCGv t0, t1;
2077
2078 t0 = tcg_temp_new();
2079 /* AND rS with a mask that is 0 when rB >= 0x40 */
2080 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2081 tcg_gen_sari_tl(t0, t0, 0x3f);
2082 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2083 t1 = tcg_temp_new();
2084 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2085 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2086 tcg_temp_free(t1);
2087 tcg_temp_free(t0);
2088 if (unlikely(Rc(ctx->opcode) != 0))
2089 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2090 }
2091 #endif
2092
2093 /*** Floating-Point arithmetic ***/
2094 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2095 static void gen_f##name(DisasContext *ctx) \
2096 { \
2097 if (unlikely(!ctx->fpu_enabled)) { \
2098 gen_exception(ctx, POWERPC_EXCP_FPU); \
2099 return; \
2100 } \
2101 /* NIP cannot be restored if the memory exception comes from an helper */ \
2102 gen_update_nip(ctx, ctx->nip - 4); \
2103 gen_reset_fpstatus(); \
2104 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2105 cpu_fpr[rA(ctx->opcode)], \
2106 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2107 if (isfloat) { \
2108 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2109 cpu_fpr[rD(ctx->opcode)]); \
2110 } \
2111 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2112 Rc(ctx->opcode) != 0); \
2113 }
2114
2115 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2116 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2117 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2118
2119 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2120 static void gen_f##name(DisasContext *ctx) \
2121 { \
2122 if (unlikely(!ctx->fpu_enabled)) { \
2123 gen_exception(ctx, POWERPC_EXCP_FPU); \
2124 return; \
2125 } \
2126 /* NIP cannot be restored if the memory exception comes from an helper */ \
2127 gen_update_nip(ctx, ctx->nip - 4); \
2128 gen_reset_fpstatus(); \
2129 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2130 cpu_fpr[rA(ctx->opcode)], \
2131 cpu_fpr[rB(ctx->opcode)]); \
2132 if (isfloat) { \
2133 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2134 cpu_fpr[rD(ctx->opcode)]); \
2135 } \
2136 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2137 set_fprf, Rc(ctx->opcode) != 0); \
2138 }
2139 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2140 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2141 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2142
2143 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2144 static void gen_f##name(DisasContext *ctx) \
2145 { \
2146 if (unlikely(!ctx->fpu_enabled)) { \
2147 gen_exception(ctx, POWERPC_EXCP_FPU); \
2148 return; \
2149 } \
2150 /* NIP cannot be restored if the memory exception comes from an helper */ \
2151 gen_update_nip(ctx, ctx->nip - 4); \
2152 gen_reset_fpstatus(); \
2153 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2154 cpu_fpr[rA(ctx->opcode)], \
2155 cpu_fpr[rC(ctx->opcode)]); \
2156 if (isfloat) { \
2157 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2158 cpu_fpr[rD(ctx->opcode)]); \
2159 } \
2160 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2161 set_fprf, Rc(ctx->opcode) != 0); \
2162 }
2163 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2164 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2165 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2166
2167 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2168 static void gen_f##name(DisasContext *ctx) \
2169 { \
2170 if (unlikely(!ctx->fpu_enabled)) { \
2171 gen_exception(ctx, POWERPC_EXCP_FPU); \
2172 return; \
2173 } \
2174 /* NIP cannot be restored if the memory exception comes from an helper */ \
2175 gen_update_nip(ctx, ctx->nip - 4); \
2176 gen_reset_fpstatus(); \
2177 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2178 cpu_fpr[rB(ctx->opcode)]); \
2179 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2180 set_fprf, Rc(ctx->opcode) != 0); \
2181 }
2182
2183 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2184 static void gen_f##name(DisasContext *ctx) \
2185 { \
2186 if (unlikely(!ctx->fpu_enabled)) { \
2187 gen_exception(ctx, POWERPC_EXCP_FPU); \
2188 return; \
2189 } \
2190 /* NIP cannot be restored if the memory exception comes from an helper */ \
2191 gen_update_nip(ctx, ctx->nip - 4); \
2192 gen_reset_fpstatus(); \
2193 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2194 cpu_fpr[rB(ctx->opcode)]); \
2195 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2196 set_fprf, Rc(ctx->opcode) != 0); \
2197 }
2198
2199 /* fadd - fadds */
2200 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2201 /* fdiv - fdivs */
2202 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2203 /* fmul - fmuls */
2204 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2205
2206 /* fre */
2207 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2208
2209 /* fres */
2210 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2211
2212 /* frsqrte */
2213 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2214
2215 /* frsqrtes */
2216 static void gen_frsqrtes(DisasContext *ctx)
2217 {
2218 if (unlikely(!ctx->fpu_enabled)) {
2219 gen_exception(ctx, POWERPC_EXCP_FPU);
2220 return;
2221 }
2222 /* NIP cannot be restored if the memory exception comes from an helper */
2223 gen_update_nip(ctx, ctx->nip - 4);
2224 gen_reset_fpstatus();
2225 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2226 cpu_fpr[rB(ctx->opcode)]);
2227 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2228 cpu_fpr[rD(ctx->opcode)]);
2229 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2230 }
2231
2232 /* fsel */
2233 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2234 /* fsub - fsubs */
2235 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2236 /* Optional: */
2237
2238 /* fsqrt */
2239 static void gen_fsqrt(DisasContext *ctx)
2240 {
2241 if (unlikely(!ctx->fpu_enabled)) {
2242 gen_exception(ctx, POWERPC_EXCP_FPU);
2243 return;
2244 }
2245 /* NIP cannot be restored if the memory exception comes from an helper */
2246 gen_update_nip(ctx, ctx->nip - 4);
2247 gen_reset_fpstatus();
2248 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2249 cpu_fpr[rB(ctx->opcode)]);
2250 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2251 }
2252
2253 static void gen_fsqrts(DisasContext *ctx)
2254 {
2255 if (unlikely(!ctx->fpu_enabled)) {
2256 gen_exception(ctx, POWERPC_EXCP_FPU);
2257 return;
2258 }
2259 /* NIP cannot be restored if the memory exception comes from an helper */
2260 gen_update_nip(ctx, ctx->nip - 4);
2261 gen_reset_fpstatus();
2262 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2263 cpu_fpr[rB(ctx->opcode)]);
2264 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2265 cpu_fpr[rD(ctx->opcode)]);
2266 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2267 }
2268
2269 /*** Floating-Point multiply-and-add ***/
2270 /* fmadd - fmadds */
2271 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2272 /* fmsub - fmsubs */
2273 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2274 /* fnmadd - fnmadds */
2275 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2276 /* fnmsub - fnmsubs */
2277 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2278
2279 /*** Floating-Point round & convert ***/
2280 /* fctiw */
2281 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2282 /* fctiwu */
2283 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2284 /* fctiwz */
2285 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2286 /* fctiwuz */
2287 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2288 /* frsp */
2289 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2290 #if defined(TARGET_PPC64)
2291 /* fcfid */
2292 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2293 /* fcfids */
2294 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2295 /* fcfidu */
2296 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2297 /* fcfidus */
2298 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2299 /* fctid */
2300 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2301 /* fctidu */
2302 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2303 /* fctidz */
2304 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2305 /* fctidu */
2306 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2307 #endif
2308
2309 /* frin */
2310 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2311 /* friz */
2312 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2313 /* frip */
2314 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2315 /* frim */
2316 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2317
2318 static void gen_ftdiv(DisasContext *ctx)
2319 {
2320 if (unlikely(!ctx->fpu_enabled)) {
2321 gen_exception(ctx, POWERPC_EXCP_FPU);
2322 return;
2323 }
2324 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2325 cpu_fpr[rB(ctx->opcode)]);
2326 }
2327
2328 static void gen_ftsqrt(DisasContext *ctx)
2329 {
2330 if (unlikely(!ctx->fpu_enabled)) {
2331 gen_exception(ctx, POWERPC_EXCP_FPU);
2332 return;
2333 }
2334 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2335 }
2336
2337
2338
2339 /*** Floating-Point compare ***/
2340
2341 /* fcmpo */
2342 static void gen_fcmpo(DisasContext *ctx)
2343 {
2344 TCGv_i32 crf;
2345 if (unlikely(!ctx->fpu_enabled)) {
2346 gen_exception(ctx, POWERPC_EXCP_FPU);
2347 return;
2348 }
2349 /* NIP cannot be restored if the memory exception comes from an helper */
2350 gen_update_nip(ctx, ctx->nip - 4);
2351 gen_reset_fpstatus();
2352 crf = tcg_const_i32(crfD(ctx->opcode));
2353 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2354 cpu_fpr[rB(ctx->opcode)], crf);
2355 tcg_temp_free_i32(crf);
2356 gen_helper_float_check_status(cpu_env);
2357 }
2358
2359 /* fcmpu */
2360 static void gen_fcmpu(DisasContext *ctx)
2361 {
2362 TCGv_i32 crf;
2363 if (unlikely(!ctx->fpu_enabled)) {
2364 gen_exception(ctx, POWERPC_EXCP_FPU);
2365 return;
2366 }
2367 /* NIP cannot be restored if the memory exception comes from an helper */
2368 gen_update_nip(ctx, ctx->nip - 4);
2369 gen_reset_fpstatus();
2370 crf = tcg_const_i32(crfD(ctx->opcode));
2371 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2372 cpu_fpr[rB(ctx->opcode)], crf);
2373 tcg_temp_free_i32(crf);
2374 gen_helper_float_check_status(cpu_env);
2375 }
2376
2377 /*** Floating-point move ***/
2378 /* fabs */
2379 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2380 static void gen_fabs(DisasContext *ctx)
2381 {
2382 if (unlikely(!ctx->fpu_enabled)) {
2383 gen_exception(ctx, POWERPC_EXCP_FPU);
2384 return;
2385 }
2386 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2387 ~(1ULL << 63));
2388 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2389 }
2390
2391 /* fmr - fmr. */
2392 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2393 static void gen_fmr(DisasContext *ctx)
2394 {
2395 if (unlikely(!ctx->fpu_enabled)) {
2396 gen_exception(ctx, POWERPC_EXCP_FPU);
2397 return;
2398 }
2399 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2400 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2401 }
2402
2403 /* fnabs */
2404 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2405 static void gen_fnabs(DisasContext *ctx)
2406 {
2407 if (unlikely(!ctx->fpu_enabled)) {
2408 gen_exception(ctx, POWERPC_EXCP_FPU);
2409 return;
2410 }
2411 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2412 1ULL << 63);
2413 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2414 }
2415
2416 /* fneg */
2417 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2418 static void gen_fneg(DisasContext *ctx)
2419 {
2420 if (unlikely(!ctx->fpu_enabled)) {
2421 gen_exception(ctx, POWERPC_EXCP_FPU);
2422 return;
2423 }
2424 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2425 1ULL << 63);
2426 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2427 }
2428
2429 /* fcpsgn: PowerPC 2.05 specification */
2430 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2431 static void gen_fcpsgn(DisasContext *ctx)
2432 {
2433 if (unlikely(!ctx->fpu_enabled)) {
2434 gen_exception(ctx, POWERPC_EXCP_FPU);
2435 return;
2436 }
2437 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2438 cpu_fpr[rB(ctx->opcode)], 0, 63);
2439 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2440 }
2441
2442 static void gen_fmrgew(DisasContext *ctx)
2443 {
2444 TCGv_i64 b0;
2445 if (unlikely(!ctx->fpu_enabled)) {
2446 gen_exception(ctx, POWERPC_EXCP_FPU);
2447 return;
2448 }
2449 b0 = tcg_temp_new_i64();
2450 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2451 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2452 b0, 0, 32);
2453 tcg_temp_free_i64(b0);
2454 }
2455
2456 static void gen_fmrgow(DisasContext *ctx)
2457 {
2458 if (unlikely(!ctx->fpu_enabled)) {
2459 gen_exception(ctx, POWERPC_EXCP_FPU);
2460 return;
2461 }
2462 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2463 cpu_fpr[rB(ctx->opcode)],
2464 cpu_fpr[rA(ctx->opcode)],
2465 32, 32);
2466 }
2467
2468 /*** Floating-Point status & ctrl register ***/
2469
2470 /* mcrfs */
2471 static void gen_mcrfs(DisasContext *ctx)
2472 {
2473 TCGv tmp = tcg_temp_new();
2474 int bfa;
2475
2476 if (unlikely(!ctx->fpu_enabled)) {
2477 gen_exception(ctx, POWERPC_EXCP_FPU);
2478 return;
2479 }
2480 bfa = 4 * (7 - crfS(ctx->opcode));
2481 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2482 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2483 tcg_temp_free(tmp);
2484 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2485 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2486 }
2487
2488 /* mffs */
2489 static void gen_mffs(DisasContext *ctx)
2490 {
2491 if (unlikely(!ctx->fpu_enabled)) {
2492 gen_exception(ctx, POWERPC_EXCP_FPU);
2493 return;
2494 }
2495 gen_reset_fpstatus();
2496 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2497 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2498 }
2499
2500 /* mtfsb0 */
2501 static void gen_mtfsb0(DisasContext *ctx)
2502 {
2503 uint8_t crb;
2504
2505 if (unlikely(!ctx->fpu_enabled)) {
2506 gen_exception(ctx, POWERPC_EXCP_FPU);
2507 return;
2508 }
2509 crb = 31 - crbD(ctx->opcode);
2510 gen_reset_fpstatus();
2511 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2512 TCGv_i32 t0;
2513 /* NIP cannot be restored if the memory exception comes from an helper */
2514 gen_update_nip(ctx, ctx->nip - 4);
2515 t0 = tcg_const_i32(crb);
2516 gen_helper_fpscr_clrbit(cpu_env, t0);
2517 tcg_temp_free_i32(t0);
2518 }
2519 if (unlikely(Rc(ctx->opcode) != 0)) {
2520 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2521 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2522 }
2523 }
2524
2525 /* mtfsb1 */
2526 static void gen_mtfsb1(DisasContext *ctx)
2527 {
2528 uint8_t crb;
2529
2530 if (unlikely(!ctx->fpu_enabled)) {
2531 gen_exception(ctx, POWERPC_EXCP_FPU);
2532 return;
2533 }
2534 crb = 31 - crbD(ctx->opcode);
2535 gen_reset_fpstatus();
2536 /* XXX: we pretend we can only do IEEE floating-point computations */
2537 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2538 TCGv_i32 t0;
2539 /* NIP cannot be restored if the memory exception comes from an helper */
2540 gen_update_nip(ctx, ctx->nip - 4);
2541 t0 = tcg_const_i32(crb);
2542 gen_helper_fpscr_setbit(cpu_env, t0);
2543 tcg_temp_free_i32(t0);
2544 }
2545 if (unlikely(Rc(ctx->opcode) != 0)) {
2546 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2547 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2548 }
2549 /* We can raise a differed exception */
2550 gen_helper_float_check_status(cpu_env);
2551 }
2552
2553 /* mtfsf */
2554 static void gen_mtfsf(DisasContext *ctx)
2555 {
2556 TCGv_i32 t0;
2557 int flm, l, w;
2558
2559 if (unlikely(!ctx->fpu_enabled)) {
2560 gen_exception(ctx, POWERPC_EXCP_FPU);
2561 return;
2562 }
2563 flm = FPFLM(ctx->opcode);
2564 l = FPL(ctx->opcode);
2565 w = FPW(ctx->opcode);
2566 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2567 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2568 return;
2569 }
2570 /* NIP cannot be restored if the memory exception comes from an helper */
2571 gen_update_nip(ctx, ctx->nip - 4);
2572 gen_reset_fpstatus();
2573 if (l) {
2574 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2575 } else {
2576 t0 = tcg_const_i32(flm << (w * 8));
2577 }
2578 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2579 tcg_temp_free_i32(t0);
2580 if (unlikely(Rc(ctx->opcode) != 0)) {
2581 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2582 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2583 }
2584 /* We can raise a differed exception */
2585 gen_helper_float_check_status(cpu_env);
2586 }
2587
2588 /* mtfsfi */
2589 static void gen_mtfsfi(DisasContext *ctx)
2590 {
2591 int bf, sh, w;
2592 TCGv_i64 t0;
2593 TCGv_i32 t1;
2594
2595 if (unlikely(!ctx->fpu_enabled)) {
2596 gen_exception(ctx, POWERPC_EXCP_FPU);
2597 return;
2598 }
2599 w = FPW(ctx->opcode);
2600 bf = FPBF(ctx->opcode);
2601 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2602 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2603 return;
2604 }
2605 sh = (8 * w) + 7 - bf;
2606 /* NIP cannot be restored if the memory exception comes from an helper */
2607 gen_update_nip(ctx, ctx->nip - 4);
2608 gen_reset_fpstatus();
2609 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2610 t1 = tcg_const_i32(1 << sh);
2611 gen_helper_store_fpscr(cpu_env, t0, t1);
2612 tcg_temp_free_i64(t0);
2613 tcg_temp_free_i32(t1);
2614 if (unlikely(Rc(ctx->opcode) != 0)) {
2615 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2616 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2617 }
2618 /* We can raise a differed exception */
2619 gen_helper_float_check_status(cpu_env);
2620 }
2621
2622 /*** Addressing modes ***/
2623 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2624 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2625 target_long maskl)
2626 {
2627 target_long simm = SIMM(ctx->opcode);
2628
2629 simm &= ~maskl;
2630 if (rA(ctx->opcode) == 0) {
2631 if (NARROW_MODE(ctx)) {
2632 simm = (uint32_t)simm;
2633 }
2634 tcg_gen_movi_tl(EA, simm);
2635 } else if (likely(simm != 0)) {
2636 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2637 if (NARROW_MODE(ctx)) {
2638 tcg_gen_ext32u_tl(EA, EA);
2639 }
2640 } else {
2641 if (NARROW_MODE(ctx)) {
2642 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2643 } else {
2644 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2645 }
2646 }
2647 }
2648
2649 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2650 {
2651 if (rA(ctx->opcode) == 0) {
2652 if (NARROW_MODE(ctx)) {
2653 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2654 } else {
2655 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2656 }
2657 } else {
2658 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2659 if (NARROW_MODE(ctx)) {
2660 tcg_gen_ext32u_tl(EA, EA);
2661 }
2662 }
2663 }
2664
2665 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2666 {
2667 if (rA(ctx->opcode) == 0) {
2668 tcg_gen_movi_tl(EA, 0);
2669 } else if (NARROW_MODE(ctx)) {
2670 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2671 } else {
2672 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2673 }
2674 }
2675
2676 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2677 target_long val)
2678 {
2679 tcg_gen_addi_tl(ret, arg1, val);
2680 if (NARROW_MODE(ctx)) {
2681 tcg_gen_ext32u_tl(ret, ret);
2682 }
2683 }
2684
2685 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2686 {
2687 int l1 = gen_new_label();
2688 TCGv t0 = tcg_temp_new();
2689 TCGv_i32 t1, t2;
2690 /* NIP cannot be restored if the memory exception comes from an helper */
2691 gen_update_nip(ctx, ctx->nip - 4);
2692 tcg_gen_andi_tl(t0, EA, mask);
2693 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2694 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2695 t2 = tcg_const_i32(0);
2696 gen_helper_raise_exception_err(cpu_env, t1, t2);
2697 tcg_temp_free_i32(t1);
2698 tcg_temp_free_i32(t2);
2699 gen_set_label(l1);
2700 tcg_temp_free(t0);
2701 }
2702
2703 /*** Integer load ***/
2704 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2705 {
2706 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2707 }
2708
2709 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2710 {
2711 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2712 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2713 }
2714
2715 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2716 {
2717 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2718 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2719 }
2720
2721 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2722 {
2723 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2724 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2725 }
2726
2727 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2728 {
2729 TCGv tmp = tcg_temp_new();
2730 gen_qemu_ld32u(ctx, tmp, addr);
2731 tcg_gen_extu_tl_i64(val, tmp);
2732 tcg_temp_free(tmp);
2733 }
2734
2735 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2736 {
2737 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2738 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2739 }
2740
2741 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2742 {
2743 TCGv tmp = tcg_temp_new();
2744 gen_qemu_ld32s(ctx, tmp, addr);
2745 tcg_gen_ext_tl_i64(val, tmp);
2746 tcg_temp_free(tmp);
2747 }
2748
2749 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2750 {
2751 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2752 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2753 }
2754
2755 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2756 {
2757 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2758 }
2759
2760 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2761 {
2762 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2763 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2764 }
2765
2766 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2767 {
2768 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2769 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2770 }
2771
2772 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2773 {
2774 TCGv tmp = tcg_temp_new();
2775 tcg_gen_trunc_i64_tl(tmp, val);
2776 gen_qemu_st32(ctx, tmp, addr);
2777 tcg_temp_free(tmp);
2778 }
2779
2780 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2781 {
2782 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2783 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2784 }
2785
2786 #define GEN_LD(name, ldop, opc, type) \
2787 static void glue(gen_, name)(DisasContext *ctx) \
2788 { \
2789 TCGv EA; \
2790 gen_set_access_type(ctx, ACCESS_INT); \
2791 EA = tcg_temp_new(); \
2792 gen_addr_imm_index(ctx, EA, 0); \
2793 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2794 tcg_temp_free(EA); \
2795 }
2796
2797 #define GEN_LDU(name, ldop, opc, type) \
2798 static void glue(gen_, name##u)(DisasContext *ctx) \
2799 { \
2800 TCGv EA; \
2801 if (unlikely(rA(ctx->opcode) == 0 || \
2802 rA(ctx->opcode) == rD(ctx->opcode))) { \
2803 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2804 return; \
2805 } \
2806 gen_set_access_type(ctx, ACCESS_INT); \
2807 EA = tcg_temp_new(); \
2808 if (type == PPC_64B) \
2809 gen_addr_imm_index(ctx, EA, 0x03); \
2810 else \
2811 gen_addr_imm_index(ctx, EA, 0); \
2812 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2813 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2814 tcg_temp_free(EA); \
2815 }
2816
2817 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2818 static void glue(gen_, name##ux)(DisasContext *ctx) \
2819 { \
2820 TCGv EA; \
2821 if (unlikely(rA(ctx->opcode) == 0 || \
2822 rA(ctx->opcode) == rD(ctx->opcode))) { \
2823 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2824 return; \
2825 } \
2826 gen_set_access_type(ctx, ACCESS_INT); \
2827 EA = tcg_temp_new(); \
2828 gen_addr_reg_index(ctx, EA); \
2829 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2830 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2831 tcg_temp_free(EA); \
2832 }
2833
2834 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2835 static void glue(gen_, name##x)(DisasContext *ctx) \
2836 { \
2837 TCGv EA; \
2838 gen_set_access_type(ctx, ACCESS_INT); \
2839 EA = tcg_temp_new(); \
2840 gen_addr_reg_index(ctx, EA); \
2841 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2842 tcg_temp_free(EA); \
2843 }
2844 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2845 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2846
2847 #define GEN_LDS(name, ldop, op, type) \
2848 GEN_LD(name, ldop, op | 0x20, type); \
2849 GEN_LDU(name, ldop, op | 0x21, type); \
2850 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2851 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2852
2853 /* lbz lbzu lbzux lbzx */
2854 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2855 /* lha lhau lhaux lhax */
2856 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2857 /* lhz lhzu lhzux lhzx */
2858 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2859 /* lwz lwzu lwzux lwzx */
2860 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2861 #if defined(TARGET_PPC64)
2862 /* lwaux */
2863 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2864 /* lwax */
2865 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2866 /* ldux */
2867 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2868 /* ldx */
2869 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2870
2871 static void gen_ld(DisasContext *ctx)
2872 {
2873 TCGv EA;
2874 if (Rc(ctx->opcode)) {
2875 if (unlikely(rA(ctx->opcode) == 0 ||
2876 rA(ctx->opcode) == rD(ctx->opcode))) {
2877 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2878 return;
2879 }
2880 }
2881 gen_set_access_type(ctx, ACCESS_INT);
2882 EA = tcg_temp_new();
2883 gen_addr_imm_index(ctx, EA, 0x03);
2884 if (ctx->opcode & 0x02) {
2885 /* lwa (lwau is undefined) */
2886 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2887 } else {
2888 /* ld - ldu */
2889 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2890 }
2891 if (Rc(ctx->opcode))
2892 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2893 tcg_temp_free(EA);
2894 }
2895
2896 /* lq */
2897 static void gen_lq(DisasContext *ctx)
2898 {
2899 int ra, rd;
2900 TCGv EA;
2901
2902 /* lq is a legal user mode instruction starting in ISA 2.07 */
2903 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2904 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2905
2906 if (!legal_in_user_mode && is_user_mode(ctx)) {
2907 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2908 return;
2909 }
2910
2911 if (!le_is_supported && ctx->le_mode) {
2912 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2913 return;
2914 }
2915
2916 ra = rA(ctx->opcode);
2917 rd = rD(ctx->opcode);
2918 if (unlikely((rd & 1) || rd == ra)) {
2919 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2920 return;
2921 }
2922
2923 gen_set_access_type(ctx, ACCESS_INT);
2924 EA = tcg_temp_new();
2925 gen_addr_imm_index(ctx, EA, 0x0F);
2926
2927 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2928 64-bit byteswap already. */
2929 if (unlikely(ctx->le_mode)) {
2930 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2931 gen_addr_add(ctx, EA, EA, 8);
2932 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2933 } else {
2934 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2935 gen_addr_add(ctx, EA, EA, 8);
2936 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2937 }
2938 tcg_temp_free(EA);
2939 }
2940 #endif
2941
2942 /*** Integer store ***/
2943 #define GEN_ST(name, stop, opc, type) \
2944 static void glue(gen_, name)(DisasContext *ctx) \
2945 { \
2946 TCGv EA; \
2947 gen_set_access_type(ctx, ACCESS_INT); \
2948 EA = tcg_temp_new(); \
2949 gen_addr_imm_index(ctx, EA, 0); \
2950 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2951 tcg_temp_free(EA); \
2952 }
2953
2954 #define GEN_STU(name, stop, opc, type) \
2955 static void glue(gen_, stop##u)(DisasContext *ctx) \
2956 { \
2957 TCGv EA; \
2958 if (unlikely(rA(ctx->opcode) == 0)) { \
2959 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2960 return; \
2961 } \
2962 gen_set_access_type(ctx, ACCESS_INT); \
2963 EA = tcg_temp_new(); \
2964 if (type == PPC_64B) \
2965 gen_addr_imm_index(ctx, EA, 0x03); \
2966 else \
2967 gen_addr_imm_index(ctx, EA, 0); \
2968 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2969 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2970 tcg_temp_free(EA); \
2971 }
2972
2973 #define GEN_STUX(name, stop, opc2, opc3, type) \
2974 static void glue(gen_, name##ux)(DisasContext *ctx) \
2975 { \
2976 TCGv EA; \
2977 if (unlikely(rA(ctx->opcode) == 0)) { \
2978 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2979 return; \
2980 } \
2981 gen_set_access_type(ctx, ACCESS_INT); \
2982 EA = tcg_temp_new(); \
2983 gen_addr_reg_index(ctx, EA); \
2984 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2985 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2986 tcg_temp_free(EA); \
2987 }
2988
2989 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2990 static void glue(gen_, name##x)(DisasContext *ctx) \
2991 { \
2992 TCGv EA; \
2993 gen_set_access_type(ctx, ACCESS_INT); \
2994 EA = tcg_temp_new(); \
2995 gen_addr_reg_index(ctx, EA); \
2996 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2997 tcg_temp_free(EA); \
2998 }
2999 #define GEN_STX(name, stop, opc2, opc3, type) \
3000 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
3001
3002 #define GEN_STS(name, stop, op, type) \
3003 GEN_ST(name, stop, op | 0x20, type); \
3004 GEN_STU(name, stop, op | 0x21, type); \
3005 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3006 GEN_STX(name, stop, 0x17, op | 0x00, type)
3007
3008 /* stb stbu stbux stbx */
3009 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3010 /* sth sthu sthux sthx */
3011 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3012 /* stw stwu stwux stwx */
3013 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3014 #if defined(TARGET_PPC64)
3015 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3016 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
3017
3018 static void gen_std(DisasContext *ctx)
3019 {
3020 int rs;
3021 TCGv EA;
3022
3023 rs = rS(ctx->opcode);
3024 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3025
3026 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3027 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3028
3029 if (!legal_in_user_mode && is_user_mode(ctx)) {
3030 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3031 return;
3032 }
3033
3034 if (!le_is_supported && ctx->le_mode) {
3035 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3036 return;
3037 }
3038
3039 if (unlikely(rs & 1)) {
3040 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3041 return;
3042 }
3043 gen_set_access_type(ctx, ACCESS_INT);
3044 EA = tcg_temp_new();
3045 gen_addr_imm_index(ctx, EA, 0x03);
3046
3047 /* We only need to swap high and low halves. gen_qemu_st64 does
3048 necessary 64-bit byteswap already. */
3049 if (unlikely(ctx->le_mode)) {
3050 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3051 gen_addr_add(ctx, EA, EA, 8);
3052 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3053 } else {
3054 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3055 gen_addr_add(ctx, EA, EA, 8);
3056 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3057 }
3058 tcg_temp_free(EA);
3059 } else {
3060 /* std / stdu*/
3061 if (Rc(ctx->opcode)) {
3062 if (unlikely(rA(ctx->opcode) == 0)) {
3063 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3064 return;
3065 }
3066 }
3067 gen_set_access_type(ctx, ACCESS_INT);
3068 EA = tcg_temp_new();
3069 gen_addr_imm_index(ctx, EA, 0x03);
3070 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3071 if (Rc(ctx->opcode))
3072 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3073 tcg_temp_free(EA);
3074 }
3075 }
3076 #endif
3077 /*** Integer load and store with byte reverse ***/
3078
3079 /* lhbrx */
3080 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3081 {
3082 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3083 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3084 }
3085 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3086
3087 /* lwbrx */
3088 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3089 {
3090 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3091 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3092 }
3093 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3094
3095 #if defined(TARGET_PPC64)
3096 /* ldbrx */
3097 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3098 {
3099 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3100 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3101 }
3102 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3103 #endif /* TARGET_PPC64 */
3104
3105 /* sthbrx */
3106 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3107 {
3108 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3109 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3110 }
3111 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3112
3113 /* stwbrx */
3114 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3115 {
3116 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3117 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3118 }
3119 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3120
3121 #if defined(TARGET_PPC64)
3122 /* stdbrx */
3123 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3124 {
3125 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3126 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3127 }
3128 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3129 #endif /* TARGET_PPC64 */
3130
3131 /*** Integer load and store multiple ***/
3132
3133 /* lmw */
3134 static void gen_lmw(DisasContext *ctx)
3135 {
3136 TCGv t0;
3137 TCGv_i32 t1;
3138 gen_set_access_type(ctx, ACCESS_INT);
3139 /* NIP cannot be restored if the memory exception comes from an helper */
3140 gen_update_nip(ctx, ctx->nip - 4);
3141 t0 = tcg_temp_new();
3142 t1 = tcg_const_i32(rD(ctx->opcode));
3143 gen_addr_imm_index(ctx, t0, 0);
3144 gen_helper_lmw(cpu_env, t0, t1);
3145 tcg_temp_free(t0);
3146 tcg_temp_free_i32(t1);
3147 }
3148
3149 /* stmw */
3150 static void gen_stmw(DisasContext *ctx)
3151 {
3152 TCGv t0;
3153 TCGv_i32 t1;
3154 gen_set_access_type(ctx, ACCESS_INT);
3155 /* NIP cannot be restored if the memory exception comes from an helper */
3156 gen_update_nip(ctx, ctx->nip - 4);
3157 t0 = tcg_temp_new();
3158 t1 = tcg_const_i32(rS(ctx->opcode));
3159 gen_addr_imm_index(ctx, t0, 0);
3160 gen_helper_stmw(cpu_env, t0, t1);
3161 tcg_temp_free(t0);
3162 tcg_temp_free_i32(t1);
3163 }
3164
3165 /*** Integer load and store strings ***/
3166
3167 /* lswi */
3168 /* PowerPC32 specification says we must generate an exception if
3169 * rA is in the range of registers to be loaded.
3170 * In an other hand, IBM says this is valid, but rA won't be loaded.
3171 * For now, I'll follow the spec...
3172 */
3173 static void gen_lswi(DisasContext *ctx)
3174 {
3175 TCGv t0;
3176 TCGv_i32 t1, t2;
3177 int nb = NB(ctx->opcode);
3178 int start = rD(ctx->opcode);
3179 int ra = rA(ctx->opcode);
3180 int nr;
3181
3182 if (nb == 0)
3183 nb = 32;
3184 nr = nb / 4;
3185 if (unlikely(((start + nr) > 32 &&
3186 start <= ra && (start + nr - 32) > ra) ||
3187 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3188 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3189 return;
3190 }
3191 gen_set_access_type(ctx, ACCESS_INT);
3192 /* NIP cannot be restored if the memory exception comes from an helper */
3193 gen_update_nip(ctx, ctx->nip - 4);
3194 t0 = tcg_temp_new();
3195 gen_addr_register(ctx, t0);
3196 t1 = tcg_const_i32(nb);
3197 t2 = tcg_const_i32(start);
3198 gen_helper_lsw(cpu_env, t0, t1, t2);
3199 tcg_temp_free(t0);
3200 tcg_temp_free_i32(t1);
3201 tcg_temp_free_i32(t2);
3202 }
3203
3204 /* lswx */
3205 static void gen_lswx(DisasContext *ctx)
3206 {
3207 TCGv t0;
3208 TCGv_i32 t1, t2, t3;
3209 gen_set_access_type(ctx, ACCESS_INT);
3210 /* NIP cannot be restored if the memory exception comes from an helper */
3211 gen_update_nip(ctx, ctx->nip - 4);
3212 t0 = tcg_temp_new();
3213 gen_addr_reg_index(ctx, t0);
3214 t1 = tcg_const_i32(rD(ctx->opcode));
3215 t2 = tcg_const_i32(rA(ctx->opcode));
3216 t3 = tcg_const_i32(rB(ctx->opcode));
3217 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3218 tcg_temp_free(t0);
3219 tcg_temp_free_i32(t1);
3220 tcg_temp_free_i32(t2);
3221 tcg_temp_free_i32(t3);
3222 }
3223
3224 /* stswi */
3225 static void gen_stswi(DisasContext *ctx)
3226 {
3227 TCGv t0;
3228 TCGv_i32 t1, t2;
3229 int nb = NB(ctx->opcode);
3230 gen_set_access_type(ctx, ACCESS_INT);
3231 /* NIP cannot be restored if the memory exception comes from an helper */
3232 gen_update_nip(ctx, ctx->nip - 4);
3233 t0 = tcg_temp_new();
3234 gen_addr_register(ctx, t0);
3235 if (nb == 0)
3236 nb = 32;
3237 t1 = tcg_const_i32(nb);
3238 t2 = tcg_const_i32(rS(ctx->opcode));
3239 gen_helper_stsw(cpu_env, t0, t1, t2);
3240 tcg_temp_free(t0);
3241 tcg_temp_free_i32(t1);
3242 tcg_temp_free_i32(t2);
3243 }
3244
3245 /* stswx */
3246 static void gen_stswx(DisasContext *ctx)
3247 {
3248 TCGv t0;
3249 TCGv_i32 t1, t2;
3250 gen_set_access_type(ctx, ACCESS_INT);
3251 /* NIP cannot be restored if the memory exception comes from an helper */
3252 gen_update_nip(ctx, ctx->nip - 4);
3253 t0 = tcg_temp_new();
3254 gen_addr_reg_index(ctx, t0);
3255 t1 = tcg_temp_new_i32();
3256 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3257 tcg_gen_andi_i32(t1, t1, 0x7F);
3258 t2 = tcg_const_i32(rS(ctx->opcode));
3259 gen_helper_stsw(cpu_env, t0, t1, t2);
3260 tcg_temp_free(t0);
3261 tcg_temp_free_i32(t1);
3262 tcg_temp_free_i32(t2);
3263 }
3264
3265 /*** Memory synchronisation ***/
3266 /* eieio */
3267 static void gen_eieio(DisasContext *ctx)
3268 {
3269 }
3270
3271 /* isync */
3272 static void gen_isync(DisasContext *ctx)
3273 {
3274 gen_stop_exception(ctx);
3275 }
3276
3277 #define LARX(name, len, loadop) \
3278 static void gen_##name(DisasContext *ctx) \
3279 { \
3280 TCGv t0; \
3281 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3282 gen_set_access_type(ctx, ACCESS_RES); \
3283 t0 = tcg_temp_local_new(); \
3284 gen_addr_reg_index(ctx, t0); \
3285 if ((len) > 1) { \
3286 gen_check_align(ctx, t0, (len)-1); \
3287 } \
3288 gen_qemu_##loadop(ctx, gpr, t0); \
3289 tcg_gen_mov_tl(cpu_reserve, t0); \
3290 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3291 tcg_temp_free(t0); \
3292 }
3293
3294 /* lwarx */
3295 LARX(lbarx, 1, ld8u);
3296 LARX(lharx, 2, ld16u);
3297 LARX(lwarx, 4, ld32u);
3298
3299
3300 #if defined(CONFIG_USER_ONLY)
3301 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3302 int reg, int size)
3303 {
3304 TCGv t0 = tcg_temp_new();
3305 uint32_t save_exception = ctx->exception;
3306
3307 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3308 tcg_gen_movi_tl(t0, (size << 5) | reg);
3309 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3310 tcg_temp_free(t0);
3311 gen_update_nip(ctx, ctx->nip-4);
3312 ctx->exception = POWERPC_EXCP_BRANCH;
3313 gen_exception(ctx, POWERPC_EXCP_STCX);
3314 ctx->exception = save_exception;
3315 }
3316 #else
3317 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3318 int reg, int size)
3319 {
3320 int l1;
3321
3322 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3323 l1 = gen_new_label();
3324 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3325 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3326 #if defined(TARGET_PPC64)
3327 if (size == 8) {
3328 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3329 } else
3330 #endif
3331 if (size == 4) {
3332 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3333 } else if (size == 2) {
3334 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3335 #if defined(TARGET_PPC64)
3336 } else if (size == 16) {
3337 TCGv gpr1, gpr2 , EA8;
3338 if (unlikely(ctx->le_mode)) {
3339 gpr1 = cpu_gpr[reg+1];
3340 gpr2 = cpu_gpr[reg];
3341 } else {
3342 gpr1 = cpu_gpr[reg];
3343 gpr2 = cpu_gpr[reg+1];
3344 }
3345 gen_qemu_st64(ctx, gpr1, EA);
3346 EA8 = tcg_temp_local_new();
3347 gen_addr_add(ctx, EA8, EA, 8);
3348 gen_qemu_st64(ctx, gpr2, EA8);
3349 tcg_temp_free(EA8);
3350 #endif
3351 } else {
3352 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3353 }
3354 gen_set_label(l1);
3355 tcg_gen_movi_tl(cpu_reserve, -1);
3356 }
3357 #endif
3358
3359 #define STCX(name, len) \
3360 static void gen_##name(DisasContext *ctx) \
3361 { \
3362 TCGv t0; \
3363 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3364 gen_inval_exception(ctx, \
3365 POWERPC_EXCP_INVAL_INVAL); \
3366 return; \
3367 } \
3368 gen_set_access_type(ctx, ACCESS_RES); \
3369 t0 = tcg_temp_local_new(); \
3370 gen_addr_reg_index(ctx, t0); \
3371 if (len > 1) { \
3372 gen_check_align(ctx, t0, (len)-1); \
3373 } \
3374 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3375 tcg_temp_free(t0); \
3376 }
3377
3378 STCX(stbcx_, 1);
3379 STCX(sthcx_, 2);
3380 STCX(stwcx_, 4);
3381
3382 #if defined(TARGET_PPC64)
3383 /* ldarx */
3384 LARX(ldarx, 8, ld64);
3385
3386 /* lqarx */
3387 static void gen_lqarx(DisasContext *ctx)
3388 {
3389 TCGv EA;
3390 int rd = rD(ctx->opcode);
3391 TCGv gpr1, gpr2;
3392
3393 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3394 (rd == rB(ctx->opcode)))) {
3395 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3396 return;
3397 }
3398
3399 gen_set_access_type(ctx, ACCESS_RES);
3400 EA = tcg_temp_local_new();
3401 gen_addr_reg_index(ctx, EA);
3402 gen_check_align(ctx, EA, 15);
3403 if (unlikely(ctx->le_mode)) {
3404 gpr1 = cpu_gpr[rd+1];
3405 gpr2 = cpu_gpr[rd];
3406 } else {
3407 gpr1 = cpu_gpr[rd];
3408 gpr2 = cpu_gpr[rd+1];
3409 }
3410 gen_qemu_ld64(ctx, gpr1, EA);
3411 tcg_gen_mov_tl(cpu_reserve, EA);
3412
3413 gen_addr_add(ctx, EA, EA, 8);
3414 gen_qemu_ld64(ctx, gpr2, EA);
3415
3416 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3417 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3418
3419 tcg_temp_free(EA);
3420 }
3421
3422 /* stdcx. */
3423 STCX(stdcx_, 8);
3424 STCX(stqcx_, 16);
3425 #endif /* defined(TARGET_PPC64) */
3426
3427 /* sync */
3428 static void gen_sync(DisasContext *ctx)
3429 {
3430 }
3431
3432 /* wait */
3433 static void gen_wait(DisasContext *ctx)
3434 {
3435 TCGv_i32 t0 = tcg_temp_new_i32();
3436 tcg_gen_st_i32(t0, cpu_env,
3437 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3438 tcg_temp_free_i32(t0);
3439 /* Stop translation, as the CPU is supposed to sleep from now */
3440 gen_exception_err(ctx, EXCP_HLT, 1);
3441 }
3442
3443 /*** Floating-point load ***/
3444 #define GEN_LDF(name, ldop, opc, type) \
3445 static void glue(gen_, name)(DisasContext *ctx) \
3446 { \
3447 TCGv EA; \
3448 if (unlikely(!ctx->fpu_enabled)) { \
3449 gen_exception(ctx, POWERPC_EXCP_FPU); \
3450 return; \
3451 } \
3452 gen_set_access_type(ctx, ACCESS_FLOAT); \
3453 EA = tcg_temp_new(); \
3454 gen_addr_imm_index(ctx, EA, 0); \
3455 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3456 tcg_temp_free(EA); \
3457 }
3458
3459 #define GEN_LDUF(name, ldop, opc, type) \
3460 static void glue(gen_, name##u)(DisasContext *ctx) \
3461 { \
3462 TCGv EA; \
3463 if (unlikely(!ctx->fpu_enabled)) { \
3464 gen_exception(ctx, POWERPC_EXCP_FPU); \
3465 return; \
3466 } \
3467 if (unlikely(rA(ctx->opcode) == 0)) { \
3468 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3469 return; \
3470 } \
3471 gen_set_access_type(ctx, ACCESS_FLOAT); \
3472 EA = tcg_temp_new(); \
3473 gen_addr_imm_index(ctx, EA, 0); \
3474 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3475 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3476 tcg_temp_free(EA); \
3477 }
3478
3479 #define GEN_LDUXF(name, ldop, opc, type) \
3480 static void glue(gen_, name##ux)(DisasContext *ctx) \
3481 { \
3482 TCGv EA; \
3483 if (unlikely(!ctx->fpu_enabled)) { \
3484 gen_exception(ctx, POWERPC_EXCP_FPU); \
3485 return; \
3486 } \
3487 if (unlikely(rA(ctx->opcode) == 0)) { \
3488 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3489 return; \
3490 } \
3491 gen_set_access_type(ctx, ACCESS_FLOAT); \
3492 EA = tcg_temp_new(); \
3493 gen_addr_reg_index(ctx, EA); \
3494 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3495 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3496 tcg_temp_free(EA); \
3497 }
3498
3499 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3500 static void glue(gen_, name##x)(DisasContext *ctx) \
3501 { \
3502 TCGv EA; \
3503 if (unlikely(!ctx->fpu_enabled)) { \
3504 gen_exception(ctx, POWERPC_EXCP_FPU); \
3505 return; \
3506 } \
3507 gen_set_access_type(ctx, ACCESS_FLOAT); \
3508 EA = tcg_temp_new(); \
3509 gen_addr_reg_index(ctx, EA); \
3510 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3511 tcg_temp_free(EA); \
3512 }
3513
3514 #define GEN_LDFS(name, ldop, op, type) \
3515 GEN_LDF(name, ldop, op | 0x20, type); \
3516 GEN_LDUF(name, ldop, op | 0x21, type); \
3517 GEN_LDUXF(name, ldop, op | 0x01, type); \
3518 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3519
3520 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3521 {
3522 TCGv t0 = tcg_temp_new();
3523 TCGv_i32 t1 = tcg_temp_new_i32();
3524 gen_qemu_ld32u(ctx, t0, arg2);
3525 tcg_gen_trunc_tl_i32(t1, t0);
3526 tcg_temp_free(t0);
3527 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3528 tcg_temp_free_i32(t1);
3529 }
3530
3531 /* lfd lfdu lfdux lfdx */
3532 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3533 /* lfs lfsu lfsux lfsx */
3534 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3535
3536 /* lfdp */
3537 static void gen_lfdp(DisasContext *ctx)
3538 {
3539 TCGv EA;
3540 if (unlikely(!ctx->fpu_enabled)) {
3541 gen_exception(ctx, POWERPC_EXCP_FPU);
3542 return;
3543 }
3544 gen_set_access_type(ctx, ACCESS_FLOAT);
3545 EA = tcg_temp_new();
3546 gen_addr_imm_index(ctx, EA, 0);
3547 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3548 64-bit byteswap already. */
3549 if (unlikely(ctx->le_mode)) {
3550 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3551 tcg_gen_addi_tl(EA, EA, 8);
3552 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3553 } else {
3554 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3555 tcg_gen_addi_tl(EA, EA, 8);
3556 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3557 }
3558 tcg_temp_free(EA);
3559 }
3560
3561 /* lfdpx */
3562 static void gen_lfdpx(DisasContext *ctx)
3563 {
3564 TCGv EA;
3565 if (unlikely(!ctx->fpu_enabled)) {
3566 gen_exception(ctx, POWERPC_EXCP_FPU);
3567 return;
3568 }
3569 gen_set_access_type(ctx, ACCESS_FLOAT);
3570 EA = tcg_temp_new();
3571 gen_addr_reg_index(ctx, EA);
3572 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3573 64-bit byteswap already. */
3574 if (unlikely(ctx->le_mode)) {
3575 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3576 tcg_gen_addi_tl(EA, EA, 8);
3577 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3578 } else {
3579 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3580 tcg_gen_addi_tl(EA, EA, 8);
3581 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3582 }
3583 tcg_temp_free(EA);
3584 }
3585
3586 /* lfiwax */
3587 static void gen_lfiwax(DisasContext *ctx)
3588 {
3589 TCGv EA;
3590 TCGv t0;
3591 if (unlikely(!ctx->fpu_enabled)) {
3592 gen_exception(ctx, POWERPC_EXCP_FPU);
3593 return;
3594 }
3595 gen_set_access_type(ctx, ACCESS_FLOAT);
3596 EA = tcg_temp_new();
3597 t0 = tcg_temp_new();
3598 gen_addr_reg_index(ctx, EA);
3599 gen_qemu_ld32s(ctx, t0, EA);
3600 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3601 tcg_temp_free(EA);
3602 tcg_temp_free(t0);
3603 }
3604
3605 /* lfiwzx */
3606 static void gen_lfiwzx(DisasContext *ctx)
3607 {
3608 TCGv EA;
3609 if (unlikely(!ctx->fpu_enabled)) {
3610 gen_exception(ctx, POWERPC_EXCP_FPU);
3611 return;
3612 }
3613 gen_set_access_type(ctx, ACCESS_FLOAT);
3614 EA = tcg_temp_new();
3615 gen_addr_reg_index(ctx, EA);
3616 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3617 tcg_temp_free(EA);
3618 }
3619 /*** Floating-point store ***/
3620 #define GEN_STF(name, stop, opc, type) \
3621 static void glue(gen_, name)(DisasContext *ctx) \
3622 { \
3623 TCGv EA; \
3624 if (unlikely(!ctx->fpu_enabled)) { \
3625 gen_exception(ctx, POWERPC_EXCP_FPU); \
3626 return; \
3627 } \
3628 gen_set_access_type(ctx, ACCESS_FLOAT); \
3629 EA = tcg_temp_new(); \
3630 gen_addr_imm_index(ctx, EA, 0); \
3631 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3632 tcg_temp_free(EA); \
3633 }
3634
3635 #define GEN_STUF(name, stop, opc, type) \
3636 static void glue(gen_, name##u)(DisasContext *ctx) \
3637 { \
3638 TCGv EA; \
3639 if (unlikely(!ctx->fpu_enabled)) { \
3640 gen_exception(ctx, POWERPC_EXCP_FPU); \
3641 return; \
3642 } \
3643 if (unlikely(rA(ctx->opcode) == 0)) { \
3644 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3645 return; \
3646 } \
3647 gen_set_access_type(ctx, ACCESS_FLOAT); \
3648 EA = tcg_temp_new(); \
3649 gen_addr_imm_index(ctx, EA, 0); \
3650 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3651 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3652 tcg_temp_free(EA); \
3653 }
3654
3655 #define GEN_STUXF(name, stop, opc, type) \
3656 static void glue(gen_, name##ux)(DisasContext *ctx) \
3657 { \
3658 TCGv EA; \
3659 if (unlikely(!ctx->fpu_enabled)) { \
3660 gen_exception(ctx, POWERPC_EXCP_FPU); \
3661 return; \
3662 } \
3663 if (unlikely(rA(ctx->opcode) == 0)) { \
3664 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3665 return; \
3666 } \
3667 gen_set_access_type(ctx, ACCESS_FLOAT); \
3668 EA = tcg_temp_new(); \
3669 gen_addr_reg_index(ctx, EA); \
3670 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3671 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3672 tcg_temp_free(EA); \
3673 }
3674
3675 #define GEN_STXF(name, stop, opc2, opc3, type) \
3676 static void glue(gen_, name##x)(DisasContext *ctx) \
3677 { \
3678 TCGv EA; \
3679 if (unlikely(!ctx->fpu_enabled)) { \
3680 gen_exception(ctx, POWERPC_EXCP_FPU); \
3681 return; \
3682 } \
3683 gen_set_access_type(ctx, ACCESS_FLOAT); \
3684 EA = tcg_temp_new(); \
3685 gen_addr_reg_index(ctx, EA); \
3686 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3687 tcg_temp_free(EA); \
3688 }
3689
3690 #define GEN_STFS(name, stop, op, type) \
3691 GEN_STF(name, stop, op | 0x20, type); \
3692 GEN_STUF(name, stop, op | 0x21, type); \
3693 GEN_STUXF(name, stop, op | 0x01, type); \
3694 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3695
3696 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3697 {
3698 TCGv_i32 t0 = tcg_temp_new_i32();
3699 TCGv t1 = tcg_temp_new();
3700 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3701 tcg_gen_extu_i32_tl(t1, t0);
3702 tcg_temp_free_i32(t0);
3703 gen_qemu_st32(ctx, t1, arg2);
3704 tcg_temp_free(t1);
3705 }
3706
3707 /* stfd stfdu stfdux stfdx */
3708 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3709 /* stfs stfsu stfsux stfsx */
3710 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3711
3712 /* stfdp */
3713 static void gen_stfdp(DisasContext *ctx)
3714 {
3715 TCGv EA;
3716 if (unlikely(!ctx->fpu_enabled)) {
3717 gen_exception(ctx, POWERPC_EXCP_FPU);
3718 return;
3719 }
3720 gen_set_access_type(ctx, ACCESS_FLOAT);
3721 EA = tcg_temp_new();
3722 gen_addr_imm_index(ctx, EA, 0);
3723 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3724 64-bit byteswap already. */
3725 if (unlikely(ctx->le_mode)) {
3726 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3727 tcg_gen_addi_tl(EA, EA, 8);
3728 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3729 } else {
3730 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3731 tcg_gen_addi_tl(EA, EA, 8);
3732 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3733 }
3734 tcg_temp_free(EA);
3735 }
3736
3737 /* stfdpx */
3738 static void gen_stfdpx(DisasContext *ctx)
3739 {
3740 TCGv EA;
3741 if (unlikely(!ctx->fpu_enabled)) {
3742 gen_exception(ctx, POWERPC_EXCP_FPU);
3743 return;
3744 }
3745 gen_set_access_type(ctx, ACCESS_FLOAT);
3746 EA = tcg_temp_new();
3747 gen_addr_reg_index(ctx, EA);
3748 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3749 64-bit byteswap already. */
3750 if (unlikely(ctx->le_mode)) {
3751 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3752 tcg_gen_addi_tl(EA, EA, 8);
3753 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3754 } else {
3755 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3756 tcg_gen_addi_tl(EA, EA, 8);
3757 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3758 }
3759 tcg_temp_free(EA);
3760 }
3761
3762 /* Optional: */
3763 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3764 {
3765 TCGv t0 = tcg_temp_new();
3766 tcg_gen_trunc_i64_tl(t0, arg1),
3767 gen_qemu_st32(ctx, t0, arg2);
3768 tcg_temp_free(t0);
3769 }
3770 /* stfiwx */
3771 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3772
3773 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3774 {
3775 #if defined(TARGET_PPC64)
3776 if (ctx->has_cfar)
3777 tcg_gen_movi_tl(cpu_cfar, nip);
3778 #endif
3779 }
3780
3781 /*** Branch ***/
3782 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3783 {
3784 TranslationBlock *tb;
3785 tb = ctx->tb;
3786 if (NARROW_MODE(ctx)) {
3787 dest = (uint32_t) dest;
3788 }
3789 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3790 likely(!ctx->singlestep_enabled)) {
3791 tcg_gen_goto_tb(n);
3792 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3793 tcg_gen_exit_tb((uintptr_t)tb + n);
3794 } else {
3795 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3796 if (unlikely(ctx->singlestep_enabled)) {
3797 if ((ctx->singlestep_enabled &
3798 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3799 (ctx->exception == POWERPC_EXCP_BRANCH ||
3800 ctx->exception == POWERPC_EXCP_TRACE)) {
3801 target_ulong tmp = ctx->nip;
3802 ctx->nip = dest;
3803 gen_exception(ctx, POWERPC_EXCP_TRACE);
3804 ctx->nip = tmp;
3805 }
3806 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3807 gen_debug_exception(ctx);
3808 }
3809 }
3810 tcg_gen_exit_tb(0);
3811 }
3812 }
3813
3814 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3815 {
3816 if (NARROW_MODE(ctx)) {
3817 nip = (uint32_t)nip;
3818 }
3819 tcg_gen_movi_tl(cpu_lr, nip);
3820 }
3821
3822 /* b ba bl bla */
3823 static void gen_b(DisasContext *ctx)
3824 {
3825 target_ulong li, target;
3826
3827 ctx->exception = POWERPC_EXCP_BRANCH;
3828 /* sign extend LI */
3829 li = LI(ctx->opcode);
3830 li = (li ^ 0x02000000) - 0x02000000;
3831 if (likely(AA(ctx->opcode) == 0)) {
3832 target = ctx->nip + li - 4;
3833 } else {
3834 target = li;
3835 }
3836 if (LK(ctx->opcode)) {
3837 gen_setlr(ctx, ctx->nip);
3838 }
3839 gen_update_cfar(ctx, ctx->nip);
3840 gen_goto_tb(ctx, 0, target);
3841 }
3842
3843 #define BCOND_IM 0
3844 #define BCOND_LR 1
3845 #define BCOND_CTR 2
3846 #define BCOND_TAR 3
3847
3848 static inline void gen_bcond(DisasContext *ctx, int type)
3849 {
3850 uint32_t bo = BO(ctx->opcode);
3851 int l1;
3852 TCGv target;
3853
3854 ctx->exception = POWERPC_EXCP_BRANCH;
3855 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3856 target = tcg_temp_local_new();
3857 if (type == BCOND_CTR)
3858 tcg_gen_mov_tl(target, cpu_ctr);
3859 else if (type == BCOND_TAR)
3860 gen_load_spr(target, SPR_TAR);
3861 else
3862 tcg_gen_mov_tl(target, cpu_lr);
3863 } else {
3864 TCGV_UNUSED(target);
3865 }
3866 if (LK(ctx->opcode))
3867 gen_setlr(ctx, ctx->nip);
3868 l1 = gen_new_label();
3869 if ((bo & 0x4) == 0) {
3870 /* Decrement and test CTR */
3871 TCGv temp = tcg_temp_new();
3872 if (unlikely(type == BCOND_CTR)) {
3873 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3874 return;
3875 }
3876 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3877 if (NARROW_MODE(ctx)) {
3878 tcg_gen_ext32u_tl(temp, cpu_ctr);
3879 } else {
3880 tcg_gen_mov_tl(temp, cpu_ctr);
3881 }
3882 if (bo & 0x2) {
3883 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3884 } else {
3885 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3886 }
3887 tcg_temp_free(temp);
3888 }
3889 if ((bo & 0x10) == 0) {
3890 /* Test CR */
3891 uint32_t bi = BI(ctx->opcode);
3892 uint32_t mask = 1 << (3 - (bi & 0x03));
3893 TCGv_i32 temp = tcg_temp_new_i32();
3894
3895 if (bo & 0x8) {
3896 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3897 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3898 } else {
3899 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3900 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3901 }
3902 tcg_temp_free_i32(temp);
3903 }
3904 gen_update_cfar(ctx, ctx->nip);
3905 if (type == BCOND_IM) {
3906 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3907 if (likely(AA(ctx->opcode) == 0)) {
3908 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3909 } else {
3910 gen_goto_tb(ctx, 0, li);
3911 }
3912 gen_set_label(l1);
3913 gen_goto_tb(ctx, 1, ctx->nip);
3914 } else {
3915 if (NARROW_MODE(ctx)) {
3916 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3917 } else {
3918 tcg_gen_andi_tl(cpu_nip, target, ~3);
3919 }
3920 tcg_gen_exit_tb(0);
3921 gen_set_label(l1);
3922 gen_update_nip(ctx, ctx->nip);
3923 tcg_gen_exit_tb(0);
3924 }
3925 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3926 tcg_temp_free(target);
3927 }
3928 }
3929
3930 static void gen_bc(DisasContext *ctx)
3931 {
3932 gen_bcond(ctx, BCOND_IM);
3933 }
3934
3935 static void gen_bcctr(DisasContext *ctx)
3936 {
3937 gen_bcond(ctx, BCOND_CTR);
3938 }
3939
3940 static void gen_bclr(DisasContext *ctx)
3941 {
3942 gen_bcond(ctx, BCOND_LR);
3943 }
3944
3945 static void gen_bctar(DisasContext *ctx)
3946 {
3947 gen_bcond(ctx, BCOND_TAR);
3948 }
3949
3950 /*** Condition register logical ***/
3951 #define GEN_CRLOGIC(name, tcg_op, opc) \
3952 static void glue(gen_, name)(DisasContext *ctx) \
3953 { \
3954 uint8_t bitmask; \
3955 int sh; \
3956 TCGv_i32 t0, t1; \
3957 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3958 t0 = tcg_temp_new_i32(); \
3959 if (sh > 0) \
3960 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3961 else if (sh < 0) \
3962 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3963 else \
3964 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3965 t1 = tcg_temp_new_i32(); \
3966 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3967 if (sh > 0) \
3968 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3969 else if (sh < 0) \
3970 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3971 else \
3972 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3973 tcg_op(t0, t0, t1); \
3974 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3975 tcg_gen_andi_i32(t0, t0, bitmask); \
3976 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3977 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3978 tcg_temp_free_i32(t0); \
3979 tcg_temp_free_i32(t1); \
3980 }
3981
3982 /* crand */
3983 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3984 /* crandc */
3985 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3986 /* creqv */
3987 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3988 /* crnand */
3989 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3990 /* crnor */
3991 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3992 /* cror */
3993 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3994 /* crorc */
3995 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3996 /* crxor */
3997 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3998
3999 /* mcrf */
4000 static void gen_mcrf(DisasContext *ctx)
4001 {
4002 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4003 }
4004
4005 /*** System linkage ***/
4006
4007 /* rfi (mem_idx only) */
4008 static void gen_rfi(DisasContext *ctx)
4009 {
4010 #if defined(CONFIG_USER_ONLY)
4011 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4012 #else
4013 /* Restore CPU state */
4014 if (unlikely(!ctx->mem_idx)) {
4015 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4016 return;
4017 }
4018 gen_update_cfar(ctx, ctx->nip);
4019 gen_helper_rfi(cpu_env);
4020 gen_sync_exception(ctx);
4021 #endif
4022 }
4023
4024 #if defined(TARGET_PPC64)
4025 static void gen_rfid(DisasContext *ctx)
4026 {
4027 #if defined(CONFIG_USER_ONLY)
4028 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4029 #else
4030 /* Restore CPU state */
4031 if (unlikely(!ctx->mem_idx)) {
4032 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4033 return;
4034 }
4035 gen_update_cfar(ctx, ctx->nip);
4036 gen_helper_rfid(cpu_env);
4037 gen_sync_exception(ctx);
4038 #endif
4039 }
4040
4041 static void gen_hrfid(DisasContext *ctx)
4042 {
4043 #if defined(CONFIG_USER_ONLY)
4044 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4045 #else
4046 /* Restore CPU state */
4047 if (unlikely(ctx->mem_idx <= 1)) {
4048 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4049 return;
4050 }
4051 gen_helper_hrfid(cpu_env);
4052 gen_sync_exception(ctx);
4053 #endif
4054 }
4055 #endif
4056
4057 /* sc */
4058 #if defined(CONFIG_USER_ONLY)
4059 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4060 #else
4061 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4062 #endif
4063 static void gen_sc(DisasContext *ctx)
4064 {
4065 uint32_t lev;
4066
4067 lev = (ctx->opcode >> 5) & 0x7F;
4068 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4069 }
4070
4071 /*** Trap ***/
4072
4073 /* tw */
4074 static void gen_tw(DisasContext *ctx)
4075 {
4076 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4077 /* Update the nip since this might generate a trap exception */
4078 gen_update_nip(ctx, ctx->nip);
4079 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4080 t0);
4081 tcg_temp_free_i32(t0);
4082 }
4083
4084 /* twi */
4085 static void gen_twi(DisasContext *ctx)
4086 {
4087 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4088 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4089 /* Update the nip since this might generate a trap exception */
4090 gen_update_nip(ctx, ctx->nip);
4091 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4092 tcg_temp_free(t0);
4093 tcg_temp_free_i32(t1);
4094 }
4095
4096 #if defined(TARGET_PPC64)
4097 /* td */
4098 static void gen_td(DisasContext *ctx)
4099 {
4100 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4101 /* Update the nip since this might generate a trap exception */
4102 gen_update_nip(ctx, ctx->nip);
4103 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4104 t0);
4105 tcg_temp_free_i32(t0);
4106 }
4107
4108 /* tdi */
4109 static void gen_tdi(DisasContext *ctx)
4110 {
4111 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4112 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4113 /* Update the nip since this might generate a trap exception */
4114 gen_update_nip(ctx, ctx->nip);
4115 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4116 tcg_temp_free(t0);
4117 tcg_temp_free_i32(t1);
4118 }
4119 #endif
4120
4121 /*** Processor control ***/
4122
4123 static void gen_read_xer(TCGv dst)
4124 {
4125 TCGv t0 = tcg_temp_new();
4126 TCGv t1 = tcg_temp_new();
4127 TCGv t2 = tcg_temp_new();
4128 tcg_gen_mov_tl(dst, cpu_xer);
4129 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4130 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4131 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4132 tcg_gen_or_tl(t0, t0, t1);
4133 tcg_gen_or_tl(dst, dst, t2);
4134 tcg_gen_or_tl(dst, dst, t0);
4135 tcg_temp_free(t0);
4136 tcg_temp_free(t1);
4137 tcg_temp_free(t2);
4138 }
4139
4140 static void gen_write_xer(TCGv src)
4141 {
4142 tcg_gen_andi_tl(cpu_xer, src,
4143 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4144 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4145 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4146 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4147 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4148 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4149 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4150 }
4151
4152 /* mcrxr */
4153 static void gen_mcrxr(DisasContext *ctx)
4154 {
4155 TCGv_i32 t0 = tcg_temp_new_i32();
4156 TCGv_i32 t1 = tcg_temp_new_i32();
4157 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4158
4159 tcg_gen_trunc_tl_i32(t0, cpu_so);
4160 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4161 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4162 tcg_gen_shli_i32(t0, t0, 3);
4163 tcg_gen_shli_i32(t1, t1, 2);
4164 tcg_gen_shli_i32(dst, dst, 1);
4165 tcg_gen_or_i32(dst, dst, t0);
4166 tcg_gen_or_i32(dst, dst, t1);
4167 tcg_temp_free_i32(t0);
4168 tcg_temp_free_i32(t1);
4169
4170 tcg_gen_movi_tl(cpu_so, 0);
4171 tcg_gen_movi_tl(cpu_ov, 0);
4172 tcg_gen_movi_tl(cpu_ca, 0);
4173 }
4174
4175 /* mfcr mfocrf */
4176 static void gen_mfcr(DisasContext *ctx)
4177 {
4178 uint32_t crm, crn;
4179
4180 if (likely(ctx->opcode & 0x00100000)) {
4181 crm = CRM(ctx->opcode);
4182 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4183 crn = ctz32 (crm);
4184 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4185 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4186 cpu_gpr[rD(ctx->opcode)], crn * 4);
4187 }
4188 } else {
4189 TCGv_i32 t0 = tcg_temp_new_i32();
4190 tcg_gen_mov_i32(t0, cpu_crf[0]);
4191 tcg_gen_shli_i32(t0, t0, 4);
4192 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4193 tcg_gen_shli_i32(t0, t0, 4);
4194 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4195 tcg_gen_shli_i32(t0, t0, 4);
4196 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4197 tcg_gen_shli_i32(t0, t0, 4);
4198 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4199 tcg_gen_shli_i32(t0, t0, 4);
4200 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4201 tcg_gen_shli_i32(t0, t0, 4);
4202 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4203 tcg_gen_shli_i32(t0, t0, 4);
4204 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4205 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4206 tcg_temp_free_i32(t0);
4207 }
4208 }
4209
4210 /* mfmsr */
4211 static void gen_mfmsr(DisasContext *ctx)
4212 {
4213 #if defined(CONFIG_USER_ONLY)
4214 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4215 #else
4216 if (unlikely(!ctx->mem_idx)) {
4217 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4218 return;
4219 }
4220 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4221 #endif
4222 }
4223
4224 static void spr_noaccess(void *opaque, int gprn, int sprn)
4225 {
4226 #if 0
4227 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4228 printf("ERROR: try to access SPR %d !\n", sprn);
4229 #endif
4230 }
4231 #define SPR_NOACCESS (&spr_noaccess)
4232
4233 /* mfspr */
4234 static inline void gen_op_mfspr(DisasContext *ctx)
4235 {
4236 void (*read_cb)(void *opaque, int gprn, int sprn);
4237 uint32_t sprn = SPR(ctx->opcode);
4238
4239 #if !defined(CONFIG_USER_ONLY)
4240 if (ctx->mem_idx == 2)
4241 read_cb = ctx->spr_cb[sprn].hea_read;
4242 else if (ctx->mem_idx)
4243 read_cb = ctx->spr_cb[sprn].oea_read;
4244 else
4245 #endif
4246 read_cb = ctx->spr_cb[sprn].uea_read;
4247 if (likely(read_cb != NULL)) {
4248 if (likely(read_cb != SPR_NOACCESS)) {
4249 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4250 } else {
4251 /* Privilege exception */
4252 /* This is a hack to avoid warnings when running Linux:
4253 * this OS breaks the PowerPC virtualisation model,
4254 * allowing userland application to read the PVR
4255 */
4256 if (sprn != SPR_PVR) {
4257 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4258 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4259 printf("Trying to read privileged spr %d (0x%03x) at "
4260 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4261 }
4262 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4263 }
4264 } else {
4265 /* Not defined */
4266 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4267 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4268 printf("Trying to read invalid spr %d (0x%03x) at "
4269 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4270 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4271 }
4272 }
4273
4274 static void gen_mfspr(DisasContext *ctx)
4275 {
4276 gen_op_mfspr(ctx);
4277 }
4278
4279 /* mftb */
4280 static void gen_mftb(DisasContext *ctx)
4281 {
4282 gen_op_mfspr(ctx);
4283 }
4284
4285 /* mtcrf mtocrf*/
4286 static void gen_mtcrf(DisasContext *ctx)
4287 {
4288 uint32_t crm, crn;
4289
4290 crm = CRM(ctx->opcode);
4291 if (likely((ctx->opcode & 0x00100000))) {
4292 if (crm && ((crm & (crm - 1)) == 0)) {
4293 TCGv_i32 temp = tcg_temp_new_i32();
4294 crn = ctz32 (crm);
4295 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4296 tcg_gen_shri_i32(temp, temp, crn * 4);
4297 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4298 tcg_temp_free_i32(temp);
4299 }
4300 } else {
4301 TCGv_i32 temp = tcg_temp_new_i32();
4302 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4303 for (crn = 0 ; crn < 8 ; crn++) {
4304 if (crm & (1 << crn)) {
4305 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4306 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4307 }
4308 }
4309 tcg_temp_free_i32(temp);
4310 }
4311 }
4312
4313 /* mtmsr */
4314 #if defined(TARGET_PPC64)
4315 static void gen_mtmsrd(DisasContext *ctx)
4316 {
4317 #if defined(CONFIG_USER_ONLY)
4318 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4319 #else
4320 if (unlikely(!ctx->mem_idx)) {
4321 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4322 return;
4323 }
4324 if (ctx->opcode & 0x00010000) {
4325 /* Special form that does not need any synchronisation */
4326 TCGv t0 = tcg_temp_new();
4327 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4328 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4329 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4330 tcg_temp_free(t0);
4331 } else {
4332 /* XXX: we need to update nip before the store
4333 * if we enter power saving mode, we will exit the loop
4334 * directly from ppc_store_msr
4335 */
4336 gen_update_nip(ctx, ctx->nip);
4337 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4338 /* Must stop the translation as machine state (may have) changed */
4339 /* Note that mtmsr is not always defined as context-synchronizing */
4340 gen_stop_exception(ctx);
4341 }
4342 #endif
4343 }
4344 #endif
4345
4346 static void gen_mtmsr(DisasContext *ctx)
4347 {
4348 #if defined(CONFIG_USER_ONLY)
4349 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4350 #else
4351 if (unlikely(!ctx->mem_idx)) {
4352 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4353 return;
4354 }
4355 if (ctx->opcode & 0x00010000) {
4356 /* Special form that does not need any synchronisation */
4357 TCGv t0 = tcg_temp_new();
4358 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4359 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4360 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4361 tcg_temp_free(t0);
4362 } else {
4363 TCGv msr = tcg_temp_new();
4364
4365 /* XXX: we need to update nip before the store
4366 * if we enter power saving mode, we will exit the loop
4367 * directly from ppc_store_msr
4368 */
4369 gen_update_nip(ctx, ctx->nip);
4370 #if defined(TARGET_PPC64)
4371 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4372 #else
4373 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4374 #endif
4375 gen_helper_store_msr(cpu_env, msr);
4376 tcg_temp_free(msr);
4377 /* Must stop the translation as machine state (may have) changed */
4378 /* Note that mtmsr is not always defined as context-synchronizing */
4379 gen_stop_exception(ctx);
4380 }
4381 #endif
4382 }
4383
4384 /* mtspr */
4385 static void gen_mtspr(DisasContext *ctx)
4386 {
4387 void (*write_cb)(void *opaque, int sprn, int gprn);
4388 uint32_t sprn = SPR(ctx->opcode);
4389
4390 #if !defined(CONFIG_USER_ONLY)
4391 if (ctx->mem_idx == 2)
4392 write_cb = ctx->spr_cb[sprn].hea_write;
4393 else if (ctx->mem_idx)
4394 write_cb = ctx->spr_cb[sprn].oea_write;
4395 else
4396 #endif
4397 write_cb = ctx->spr_cb[sprn].uea_write;
4398 if (likely(write_cb != NULL)) {
4399 if (likely(write_cb != SPR_NOACCESS)) {
4400 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4401 } else {
4402 /* Privilege exception */
4403 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4404 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4405 printf("Trying to write privileged spr %d (0x%03x) at "
4406 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4407 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4408 }
4409 } else {
4410 /* Not defined */
4411 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4412 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4413 printf("Trying to write invalid spr %d (0x%03x) at "
4414 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4415 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4416 }
4417 }
4418
4419 /*** Cache management ***/
4420
4421 /* dcbf */
4422 static void gen_dcbf(DisasContext *ctx)
4423 {
4424 /* XXX: specification says this is treated as a load by the MMU */
4425 TCGv t0;
4426 gen_set_access_type(ctx, ACCESS_CACHE);
4427 t0 = tcg_temp_new();
4428 gen_addr_reg_index(ctx, t0);
4429 gen_qemu_ld8u(ctx, t0, t0);
4430 tcg_temp_free(t0);
4431 }
4432
4433 /* dcbi (Supervisor only) */
4434 static void gen_dcbi(DisasContext *ctx)
4435 {
4436 #if defined(CONFIG_USER_ONLY)
4437 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4438 #else
4439 TCGv EA, val;
4440 if (unlikely(!ctx->mem_idx)) {
4441 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4442 return;
4443 }
4444 EA = tcg_temp_new();
4445 gen_set_access_type(ctx, ACCESS_CACHE);
4446 gen_addr_reg_index(ctx, EA);
4447 val = tcg_temp_new();
4448 /* XXX: specification says this should be treated as a store by the MMU */
4449 gen_qemu_ld8u(ctx, val, EA);
4450 gen_qemu_st8(ctx, val, EA);
4451 tcg_temp_free(val);
4452 tcg_temp_free(EA);
4453 #endif
4454 }
4455
4456 /* dcdst */
4457 static void gen_dcbst(DisasContext *ctx)
4458 {
4459 /* XXX: specification say this is treated as a load by the MMU */
4460 TCGv t0;
4461 gen_set_access_type(ctx, ACCESS_CACHE);
4462 t0 = tcg_temp_new();
4463 gen_addr_reg_index(ctx, t0);
4464 gen_qemu_ld8u(ctx, t0, t0);
4465 tcg_temp_free(t0);
4466 }
4467
4468 /* dcbt */
4469 static void gen_dcbt(DisasContext *ctx)
4470 {
4471 /* interpreted as no-op */
4472 /* XXX: specification say this is treated as a load by the MMU
4473 * but does not generate any exception
4474 */
4475 }
4476
4477 /* dcbtst */
4478 static void gen_dcbtst(DisasContext *ctx)
4479 {
4480 /* interpreted as no-op */
4481 /* XXX: specification say this is treated as a load by the MMU
4482 * but does not generate any exception
4483 */
4484 }
4485
4486 /* dcbtls */
4487 static void gen_dcbtls(DisasContext *ctx)
4488 {
4489 /* Always fails locking the cache */
4490 TCGv t0 = tcg_temp_new();
4491 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4492 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4493 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4494 tcg_temp_free(t0);
4495 }
4496
4497 /* dcbz */
4498 static void gen_dcbz(DisasContext *ctx)
4499 {
4500 TCGv tcgv_addr;
4501 TCGv_i32 tcgv_is_dcbzl;
4502 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4503
4504 gen_set_access_type(ctx, ACCESS_CACHE);
4505 /* NIP cannot be restored if the memory exception comes from an helper */
4506 gen_update_nip(ctx, ctx->nip - 4);
4507 tcgv_addr = tcg_temp_new();
4508 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4509
4510 gen_addr_reg_index(ctx, tcgv_addr);
4511 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4512
4513 tcg_temp_free(tcgv_addr);
4514 tcg_temp_free_i32(tcgv_is_dcbzl);
4515 }
4516
4517 /* dst / dstt */
4518 static void gen_dst(DisasContext *ctx)
4519 {
4520 if (rA(ctx->opcode) == 0) {
4521 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4522 } else {
4523 /* interpreted as no-op */
4524 }
4525 }
4526
4527 /* dstst /dststt */
4528 static void gen_dstst(DisasContext *ctx)
4529 {
4530 if (rA(ctx->opcode) == 0) {
4531 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4532 } else {
4533 /* interpreted as no-op */
4534 }
4535
4536 }
4537
4538 /* dss / dssall */
4539 static void gen_dss(DisasContext *ctx)
4540 {
4541 /* interpreted as no-op */
4542 }
4543
4544 /* icbi */
4545 static void gen_icbi(DisasContext *ctx)
4546 {
4547 TCGv t0;
4548 gen_set_access_type(ctx, ACCESS_CACHE);
4549 /* NIP cannot be restored if the memory exception comes from an helper */
4550 gen_update_nip(ctx, ctx->nip - 4);
4551 t0 = tcg_temp_new();
4552 gen_addr_reg_index(ctx, t0);
4553 gen_helper_icbi(cpu_env, t0);
4554 tcg_temp_free(t0);
4555 }
4556
4557 /* Optional: */
4558 /* dcba */
4559 static void gen_dcba(DisasContext *ctx)
4560 {
4561 /* interpreted as no-op */
4562 /* XXX: specification say this is treated as a store by the MMU
4563 * but does not generate any exception
4564 */
4565 }
4566
4567 /*** Segment register manipulation ***/
4568 /* Supervisor only: */
4569
4570 /* mfsr */
4571 static void gen_mfsr(DisasContext *ctx)
4572 {
4573 #if defined(CONFIG_USER_ONLY)
4574 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4575 #else
4576 TCGv t0;
4577 if (unlikely(!ctx->mem_idx)) {
4578 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4579 return;
4580 }
4581 t0 = tcg_const_tl(SR(ctx->opcode));
4582 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4583 tcg_temp_free(t0);
4584 #endif
4585 }
4586
4587 /* mfsrin */
4588 static void gen_mfsrin(DisasContext *ctx)
4589 {
4590 #if defined(CONFIG_USER_ONLY)
4591 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4592 #else
4593 TCGv t0;
4594 if (unlikely(!ctx->mem_idx)) {
4595 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4596 return;
4597 }
4598 t0 = tcg_temp_new();
4599 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4600 tcg_gen_andi_tl(t0, t0, 0xF);
4601 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4602 tcg_temp_free(t0);
4603 #endif
4604 }
4605
4606 /* mtsr */
4607 static void gen_mtsr(DisasContext *ctx)
4608 {
4609 #if defined(CONFIG_USER_ONLY)
4610 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4611 #else
4612 TCGv t0;
4613 if (unlikely(!ctx->mem_idx)) {
4614 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4615 return;
4616 }
4617 t0 = tcg_const_tl(SR(ctx->opcode));
4618 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4619 tcg_temp_free(t0);
4620 #endif
4621 }
4622
4623 /* mtsrin */
4624 static void gen_mtsrin(DisasContext *ctx)
4625 {
4626 #if defined(CONFIG_USER_ONLY)
4627 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4628 #else
4629 TCGv t0;
4630 if (unlikely(!ctx->mem_idx)) {
4631 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4632 return;
4633 }
4634 t0 = tcg_temp_new();
4635 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4636 tcg_gen_andi_tl(t0, t0, 0xF);
4637 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4638 tcg_temp_free(t0);
4639 #endif
4640 }
4641
4642 #if defined(TARGET_PPC64)
4643 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4644
4645 /* mfsr */
4646 static void gen_mfsr_64b(DisasContext *ctx)
4647 {
4648 #if defined(CONFIG_USER_ONLY)
4649 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4650 #else
4651 TCGv t0;
4652 if (unlikely(!ctx->mem_idx)) {
4653 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4654 return;
4655 }
4656 t0 = tcg_const_tl(SR(ctx->opcode));
4657 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4658 tcg_temp_free(t0);
4659 #endif
4660 }
4661
4662 /* mfsrin */
4663 static void gen_mfsrin_64b(DisasContext *ctx)
4664 {
4665 #if defined(CONFIG_USER_ONLY)
4666 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4667 #else
4668 TCGv t0;
4669 if (unlikely(!ctx->mem_idx)) {
4670 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4671 return;
4672 }
4673 t0 = tcg_temp_new();
4674 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4675 tcg_gen_andi_tl(t0, t0, 0xF);
4676 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4677 tcg_temp_free(t0);
4678 #endif
4679 }
4680
4681 /* mtsr */
4682 static void gen_mtsr_64b(DisasContext *ctx)
4683 {
4684 #if defined(CONFIG_USER_ONLY)
4685 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4686 #else
4687 TCGv t0;
4688 if (unlikely(!ctx->mem_idx)) {
4689 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4690 return;
4691 }
4692 t0 = tcg_const_tl(SR(ctx->opcode));
4693 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4694 tcg_temp_free(t0);
4695 #endif
4696 }
4697
4698 /* mtsrin */
4699 static void gen_mtsrin_64b(DisasContext *ctx)
4700 {
4701 #if defined(CONFIG_USER_ONLY)
4702 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4703 #else
4704 TCGv t0;
4705 if (unlikely(!ctx->mem_idx)) {
4706 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4707 return;
4708 }
4709 t0 = tcg_temp_new();
4710 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4711 tcg_gen_andi_tl(t0, t0, 0xF);
4712 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4713 tcg_temp_free(t0);
4714 #endif
4715 }
4716
4717 /* slbmte */
4718 static void gen_slbmte(DisasContext *ctx)
4719 {
4720 #if defined(CONFIG_USER_ONLY)
4721 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4722 #else
4723 if (unlikely(!ctx->mem_idx)) {
4724 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4725 return;
4726 }
4727 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4728 cpu_gpr[rS(ctx->opcode)]);
4729 #endif
4730 }
4731
4732 static void gen_slbmfee(DisasContext *ctx)
4733 {
4734 #if defined(CONFIG_USER_ONLY)
4735 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4736 #else
4737 if (unlikely(!ctx->mem_idx)) {
4738 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4739 return;
4740 }
4741 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4742 cpu_gpr[rB(ctx->opcode)]);
4743 #endif
4744 }
4745
4746 static void gen_slbmfev(DisasContext *ctx)
4747 {
4748 #if defined(CONFIG_USER_ONLY)
4749 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4750 #else
4751 if (unlikely(!ctx->mem_idx)) {
4752 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4753 return;
4754 }
4755 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4756 cpu_gpr[rB(ctx->opcode)]);
4757 #endif
4758 }
4759 #endif /* defined(TARGET_PPC64) */
4760
4761 /*** Lookaside buffer management ***/
4762 /* Optional & mem_idx only: */
4763
4764 /* tlbia */
4765 static void gen_tlbia(DisasContext *ctx)
4766 {
4767 #if defined(CONFIG_USER_ONLY)
4768 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4769 #else
4770 if (unlikely(!ctx->mem_idx)) {
4771 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4772 return;
4773 }
4774 gen_helper_tlbia(cpu_env);
4775 #endif
4776 }
4777
4778 /* tlbiel */
4779 static void gen_tlbiel(DisasContext *ctx)
4780 {
4781 #if defined(CONFIG_USER_ONLY)
4782 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4783 #else
4784 if (unlikely(!ctx->mem_idx)) {
4785 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4786 return;
4787 }
4788 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4789 #endif
4790 }
4791
4792 /* tlbie */
4793 static void gen_tlbie(DisasContext *ctx)
4794 {
4795 #if defined(CONFIG_USER_ONLY)
4796 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4797 #else
4798 if (unlikely(!ctx->mem_idx)) {
4799 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4800 return;
4801 }
4802 if (NARROW_MODE(ctx)) {
4803 TCGv t0 = tcg_temp_new();
4804 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4805 gen_helper_tlbie(cpu_env, t0);
4806 tcg_temp_free(t0);
4807 } else {
4808 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4809 }
4810 #endif
4811 }
4812
4813 /* tlbsync */
4814 static void gen_tlbsync(DisasContext *ctx)
4815 {
4816 #if defined(CONFIG_USER_ONLY)
4817 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4818 #else
4819 if (unlikely(!ctx->mem_idx)) {
4820 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4821 return;
4822 }
4823 /* This has no effect: it should ensure that all previous
4824 * tlbie have completed
4825 */
4826 gen_stop_exception(ctx);
4827 #endif
4828 }
4829
4830 #if defined(TARGET_PPC64)
4831 /* slbia */
4832 static void gen_slbia(DisasContext *ctx)
4833 {
4834 #if defined(CONFIG_USER_ONLY)
4835 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4836 #else
4837 if (unlikely(!ctx->mem_idx)) {
4838 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4839 return;
4840 }
4841 gen_helper_slbia(cpu_env);
4842 #endif
4843 }
4844
4845 /* slbie */
4846 static void gen_slbie(DisasContext *ctx)
4847 {
4848 #if defined(CONFIG_USER_ONLY)
4849 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4850 #else
4851 if (unlikely(!ctx->mem_idx)) {
4852 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4853 return;
4854 }
4855 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4856 #endif
4857 }
4858 #endif
4859
4860 /*** External control ***/
4861 /* Optional: */
4862
4863 /* eciwx */
4864 static void gen_eciwx(DisasContext *ctx)
4865 {
4866 TCGv t0;
4867 /* Should check EAR[E] ! */
4868 gen_set_access_type(ctx, ACCESS_EXT);
4869 t0 = tcg_temp_new();
4870 gen_addr_reg_index(ctx, t0);
4871 gen_check_align(ctx, t0, 0x03);
4872 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4873 tcg_temp_free(t0);
4874 }
4875
4876 /* ecowx */
4877 static void gen_ecowx(DisasContext *ctx)
4878 {
4879 TCGv t0;
4880 /* Should check EAR[E] ! */
4881 gen_set_access_type(ctx, ACCESS_EXT);
4882 t0 = tcg_temp_new();
4883 gen_addr_reg_index(ctx, t0);
4884 gen_check_align(ctx, t0, 0x03);
4885 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4886 tcg_temp_free(t0);
4887 }
4888
4889 /* PowerPC 601 specific instructions */
4890
4891 /* abs - abs. */
4892 static void gen_abs(DisasContext *ctx)
4893 {
4894 int l1 = gen_new_label();
4895 int l2 = gen_new_label();
4896 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4897 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4898 tcg_gen_br(l2);
4899 gen_set_label(l1);
4900 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4901 gen_set_label(l2);
4902 if (unlikely(Rc(ctx->opcode) != 0))
4903 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4904 }
4905
4906 /* abso - abso. */
4907 static void gen_abso(DisasContext *ctx)
4908 {
4909 int l1 = gen_new_label();
4910 int l2 = gen_new_label();
4911 int l3 = gen_new_label();
4912 /* Start with XER OV disabled, the most likely case */
4913 tcg_gen_movi_tl(cpu_ov, 0);
4914 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4915 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4916 tcg_gen_movi_tl(cpu_ov, 1);
4917 tcg_gen_movi_tl(cpu_so, 1);
4918 tcg_gen_br(l2);
4919 gen_set_label(l1);
4920 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4921 tcg_gen_br(l3);
4922 gen_set_label(l2);
4923 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4924 gen_set_label(l3);
4925 if (unlikely(Rc(ctx->opcode) != 0))
4926 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4927 }
4928
4929 /* clcs */
4930 static void gen_clcs(DisasContext *ctx)
4931 {
4932 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4933 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4934 tcg_temp_free_i32(t0);
4935 /* Rc=1 sets CR0 to an undefined state */
4936 }
4937
4938 /* div - div. */
4939 static void gen_div(DisasContext *ctx)
4940 {
4941 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4942 cpu_gpr[rB(ctx->opcode)]);
4943 if (unlikely(Rc(ctx->opcode) != 0))
4944 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4945 }
4946
4947 /* divo - divo. */
4948 static void gen_divo(DisasContext *ctx)
4949 {
4950 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4951 cpu_gpr[rB(ctx->opcode)]);
4952 if (unlikely(Rc(ctx->opcode) != 0))
4953 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4954 }
4955
4956 /* divs - divs. */
4957 static void gen_divs(DisasContext *ctx)
4958 {
4959 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4960 cpu_gpr[rB(ctx->opcode)]);
4961 if (unlikely(Rc(ctx->opcode) != 0))
4962 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4963 }
4964
4965 /* divso - divso. */
4966 static void gen_divso(DisasContext *ctx)
4967 {
4968 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4969 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4970 if (unlikely(Rc(ctx->opcode) != 0))
4971 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4972 }
4973
4974 /* doz - doz. */
4975 static void gen_doz(DisasContext *ctx)
4976 {
4977 int l1 = gen_new_label();
4978 int l2 = gen_new_label();
4979 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4980 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4981 tcg_gen_br(l2);
4982 gen_set_label(l1);
4983 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4984 gen_set_label(l2);
4985 if (unlikely(Rc(ctx->opcode) != 0))
4986 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4987 }
4988
4989 /* dozo - dozo. */
4990 static void gen_dozo(DisasContext *ctx)
4991 {
4992 int l1 = gen_new_label();
4993 int l2 = gen_new_label();
4994 TCGv t0 = tcg_temp_new();
4995 TCGv t1 = tcg_temp_new();
4996 TCGv t2 = tcg_temp_new();
4997 /* Start with XER OV disabled, the most likely case */
4998 tcg_gen_movi_tl(cpu_ov, 0);
4999 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5000 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5001 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5002 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5003 tcg_gen_andc_tl(t1, t1, t2);
5004 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5005 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5006 tcg_gen_movi_tl(cpu_ov, 1);
5007 tcg_gen_movi_tl(cpu_so, 1);
5008 tcg_gen_br(l2);
5009 gen_set_label(l1);
5010 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5011 gen_set_label(l2);
5012 tcg_temp_free(t0);
5013 tcg_temp_free(t1);
5014 tcg_temp_free(t2);
5015 if (unlikely(Rc(ctx->opcode) != 0))
5016 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5017 }
5018
5019 /* dozi */
5020 static void gen_dozi(DisasContext *ctx)
5021 {
5022 target_long simm = SIMM(ctx->opcode);
5023 int l1 = gen_new_label();
5024 int l2 = gen_new_label();
5025 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5026 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5027 tcg_gen_br(l2);
5028 gen_set_label(l1);
5029 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5030 gen_set_label(l2);
5031 if (unlikely(Rc(ctx->opcode) != 0))
5032 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5033 }
5034
5035 /* lscbx - lscbx. */
5036 static void gen_lscbx(DisasContext *ctx)
5037 {
5038 TCGv t0 = tcg_temp_new();
5039 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5040 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5041 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5042
5043 gen_addr_reg_index(ctx, t0);
5044 /* NIP cannot be restored if the memory exception comes from an helper */
5045 gen_update_nip(ctx, ctx->nip - 4);
5046 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5047 tcg_temp_free_i32(t1);
5048 tcg_temp_free_i32(t2);
5049 tcg_temp_free_i32(t3);
5050 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5051 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5052 if (unlikely(Rc(ctx->opcode) != 0))
5053 gen_set_Rc0(ctx, t0);
5054 tcg_temp_free(t0);
5055 }
5056
5057 /* maskg - maskg. */
5058 static void gen_maskg(DisasContext *ctx)
5059 {
5060 int l1 = gen_new_label();
5061 TCGv t0 = tcg_temp_new();
5062 TCGv t1 = tcg_temp_new();
5063 TCGv t2 = tcg_temp_new();
5064 TCGv t3 = tcg_temp_new();
5065 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5066 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5067 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5068 tcg_gen_addi_tl(t2, t0, 1);
5069 tcg_gen_shr_tl(t2, t3, t2);
5070 tcg_gen_shr_tl(t3, t3, t1);
5071 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5072 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5073 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5074 gen_set_label(l1);
5075 tcg_temp_free(t0);
5076 tcg_temp_free(t1);
5077 tcg_temp_free(t2);
5078 tcg_temp_free(t3);
5079 if (unlikely(Rc(ctx->opcode) != 0))
5080 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5081 }
5082
5083 /* maskir - maskir. */
5084 static void gen_maskir(DisasContext *ctx)
5085 {
5086 TCGv t0 = tcg_temp_new();
5087 TCGv t1 = tcg_temp_new();
5088 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5089 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5090 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5091 tcg_temp_free(t0);
5092 tcg_temp_free(t1);
5093 if (unlikely(Rc(ctx->opcode) != 0))
5094 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5095 }
5096
5097 /* mul - mul. */
5098 static void gen_mul(DisasContext *ctx)
5099 {
5100 TCGv_i64 t0 = tcg_temp_new_i64();
5101 TCGv_i64 t1 = tcg_temp_new_i64();
5102 TCGv t2 = tcg_temp_new();
5103 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5104 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5105 tcg_gen_mul_i64(t0, t0, t1);
5106 tcg_gen_trunc_i64_tl(t2, t0);
5107 gen_store_spr(SPR_MQ, t2);
5108 tcg_gen_shri_i64(t1, t0, 32);
5109 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5110 tcg_temp_free_i64(t0);
5111 tcg_temp_free_i64(t1);
5112 tcg_temp_free(t2);
5113 if (unlikely(Rc(ctx->opcode) != 0))
5114 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5115 }
5116
5117 /* mulo - mulo. */
5118 static void gen_mulo(DisasContext *ctx)
5119 {
5120 int l1 = gen_new_label();
5121 TCGv_i64 t0 = tcg_temp_new_i64();
5122 TCGv_i64 t1 = tcg_temp_new_i64();
5123 TCGv t2 = tcg_temp_new();
5124 /* Start with XER OV disabled, the most likely case */
5125 tcg_gen_movi_tl(cpu_ov, 0);
5126 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5127 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5128 tcg_gen_mul_i64(t0, t0, t1);
5129 tcg_gen_trunc_i64_tl(t2, t0);
5130 gen_store_spr(SPR_MQ, t2);
5131 tcg_gen_shri_i64(t1, t0, 32);
5132 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5133 tcg_gen_ext32s_i64(t1, t0);
5134 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5135 tcg_gen_movi_tl(cpu_ov, 1);
5136 tcg_gen_movi_tl(cpu_so, 1);
5137 gen_set_label(l1);
5138 tcg_temp_free_i64(t0);
5139 tcg_temp_free_i64(t1);
5140 tcg_temp_free(t2);
5141 if (unlikely(Rc(ctx->opcode) != 0))
5142 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5143 }
5144
5145 /* nabs - nabs. */
5146 static void gen_nabs(DisasContext *ctx)
5147 {
5148 int l1 = gen_new_label();
5149 int l2 = gen_new_label();
5150 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5151 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5152 tcg_gen_br(l2);
5153 gen_set_label(l1);
5154 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5155 gen_set_label(l2);
5156 if (unlikely(Rc(ctx->opcode) != 0))
5157 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5158 }
5159
5160 /* nabso - nabso. */
5161 static void gen_nabso(DisasContext *ctx)
5162 {
5163 int l1 = gen_new_label();
5164 int l2 = gen_new_label();
5165 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5166 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5167 tcg_gen_br(l2);
5168 gen_set_label(l1);
5169 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5170 gen_set_label(l2);
5171 /* nabs never overflows */
5172 tcg_gen_movi_tl(cpu_ov, 0);
5173 if (unlikely(Rc(ctx->opcode) != 0))
5174 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5175 }
5176
5177 /* rlmi - rlmi. */
5178 static void gen_rlmi(DisasContext *ctx)
5179 {
5180 uint32_t mb = MB(ctx->opcode);
5181 uint32_t me = ME(ctx->opcode);
5182 TCGv t0 = tcg_temp_new();
5183 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5184 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5185 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5186 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5187 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5188 tcg_temp_free(t0);
5189 if (unlikely(Rc(ctx->opcode) != 0))
5190 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5191 }
5192
5193 /* rrib - rrib. */
5194 static void gen_rrib(DisasContext *ctx)
5195 {
5196 TCGv t0 = tcg_temp_new();
5197 TCGv t1 = tcg_temp_new();
5198 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5199 tcg_gen_movi_tl(t1, 0x80000000);
5200 tcg_gen_shr_tl(t1, t1, t0);
5201 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5202 tcg_gen_and_tl(t0, t0, t1);
5203 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5204 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5205 tcg_temp_free(t0);
5206 tcg_temp_free(t1);
5207 if (unlikely(Rc(ctx->opcode) != 0))
5208 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5209 }
5210
5211 /* sle - sle. */
5212 static void gen_sle(DisasContext *ctx)
5213 {
5214 TCGv t0 = tcg_temp_new();
5215 TCGv t1 = tcg_temp_new();
5216 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5217 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5218 tcg_gen_subfi_tl(t1, 32, t1);
5219 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5220 tcg_gen_or_tl(t1, t0, t1);
5221 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5222 gen_store_spr(SPR_MQ, t1);
5223 tcg_temp_free(t0);
5224 tcg_temp_free(t1);
5225 if (unlikely(Rc(ctx->opcode) != 0))
5226 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5227 }
5228
5229 /* sleq - sleq. */
5230 static void gen_sleq(DisasContext *ctx)
5231 {
5232 TCGv t0 = tcg_temp_new();
5233 TCGv t1 = tcg_temp_new();
5234 TCGv t2 = tcg_temp_new();
5235 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5236 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5237 tcg_gen_shl_tl(t2, t2, t0);
5238 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5239 gen_load_spr(t1, SPR_MQ);
5240 gen_store_spr(SPR_MQ, t0);
5241 tcg_gen_and_tl(t0, t0, t2);
5242 tcg_gen_andc_tl(t1, t1, t2);
5243 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5244 tcg_temp_free(t0);
5245 tcg_temp_free(t1);
5246 tcg_temp_free(t2);
5247 if (unlikely(Rc(ctx->opcode) != 0))
5248 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5249 }
5250
5251 /* sliq - sliq. */
5252 static void gen_sliq(DisasContext *ctx)
5253 {
5254 int sh = SH(ctx->opcode);
5255 TCGv t0 = tcg_temp_new();
5256 TCGv t1 = tcg_temp_new();
5257 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5258 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5259 tcg_gen_or_tl(t1, t0, t1);
5260 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5261 gen_store_spr(SPR_MQ, t1);
5262 tcg_temp_free(t0);
5263 tcg_temp_free(t1);
5264 if (unlikely(Rc(ctx->opcode) != 0))
5265 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5266 }
5267
5268 /* slliq - slliq. */
5269 static void gen_slliq(DisasContext *ctx)
5270 {
5271 int sh = SH(ctx->opcode);
5272 TCGv t0 = tcg_temp_new();
5273 TCGv t1 = tcg_temp_new();
5274 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5275 gen_load_spr(t1, SPR_MQ);
5276 gen_store_spr(SPR_MQ, t0);
5277 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5278 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5279 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5280 tcg_temp_free(t0);
5281 tcg_temp_free(t1);
5282 if (unlikely(Rc(ctx->opcode) != 0))
5283 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5284 }
5285
5286 /* sllq - sllq. */
5287 static void gen_sllq(DisasContext *ctx)
5288 {
5289 int l1 = gen_new_label();
5290 int l2 = gen_new_label();
5291 TCGv t0 = tcg_temp_local_new();
5292 TCGv t1 = tcg_temp_local_new();
5293 TCGv t2 = tcg_temp_local_new();
5294 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5295 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5296 tcg_gen_shl_tl(t1, t1, t2);
5297 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5298 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5299 gen_load_spr(t0, SPR_MQ);
5300 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5301 tcg_gen_br(l2);
5302 gen_set_label(l1);
5303 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5304 gen_load_spr(t2, SPR_MQ);
5305 tcg_gen_andc_tl(t1, t2, t1);
5306 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5307 gen_set_label(l2);
5308 tcg_temp_free(t0);
5309 tcg_temp_free(t1);
5310 tcg_temp_free(t2);
5311 if (unlikely(Rc(ctx->opcode) != 0))
5312 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5313 }
5314
5315 /* slq - slq. */
5316 static void gen_slq(DisasContext *ctx)
5317 {
5318 int l1 = gen_new_label();
5319 TCGv t0 = tcg_temp_new();
5320 TCGv t1 = tcg_temp_new();
5321 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5322 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5323 tcg_gen_subfi_tl(t1, 32, t1);
5324 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5325 tcg_gen_or_tl(t1, t0, t1);
5326 gen_store_spr(SPR_MQ, t1);
5327 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5328 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5329 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5330 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5331 gen_set_label(l1);
5332 tcg_temp_free(t0);
5333 tcg_temp_free(t1);
5334 if (unlikely(Rc(ctx->opcode) != 0))
5335 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5336 }
5337
5338 /* sraiq - sraiq. */
5339 static void gen_sraiq(DisasContext *ctx)
5340 {
5341 int sh = SH(ctx->opcode);
5342 int l1 = gen_new_label();
5343 TCGv t0 = tcg_temp_new();
5344 TCGv t1 = tcg_temp_new();
5345 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5346 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5347 tcg_gen_or_tl(t0, t0, t1);
5348 gen_store_spr(SPR_MQ, t0);
5349 tcg_gen_movi_tl(cpu_ca, 0);
5350 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5351 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5352 tcg_gen_movi_tl(cpu_ca, 1);
5353 gen_set_label(l1);
5354 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5355 tcg_temp_free(t0);
5356 tcg_temp_free(t1);
5357 if (unlikely(Rc(ctx->opcode) != 0))
5358 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5359 }
5360
5361 /* sraq - sraq. */
5362 static void gen_sraq(DisasContext *ctx)
5363 {
5364 int l1 = gen_new_label();
5365 int l2 = gen_new_label();
5366 TCGv t0 = tcg_temp_new();
5367 TCGv t1 = tcg_temp_local_new();
5368 TCGv t2 = tcg_temp_local_new();
5369 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5370 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5371 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5372 tcg_gen_subfi_tl(t2, 32, t2);
5373 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5374 tcg_gen_or_tl(t0, t0, t2);
5375 gen_store_spr(SPR_MQ, t0);
5376 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5377 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5378 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5379 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5380 gen_set_label(l1);
5381 tcg_temp_free(t0);
5382 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5383 tcg_gen_movi_tl(cpu_ca, 0);
5384 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5385 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5386 tcg_gen_movi_tl(cpu_ca, 1);
5387 gen_set_label(l2);
5388 tcg_temp_free(t1);
5389 tcg_temp_free(t2);
5390 if (unlikely(Rc(ctx->opcode) != 0))
5391 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5392 }
5393
5394 /* sre - sre. */
5395 static void gen_sre(DisasContext *ctx)
5396 {
5397 TCGv t0 = tcg_temp_new();
5398 TCGv t1 = tcg_temp_new();
5399 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5400 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5401 tcg_gen_subfi_tl(t1, 32, t1);
5402 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5403 tcg_gen_or_tl(t1, t0, t1);
5404 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5405 gen_store_spr(SPR_MQ, t1);
5406 tcg_temp_free(t0);
5407 tcg_temp_free(t1);
5408 if (unlikely(Rc(ctx->opcode) != 0))
5409 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5410 }
5411
5412 /* srea - srea. */
5413 static void gen_srea(DisasContext *ctx)
5414 {
5415 TCGv t0 = tcg_temp_new();
5416 TCGv t1 = tcg_temp_new();
5417 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5418 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5419 gen_store_spr(SPR_MQ, t0);
5420 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5421 tcg_temp_free(t0);
5422 tcg_temp_free(t1);
5423 if (unlikely(Rc(ctx->opcode) != 0))
5424 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5425 }
5426
5427 /* sreq */
5428 static void gen_sreq(DisasContext *ctx)
5429 {
5430 TCGv t0 = tcg_temp_new();
5431 TCGv t1 = tcg_temp_new();
5432 TCGv t2 = tcg_temp_new();
5433 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5434 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5435 tcg_gen_shr_tl(t1, t1, t0);
5436 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5437 gen_load_spr(t2, SPR_MQ);
5438 gen_store_spr(SPR_MQ, t0);
5439 tcg_gen_and_tl(t0, t0, t1);
5440 tcg_gen_andc_tl(t2, t2, t1);
5441 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5442 tcg_temp_free(t0);
5443 tcg_temp_free(t1);
5444 tcg_temp_free(t2);
5445 if (unlikely(Rc(ctx->opcode) != 0))
5446 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5447 }
5448
5449 /* sriq */
5450 static void gen_sriq(DisasContext *ctx)
5451 {
5452 int sh = SH(ctx->opcode);
5453 TCGv t0 = tcg_temp_new();
5454 TCGv t1 = tcg_temp_new();
5455 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5456 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5457 tcg_gen_or_tl(t1, t0, t1);
5458 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5459 gen_store_spr(SPR_MQ, t1);
5460 tcg_temp_free(t0);
5461 tcg_temp_free(t1);
5462 if (unlikely(Rc(ctx->opcode) != 0))
5463 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5464 }
5465
5466 /* srliq */
5467 static void gen_srliq(DisasContext *ctx)
5468 {
5469 int sh = SH(ctx->opcode);
5470 TCGv t0 = tcg_temp_new();
5471 TCGv t1 = tcg_temp_new();
5472 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5473 gen_load_spr(t1, SPR_MQ);
5474 gen_store_spr(SPR_MQ, t0);
5475 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5476 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5477 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5478 tcg_temp_free(t0);
5479 tcg_temp_free(t1);
5480 if (unlikely(Rc(ctx->opcode) != 0))
5481 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5482 }
5483
5484 /* srlq */
5485 static void gen_srlq(DisasContext *ctx)
5486 {
5487 int l1 = gen_new_label();
5488 int l2 = gen_new_label();
5489 TCGv t0 = tcg_temp_local_new();
5490 TCGv t1 = tcg_temp_local_new();
5491 TCGv t2 = tcg_temp_local_new();
5492 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5493 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5494 tcg_gen_shr_tl(t2, t1, t2);
5495 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5496 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5497 gen_load_spr(t0, SPR_MQ);
5498 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5499 tcg_gen_br(l2);
5500 gen_set_label(l1);
5501 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5502 tcg_gen_and_tl(t0, t0, t2);
5503 gen_load_spr(t1, SPR_MQ);
5504 tcg_gen_andc_tl(t1, t1, t2);
5505 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5506 gen_set_label(l2);
5507 tcg_temp_free(t0);
5508 tcg_temp_free(t1);
5509 tcg_temp_free(t2);
5510 if (unlikely(Rc(ctx->opcode) != 0))
5511 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5512 }
5513
5514 /* srq */
5515 static void gen_srq(DisasContext *ctx)
5516 {
5517 int l1 = gen_new_label();
5518 TCGv t0 = tcg_temp_new();
5519 TCGv t1 = tcg_temp_new();
5520 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5521 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5522 tcg_gen_subfi_tl(t1, 32, t1);
5523 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5524 tcg_gen_or_tl(t1, t0, t1);
5525 gen_store_spr(SPR_MQ, t1);
5526 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5527 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5528 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5529 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5530 gen_set_label(l1);
5531 tcg_temp_free(t0);
5532 tcg_temp_free(t1);
5533 if (unlikely(Rc(ctx->opcode) != 0))
5534 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5535 }
5536
5537 /* PowerPC 602 specific instructions */
5538
5539 /* dsa */
5540 static void gen_dsa(DisasContext *ctx)
5541 {
5542 /* XXX: TODO */
5543 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5544 }
5545
5546 /* esa */
5547 static void gen_esa(DisasContext *ctx)
5548 {
5549 /* XXX: TODO */
5550 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5551 }
5552
5553 /* mfrom */
5554 static void gen_mfrom(DisasContext *ctx)
5555 {
5556 #if defined(CONFIG_USER_ONLY)
5557 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5558 #else
5559 if (unlikely(!ctx->mem_idx)) {
5560 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5561 return;
5562 }
5563 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5564 #endif
5565 }
5566
5567 /* 602 - 603 - G2 TLB management */
5568
5569 /* tlbld */
5570 static void gen_tlbld_6xx(DisasContext *ctx)
5571 {
5572 #if defined(CONFIG_USER_ONLY)
5573 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5574 #else
5575 if (unlikely(!ctx->mem_idx)) {
5576 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5577 return;
5578 }
5579 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5580 #endif
5581 }
5582
5583 /* tlbli */
5584 static void gen_tlbli_6xx(DisasContext *ctx)
5585 {
5586 #if defined(CONFIG_USER_ONLY)
5587 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5588 #else
5589 if (unlikely(!ctx->mem_idx)) {
5590 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5591 return;
5592 }
5593 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5594 #endif
5595 }
5596
5597 /* 74xx TLB management */
5598
5599 /* tlbld */
5600 static void gen_tlbld_74xx(DisasContext *ctx)
5601 {
5602 #if defined(CONFIG_USER_ONLY)
5603 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5604 #else
5605 if (unlikely(!ctx->mem_idx)) {
5606 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5607 return;
5608 }
5609 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5610 #endif
5611 }
5612
5613 /* tlbli */
5614 static void gen_tlbli_74xx(DisasContext *ctx)
5615 {
5616 #if defined(CONFIG_USER_ONLY)
5617 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5618 #else
5619 if (unlikely(!ctx->mem_idx)) {
5620 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5621 return;
5622 }
5623 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5624 #endif
5625 }
5626
5627 /* POWER instructions not in PowerPC 601 */
5628
5629 /* clf */
5630 static void gen_clf(DisasContext *ctx)
5631 {
5632 /* Cache line flush: implemented as no-op */
5633 }
5634
5635 /* cli */
5636 static void gen_cli(DisasContext *ctx)
5637 {
5638 /* Cache line invalidate: privileged and treated as no-op */
5639 #if defined(CONFIG_USER_ONLY)
5640 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5641 #else
5642 if (unlikely(!ctx->mem_idx)) {
5643 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5644 return;
5645 }
5646 #endif
5647 }
5648
5649 /* dclst */
5650 static void gen_dclst(DisasContext *ctx)
5651 {
5652 /* Data cache line store: treated as no-op */
5653 }
5654
5655 static void gen_mfsri(DisasContext *ctx)
5656 {
5657 #if defined(CONFIG_USER_ONLY)
5658 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5659 #else
5660 int ra = rA(ctx->opcode);
5661 int rd = rD(ctx->opcode);
5662 TCGv t0;
5663 if (unlikely(!ctx->mem_idx)) {
5664 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5665 return;
5666 }
5667 t0 = tcg_temp_new();
5668 gen_addr_reg_index(ctx, t0);
5669 tcg_gen_shri_tl(t0, t0, 28);
5670 tcg_gen_andi_tl(t0, t0, 0xF);
5671 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5672 tcg_temp_free(t0);
5673 if (ra != 0 && ra != rd)
5674 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5675 #endif
5676 }
5677
5678 static void gen_rac(DisasContext *ctx)
5679 {
5680 #if defined(CONFIG_USER_ONLY)
5681 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5682 #else
5683 TCGv t0;
5684 if (unlikely(!ctx->mem_idx)) {
5685 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5686 return;
5687 }
5688 t0 = tcg_temp_new();
5689 gen_addr_reg_index(ctx, t0);
5690 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5691 tcg_temp_free(t0);
5692 #endif
5693 }
5694
5695 static void gen_rfsvc(DisasContext *ctx)
5696 {
5697 #if defined(CONFIG_USER_ONLY)
5698 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5699 #else
5700 if (unlikely(!ctx->mem_idx)) {
5701 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5702 return;
5703 }
5704 gen_helper_rfsvc(cpu_env);
5705 gen_sync_exception(ctx);
5706 #endif
5707 }
5708
5709 /* svc is not implemented for now */
5710
5711 /* POWER2 specific instructions */
5712 /* Quad manipulation (load/store two floats at a time) */
5713
5714 /* lfq */
5715 static void gen_lfq(DisasContext *ctx)
5716 {
5717 int rd = rD(ctx->opcode);
5718 TCGv t0;
5719 gen_set_access_type(ctx, ACCESS_FLOAT);
5720 t0 = tcg_temp_new();
5721 gen_addr_imm_index(ctx, t0, 0);
5722 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5723 gen_addr_add(ctx, t0, t0, 8);
5724 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5725 tcg_temp_free(t0);
5726 }
5727
5728 /* lfqu */
5729 static void gen_lfqu(DisasContext *ctx)
5730 {
5731 int ra = rA(ctx->opcode);
5732 int rd = rD(ctx->opcode);
5733 TCGv t0, t1;
5734 gen_set_access_type(ctx, ACCESS_FLOAT);
5735 t0 = tcg_temp_new();
5736 t1 = tcg_temp_new();
5737 gen_addr_imm_index(ctx, t0, 0);
5738 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5739 gen_addr_add(ctx, t1, t0, 8);
5740 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5741 if (ra != 0)
5742 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5743 tcg_temp_free(t0);
5744 tcg_temp_free(t1);
5745 }
5746
5747 /* lfqux */
5748 static void gen_lfqux(DisasContext *ctx)
5749 {
5750 int ra = rA(ctx->opcode);
5751 int rd = rD(ctx->opcode);
5752 gen_set_access_type(ctx, ACCESS_FLOAT);
5753 TCGv t0, t1;
5754 t0 = tcg_temp_new();
5755 gen_addr_reg_index(ctx, t0);
5756 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5757 t1 = tcg_temp_new();
5758 gen_addr_add(ctx, t1, t0, 8);
5759 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5760 tcg_temp_free(t1);
5761 if (ra != 0)
5762 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5763 tcg_temp_free(t0);
5764 }
5765
5766 /* lfqx */
5767 static void gen_lfqx(DisasContext *ctx)
5768 {
5769 int rd = rD(ctx->opcode);
5770 TCGv t0;
5771 gen_set_access_type(ctx, ACCESS_FLOAT);
5772 t0 = tcg_temp_new();
5773 gen_addr_reg_index(ctx, t0);
5774 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5775 gen_addr_add(ctx, t0, t0, 8);
5776 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5777 tcg_temp_free(t0);
5778 }
5779
5780 /* stfq */
5781 static void gen_stfq(DisasContext *ctx)
5782 {
5783 int rd = rD(ctx->opcode);
5784 TCGv t0;
5785 gen_set_access_type(ctx, ACCESS_FLOAT);
5786 t0 = tcg_temp_new();
5787 gen_addr_imm_index(ctx, t0, 0);
5788 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5789 gen_addr_add(ctx, t0, t0, 8);
5790 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5791 tcg_temp_free(t0);
5792 }
5793
5794 /* stfqu */
5795 static void gen_stfqu(DisasContext *ctx)
5796 {
5797 int ra = rA(ctx->opcode);
5798 int rd = rD(ctx->opcode);
5799 TCGv t0, t1;
5800 gen_set_access_type(ctx, ACCESS_FLOAT);
5801 t0 = tcg_temp_new();
5802 gen_addr_imm_index(ctx, t0, 0);
5803 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5804 t1 = tcg_temp_new();
5805 gen_addr_add(ctx, t1, t0, 8);
5806 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5807 tcg_temp_free(t1);
5808 if (ra != 0)
5809 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5810 tcg_temp_free(t0);
5811 }
5812
5813 /* stfqux */
5814 static void gen_stfqux(DisasContext *ctx)
5815 {
5816 int ra = rA(ctx->opcode);
5817 int rd = rD(ctx->opcode);
5818 TCGv t0, t1;
5819 gen_set_access_type(ctx, ACCESS_FLOAT);
5820 t0 = tcg_temp_new();
5821 gen_addr_reg_index(ctx, t0);
5822 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5823 t1 = tcg_temp_new();
5824 gen_addr_add(ctx, t1, t0, 8);
5825 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5826 tcg_temp_free(t1);
5827 if (ra != 0)
5828 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5829 tcg_temp_free(t0);
5830 }
5831
5832 /* stfqx */
5833 static void gen_stfqx(DisasContext *ctx)
5834 {
5835 int rd = rD(ctx->opcode);
5836 TCGv t0;
5837 gen_set_access_type(ctx, ACCESS_FLOAT);
5838 t0 = tcg_temp_new();
5839 gen_addr_reg_index(ctx, t0);
5840 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5841 gen_addr_add(ctx, t0, t0, 8);
5842 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5843 tcg_temp_free(t0);
5844 }
5845
5846 /* BookE specific instructions */
5847
5848 /* XXX: not implemented on 440 ? */
5849 static void gen_mfapidi(DisasContext *ctx)
5850 {
5851 /* XXX: TODO */
5852 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5853 }
5854
5855 /* XXX: not implemented on 440 ? */
5856 static void gen_tlbiva(DisasContext *ctx)
5857 {
5858 #if defined(CONFIG_USER_ONLY)
5859 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5860 #else
5861 TCGv t0;
5862 if (unlikely(!ctx->mem_idx)) {
5863 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5864 return;
5865 }
5866 t0 = tcg_temp_new();
5867 gen_addr_reg_index(ctx, t0);
5868 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5869 tcg_temp_free(t0);
5870 #endif
5871 }
5872
5873 /* All 405 MAC instructions are translated here */
5874 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5875 int ra, int rb, int rt, int Rc)
5876 {
5877 TCGv t0, t1;
5878
5879 t0 = tcg_temp_local_new();
5880 t1 = tcg_temp_local_new();
5881
5882 switch (opc3 & 0x0D) {
5883 case 0x05:
5884 /* macchw - macchw. - macchwo - macchwo. */
5885 /* macchws - macchws. - macchwso - macchwso. */
5886 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5887 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5888 /* mulchw - mulchw. */
5889 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5890 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5891 tcg_gen_ext16s_tl(t1, t1);
5892 break;
5893 case 0x04:
5894 /* macchwu - macchwu. - macchwuo - macchwuo. */
5895 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5896 /* mulchwu - mulchwu. */
5897 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5898 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5899 tcg_gen_ext16u_tl(t1, t1);
5900 break;
5901 case 0x01:
5902 /* machhw - machhw. - machhwo - machhwo. */
5903 /* machhws - machhws. - machhwso - machhwso. */
5904 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5905 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5906 /* mulhhw - mulhhw. */
5907 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5908 tcg_gen_ext16s_tl(t0, t0);
5909 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5910 tcg_gen_ext16s_tl(t1, t1);
5911 break;
5912 case 0x00:
5913 /* machhwu - machhwu. - machhwuo - machhwuo. */
5914 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5915 /* mulhhwu - mulhhwu. */
5916 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5917 tcg_gen_ext16u_tl(t0, t0);
5918 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5919 tcg_gen_ext16u_tl(t1, t1);
5920 break;
5921 case 0x0D:
5922 /* maclhw - maclhw. - maclhwo - maclhwo. */
5923 /* maclhws - maclhws. - maclhwso - maclhwso. */
5924 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5925 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5926 /* mullhw - mullhw. */
5927 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5928 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5929 break;
5930 case 0x0C:
5931 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5932 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5933 /* mullhwu - mullhwu. */
5934 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5935 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5936 break;
5937 }
5938 if (opc2 & 0x04) {
5939 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5940 tcg_gen_mul_tl(t1, t0, t1);
5941 if (opc2 & 0x02) {
5942 /* nmultiply-and-accumulate (0x0E) */
5943 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5944 } else {
5945 /* multiply-and-accumulate (0x0C) */
5946 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5947 }
5948
5949 if (opc3 & 0x12) {
5950 /* Check overflow and/or saturate */
5951 int l1 = gen_new_label();
5952
5953 if (opc3 & 0x10) {
5954 /* Start with XER OV disabled, the most likely case */
5955 tcg_gen_movi_tl(cpu_ov, 0);
5956 }
5957 if (opc3 & 0x01) {
5958 /* Signed */
5959 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5960 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5961 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5962 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5963 if (opc3 & 0x02) {
5964 /* Saturate */
5965 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5966 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5967 }
5968 } else {
5969 /* Unsigned */
5970 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5971 if (opc3 & 0x02) {
5972 /* Saturate */
5973 tcg_gen_movi_tl(t0, UINT32_MAX);
5974 }
5975 }
5976 if (opc3 & 0x10) {
5977 /* Check overflow */
5978 tcg_gen_movi_tl(cpu_ov, 1);
5979 tcg_gen_movi_tl(cpu_so, 1);
5980 }
5981 gen_set_label(l1);
5982 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5983 }
5984 } else {
5985 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5986 }
5987 tcg_temp_free(t0);
5988 tcg_temp_free(t1);
5989 if (unlikely(Rc) != 0) {
5990 /* Update Rc0 */
5991 gen_set_Rc0(ctx, cpu_gpr[rt]);
5992 }
5993 }
5994
5995 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5996 static void glue(gen_, name)(DisasContext *ctx) \
5997 { \
5998 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5999 rD(ctx->opcode), Rc(ctx->opcode)); \
6000 }
6001
6002 /* macchw - macchw. */
6003 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
6004 /* macchwo - macchwo. */
6005 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
6006 /* macchws - macchws. */
6007 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
6008 /* macchwso - macchwso. */
6009 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
6010 /* macchwsu - macchwsu. */
6011 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
6012 /* macchwsuo - macchwsuo. */
6013 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
6014 /* macchwu - macchwu. */
6015 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6016 /* macchwuo - macchwuo. */
6017 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6018 /* machhw - machhw. */
6019 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6020 /* machhwo - machhwo. */
6021 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6022 /* machhws - machhws. */
6023 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6024 /* machhwso - machhwso. */
6025 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6026 /* machhwsu - machhwsu. */
6027 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6028 /* machhwsuo - machhwsuo. */
6029 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6030 /* machhwu - machhwu. */
6031 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6032 /* machhwuo - machhwuo. */
6033 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6034 /* maclhw - maclhw. */
6035 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6036 /* maclhwo - maclhwo. */
6037 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6038 /* maclhws - maclhws. */
6039 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6040 /* maclhwso - maclhwso. */
6041 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6042 /* maclhwu - maclhwu. */
6043 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6044 /* maclhwuo - maclhwuo. */
6045 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6046 /* maclhwsu - maclhwsu. */
6047 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6048 /* maclhwsuo - maclhwsuo. */
6049 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6050 /* nmacchw - nmacchw. */
6051 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6052 /* nmacchwo - nmacchwo. */
6053 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6054 /* nmacchws - nmacchws. */
6055 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6056 /* nmacchwso - nmacchwso. */
6057 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6058 /* nmachhw - nmachhw. */
6059 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6060 /* nmachhwo - nmachhwo. */
6061 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6062 /* nmachhws - nmachhws. */
6063 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6064 /* nmachhwso - nmachhwso. */
6065 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6066 /* nmaclhw - nmaclhw. */
6067 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6068 /* nmaclhwo - nmaclhwo. */
6069 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6070 /* nmaclhws - nmaclhws. */
6071 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6072 /* nmaclhwso - nmaclhwso. */
6073 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6074
6075 /* mulchw - mulchw. */
6076 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6077 /* mulchwu - mulchwu. */
6078 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6079 /* mulhhw - mulhhw. */
6080 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6081 /* mulhhwu - mulhhwu. */
6082 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6083 /* mullhw - mullhw. */
6084 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6085 /* mullhwu - mullhwu. */
6086 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6087
6088 /* mfdcr */
6089 static void gen_mfdcr(DisasContext *ctx)
6090 {
6091 #if defined(CONFIG_USER_ONLY)
6092 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6093 #else
6094 TCGv dcrn;
6095 if (unlikely(!ctx->mem_idx)) {
6096 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6097 return;
6098 }
6099 /* NIP cannot be restored if the memory exception comes from an helper */
6100 gen_update_nip(ctx, ctx->nip - 4);
6101 dcrn = tcg_const_tl(SPR(ctx->opcode));
6102 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6103 tcg_temp_free(dcrn);
6104 #endif
6105 }
6106
6107 /* mtdcr */
6108 static void gen_mtdcr(DisasContext *ctx)
6109 {
6110 #if defined(CONFIG_USER_ONLY)
6111 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6112 #else
6113 TCGv dcrn;
6114 if (unlikely(!ctx->mem_idx)) {
6115 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6116 return;
6117 }
6118 /* NIP cannot be restored if the memory exception comes from an helper */
6119 gen_update_nip(ctx, ctx->nip - 4);
6120 dcrn = tcg_const_tl(SPR(ctx->opcode));
6121 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6122 tcg_temp_free(dcrn);
6123 #endif
6124 }
6125
6126 /* mfdcrx */
6127 /* XXX: not implemented on 440 ? */
6128 static void gen_mfdcrx(DisasContext *ctx)
6129 {
6130 #if defined(CONFIG_USER_ONLY)
6131 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6132 #else
6133 if (unlikely(!ctx->mem_idx)) {
6134 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6135 return;
6136 }
6137 /* NIP cannot be restored if the memory exception comes from an helper */
6138 gen_update_nip(ctx, ctx->nip - 4);
6139 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6140 cpu_gpr[rA(ctx->opcode)]);
6141 /* Note: Rc update flag set leads to undefined state of Rc0 */
6142 #endif
6143 }
6144
6145 /* mtdcrx */
6146 /* XXX: not implemented on 440 ? */
6147 static void gen_mtdcrx(DisasContext *ctx)
6148 {
6149 #if defined(CONFIG_USER_ONLY)
6150 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6151 #else
6152 if (unlikely(!ctx->mem_idx)) {
6153 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6154 return;
6155 }
6156 /* NIP cannot be restored if the memory exception comes from an helper */
6157 gen_update_nip(ctx, ctx->nip - 4);
6158 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6159 cpu_gpr[rS(ctx->opcode)]);
6160 /* Note: Rc update flag set leads to undefined state of Rc0 */
6161 #endif
6162 }
6163
6164 /* mfdcrux (PPC 460) : user-mode access to DCR */
6165 static void gen_mfdcrux(DisasContext *ctx)
6166 {
6167 /* NIP cannot be restored if the memory exception comes from an helper */
6168 gen_update_nip(ctx, ctx->nip - 4);
6169 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6170 cpu_gpr[rA(ctx->opcode)]);
6171 /* Note: Rc update flag set leads to undefined state of Rc0 */
6172 }
6173
6174 /* mtdcrux (PPC 460) : user-mode access to DCR */
6175 static void gen_mtdcrux(DisasContext *ctx)
6176 {
6177 /* NIP cannot be restored if the memory exception comes from an helper */
6178 gen_update_nip(ctx, ctx->nip - 4);
6179 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6180 cpu_gpr[rS(ctx->opcode)]);
6181 /* Note: Rc update flag set leads to undefined state of Rc0 */
6182 }
6183
6184 /* dccci */
6185 static void gen_dccci(DisasContext *ctx)
6186 {
6187 #if defined(CONFIG_USER_ONLY)
6188 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6189 #else
6190 if (unlikely(!ctx->mem_idx)) {
6191 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6192 return;
6193 }
6194 /* interpreted as no-op */
6195 #endif
6196 }
6197
6198 /* dcread */
6199 static void gen_dcread(DisasContext *ctx)
6200 {
6201 #if defined(CONFIG_USER_ONLY)
6202 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6203 #else
6204 TCGv EA, val;
6205 if (unlikely(!ctx->mem_idx)) {
6206 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6207 return;
6208 }
6209 gen_set_access_type(ctx, ACCESS_CACHE);
6210 EA = tcg_temp_new();
6211 gen_addr_reg_index(ctx, EA);
6212 val = tcg_temp_new();
6213 gen_qemu_ld32u(ctx, val, EA);
6214 tcg_temp_free(val);
6215 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6216 tcg_temp_free(EA);
6217 #endif
6218 }
6219
6220 /* icbt */
6221 static void gen_icbt_40x(DisasContext *ctx)
6222 {
6223 /* interpreted as no-op */
6224 /* XXX: specification say this is treated as a load by the MMU
6225 * but does not generate any exception
6226 */
6227 }
6228
6229 /* iccci */
6230 static void gen_iccci(DisasContext *ctx)
6231 {
6232 #if defined(CONFIG_USER_ONLY)
6233 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6234 #else
6235 if (unlikely(!ctx->mem_idx)) {
6236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6237 return;
6238 }
6239 /* interpreted as no-op */
6240 #endif
6241 }
6242
6243 /* icread */
6244 static void gen_icread(DisasContext *ctx)
6245 {
6246 #if defined(CONFIG_USER_ONLY)
6247 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6248 #else
6249 if (unlikely(!ctx->mem_idx)) {
6250 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6251 return;
6252 }
6253 /* interpreted as no-op */
6254 #endif
6255 }
6256
6257 /* rfci (mem_idx only) */
6258 static void gen_rfci_40x(DisasContext *ctx)
6259 {
6260 #if defined(CONFIG_USER_ONLY)
6261 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6262 #else
6263 if (unlikely(!ctx->mem_idx)) {
6264 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6265 return;
6266 }
6267 /* Restore CPU state */
6268 gen_helper_40x_rfci(cpu_env);
6269 gen_sync_exception(ctx);
6270 #endif
6271 }
6272
6273 static void gen_rfci(DisasContext *ctx)
6274 {
6275 #if defined(CONFIG_USER_ONLY)
6276 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6277 #else
6278 if (unlikely(!ctx->mem_idx)) {
6279 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6280 return;
6281 }
6282 /* Restore CPU state */
6283 gen_helper_rfci(cpu_env);
6284 gen_sync_exception(ctx);
6285 #endif
6286 }
6287
6288 /* BookE specific */
6289
6290 /* XXX: not implemented on 440 ? */
6291 static void gen_rfdi(DisasContext *ctx)
6292 {
6293 #if defined(CONFIG_USER_ONLY)
6294 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6295 #else
6296 if (unlikely(!ctx->mem_idx)) {
6297 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6298 return;
6299 }
6300 /* Restore CPU state */
6301 gen_helper_rfdi(cpu_env);
6302 gen_sync_exception(ctx);
6303 #endif
6304 }
6305
6306 /* XXX: not implemented on 440 ? */
6307 static void gen_rfmci(DisasContext *ctx)
6308 {
6309 #if defined(CONFIG_USER_ONLY)
6310 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6311 #else
6312 if (unlikely(!ctx->mem_idx)) {
6313 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6314 return;
6315 }
6316 /* Restore CPU state */
6317 gen_helper_rfmci(cpu_env);
6318 gen_sync_exception(ctx);
6319 #endif
6320 }
6321
6322 /* TLB management - PowerPC 405 implementation */
6323
6324 /* tlbre */
6325 static void gen_tlbre_40x(DisasContext *ctx)
6326 {
6327 #if defined(CONFIG_USER_ONLY)
6328 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6329 #else
6330 if (unlikely(!ctx->mem_idx)) {
6331 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6332 return;
6333 }
6334 switch (rB(ctx->opcode)) {
6335 case 0:
6336 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6337 cpu_gpr[rA(ctx->opcode)]);
6338 break;
6339 case 1:
6340 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6341 cpu_gpr[rA(ctx->opcode)]);
6342 break;
6343 default:
6344 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6345 break;
6346 }
6347 #endif
6348 }
6349
6350 /* tlbsx - tlbsx. */
6351 static void gen_tlbsx_40x(DisasContext *ctx)
6352 {
6353 #if defined(CONFIG_USER_ONLY)
6354 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6355 #else
6356 TCGv t0;
6357 if (unlikely(!ctx->mem_idx)) {
6358 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6359 return;
6360 }
6361 t0 = tcg_temp_new();
6362 gen_addr_reg_index(ctx, t0);
6363 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6364 tcg_temp_free(t0);
6365 if (Rc(ctx->opcode)) {
6366 int l1 = gen_new_label();
6367 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6368 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6369 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6370 gen_set_label(l1);
6371 }
6372 #endif
6373 }
6374
6375 /* tlbwe */
6376 static void gen_tlbwe_40x(DisasContext *ctx)
6377 {
6378 #if defined(CONFIG_USER_ONLY)
6379 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6380 #else
6381 if (unlikely(!ctx->mem_idx)) {
6382 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6383 return;
6384 }
6385 switch (rB(ctx->opcode)) {
6386 case 0:
6387 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6388 cpu_gpr[rS(ctx->opcode)]);
6389 break;
6390 case 1:
6391 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6392 cpu_gpr[rS(ctx->opcode)]);
6393 break;
6394 default:
6395 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6396 break;
6397 }
6398 #endif
6399 }
6400
6401 /* TLB management - PowerPC 440 implementation */
6402
6403 /* tlbre */
6404 static void gen_tlbre_440(DisasContext *ctx)
6405 {
6406 #if defined(CONFIG_USER_ONLY)
6407 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6408 #else
6409 if (unlikely(!ctx->mem_idx)) {
6410 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6411 return;
6412 }
6413 switch (rB(ctx->opcode)) {
6414 case 0:
6415 case 1:
6416 case 2:
6417 {
6418 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6419 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6420 t0, cpu_gpr[rA(ctx->opcode)]);
6421 tcg_temp_free_i32(t0);
6422 }
6423 break;
6424 default:
6425 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6426 break;
6427 }
6428 #endif
6429 }
6430
6431 /* tlbsx - tlbsx. */
6432 static void gen_tlbsx_440(DisasContext *ctx)
6433 {
6434 #if defined(CONFIG_USER_ONLY)
6435 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6436 #else
6437 TCGv t0;
6438 if (unlikely(!ctx->mem_idx)) {
6439 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6440 return;
6441 }
6442 t0 = tcg_temp_new();
6443 gen_addr_reg_index(ctx, t0);
6444 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6445 tcg_temp_free(t0);
6446 if (Rc(ctx->opcode)) {
6447 int l1 = gen_new_label();
6448 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6449 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6450 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6451 gen_set_label(l1);
6452 }
6453 #endif
6454 }
6455
6456 /* tlbwe */
6457 static void gen_tlbwe_440(DisasContext *ctx)
6458 {
6459 #if defined(CONFIG_USER_ONLY)
6460 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6461 #else
6462 if (unlikely(!ctx->mem_idx)) {
6463 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6464 return;
6465 }
6466 switch (rB(ctx->opcode)) {
6467 case 0:
6468 case 1:
6469 case 2:
6470 {
6471 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6472 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6473 cpu_gpr[rS(ctx->opcode)]);
6474 tcg_temp_free_i32(t0);
6475 }
6476 break;
6477 default:
6478 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6479 break;
6480 }
6481 #endif
6482 }
6483
6484 /* TLB management - PowerPC BookE 2.06 implementation */
6485
6486 /* tlbre */
6487 static void gen_tlbre_booke206(DisasContext *ctx)
6488 {
6489 #if defined(CONFIG_USER_ONLY)
6490 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6491 #else
6492 if (unlikely(!ctx->mem_idx)) {
6493 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6494 return;
6495 }
6496
6497 gen_helper_booke206_tlbre(cpu_env);
6498 #endif
6499 }
6500
6501 /* tlbsx - tlbsx. */
6502 static void gen_tlbsx_booke206(DisasContext *ctx)
6503 {
6504 #if defined(CONFIG_USER_ONLY)
6505 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6506 #else
6507 TCGv t0;
6508 if (unlikely(!ctx->mem_idx)) {
6509 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6510 return;
6511 }
6512
6513 if (rA(ctx->opcode)) {
6514 t0 = tcg_temp_new();
6515 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6516 } else {
6517 t0 = tcg_const_tl(0);
6518 }
6519
6520 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6521 gen_helper_booke206_tlbsx(cpu_env, t0);
6522 tcg_temp_free(t0);
6523 #endif
6524 }
6525
6526 /* tlbwe */
6527 static void gen_tlbwe_booke206(DisasContext *ctx)
6528 {
6529 #if defined(CONFIG_USER_ONLY)
6530 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6531 #else
6532 if (unlikely(!ctx->mem_idx)) {
6533 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6534 return;
6535 }
6536 gen_update_nip(ctx, ctx->nip - 4);
6537 gen_helper_booke206_tlbwe(cpu_env);
6538 #endif
6539 }
6540
6541 static void gen_tlbivax_booke206(DisasContext *ctx)
6542 {
6543 #if defined(CONFIG_USER_ONLY)
6544 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6545 #else
6546 TCGv t0;
6547 if (unlikely(!ctx->mem_idx)) {
6548 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6549 return;
6550 }
6551
6552 t0 = tcg_temp_new();
6553 gen_addr_reg_index(ctx, t0);
6554
6555 gen_helper_booke206_tlbivax(cpu_env, t0);
6556 tcg_temp_free(t0);
6557 #endif
6558 }
6559
6560 static void gen_tlbilx_booke206(DisasContext *ctx)
6561 {
6562 #if defined(CONFIG_USER_ONLY)
6563 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6564 #else
6565 TCGv t0;
6566 if (unlikely(!ctx->mem_idx)) {
6567 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6568 return;
6569 }
6570
6571 t0 = tcg_temp_new();
6572 gen_addr_reg_index(ctx, t0);
6573
6574 switch((ctx->opcode >> 21) & 0x3) {
6575 case 0:
6576 gen_helper_booke206_tlbilx0(cpu_env, t0);
6577 break;
6578 case 1:
6579 gen_helper_booke206_tlbilx1(cpu_env, t0);
6580 break;
6581 case 3:
6582 gen_helper_booke206_tlbilx3(cpu_env, t0);
6583 break;
6584 default:
6585 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6586 break;
6587 }
6588
6589 tcg_temp_free(t0);
6590 #endif
6591 }
6592
6593
6594 /* wrtee */
6595 static void gen_wrtee(DisasContext *ctx)
6596 {
6597 #if defined(CONFIG_USER_ONLY)
6598 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6599 #else
6600 TCGv t0;
6601 if (unlikely(!ctx->mem_idx)) {
6602 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6603 return;
6604 }
6605 t0 = tcg_temp_new();
6606 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6607 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6608 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6609 tcg_temp_free(t0);
6610 /* Stop translation to have a chance to raise an exception
6611 * if we just set msr_ee to 1
6612 */
6613 gen_stop_exception(ctx);
6614 #endif
6615 }
6616
6617 /* wrteei */
6618 static void gen_wrteei(DisasContext *ctx)
6619 {
6620 #if defined(CONFIG_USER_ONLY)
6621 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6622 #else
6623 if (unlikely(!ctx->mem_idx)) {
6624 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6625 return;
6626 }
6627 if (ctx->opcode & 0x00008000) {
6628 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6629 /* Stop translation to have a chance to raise an exception */
6630 gen_stop_exception(ctx);
6631 } else {
6632 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6633 }
6634 #endif
6635 }
6636
6637 /* PowerPC 440 specific instructions */
6638
6639 /* dlmzb */
6640 static void gen_dlmzb(DisasContext *ctx)
6641 {
6642 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6643 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6644 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6645 tcg_temp_free_i32(t0);
6646 }
6647
6648 /* mbar replaces eieio on 440 */
6649 static void gen_mbar(DisasContext *ctx)
6650 {
6651 /* interpreted as no-op */
6652 }
6653
6654 /* msync replaces sync on 440 */
6655 static void gen_msync_4xx(DisasContext *ctx)
6656 {
6657 /* interpreted as no-op */
6658 }
6659
6660 /* icbt */
6661 static void gen_icbt_440(DisasContext *ctx)
6662 {
6663 /* interpreted as no-op */
6664 /* XXX: specification say this is treated as a load by the MMU
6665 * but does not generate any exception
6666 */
6667 }
6668
6669 /* Embedded.Processor Control */
6670
6671 static void gen_msgclr(DisasContext *ctx)
6672 {
6673 #if defined(CONFIG_USER_ONLY)
6674 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6675 #else
6676 if (unlikely(ctx->mem_idx == 0)) {
6677 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6678 return;
6679 }
6680
6681 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6682 #endif
6683 }
6684
6685 static void gen_msgsnd(DisasContext *ctx)
6686 {
6687 #if defined(CONFIG_USER_ONLY)
6688 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6689 #else
6690 if (unlikely(ctx->mem_idx == 0)) {
6691 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6692 return;
6693 }
6694
6695 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6696 #endif
6697 }
6698
6699 /*** Altivec vector extension ***/
6700 /* Altivec registers moves */
6701
6702 static inline TCGv_ptr gen_avr_ptr(int reg)
6703 {
6704 TCGv_ptr r = tcg_temp_new_ptr();
6705 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6706 return r;
6707 }
6708
6709 #define GEN_VR_LDX(name, opc2, opc3) \
6710 static void glue(gen_, name)(DisasContext *ctx) \
6711 { \
6712 TCGv EA; \
6713 if (unlikely(!ctx->altivec_enabled)) { \
6714 gen_exception(ctx, POWERPC_EXCP_VPU); \
6715 return; \
6716 } \
6717 gen_set_access_type(ctx, ACCESS_INT); \
6718 EA = tcg_temp_new(); \
6719 gen_addr_reg_index(ctx, EA); \
6720 tcg_gen_andi_tl(EA, EA, ~0xf); \
6721 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6722 64-bit byteswap already. */ \
6723 if (ctx->le_mode) { \
6724 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6725 tcg_gen_addi_tl(EA, EA, 8); \
6726 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6727 } else { \
6728 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6729 tcg_gen_addi_tl(EA, EA, 8); \
6730 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6731 } \
6732 tcg_temp_free(EA); \
6733 }
6734
6735 #define GEN_VR_STX(name, opc2, opc3) \
6736 static void gen_st##name(DisasContext *ctx) \
6737 { \
6738 TCGv EA; \
6739 if (unlikely(!ctx->altivec_enabled)) { \
6740 gen_exception(ctx, POWERPC_EXCP_VPU); \
6741 return; \
6742 } \
6743 gen_set_access_type(ctx, ACCESS_INT); \
6744 EA = tcg_temp_new(); \
6745 gen_addr_reg_index(ctx, EA); \
6746 tcg_gen_andi_tl(EA, EA, ~0xf); \
6747 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6748 64-bit byteswap already. */ \
6749 if (ctx->le_mode) { \
6750 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6751 tcg_gen_addi_tl(EA, EA, 8); \
6752 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6753 } else { \
6754 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6755 tcg_gen_addi_tl(EA, EA, 8); \
6756 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6757 } \
6758 tcg_temp_free(EA); \
6759 }
6760
6761 #define GEN_VR_LVE(name, opc2, opc3) \
6762 static void gen_lve##name(DisasContext *ctx) \
6763 { \
6764 TCGv EA; \
6765 TCGv_ptr rs; \
6766 if (unlikely(!ctx->altivec_enabled)) { \
6767 gen_exception(ctx, POWERPC_EXCP_VPU); \
6768 return; \
6769 } \
6770 gen_set_access_type(ctx, ACCESS_INT); \
6771 EA = tcg_temp_new(); \
6772 gen_addr_reg_index(ctx, EA); \
6773 rs = gen_avr_ptr(rS(ctx->opcode)); \
6774 gen_helper_lve##name(cpu_env, rs, EA); \
6775 tcg_temp_free(EA); \
6776 tcg_temp_free_ptr(rs); \
6777 }
6778
6779 #define GEN_VR_STVE(name, opc2, opc3) \
6780 static void gen_stve##name(DisasContext *ctx) \
6781 { \
6782 TCGv EA; \
6783 TCGv_ptr rs; \
6784 if (unlikely(!ctx->altivec_enabled)) { \
6785 gen_exception(ctx, POWERPC_EXCP_VPU); \
6786 return; \
6787 } \
6788 gen_set_access_type(ctx, ACCESS_INT); \
6789 EA = tcg_temp_new(); \
6790 gen_addr_reg_index(ctx, EA); \
6791 rs = gen_avr_ptr(rS(ctx->opcode)); \
6792 gen_helper_stve##name(cpu_env, rs, EA); \
6793 tcg_temp_free(EA); \
6794 tcg_temp_free_ptr(rs); \
6795 }
6796
6797 GEN_VR_LDX(lvx, 0x07, 0x03);
6798 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6799 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6800
6801 GEN_VR_LVE(bx, 0x07, 0x00);
6802 GEN_VR_LVE(hx, 0x07, 0x01);
6803 GEN_VR_LVE(wx, 0x07, 0x02);
6804
6805 GEN_VR_STX(svx, 0x07, 0x07);
6806 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6807 GEN_VR_STX(svxl, 0x07, 0x0F);
6808
6809 GEN_VR_STVE(bx, 0x07, 0x04);
6810 GEN_VR_STVE(hx, 0x07, 0x05);
6811 GEN_VR_STVE(wx, 0x07, 0x06);
6812
6813 static void gen_lvsl(DisasContext *ctx)
6814 {
6815 TCGv_ptr rd;
6816 TCGv EA;
6817 if (unlikely(!ctx->altivec_enabled)) {
6818 gen_exception(ctx, POWERPC_EXCP_VPU);
6819 return;
6820 }
6821 EA = tcg_temp_new();
6822 gen_addr_reg_index(ctx, EA);
6823 rd = gen_avr_ptr(rD(ctx->opcode));
6824 gen_helper_lvsl(rd, EA);
6825 tcg_temp_free(EA);
6826 tcg_temp_free_ptr(rd);
6827 }
6828
6829 static void gen_lvsr(DisasContext *ctx)
6830 {
6831 TCGv_ptr rd;
6832 TCGv EA;
6833 if (unlikely(!ctx->altivec_enabled)) {
6834 gen_exception(ctx, POWERPC_EXCP_VPU);
6835 return;
6836 }
6837 EA = tcg_temp_new();
6838 gen_addr_reg_index(ctx, EA);
6839 rd = gen_avr_ptr(rD(ctx->opcode));
6840 gen_helper_lvsr(rd, EA);
6841 tcg_temp_free(EA);
6842 tcg_temp_free_ptr(rd);
6843 }
6844
6845 static void gen_mfvscr(DisasContext *ctx)
6846 {
6847 TCGv_i32 t;
6848 if (unlikely(!ctx->altivec_enabled)) {
6849 gen_exception(ctx, POWERPC_EXCP_VPU);
6850 return;
6851 }
6852 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6853 t = tcg_temp_new_i32();
6854 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6855 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6856 tcg_temp_free_i32(t);
6857 }
6858
6859 static void gen_mtvscr(DisasContext *ctx)
6860 {
6861 TCGv_ptr p;
6862 if (unlikely(!ctx->altivec_enabled)) {
6863 gen_exception(ctx, POWERPC_EXCP_VPU);
6864 return;
6865 }
6866 p = gen_avr_ptr(rD(ctx->opcode));
6867 gen_helper_mtvscr(cpu_env, p);
6868 tcg_temp_free_ptr(p);
6869 }
6870
6871 /* Logical operations */
6872 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6873 static void glue(gen_, name)(DisasContext *ctx) \
6874 { \
6875 if (unlikely(!ctx->altivec_enabled)) { \
6876 gen_exception(ctx, POWERPC_EXCP_VPU); \
6877 return; \
6878 } \
6879 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6880 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6881 }
6882
6883 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6884 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6885 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6886 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6887 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6888 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6889 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6890 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
6891
6892 #define GEN_VXFORM(name, opc2, opc3) \
6893 static void glue(gen_, name)(DisasContext *ctx) \
6894 { \
6895 TCGv_ptr ra, rb, rd; \
6896 if (unlikely(!ctx->altivec_enabled)) { \
6897 gen_exception(ctx, POWERPC_EXCP_VPU); \
6898 return; \
6899 } \
6900 ra = gen_avr_ptr(rA(ctx->opcode)); \
6901 rb = gen_avr_ptr(rB(ctx->opcode)); \
6902 rd = gen_avr_ptr(rD(ctx->opcode)); \
6903 gen_helper_##name (rd, ra, rb); \
6904 tcg_temp_free_ptr(ra); \
6905 tcg_temp_free_ptr(rb); \
6906 tcg_temp_free_ptr(rd); \
6907 }
6908
6909 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6910 static void glue(gen_, name)(DisasContext *ctx) \
6911 { \
6912 TCGv_ptr ra, rb, rd; \
6913 if (unlikely(!ctx->altivec_enabled)) { \
6914 gen_exception(ctx, POWERPC_EXCP_VPU); \
6915 return; \
6916 } \
6917 ra = gen_avr_ptr(rA(ctx->opcode)); \
6918 rb = gen_avr_ptr(rB(ctx->opcode)); \
6919 rd = gen_avr_ptr(rD(ctx->opcode)); \
6920 gen_helper_##name(cpu_env, rd, ra, rb); \
6921 tcg_temp_free_ptr(ra); \
6922 tcg_temp_free_ptr(rb); \
6923 tcg_temp_free_ptr(rd); \
6924 }
6925
6926 #define GEN_VXFORM3(name, opc2, opc3) \
6927 static void glue(gen_, name)(DisasContext *ctx) \
6928 { \
6929 TCGv_ptr ra, rb, rc, rd; \
6930 if (unlikely(!ctx->altivec_enabled)) { \
6931 gen_exception(ctx, POWERPC_EXCP_VPU); \
6932 return; \
6933 } \
6934 ra = gen_avr_ptr(rA(ctx->opcode)); \
6935 rb = gen_avr_ptr(rB(ctx->opcode)); \
6936 rc = gen_avr_ptr(rC(ctx->opcode)); \
6937 rd = gen_avr_ptr(rD(ctx->opcode)); \
6938 gen_helper_##name(rd, ra, rb, rc); \
6939 tcg_temp_free_ptr(ra); \
6940 tcg_temp_free_ptr(rb); \
6941 tcg_temp_free_ptr(rc); \
6942 tcg_temp_free_ptr(rd); \
6943 }
6944
6945 /*
6946 * Support for Altivec instruction pairs that use bit 31 (Rc) as
6947 * an opcode bit. In general, these pairs come from different
6948 * versions of the ISA, so we must also support a pair of flags for
6949 * each instruction.
6950 */
6951 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
6952 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6953 { \
6954 if ((Rc(ctx->opcode) == 0) && \
6955 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
6956 gen_##name0(ctx); \
6957 } else if ((Rc(ctx->opcode) == 1) && \
6958 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
6959 gen_##name1(ctx); \
6960 } else { \
6961 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
6962 } \
6963 }
6964
6965 GEN_VXFORM(vaddubm, 0, 0);
6966 GEN_VXFORM(vadduhm, 0, 1);
6967 GEN_VXFORM(vadduwm, 0, 2);
6968 GEN_VXFORM(vaddudm, 0, 3);
6969 GEN_VXFORM(vsububm, 0, 16);
6970 GEN_VXFORM(vsubuhm, 0, 17);
6971 GEN_VXFORM(vsubuwm, 0, 18);
6972 GEN_VXFORM(vsubudm, 0, 19);
6973 GEN_VXFORM(vmaxub, 1, 0);
6974 GEN_VXFORM(vmaxuh, 1, 1);
6975 GEN_VXFORM(vmaxuw, 1, 2);
6976 GEN_VXFORM(vmaxud, 1, 3);
6977 GEN_VXFORM(vmaxsb, 1, 4);
6978 GEN_VXFORM(vmaxsh, 1, 5);
6979 GEN_VXFORM(vmaxsw, 1, 6);
6980 GEN_VXFORM(vmaxsd, 1, 7);
6981 GEN_VXFORM(vminub, 1, 8);
6982 GEN_VXFORM(vminuh, 1, 9);
6983 GEN_VXFORM(vminuw, 1, 10);
6984 GEN_VXFORM(vminud, 1, 11);
6985 GEN_VXFORM(vminsb, 1, 12);
6986 GEN_VXFORM(vminsh, 1, 13);
6987 GEN_VXFORM(vminsw, 1, 14);
6988 GEN_VXFORM(vminsd, 1, 15);
6989 GEN_VXFORM(vavgub, 1, 16);
6990 GEN_VXFORM(vavguh, 1, 17);
6991 GEN_VXFORM(vavguw, 1, 18);
6992 GEN_VXFORM(vavgsb, 1, 20);
6993 GEN_VXFORM(vavgsh, 1, 21);
6994 GEN_VXFORM(vavgsw, 1, 22);
6995 GEN_VXFORM(vmrghb, 6, 0);
6996 GEN_VXFORM(vmrghh, 6, 1);
6997 GEN_VXFORM(vmrghw, 6, 2);
6998 GEN_VXFORM(vmrglb, 6, 4);
6999 GEN_VXFORM(vmrglh, 6, 5);
7000 GEN_VXFORM(vmrglw, 6, 6);
7001
7002 static void gen_vmrgew(DisasContext *ctx)
7003 {
7004 TCGv_i64 tmp;
7005 int VT, VA, VB;
7006 if (unlikely(!ctx->altivec_enabled)) {
7007 gen_exception(ctx, POWERPC_EXCP_VPU);
7008 return;
7009 }
7010 VT = rD(ctx->opcode);
7011 VA = rA(ctx->opcode);
7012 VB = rB(ctx->opcode);
7013 tmp = tcg_temp_new_i64();
7014 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7015 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7016 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7017 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7018 tcg_temp_free_i64(tmp);
7019 }
7020
7021 static void gen_vmrgow(DisasContext *ctx)
7022 {
7023 int VT, VA, VB;
7024 if (unlikely(!ctx->altivec_enabled)) {
7025 gen_exception(ctx, POWERPC_EXCP_VPU);
7026 return;
7027 }
7028 VT = rD(ctx->opcode);
7029 VA = rA(ctx->opcode);
7030 VB = rB(ctx->opcode);
7031
7032 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7033 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7034 }
7035
7036 GEN_VXFORM(vmuloub, 4, 0);
7037 GEN_VXFORM(vmulouh, 4, 1);
7038 GEN_VXFORM(vmulouw, 4, 2);
7039 GEN_VXFORM(vmuluwm, 4, 2);
7040 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7041 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7042 GEN_VXFORM(vmulosb, 4, 4);
7043 GEN_VXFORM(vmulosh, 4, 5);
7044 GEN_VXFORM(vmulosw, 4, 6);
7045 GEN_VXFORM(vmuleub, 4, 8);
7046 GEN_VXFORM(vmuleuh, 4, 9);
7047 GEN_VXFORM(vmuleuw, 4, 10);
7048 GEN_VXFORM(vmulesb, 4, 12);
7049 GEN_VXFORM(vmulesh, 4, 13);
7050 GEN_VXFORM(vmulesw, 4, 14);
7051 GEN_VXFORM(vslb, 2, 4);
7052 GEN_VXFORM(vslh, 2, 5);
7053 GEN_VXFORM(vslw, 2, 6);
7054 GEN_VXFORM(vsld, 2, 23);
7055 GEN_VXFORM(vsrb, 2, 8);
7056 GEN_VXFORM(vsrh, 2, 9);
7057 GEN_VXFORM(vsrw, 2, 10);
7058 GEN_VXFORM(vsrd, 2, 27);
7059 GEN_VXFORM(vsrab, 2, 12);
7060 GEN_VXFORM(vsrah, 2, 13);
7061 GEN_VXFORM(vsraw, 2, 14);
7062 GEN_VXFORM(vsrad, 2, 15);
7063 GEN_VXFORM(vslo, 6, 16);
7064 GEN_VXFORM(vsro, 6, 17);
7065 GEN_VXFORM(vaddcuw, 0, 6);
7066 GEN_VXFORM(vsubcuw, 0, 22);
7067 GEN_VXFORM_ENV(vaddubs, 0, 8);
7068 GEN_VXFORM_ENV(vadduhs, 0, 9);
7069 GEN_VXFORM_ENV(vadduws, 0, 10);
7070 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7071 GEN_VXFORM_ENV(vaddshs, 0, 13);
7072 GEN_VXFORM_ENV(vaddsws, 0, 14);
7073 GEN_VXFORM_ENV(vsububs, 0, 24);
7074 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7075 GEN_VXFORM_ENV(vsubuws, 0, 26);
7076 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7077 GEN_VXFORM_ENV(vsubshs, 0, 29);
7078 GEN_VXFORM_ENV(vsubsws, 0, 30);
7079 GEN_VXFORM(vadduqm, 0, 4);
7080 GEN_VXFORM(vaddcuq, 0, 5);
7081 GEN_VXFORM3(vaddeuqm, 30, 0);
7082 GEN_VXFORM3(vaddecuq, 30, 0);
7083 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7084 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7085 GEN_VXFORM(vsubuqm, 0, 20);
7086 GEN_VXFORM(vsubcuq, 0, 21);
7087 GEN_VXFORM3(vsubeuqm, 31, 0);
7088 GEN_VXFORM3(vsubecuq, 31, 0);
7089 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7090 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7091 GEN_VXFORM(vrlb, 2, 0);
7092 GEN_VXFORM(vrlh, 2, 1);
7093 GEN_VXFORM(vrlw, 2, 2);
7094 GEN_VXFORM(vrld, 2, 3);
7095 GEN_VXFORM(vsl, 2, 7);
7096 GEN_VXFORM(vsr, 2, 11);
7097 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7098 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7099 GEN_VXFORM_ENV(vpkudum, 7, 17);
7100 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7101 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7102 GEN_VXFORM_ENV(vpkudus, 7, 19);
7103 GEN_VXFORM_ENV(vpkshus, 7, 4);
7104 GEN_VXFORM_ENV(vpkswus, 7, 5);
7105 GEN_VXFORM_ENV(vpksdus, 7, 21);
7106 GEN_VXFORM_ENV(vpkshss, 7, 6);
7107 GEN_VXFORM_ENV(vpkswss, 7, 7);
7108 GEN_VXFORM_ENV(vpksdss, 7, 23);
7109 GEN_VXFORM(vpkpx, 7, 12);
7110 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7111 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7112 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7113 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7114 GEN_VXFORM_ENV(vsumsws, 4, 30);
7115 GEN_VXFORM_ENV(vaddfp, 5, 0);
7116 GEN_VXFORM_ENV(vsubfp, 5, 1);
7117 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7118 GEN_VXFORM_ENV(vminfp, 5, 17);
7119
7120 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7121 static void glue(gen_, name)(DisasContext *ctx) \
7122 { \
7123 TCGv_ptr ra, rb, rd; \
7124 if (unlikely(!ctx->altivec_enabled)) { \
7125 gen_exception(ctx, POWERPC_EXCP_VPU); \
7126 return; \
7127 } \
7128 ra = gen_avr_ptr(rA(ctx->opcode)); \
7129 rb = gen_avr_ptr(rB(ctx->opcode)); \
7130 rd = gen_avr_ptr(rD(ctx->opcode)); \
7131 gen_helper_##opname(cpu_env, rd, ra, rb); \
7132 tcg_temp_free_ptr(ra); \
7133 tcg_temp_free_ptr(rb); \
7134 tcg_temp_free_ptr(rd); \
7135 }
7136
7137 #define GEN_VXRFORM(name, opc2, opc3) \
7138 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7139 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7140
7141 /*
7142 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7143 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7144 * come from different versions of the ISA, so we must also support a
7145 * pair of flags for each instruction.
7146 */
7147 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7148 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7149 { \
7150 if ((Rc(ctx->opcode) == 0) && \
7151 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7152 if (Rc21(ctx->opcode) == 0) { \
7153 gen_##name0(ctx); \
7154 } else { \
7155 gen_##name0##_(ctx); \
7156 } \
7157 } else if ((Rc(ctx->opcode) == 1) && \
7158 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7159 if (Rc21(ctx->opcode) == 0) { \
7160 gen_##name1(ctx); \
7161 } else { \
7162 gen_##name1##_(ctx); \
7163 } \
7164 } else { \
7165 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7166 } \
7167 }
7168
7169 GEN_VXRFORM(vcmpequb, 3, 0)
7170 GEN_VXRFORM(vcmpequh, 3, 1)
7171 GEN_VXRFORM(vcmpequw, 3, 2)
7172 GEN_VXRFORM(vcmpequd, 3, 3)
7173 GEN_VXRFORM(vcmpgtsb, 3, 12)
7174 GEN_VXRFORM(vcmpgtsh, 3, 13)
7175 GEN_VXRFORM(vcmpgtsw, 3, 14)
7176 GEN_VXRFORM(vcmpgtsd, 3, 15)
7177 GEN_VXRFORM(vcmpgtub, 3, 8)
7178 GEN_VXRFORM(vcmpgtuh, 3, 9)
7179 GEN_VXRFORM(vcmpgtuw, 3, 10)
7180 GEN_VXRFORM(vcmpgtud, 3, 11)
7181 GEN_VXRFORM(vcmpeqfp, 3, 3)
7182 GEN_VXRFORM(vcmpgefp, 3, 7)
7183 GEN_VXRFORM(vcmpgtfp, 3, 11)
7184 GEN_VXRFORM(vcmpbfp, 3, 15)
7185
7186 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7187 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7188 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7189 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7190 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7191 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7192
7193 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7194 static void glue(gen_, name)(DisasContext *ctx) \
7195 { \
7196 TCGv_ptr rd; \
7197 TCGv_i32 simm; \
7198 if (unlikely(!ctx->altivec_enabled)) { \
7199 gen_exception(ctx, POWERPC_EXCP_VPU); \
7200 return; \
7201 } \
7202 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7203 rd = gen_avr_ptr(rD(ctx->opcode)); \
7204 gen_helper_##name (rd, simm); \
7205 tcg_temp_free_i32(simm); \
7206 tcg_temp_free_ptr(rd); \
7207 }
7208
7209 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7210 GEN_VXFORM_SIMM(vspltish, 6, 13);
7211 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7212
7213 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7214 static void glue(gen_, name)(DisasContext *ctx) \
7215 { \
7216 TCGv_ptr rb, rd; \
7217 if (unlikely(!ctx->altivec_enabled)) { \
7218 gen_exception(ctx, POWERPC_EXCP_VPU); \
7219 return; \
7220 } \
7221 rb = gen_avr_ptr(rB(ctx->opcode)); \
7222 rd = gen_avr_ptr(rD(ctx->opcode)); \
7223 gen_helper_##name (rd, rb); \
7224 tcg_temp_free_ptr(rb); \
7225 tcg_temp_free_ptr(rd); \
7226 }
7227
7228 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7229 static void glue(gen_, name)(DisasContext *ctx) \
7230 { \
7231 TCGv_ptr rb, rd; \
7232 \
7233 if (unlikely(!ctx->altivec_enabled)) { \
7234 gen_exception(ctx, POWERPC_EXCP_VPU); \
7235 return; \
7236 } \
7237 rb = gen_avr_ptr(rB(ctx->opcode)); \
7238 rd = gen_avr_ptr(rD(ctx->opcode)); \
7239 gen_helper_##name(cpu_env, rd, rb); \
7240 tcg_temp_free_ptr(rb); \
7241 tcg_temp_free_ptr(rd); \
7242 }
7243
7244 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7245 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7246 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7247 GEN_VXFORM_NOA(vupklsb, 7, 10);
7248 GEN_VXFORM_NOA(vupklsh, 7, 11);
7249 GEN_VXFORM_NOA(vupklsw, 7, 27);
7250 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7251 GEN_VXFORM_NOA(vupklpx, 7, 15);
7252 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7253 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7254 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7255 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7256 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
7257 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
7258 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7259 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
7260
7261 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7262 static void glue(gen_, name)(DisasContext *ctx) \
7263 { \
7264 TCGv_ptr rd; \
7265 TCGv_i32 simm; \
7266 if (unlikely(!ctx->altivec_enabled)) { \
7267 gen_exception(ctx, POWERPC_EXCP_VPU); \
7268 return; \
7269 } \
7270 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7271 rd = gen_avr_ptr(rD(ctx->opcode)); \
7272 gen_helper_##name (rd, simm); \
7273 tcg_temp_free_i32(simm); \
7274 tcg_temp_free_ptr(rd); \
7275 }
7276
7277 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7278 static void glue(gen_, name)(DisasContext *ctx) \
7279 { \
7280 TCGv_ptr rb, rd; \
7281 TCGv_i32 uimm; \
7282 if (unlikely(!ctx->altivec_enabled)) { \
7283 gen_exception(ctx, POWERPC_EXCP_VPU); \
7284 return; \
7285 } \
7286 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7287 rb = gen_avr_ptr(rB(ctx->opcode)); \
7288 rd = gen_avr_ptr(rD(ctx->opcode)); \
7289 gen_helper_##name (rd, rb, uimm); \
7290 tcg_temp_free_i32(uimm); \
7291 tcg_temp_free_ptr(rb); \
7292 tcg_temp_free_ptr(rd); \
7293 }
7294
7295 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7296 static void glue(gen_, name)(DisasContext *ctx) \
7297 { \
7298 TCGv_ptr rb, rd; \
7299 TCGv_i32 uimm; \
7300 \
7301 if (unlikely(!ctx->altivec_enabled)) { \
7302 gen_exception(ctx, POWERPC_EXCP_VPU); \
7303 return; \
7304 } \
7305 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7306 rb = gen_avr_ptr(rB(ctx->opcode)); \
7307 rd = gen_avr_ptr(rD(ctx->opcode)); \
7308 gen_helper_##name(cpu_env, rd, rb, uimm); \
7309 tcg_temp_free_i32(uimm); \
7310 tcg_temp_free_ptr(rb); \
7311 tcg_temp_free_ptr(rd); \
7312 }
7313
7314 GEN_VXFORM_UIMM(vspltb, 6, 8);
7315 GEN_VXFORM_UIMM(vsplth, 6, 9);
7316 GEN_VXFORM_UIMM(vspltw, 6, 10);
7317 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7318 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7319 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7320 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7321
7322 static void gen_vsldoi(DisasContext *ctx)
7323 {
7324 TCGv_ptr ra, rb, rd;
7325 TCGv_i32 sh;
7326 if (unlikely(!ctx->altivec_enabled)) {
7327 gen_exception(ctx, POWERPC_EXCP_VPU);
7328 return;
7329 }
7330 ra = gen_avr_ptr(rA(ctx->opcode));
7331 rb = gen_avr_ptr(rB(ctx->opcode));
7332 rd = gen_avr_ptr(rD(ctx->opcode));
7333 sh = tcg_const_i32(VSH(ctx->opcode));
7334 gen_helper_vsldoi (rd, ra, rb, sh);
7335 tcg_temp_free_ptr(ra);
7336 tcg_temp_free_ptr(rb);
7337 tcg_temp_free_ptr(rd);
7338 tcg_temp_free_i32(sh);
7339 }
7340
7341 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7342 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7343 { \
7344 TCGv_ptr ra, rb, rc, rd; \
7345 if (unlikely(!ctx->altivec_enabled)) { \
7346 gen_exception(ctx, POWERPC_EXCP_VPU); \
7347 return; \
7348 } \
7349 ra = gen_avr_ptr(rA(ctx->opcode)); \
7350 rb = gen_avr_ptr(rB(ctx->opcode)); \
7351 rc = gen_avr_ptr(rC(ctx->opcode)); \
7352 rd = gen_avr_ptr(rD(ctx->opcode)); \
7353 if (Rc(ctx->opcode)) { \
7354 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7355 } else { \
7356 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7357 } \
7358 tcg_temp_free_ptr(ra); \
7359 tcg_temp_free_ptr(rb); \
7360 tcg_temp_free_ptr(rc); \
7361 tcg_temp_free_ptr(rd); \
7362 }
7363
7364 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7365
7366 static void gen_vmladduhm(DisasContext *ctx)
7367 {
7368 TCGv_ptr ra, rb, rc, rd;
7369 if (unlikely(!ctx->altivec_enabled)) {
7370 gen_exception(ctx, POWERPC_EXCP_VPU);
7371 return;
7372 }
7373 ra = gen_avr_ptr(rA(ctx->opcode));
7374 rb = gen_avr_ptr(rB(ctx->opcode));
7375 rc = gen_avr_ptr(rC(ctx->opcode));
7376 rd = gen_avr_ptr(rD(ctx->opcode));
7377 gen_helper_vmladduhm(rd, ra, rb, rc);
7378 tcg_temp_free_ptr(ra);
7379 tcg_temp_free_ptr(rb);
7380 tcg_temp_free_ptr(rc);
7381 tcg_temp_free_ptr(rd);
7382 }
7383
7384 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7385 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7386 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7387 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7388 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7389
7390 GEN_VXFORM_NOA(vclzb, 1, 28)
7391 GEN_VXFORM_NOA(vclzh, 1, 29)
7392 GEN_VXFORM_NOA(vclzw, 1, 30)
7393 GEN_VXFORM_NOA(vclzd, 1, 31)
7394 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7395 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7396 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7397 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7398 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7399 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7400 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7401 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7402 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7403 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7404 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7405 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7406 GEN_VXFORM(vbpermq, 6, 21);
7407 GEN_VXFORM_NOA(vgbbd, 6, 20);
7408 GEN_VXFORM(vpmsumb, 4, 16)
7409 GEN_VXFORM(vpmsumh, 4, 17)
7410 GEN_VXFORM(vpmsumw, 4, 18)
7411 GEN_VXFORM(vpmsumd, 4, 19)
7412
7413 #define GEN_BCD(op) \
7414 static void gen_##op(DisasContext *ctx) \
7415 { \
7416 TCGv_ptr ra, rb, rd; \
7417 TCGv_i32 ps; \
7418 \
7419 if (unlikely(!ctx->altivec_enabled)) { \
7420 gen_exception(ctx, POWERPC_EXCP_VPU); \
7421 return; \
7422 } \
7423 \
7424 ra = gen_avr_ptr(rA(ctx->opcode)); \
7425 rb = gen_avr_ptr(rB(ctx->opcode)); \
7426 rd = gen_avr_ptr(rD(ctx->opcode)); \
7427 \
7428 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7429 \
7430 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7431 \
7432 tcg_temp_free_ptr(ra); \
7433 tcg_temp_free_ptr(rb); \
7434 tcg_temp_free_ptr(rd); \
7435 tcg_temp_free_i32(ps); \
7436 }
7437
7438 GEN_BCD(bcdadd)
7439 GEN_BCD(bcdsub)
7440
7441 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7442 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7443 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7444 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7445 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7446 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7447 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7448 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7449
7450 static void gen_vsbox(DisasContext *ctx)
7451 {
7452 TCGv_ptr ra, rd;
7453 if (unlikely(!ctx->altivec_enabled)) {
7454 gen_exception(ctx, POWERPC_EXCP_VPU);
7455 return;
7456 }
7457 ra = gen_avr_ptr(rA(ctx->opcode));
7458 rd = gen_avr_ptr(rD(ctx->opcode));
7459 gen_helper_vsbox(rd, ra);
7460 tcg_temp_free_ptr(ra);
7461 tcg_temp_free_ptr(rd);
7462 }
7463
7464 GEN_VXFORM(vcipher, 4, 20)
7465 GEN_VXFORM(vcipherlast, 4, 20)
7466 GEN_VXFORM(vncipher, 4, 21)
7467 GEN_VXFORM(vncipherlast, 4, 21)
7468
7469 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7470 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7471 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7472 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7473
7474 #define VSHASIGMA(op) \
7475 static void gen_##op(DisasContext *ctx) \
7476 { \
7477 TCGv_ptr ra, rd; \
7478 TCGv_i32 st_six; \
7479 if (unlikely(!ctx->altivec_enabled)) { \
7480 gen_exception(ctx, POWERPC_EXCP_VPU); \
7481 return; \
7482 } \
7483 ra = gen_avr_ptr(rA(ctx->opcode)); \
7484 rd = gen_avr_ptr(rD(ctx->opcode)); \
7485 st_six = tcg_const_i32(rB(ctx->opcode)); \
7486 gen_helper_##op(rd, ra, st_six); \
7487 tcg_temp_free_ptr(ra); \
7488 tcg_temp_free_ptr(rd); \
7489 tcg_temp_free_i32(st_six); \
7490 }
7491
7492 VSHASIGMA(vshasigmaw)
7493 VSHASIGMA(vshasigmad)
7494
7495 GEN_VXFORM3(vpermxor, 22, 0xFF)
7496 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7497 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7498
7499 /*** VSX extension ***/
7500
7501 static inline TCGv_i64 cpu_vsrh(int n)
7502 {
7503 if (n < 32) {
7504 return cpu_fpr[n];
7505 } else {
7506 return cpu_avrh[n-32];
7507 }
7508 }
7509
7510 static inline TCGv_i64 cpu_vsrl(int n)
7511 {
7512 if (n < 32) {
7513 return cpu_vsr[n];
7514 } else {
7515 return cpu_avrl[n-32];
7516 }
7517 }
7518
7519 #define VSX_LOAD_SCALAR(name, operation) \
7520 static void gen_##name(DisasContext *ctx) \
7521 { \
7522 TCGv EA; \
7523 if (unlikely(!ctx->vsx_enabled)) { \
7524 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7525 return; \
7526 } \
7527 gen_set_access_type(ctx, ACCESS_INT); \
7528 EA = tcg_temp_new(); \
7529 gen_addr_reg_index(ctx, EA); \
7530 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7531 /* NOTE: cpu_vsrl is undefined */ \
7532 tcg_temp_free(EA); \
7533 }
7534
7535 VSX_LOAD_SCALAR(lxsdx, ld64)
7536 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7537 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7538 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7539
7540 static void gen_lxvd2x(DisasContext *ctx)
7541 {
7542 TCGv EA;
7543 if (unlikely(!ctx->vsx_enabled)) {
7544 gen_exception(ctx, POWERPC_EXCP_VSXU);
7545 return;
7546 }
7547 gen_set_access_type(ctx, ACCESS_INT);
7548 EA = tcg_temp_new();
7549 gen_addr_reg_index(ctx, EA);
7550 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7551 tcg_gen_addi_tl(EA, EA, 8);
7552 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7553 tcg_temp_free(EA);
7554 }
7555
7556 static void gen_lxvdsx(DisasContext *ctx)
7557 {
7558 TCGv EA;
7559 if (unlikely(!ctx->vsx_enabled)) {
7560 gen_exception(ctx, POWERPC_EXCP_VSXU);
7561 return;
7562 }
7563 gen_set_access_type(ctx, ACCESS_INT);
7564 EA = tcg_temp_new();
7565 gen_addr_reg_index(ctx, EA);
7566 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7567 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7568 tcg_temp_free(EA);
7569 }
7570
7571 static void gen_lxvw4x(DisasContext *ctx)
7572 {
7573 TCGv EA;
7574 TCGv_i64 tmp;
7575 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7576 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7577 if (unlikely(!ctx->vsx_enabled)) {
7578 gen_exception(ctx, POWERPC_EXCP_VSXU);
7579 return;
7580 }
7581 gen_set_access_type(ctx, ACCESS_INT);
7582 EA = tcg_temp_new();
7583 tmp = tcg_temp_new_i64();
7584
7585 gen_addr_reg_index(ctx, EA);
7586 gen_qemu_ld32u_i64(ctx, tmp, EA);
7587 tcg_gen_addi_tl(EA, EA, 4);
7588 gen_qemu_ld32u_i64(ctx, xth, EA);
7589 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7590
7591 tcg_gen_addi_tl(EA, EA, 4);
7592 gen_qemu_ld32u_i64(ctx, tmp, EA);
7593 tcg_gen_addi_tl(EA, EA, 4);
7594 gen_qemu_ld32u_i64(ctx, xtl, EA);
7595 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7596
7597 tcg_temp_free(EA);
7598 tcg_temp_free_i64(tmp);
7599 }
7600
7601 #define VSX_STORE_SCALAR(name, operation) \
7602 static void gen_##name(DisasContext *ctx) \
7603 { \
7604 TCGv EA; \
7605 if (unlikely(!ctx->vsx_enabled)) { \
7606 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7607 return; \
7608 } \
7609 gen_set_access_type(ctx, ACCESS_INT); \
7610 EA = tcg_temp_new(); \
7611 gen_addr_reg_index(ctx, EA); \
7612 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7613 tcg_temp_free(EA); \
7614 }
7615
7616 VSX_STORE_SCALAR(stxsdx, st64)
7617 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7618 VSX_STORE_SCALAR(stxsspx, st32fs)
7619
7620 static void gen_stxvd2x(DisasContext *ctx)
7621 {
7622 TCGv EA;
7623 if (unlikely(!ctx->vsx_enabled)) {
7624 gen_exception(ctx, POWERPC_EXCP_VSXU);
7625 return;
7626 }
7627 gen_set_access_type(ctx, ACCESS_INT);
7628 EA = tcg_temp_new();
7629 gen_addr_reg_index(ctx, EA);
7630 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7631 tcg_gen_addi_tl(EA, EA, 8);
7632 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7633 tcg_temp_free(EA);
7634 }
7635
7636 static void gen_stxvw4x(DisasContext *ctx)
7637 {
7638 TCGv_i64 tmp;
7639 TCGv EA;
7640 if (unlikely(!ctx->vsx_enabled)) {
7641 gen_exception(ctx, POWERPC_EXCP_VSXU);
7642 return;
7643 }
7644 gen_set_access_type(ctx, ACCESS_INT);
7645 EA = tcg_temp_new();
7646 gen_addr_reg_index(ctx, EA);
7647 tmp = tcg_temp_new_i64();
7648
7649 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7650 gen_qemu_st32_i64(ctx, tmp, EA);
7651 tcg_gen_addi_tl(EA, EA, 4);
7652 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7653
7654 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7655 tcg_gen_addi_tl(EA, EA, 4);
7656 gen_qemu_st32_i64(ctx, tmp, EA);
7657 tcg_gen_addi_tl(EA, EA, 4);
7658 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7659
7660 tcg_temp_free(EA);
7661 tcg_temp_free_i64(tmp);
7662 }
7663
7664 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7665 static void gen_##name(DisasContext *ctx) \
7666 { \
7667 if (xS(ctx->opcode) < 32) { \
7668 if (unlikely(!ctx->fpu_enabled)) { \
7669 gen_exception(ctx, POWERPC_EXCP_FPU); \
7670 return; \
7671 } \
7672 } else { \
7673 if (unlikely(!ctx->altivec_enabled)) { \
7674 gen_exception(ctx, POWERPC_EXCP_VPU); \
7675 return; \
7676 } \
7677 } \
7678 TCGv_i64 tmp = tcg_temp_new_i64(); \
7679 tcg_gen_##tcgop1(tmp, source); \
7680 tcg_gen_##tcgop2(target, tmp); \
7681 tcg_temp_free_i64(tmp); \
7682 }
7683
7684
7685 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7686 cpu_vsrh(xS(ctx->opcode)))
7687 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7688 cpu_gpr[rA(ctx->opcode)])
7689 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7690 cpu_gpr[rA(ctx->opcode)])
7691
7692 #if defined(TARGET_PPC64)
7693 #define MV_VSRD(name, target, source) \
7694 static void gen_##name(DisasContext *ctx) \
7695 { \
7696 if (xS(ctx->opcode) < 32) { \
7697 if (unlikely(!ctx->fpu_enabled)) { \
7698 gen_exception(ctx, POWERPC_EXCP_FPU); \
7699 return; \
7700 } \
7701 } else { \
7702 if (unlikely(!ctx->altivec_enabled)) { \
7703 gen_exception(ctx, POWERPC_EXCP_VPU); \
7704 return; \
7705 } \
7706 } \
7707 tcg_gen_mov_i64(target, source); \
7708 }
7709
7710 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7711 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7712
7713 #endif
7714
7715 static void gen_xxpermdi(DisasContext *ctx)
7716 {
7717 if (unlikely(!ctx->vsx_enabled)) {
7718 gen_exception(ctx, POWERPC_EXCP_VSXU);
7719 return;
7720 }
7721
7722 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7723 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7724 TCGv_i64 xh, xl;
7725
7726 xh = tcg_temp_new_i64();
7727 xl = tcg_temp_new_i64();
7728
7729 if ((DM(ctx->opcode) & 2) == 0) {
7730 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7731 } else {
7732 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7733 }
7734 if ((DM(ctx->opcode) & 1) == 0) {
7735 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7736 } else {
7737 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7738 }
7739
7740 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7741 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7742
7743 tcg_temp_free_i64(xh);
7744 tcg_temp_free_i64(xl);
7745 } else {
7746 if ((DM(ctx->opcode) & 2) == 0) {
7747 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7748 } else {
7749 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7750 }
7751 if ((DM(ctx->opcode) & 1) == 0) {
7752 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7753 } else {
7754 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7755 }
7756 }
7757 }
7758
7759 #define OP_ABS 1
7760 #define OP_NABS 2
7761 #define OP_NEG 3
7762 #define OP_CPSGN 4
7763 #define SGN_MASK_DP 0x8000000000000000ull
7764 #define SGN_MASK_SP 0x8000000080000000ull
7765
7766 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7767 static void glue(gen_, name)(DisasContext * ctx) \
7768 { \
7769 TCGv_i64 xb, sgm; \
7770 if (unlikely(!ctx->vsx_enabled)) { \
7771 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7772 return; \
7773 } \
7774 xb = tcg_temp_new_i64(); \
7775 sgm = tcg_temp_new_i64(); \
7776 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7777 tcg_gen_movi_i64(sgm, sgn_mask); \
7778 switch (op) { \
7779 case OP_ABS: { \
7780 tcg_gen_andc_i64(xb, xb, sgm); \
7781 break; \
7782 } \
7783 case OP_NABS: { \
7784 tcg_gen_or_i64(xb, xb, sgm); \
7785 break; \
7786 } \
7787 case OP_NEG: { \
7788 tcg_gen_xor_i64(xb, xb, sgm); \
7789 break; \
7790 } \
7791 case OP_CPSGN: { \
7792 TCGv_i64 xa = tcg_temp_new_i64(); \
7793 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7794 tcg_gen_and_i64(xa, xa, sgm); \
7795 tcg_gen_andc_i64(xb, xb, sgm); \
7796 tcg_gen_or_i64(xb, xb, xa); \
7797 tcg_temp_free_i64(xa); \
7798 break; \
7799 } \
7800 } \
7801 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7802 tcg_temp_free_i64(xb); \
7803 tcg_temp_free_i64(sgm); \
7804 }
7805
7806 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7807 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7808 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7809 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7810
7811 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7812 static void glue(gen_, name)(DisasContext * ctx) \
7813 { \
7814 TCGv_i64 xbh, xbl, sgm; \
7815 if (unlikely(!ctx->vsx_enabled)) { \
7816 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7817 return; \
7818 } \
7819 xbh = tcg_temp_new_i64(); \
7820 xbl = tcg_temp_new_i64(); \
7821 sgm = tcg_temp_new_i64(); \
7822 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7823 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7824 tcg_gen_movi_i64(sgm, sgn_mask); \
7825 switch (op) { \
7826 case OP_ABS: { \
7827 tcg_gen_andc_i64(xbh, xbh, sgm); \
7828 tcg_gen_andc_i64(xbl, xbl, sgm); \
7829 break; \
7830 } \
7831 case OP_NABS: { \
7832 tcg_gen_or_i64(xbh, xbh, sgm); \
7833 tcg_gen_or_i64(xbl, xbl, sgm); \
7834 break; \
7835 } \
7836 case OP_NEG: { \
7837 tcg_gen_xor_i64(xbh, xbh, sgm); \
7838 tcg_gen_xor_i64(xbl, xbl, sgm); \
7839 break; \
7840 } \
7841 case OP_CPSGN: { \
7842 TCGv_i64 xah = tcg_temp_new_i64(); \
7843 TCGv_i64 xal = tcg_temp_new_i64(); \
7844 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7845 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7846 tcg_gen_and_i64(xah, xah, sgm); \
7847 tcg_gen_and_i64(xal, xal, sgm); \
7848 tcg_gen_andc_i64(xbh, xbh, sgm); \
7849 tcg_gen_andc_i64(xbl, xbl, sgm); \
7850 tcg_gen_or_i64(xbh, xbh, xah); \
7851 tcg_gen_or_i64(xbl, xbl, xal); \
7852 tcg_temp_free_i64(xah); \
7853 tcg_temp_free_i64(xal); \
7854 break; \
7855 } \
7856 } \
7857 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7858 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7859 tcg_temp_free_i64(xbh); \
7860 tcg_temp_free_i64(xbl); \
7861 tcg_temp_free_i64(sgm); \
7862 }
7863
7864 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7865 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7866 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7867 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7868 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7869 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7870 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7871 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7872
7873 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7874 static void gen_##name(DisasContext * ctx) \
7875 { \
7876 TCGv_i32 opc; \
7877 if (unlikely(!ctx->vsx_enabled)) { \
7878 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7879 return; \
7880 } \
7881 /* NIP cannot be restored if the memory exception comes from an helper */ \
7882 gen_update_nip(ctx, ctx->nip - 4); \
7883 opc = tcg_const_i32(ctx->opcode); \
7884 gen_helper_##name(cpu_env, opc); \
7885 tcg_temp_free_i32(opc); \
7886 }
7887
7888 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7889 static void gen_##name(DisasContext * ctx) \
7890 { \
7891 if (unlikely(!ctx->vsx_enabled)) { \
7892 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7893 return; \
7894 } \
7895 /* NIP cannot be restored if the exception comes */ \
7896 /* from a helper. */ \
7897 gen_update_nip(ctx, ctx->nip - 4); \
7898 \
7899 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7900 cpu_vsrh(xB(ctx->opcode))); \
7901 }
7902
7903 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7904 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7905 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7906 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7907 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7908 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7909 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7910 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7911 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7912 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7913 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7914 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7915 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7916 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7917 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7918 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7919 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7920 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7921 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7922 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7923 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7924 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7925 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
7926 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7927 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
7928 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7929 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7930 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7931 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7932 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7933 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
7934 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7935 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7936 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7937 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7938 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
7939 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
7940
7941 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7942 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
7943 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
7944 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
7945 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
7946 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
7947 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
7948 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7949 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7950 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7951 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7952 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7953 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
7954 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
7955 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
7956 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
7957 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
7958
7959 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7960 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
7961 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
7962 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
7963 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
7964 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
7965 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
7966 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
7967 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
7968 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
7969 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
7970 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
7971 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
7972 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
7973 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
7974 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
7975 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
7976 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
7977 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
7978 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
7979 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
7980 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
7981 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
7982 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
7983 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
7984 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
7985 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
7986 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
7987 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
7988 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
7989 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
7990 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
7991 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
7992 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
7993 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
7994 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
7995
7996 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
7997 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
7998 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
7999 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
8000 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
8001 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
8002 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
8003 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
8004 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
8005 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8006 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8007 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8008 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8009 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8010 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8011 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8012 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
8013 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8014 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
8015 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8016 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8017 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
8018 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
8019 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8020 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8021 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8022 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8023 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8024 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8025 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8026 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
8027 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8028 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8029 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8030 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8031 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
8032
8033 #define VSX_LOGICAL(name, tcg_op) \
8034 static void glue(gen_, name)(DisasContext * ctx) \
8035 { \
8036 if (unlikely(!ctx->vsx_enabled)) { \
8037 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8038 return; \
8039 } \
8040 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8041 cpu_vsrh(xB(ctx->opcode))); \
8042 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8043 cpu_vsrl(xB(ctx->opcode))); \
8044 }
8045
8046 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8047 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8048 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8049 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8050 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8051 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8052 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8053 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8054
8055 #define VSX_XXMRG(name, high) \
8056 static void glue(gen_, name)(DisasContext * ctx) \
8057 { \
8058 TCGv_i64 a0, a1, b0, b1; \
8059 if (unlikely(!ctx->vsx_enabled)) { \
8060 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8061 return; \
8062 } \
8063 a0 = tcg_temp_new_i64(); \
8064 a1 = tcg_temp_new_i64(); \
8065 b0 = tcg_temp_new_i64(); \
8066 b1 = tcg_temp_new_i64(); \
8067 if (high) { \
8068 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8069 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8070 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8071 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8072 } else { \
8073 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8074 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8075 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8076 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8077 } \
8078 tcg_gen_shri_i64(a0, a0, 32); \
8079 tcg_gen_shri_i64(b0, b0, 32); \
8080 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8081 b0, a0, 32, 32); \
8082 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8083 b1, a1, 32, 32); \
8084 tcg_temp_free_i64(a0); \
8085 tcg_temp_free_i64(a1); \
8086 tcg_temp_free_i64(b0); \
8087 tcg_temp_free_i64(b1); \
8088 }
8089
8090 VSX_XXMRG(xxmrghw, 1)
8091 VSX_XXMRG(xxmrglw, 0)
8092
8093 static void gen_xxsel(DisasContext * ctx)
8094 {
8095 TCGv_i64 a, b, c;
8096 if (unlikely(!ctx->vsx_enabled)) {
8097 gen_exception(ctx, POWERPC_EXCP_VSXU);
8098 return;
8099 }
8100 a = tcg_temp_new_i64();
8101 b = tcg_temp_new_i64();
8102 c = tcg_temp_new_i64();
8103
8104 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8105 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8106 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8107
8108 tcg_gen_and_i64(b, b, c);
8109 tcg_gen_andc_i64(a, a, c);
8110 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8111
8112 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8113 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8114 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8115
8116 tcg_gen_and_i64(b, b, c);
8117 tcg_gen_andc_i64(a, a, c);
8118 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8119
8120 tcg_temp_free_i64(a);
8121 tcg_temp_free_i64(b);
8122 tcg_temp_free_i64(c);
8123 }
8124
8125 static void gen_xxspltw(DisasContext *ctx)
8126 {
8127 TCGv_i64 b, b2;
8128 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8129 cpu_vsrl(xB(ctx->opcode)) :
8130 cpu_vsrh(xB(ctx->opcode));
8131
8132 if (unlikely(!ctx->vsx_enabled)) {
8133 gen_exception(ctx, POWERPC_EXCP_VSXU);
8134 return;
8135 }
8136
8137 b = tcg_temp_new_i64();
8138 b2 = tcg_temp_new_i64();
8139
8140 if (UIM(ctx->opcode) & 1) {
8141 tcg_gen_ext32u_i64(b, vsr);
8142 } else {
8143 tcg_gen_shri_i64(b, vsr, 32);
8144 }
8145
8146 tcg_gen_shli_i64(b2, b, 32);
8147 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8148 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8149
8150 tcg_temp_free_i64(b);
8151 tcg_temp_free_i64(b2);
8152 }
8153
8154 static void gen_xxsldwi(DisasContext *ctx)
8155 {
8156 TCGv_i64 xth, xtl;
8157 if (unlikely(!ctx->vsx_enabled)) {
8158 gen_exception(ctx, POWERPC_EXCP_VSXU);
8159 return;
8160 }
8161 xth = tcg_temp_new_i64();
8162 xtl = tcg_temp_new_i64();
8163
8164 switch (SHW(ctx->opcode)) {
8165 case 0: {
8166 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8167 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8168 break;
8169 }
8170 case 1: {
8171 TCGv_i64 t0 = tcg_temp_new_i64();
8172 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8173 tcg_gen_shli_i64(xth, xth, 32);
8174 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8175 tcg_gen_shri_i64(t0, t0, 32);
8176 tcg_gen_or_i64(xth, xth, t0);
8177 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8178 tcg_gen_shli_i64(xtl, xtl, 32);
8179 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8180 tcg_gen_shri_i64(t0, t0, 32);
8181 tcg_gen_or_i64(xtl, xtl, t0);
8182 tcg_temp_free_i64(t0);
8183 break;
8184 }
8185 case 2: {
8186 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8187 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8188 break;
8189 }
8190 case 3: {
8191 TCGv_i64 t0 = tcg_temp_new_i64();
8192 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8193 tcg_gen_shli_i64(xth, xth, 32);
8194 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8195 tcg_gen_shri_i64(t0, t0, 32);
8196 tcg_gen_or_i64(xth, xth, t0);
8197 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8198 tcg_gen_shli_i64(xtl, xtl, 32);
8199 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8200 tcg_gen_shri_i64(t0, t0, 32);
8201 tcg_gen_or_i64(xtl, xtl, t0);
8202 tcg_temp_free_i64(t0);
8203 break;
8204 }
8205 }
8206
8207 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8208 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8209
8210 tcg_temp_free_i64(xth);
8211 tcg_temp_free_i64(xtl);
8212 }
8213
8214 /*** Decimal Floating Point ***/
8215
8216 static inline TCGv_ptr gen_fprp_ptr(int reg)
8217 {
8218 TCGv_ptr r = tcg_temp_new_ptr();
8219 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8220 return r;
8221 }
8222
8223 #if defined(TARGET_PPC64)
8224 static void gen_set_cr6_from_fpscr(DisasContext *ctx)
8225 {
8226 TCGv_i32 tmp = tcg_temp_new_i32();
8227 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
8228 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
8229 tcg_temp_free_i32(tmp);
8230 }
8231 #else
8232 static void gen_set_cr6_from_fpscr(DisasContext *ctx)
8233 {
8234 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
8235 }
8236 #endif
8237
8238 #define GEN_DFP_T_A_B_Rc(name) \
8239 static void gen_##name(DisasContext *ctx) \
8240 { \
8241 TCGv_ptr rd, ra, rb; \
8242 if (unlikely(!ctx->fpu_enabled)) { \
8243 gen_exception(ctx, POWERPC_EXCP_FPU); \
8244 return; \
8245 } \
8246 gen_update_nip(ctx, ctx->nip - 4); \
8247 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8248 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8249 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8250 gen_helper_##name(cpu_env, rd, ra, rb); \
8251 if (unlikely(Rc(ctx->opcode) != 0)) { \
8252 gen_set_cr6_from_fpscr(ctx); \
8253 } \
8254 tcg_temp_free_ptr(rd); \
8255 tcg_temp_free_ptr(ra); \
8256 tcg_temp_free_ptr(rb); \
8257 }
8258
8259 #define GEN_DFP_BF_A_B(name) \
8260 static void gen_##name(DisasContext *ctx) \
8261 { \
8262 TCGv_ptr ra, rb; \
8263 if (unlikely(!ctx->fpu_enabled)) { \
8264 gen_exception(ctx, POWERPC_EXCP_FPU); \
8265 return; \
8266 } \
8267 gen_update_nip(ctx, ctx->nip - 4); \
8268 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8269 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8270 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8271 cpu_env, ra, rb); \
8272 tcg_temp_free_ptr(ra); \
8273 tcg_temp_free_ptr(rb); \
8274 }
8275
8276 #define GEN_DFP_BF_A_DCM(name) \
8277 static void gen_##name(DisasContext *ctx) \
8278 { \
8279 TCGv_ptr ra; \
8280 TCGv_i32 dcm; \
8281 if (unlikely(!ctx->fpu_enabled)) { \
8282 gen_exception(ctx, POWERPC_EXCP_FPU); \
8283 return; \
8284 } \
8285 gen_update_nip(ctx, ctx->nip - 4); \
8286 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8287 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8288 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8289 cpu_env, ra, dcm); \
8290 tcg_temp_free_ptr(ra); \
8291 tcg_temp_free_i32(dcm); \
8292 }
8293
8294 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8295 static void gen_##name(DisasContext *ctx) \
8296 { \
8297 TCGv_ptr rt, rb; \
8298 TCGv_i32 u32_1, u32_2; \
8299 if (unlikely(!ctx->fpu_enabled)) { \
8300 gen_exception(ctx, POWERPC_EXCP_FPU); \
8301 return; \
8302 } \
8303 gen_update_nip(ctx, ctx->nip - 4); \
8304 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8305 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8306 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8307 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8308 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8309 if (unlikely(Rc(ctx->opcode) != 0)) { \
8310 gen_set_cr6_from_fpscr(ctx); \
8311 } \
8312 tcg_temp_free_ptr(rt); \
8313 tcg_temp_free_ptr(rb); \
8314 tcg_temp_free_i32(u32_1); \
8315 tcg_temp_free_i32(u32_2); \
8316 }
8317
8318 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8319 static void gen_##name(DisasContext *ctx) \
8320 { \
8321 TCGv_ptr rt, ra, rb; \
8322 TCGv_i32 i32; \
8323 if (unlikely(!ctx->fpu_enabled)) { \
8324 gen_exception(ctx, POWERPC_EXCP_FPU); \
8325 return; \
8326 } \
8327 gen_update_nip(ctx, ctx->nip - 4); \
8328 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8329 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8330 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8331 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8332 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8333 if (unlikely(Rc(ctx->opcode) != 0)) { \
8334 gen_set_cr6_from_fpscr(ctx); \
8335 } \
8336 tcg_temp_free_ptr(rt); \
8337 tcg_temp_free_ptr(rb); \
8338 tcg_temp_free_ptr(ra); \
8339 tcg_temp_free_i32(i32); \
8340 }
8341
8342 #define GEN_DFP_T_B_Rc(name) \
8343 static void gen_##name(DisasContext *ctx) \
8344 { \
8345 TCGv_ptr rt, rb; \
8346 if (unlikely(!ctx->fpu_enabled)) { \
8347 gen_exception(ctx, POWERPC_EXCP_FPU); \
8348 return; \
8349 } \
8350 gen_update_nip(ctx, ctx->nip - 4); \
8351 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8352 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8353 gen_helper_##name(cpu_env, rt, rb); \
8354 if (unlikely(Rc(ctx->opcode) != 0)) { \
8355 gen_set_cr6_from_fpscr(ctx); \
8356 } \
8357 tcg_temp_free_ptr(rt); \
8358 tcg_temp_free_ptr(rb); \
8359 }
8360
8361 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8362 static void gen_##name(DisasContext *ctx) \
8363 { \
8364 TCGv_ptr rt, rs; \
8365 TCGv_i32 i32; \
8366 if (unlikely(!ctx->fpu_enabled)) { \
8367 gen_exception(ctx, POWERPC_EXCP_FPU); \
8368 return; \
8369 } \
8370 gen_update_nip(ctx, ctx->nip - 4); \
8371 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8372 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8373 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8374 gen_helper_##name(cpu_env, rt, rs, i32); \
8375 if (unlikely(Rc(ctx->opcode) != 0)) { \
8376 gen_set_cr6_from_fpscr(ctx); \
8377 } \
8378 tcg_temp_free_ptr(rt); \
8379 tcg_temp_free_ptr(rs); \
8380 tcg_temp_free_i32(i32); \
8381 }
8382
8383 GEN_DFP_T_A_B_Rc(dadd)
8384 GEN_DFP_T_A_B_Rc(daddq)
8385 GEN_DFP_T_A_B_Rc(dsub)
8386 GEN_DFP_T_A_B_Rc(dsubq)
8387 GEN_DFP_T_A_B_Rc(dmul)
8388 GEN_DFP_T_A_B_Rc(dmulq)
8389 GEN_DFP_T_A_B_Rc(ddiv)
8390 GEN_DFP_T_A_B_Rc(ddivq)
8391 GEN_DFP_BF_A_B(dcmpu)
8392 GEN_DFP_BF_A_B(dcmpuq)
8393 GEN_DFP_BF_A_B(dcmpo)
8394 GEN_DFP_BF_A_B(dcmpoq)
8395 GEN_DFP_BF_A_DCM(dtstdc)
8396 GEN_DFP_BF_A_DCM(dtstdcq)
8397 GEN_DFP_BF_A_DCM(dtstdg)
8398 GEN_DFP_BF_A_DCM(dtstdgq)
8399 GEN_DFP_BF_A_B(dtstex)
8400 GEN_DFP_BF_A_B(dtstexq)
8401 GEN_DFP_BF_A_B(dtstsf)
8402 GEN_DFP_BF_A_B(dtstsfq)
8403 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8404 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8405 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8406 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8407 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8408 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8409 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8410 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8411 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8412 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8413 GEN_DFP_T_B_Rc(dctdp)
8414 GEN_DFP_T_B_Rc(dctqpq)
8415 GEN_DFP_T_B_Rc(drsp)
8416 GEN_DFP_T_B_Rc(drdpq)
8417 GEN_DFP_T_B_Rc(dcffix)
8418 GEN_DFP_T_B_Rc(dcffixq)
8419 GEN_DFP_T_B_Rc(dctfix)
8420 GEN_DFP_T_B_Rc(dctfixq)
8421 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8422 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8423 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8424 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8425 GEN_DFP_T_B_Rc(dxex)
8426 GEN_DFP_T_B_Rc(dxexq)
8427 GEN_DFP_T_A_B_Rc(diex)
8428 GEN_DFP_T_A_B_Rc(diexq)
8429 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8430 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8431 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8432 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8433
8434 /*** SPE extension ***/
8435 /* Register moves */
8436
8437 static inline void gen_evmra(DisasContext *ctx)
8438 {
8439
8440 if (unlikely(!ctx->spe_enabled)) {
8441 gen_exception(ctx, POWERPC_EXCP_SPEU);
8442 return;
8443 }
8444
8445 TCGv_i64 tmp = tcg_temp_new_i64();
8446
8447 /* tmp := rA_lo + rA_hi << 32 */
8448 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8449
8450 /* spe_acc := tmp */
8451 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8452 tcg_temp_free_i64(tmp);
8453
8454 /* rD := rA */
8455 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8456 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8457 }
8458
8459 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8460 {
8461 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8462 }
8463
8464 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8465 {
8466 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8467 }
8468
8469 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8470 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8471 { \
8472 if (Rc(ctx->opcode)) \
8473 gen_##name1(ctx); \
8474 else \
8475 gen_##name0(ctx); \
8476 }
8477
8478 /* Handler for undefined SPE opcodes */
8479 static inline void gen_speundef(DisasContext *ctx)
8480 {
8481 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8482 }
8483
8484 /* SPE logic */
8485 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8486 static inline void gen_##name(DisasContext *ctx) \
8487 { \
8488 if (unlikely(!ctx->spe_enabled)) { \
8489 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8490 return; \
8491 } \
8492 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8493 cpu_gpr[rB(ctx->opcode)]); \
8494 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8495 cpu_gprh[rB(ctx->opcode)]); \
8496 }
8497
8498 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8499 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8500 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8501 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8502 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8503 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8504 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8505 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8506
8507 /* SPE logic immediate */
8508 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8509 static inline void gen_##name(DisasContext *ctx) \
8510 { \
8511 TCGv_i32 t0; \
8512 if (unlikely(!ctx->spe_enabled)) { \
8513 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8514 return; \
8515 } \
8516 t0 = tcg_temp_new_i32(); \
8517 \
8518 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8519 tcg_opi(t0, t0, rB(ctx->opcode)); \
8520 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8521 \
8522 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8523 tcg_opi(t0, t0, rB(ctx->opcode)); \
8524 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8525 \
8526 tcg_temp_free_i32(t0); \
8527 }
8528 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8529 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8530 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8531 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8532
8533 /* SPE arithmetic */
8534 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8535 static inline void gen_##name(DisasContext *ctx) \
8536 { \
8537 TCGv_i32 t0; \
8538 if (unlikely(!ctx->spe_enabled)) { \
8539 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8540 return; \
8541 } \
8542 t0 = tcg_temp_new_i32(); \
8543 \
8544 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8545 tcg_op(t0, t0); \
8546 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8547 \
8548 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8549 tcg_op(t0, t0); \
8550 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8551 \
8552 tcg_temp_free_i32(t0); \
8553 }
8554
8555 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8556 {
8557 int l1 = gen_new_label();
8558 int l2 = gen_new_label();
8559
8560 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8561 tcg_gen_neg_i32(ret, arg1);
8562 tcg_gen_br(l2);
8563 gen_set_label(l1);
8564 tcg_gen_mov_i32(ret, arg1);
8565 gen_set_label(l2);
8566 }
8567 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8568 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8569 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8570 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8571 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8572 {
8573 tcg_gen_addi_i32(ret, arg1, 0x8000);
8574 tcg_gen_ext16u_i32(ret, ret);
8575 }
8576 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8577 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8578 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8579
8580 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8581 static inline void gen_##name(DisasContext *ctx) \
8582 { \
8583 TCGv_i32 t0, t1; \
8584 if (unlikely(!ctx->spe_enabled)) { \
8585 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8586 return; \
8587 } \
8588 t0 = tcg_temp_new_i32(); \
8589 t1 = tcg_temp_new_i32(); \
8590 \
8591 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8592 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8593 tcg_op(t0, t0, t1); \
8594 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8595 \
8596 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8597 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8598 tcg_op(t0, t0, t1); \
8599 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8600 \
8601 tcg_temp_free_i32(t0); \
8602 tcg_temp_free_i32(t1); \
8603 }
8604
8605 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8606 {
8607 TCGv_i32 t0;
8608 int l1, l2;
8609
8610 l1 = gen_new_label();
8611 l2 = gen_new_label();
8612 t0 = tcg_temp_local_new_i32();
8613 /* No error here: 6 bits are used */
8614 tcg_gen_andi_i32(t0, arg2, 0x3F);
8615 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8616 tcg_gen_shr_i32(ret, arg1, t0);
8617 tcg_gen_br(l2);
8618 gen_set_label(l1);
8619 tcg_gen_movi_i32(ret, 0);
8620 gen_set_label(l2);
8621 tcg_temp_free_i32(t0);
8622 }
8623 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8624 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8625 {
8626 TCGv_i32 t0;
8627 int l1, l2;
8628
8629 l1 = gen_new_label();
8630 l2 = gen_new_label();
8631 t0 = tcg_temp_local_new_i32();
8632 /* No error here: 6 bits are used */
8633 tcg_gen_andi_i32(t0, arg2, 0x3F);
8634 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8635 tcg_gen_sar_i32(ret, arg1, t0);
8636 tcg_gen_br(l2);
8637 gen_set_label(l1);
8638 tcg_gen_movi_i32(ret, 0);
8639 gen_set_label(l2);
8640 tcg_temp_free_i32(t0);
8641 }
8642 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8643 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8644 {
8645 TCGv_i32 t0;
8646 int l1, l2;
8647
8648 l1 = gen_new_label();
8649 l2 = gen_new_label();
8650 t0 = tcg_temp_local_new_i32();
8651 /* No error here: 6 bits are used */
8652 tcg_gen_andi_i32(t0, arg2, 0x3F);
8653 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8654 tcg_gen_shl_i32(ret, arg1, t0);
8655 tcg_gen_br(l2);
8656 gen_set_label(l1);
8657 tcg_gen_movi_i32(ret, 0);
8658 gen_set_label(l2);
8659 tcg_temp_free_i32(t0);
8660 }
8661 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8662 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8663 {
8664 TCGv_i32 t0 = tcg_temp_new_i32();
8665 tcg_gen_andi_i32(t0, arg2, 0x1F);
8666 tcg_gen_rotl_i32(ret, arg1, t0);
8667 tcg_temp_free_i32(t0);
8668 }
8669 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8670 static inline void gen_evmergehi(DisasContext *ctx)
8671 {
8672 if (unlikely(!ctx->spe_enabled)) {
8673 gen_exception(ctx, POWERPC_EXCP_SPEU);
8674 return;
8675 }
8676 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8677 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8678 }
8679 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8680 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8681 {
8682 tcg_gen_sub_i32(ret, arg2, arg1);
8683 }
8684 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8685
8686 /* SPE arithmetic immediate */
8687 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8688 static inline void gen_##name(DisasContext *ctx) \
8689 { \
8690 TCGv_i32 t0; \
8691 if (unlikely(!ctx->spe_enabled)) { \
8692 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8693 return; \
8694 } \
8695 t0 = tcg_temp_new_i32(); \
8696 \
8697 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8698 tcg_op(t0, t0, rA(ctx->opcode)); \
8699 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8700 \
8701 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8702 tcg_op(t0, t0, rA(ctx->opcode)); \
8703 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8704 \
8705 tcg_temp_free_i32(t0); \
8706 }
8707 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8708 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8709
8710 /* SPE comparison */
8711 #define GEN_SPEOP_COMP(name, tcg_cond) \
8712 static inline void gen_##name(DisasContext *ctx) \
8713 { \
8714 if (unlikely(!ctx->spe_enabled)) { \
8715 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8716 return; \
8717 } \
8718 int l1 = gen_new_label(); \
8719 int l2 = gen_new_label(); \
8720 int l3 = gen_new_label(); \
8721 int l4 = gen_new_label(); \
8722 \
8723 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8724 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8725 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8726 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8727 \
8728 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8729 cpu_gpr[rB(ctx->opcode)], l1); \
8730 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8731 tcg_gen_br(l2); \
8732 gen_set_label(l1); \
8733 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8734 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8735 gen_set_label(l2); \
8736 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8737 cpu_gprh[rB(ctx->opcode)], l3); \
8738 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8739 ~(CRF_CH | CRF_CH_AND_CL)); \
8740 tcg_gen_br(l4); \
8741 gen_set_label(l3); \
8742 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8743 CRF_CH | CRF_CH_OR_CL); \
8744 gen_set_label(l4); \
8745 }
8746 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8747 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8748 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8749 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8750 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8751
8752 /* SPE misc */
8753 static inline void gen_brinc(DisasContext *ctx)
8754 {
8755 /* Note: brinc is usable even if SPE is disabled */
8756 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8757 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8758 }
8759 static inline void gen_evmergelo(DisasContext *ctx)
8760 {
8761 if (unlikely(!ctx->spe_enabled)) {
8762 gen_exception(ctx, POWERPC_EXCP_SPEU);
8763 return;
8764 }
8765 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8766 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8767 }
8768 static inline void gen_evmergehilo(DisasContext *ctx)
8769 {
8770 if (unlikely(!ctx->spe_enabled)) {
8771 gen_exception(ctx, POWERPC_EXCP_SPEU);
8772 return;
8773 }
8774 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8775 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8776 }
8777 static inline void gen_evmergelohi(DisasContext *ctx)
8778 {
8779 if (unlikely(!ctx->spe_enabled)) {
8780 gen_exception(ctx, POWERPC_EXCP_SPEU);
8781 return;
8782 }
8783 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8784 TCGv tmp = tcg_temp_new();
8785 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8786 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8787 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8788 tcg_temp_free(tmp);
8789 } else {
8790 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8791 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8792 }
8793 }
8794 static inline void gen_evsplati(DisasContext *ctx)
8795 {
8796 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8797
8798 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8799 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8800 }
8801 static inline void gen_evsplatfi(DisasContext *ctx)
8802 {
8803 uint64_t imm = rA(ctx->opcode) << 27;
8804
8805 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8806 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8807 }
8808
8809 static inline void gen_evsel(DisasContext *ctx)
8810 {
8811 int l1 = gen_new_label();
8812 int l2 = gen_new_label();
8813 int l3 = gen_new_label();
8814 int l4 = gen_new_label();
8815 TCGv_i32 t0 = tcg_temp_local_new_i32();
8816 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8817 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8818 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8819 tcg_gen_br(l2);
8820 gen_set_label(l1);
8821 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8822 gen_set_label(l2);
8823 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8824 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8825 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8826 tcg_gen_br(l4);
8827 gen_set_label(l3);
8828 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8829 gen_set_label(l4);
8830 tcg_temp_free_i32(t0);
8831 }
8832
8833 static void gen_evsel0(DisasContext *ctx)
8834 {
8835 gen_evsel(ctx);
8836 }
8837
8838 static void gen_evsel1(DisasContext *ctx)
8839 {
8840 gen_evsel(ctx);
8841 }
8842
8843 static void gen_evsel2(DisasContext *ctx)
8844 {
8845 gen_evsel(ctx);
8846 }
8847
8848 static void gen_evsel3(DisasContext *ctx)
8849 {
8850 gen_evsel(ctx);
8851 }
8852
8853 /* Multiply */
8854
8855 static inline void gen_evmwumi(DisasContext *ctx)
8856 {
8857 TCGv_i64 t0, t1;
8858
8859 if (unlikely(!ctx->spe_enabled)) {
8860 gen_exception(ctx, POWERPC_EXCP_SPEU);
8861 return;
8862 }
8863
8864 t0 = tcg_temp_new_i64();
8865 t1 = tcg_temp_new_i64();
8866
8867 /* t0 := rA; t1 := rB */
8868 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8869 tcg_gen_ext32u_i64(t0, t0);
8870 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8871 tcg_gen_ext32u_i64(t1, t1);
8872
8873 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8874
8875 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8876
8877 tcg_temp_free_i64(t0);
8878 tcg_temp_free_i64(t1);
8879 }
8880
8881 static inline void gen_evmwumia(DisasContext *ctx)
8882 {
8883 TCGv_i64 tmp;
8884
8885 if (unlikely(!ctx->spe_enabled)) {
8886 gen_exception(ctx, POWERPC_EXCP_SPEU);
8887 return;
8888 }
8889
8890 gen_evmwumi(ctx); /* rD := rA * rB */
8891
8892 tmp = tcg_temp_new_i64();
8893
8894 /* acc := rD */
8895 gen_load_gpr64(tmp, rD(ctx->opcode));
8896 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8897 tcg_temp_free_i64(tmp);
8898 }
8899
8900 static inline void gen_evmwumiaa(DisasContext *ctx)
8901 {
8902 TCGv_i64 acc;
8903 TCGv_i64 tmp;
8904
8905 if (unlikely(!ctx->spe_enabled)) {
8906 gen_exception(ctx, POWERPC_EXCP_SPEU);
8907 return;
8908 }
8909
8910 gen_evmwumi(ctx); /* rD := rA * rB */
8911
8912 acc = tcg_temp_new_i64();
8913 tmp = tcg_temp_new_i64();
8914
8915 /* tmp := rD */
8916 gen_load_gpr64(tmp, rD(ctx->opcode));
8917
8918 /* Load acc */
8919 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8920
8921 /* acc := tmp + acc */
8922 tcg_gen_add_i64(acc, acc, tmp);
8923
8924 /* Store acc */
8925 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8926
8927 /* rD := acc */
8928 gen_store_gpr64(rD(ctx->opcode), acc);
8929
8930 tcg_temp_free_i64(acc);
8931 tcg_temp_free_i64(tmp);
8932 }
8933
8934 static inline void gen_evmwsmi(DisasContext *ctx)
8935 {
8936 TCGv_i64 t0, t1;
8937
8938 if (unlikely(!ctx->spe_enabled)) {
8939 gen_exception(ctx, POWERPC_EXCP_SPEU);
8940 return;
8941 }
8942
8943 t0 = tcg_temp_new_i64();
8944 t1 = tcg_temp_new_i64();
8945
8946 /* t0 := rA; t1 := rB */
8947 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8948 tcg_gen_ext32s_i64(t0, t0);
8949 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8950 tcg_gen_ext32s_i64(t1, t1);
8951
8952 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8953
8954 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8955
8956 tcg_temp_free_i64(t0);
8957 tcg_temp_free_i64(t1);
8958 }
8959
8960 static inline void gen_evmwsmia(DisasContext *ctx)
8961 {
8962 TCGv_i64 tmp;
8963
8964 gen_evmwsmi(ctx); /* rD := rA * rB */
8965
8966 tmp = tcg_temp_new_i64();
8967
8968 /* acc := rD */
8969 gen_load_gpr64(tmp, rD(ctx->opcode));
8970 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8971
8972 tcg_temp_free_i64(tmp);
8973 }
8974
8975 static inline void gen_evmwsmiaa(DisasContext *ctx)
8976 {
8977 TCGv_i64 acc = tcg_temp_new_i64();
8978 TCGv_i64 tmp = tcg_temp_new_i64();
8979
8980 gen_evmwsmi(ctx); /* rD := rA * rB */
8981
8982 acc = tcg_temp_new_i64();
8983 tmp = tcg_temp_new_i64();
8984
8985 /* tmp := rD */
8986 gen_load_gpr64(tmp, rD(ctx->opcode));
8987
8988 /* Load acc */
8989 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8990
8991 /* acc := tmp + acc */
8992 tcg_gen_add_i64(acc, acc, tmp);
8993
8994 /* Store acc */
8995 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8996
8997 /* rD := acc */
8998 gen_store_gpr64(rD(ctx->opcode), acc);
8999
9000 tcg_temp_free_i64(acc);
9001 tcg_temp_free_i64(tmp);
9002 }
9003
9004 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9005 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9006 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9007 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9008 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9009 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9010 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9011 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9012 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9013 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9014 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9015 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9016 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9017 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9018 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9019 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9020 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9021 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9022 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9023 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9024 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9025 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9026 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9027 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9028 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9029 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9030 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9031 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9032 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
9033
9034 /* SPE load and stores */
9035 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
9036 {
9037 target_ulong uimm = rB(ctx->opcode);
9038
9039 if (rA(ctx->opcode) == 0) {
9040 tcg_gen_movi_tl(EA, uimm << sh);
9041 } else {
9042 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9043 if (NARROW_MODE(ctx)) {
9044 tcg_gen_ext32u_tl(EA, EA);
9045 }
9046 }
9047 }
9048
9049 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9050 {
9051 TCGv_i64 t0 = tcg_temp_new_i64();
9052 gen_qemu_ld64(ctx, t0, addr);
9053 gen_store_gpr64(rD(ctx->opcode), t0);
9054 tcg_temp_free_i64(t0);
9055 }
9056
9057 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9058 {
9059 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9060 gen_addr_add(ctx, addr, addr, 4);
9061 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9062 }
9063
9064 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9065 {
9066 TCGv t0 = tcg_temp_new();
9067 gen_qemu_ld16u(ctx, t0, addr);
9068 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9069 gen_addr_add(ctx, addr, addr, 2);
9070 gen_qemu_ld16u(ctx, t0, addr);
9071 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9072 gen_addr_add(ctx, addr, addr, 2);
9073 gen_qemu_ld16u(ctx, t0, addr);
9074 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9075 gen_addr_add(ctx, addr, addr, 2);
9076 gen_qemu_ld16u(ctx, t0, addr);
9077 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9078 tcg_temp_free(t0);
9079 }
9080
9081 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9082 {
9083 TCGv t0 = tcg_temp_new();
9084 gen_qemu_ld16u(ctx, t0, addr);
9085 tcg_gen_shli_tl(t0, t0, 16);
9086 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9087 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9088 tcg_temp_free(t0);
9089 }
9090
9091 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9092 {
9093 TCGv t0 = tcg_temp_new();
9094 gen_qemu_ld16u(ctx, t0, addr);
9095 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9096 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9097 tcg_temp_free(t0);
9098 }
9099
9100 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9101 {
9102 TCGv t0 = tcg_temp_new();
9103 gen_qemu_ld16s(ctx, t0, addr);
9104 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9105 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9106 tcg_temp_free(t0);
9107 }
9108
9109 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9110 {
9111 TCGv t0 = tcg_temp_new();
9112 gen_qemu_ld16u(ctx, t0, addr);
9113 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9114 gen_addr_add(ctx, addr, addr, 2);
9115 gen_qemu_ld16u(ctx, t0, addr);
9116 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9117 tcg_temp_free(t0);
9118 }
9119
9120 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9121 {
9122 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9123 gen_addr_add(ctx, addr, addr, 2);
9124 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9125 }
9126
9127 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9128 {
9129 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9130 gen_addr_add(ctx, addr, addr, 2);
9131 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9132 }
9133
9134 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9135 {
9136 TCGv t0 = tcg_temp_new();
9137 gen_qemu_ld32u(ctx, t0, addr);
9138 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9139 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9140 tcg_temp_free(t0);
9141 }
9142
9143 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9144 {
9145 TCGv t0 = tcg_temp_new();
9146 gen_qemu_ld16u(ctx, t0, addr);
9147 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9148 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9149 gen_addr_add(ctx, addr, addr, 2);
9150 gen_qemu_ld16u(ctx, t0, addr);
9151 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9152 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9153 tcg_temp_free(t0);
9154 }
9155
9156 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9157 {
9158 TCGv_i64 t0 = tcg_temp_new_i64();
9159 gen_load_gpr64(t0, rS(ctx->opcode));
9160 gen_qemu_st64(ctx, t0, addr);
9161 tcg_temp_free_i64(t0);
9162 }
9163
9164 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9165 {
9166 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9167 gen_addr_add(ctx, addr, addr, 4);
9168 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9169 }
9170
9171 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9172 {
9173 TCGv t0 = tcg_temp_new();
9174 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9175 gen_qemu_st16(ctx, t0, addr);
9176 gen_addr_add(ctx, addr, addr, 2);
9177 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9178 gen_addr_add(ctx, addr, addr, 2);
9179 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9180 gen_qemu_st16(ctx, t0, addr);
9181 tcg_temp_free(t0);
9182 gen_addr_add(ctx, addr, addr, 2);
9183 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9184 }
9185
9186 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9187 {
9188 TCGv t0 = tcg_temp_new();
9189 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9190 gen_qemu_st16(ctx, t0, addr);
9191 gen_addr_add(ctx, addr, addr, 2);
9192 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9193 gen_qemu_st16(ctx, t0, addr);
9194 tcg_temp_free(t0);
9195 }
9196
9197 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9198 {
9199 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9200 gen_addr_add(ctx, addr, addr, 2);
9201 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9202 }
9203
9204 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9205 {
9206 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9207 }
9208
9209 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9210 {
9211 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9212 }
9213
9214 #define GEN_SPEOP_LDST(name, opc2, sh) \
9215 static void glue(gen_, name)(DisasContext *ctx) \
9216 { \
9217 TCGv t0; \
9218 if (unlikely(!ctx->spe_enabled)) { \
9219 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9220 return; \
9221 } \
9222 gen_set_access_type(ctx, ACCESS_INT); \
9223 t0 = tcg_temp_new(); \
9224 if (Rc(ctx->opcode)) { \
9225 gen_addr_spe_imm_index(ctx, t0, sh); \
9226 } else { \
9227 gen_addr_reg_index(ctx, t0); \
9228 } \
9229 gen_op_##name(ctx, t0); \
9230 tcg_temp_free(t0); \
9231 }
9232
9233 GEN_SPEOP_LDST(evldd, 0x00, 3);
9234 GEN_SPEOP_LDST(evldw, 0x01, 3);
9235 GEN_SPEOP_LDST(evldh, 0x02, 3);
9236 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9237 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9238 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9239 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9240 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9241 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9242 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9243 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9244
9245 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9246 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9247 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9248 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9249 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9250 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9251 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9252
9253 /* Multiply and add - TODO */
9254 #if 0
9255 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9256 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9257 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9258 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9259 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9260 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9261 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9262 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9263 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9264 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9265 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9266 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9267
9268 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9269 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9270 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9271 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9272 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9273 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9274 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9275 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9276 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9277 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9278 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9279 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9280
9281 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9282 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9283 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9284 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9285 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9286
9287 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9288 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9289 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9290 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9291 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9292 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9293 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9294 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9295 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9296 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9297 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9298 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9299
9300 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9301 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9302 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9303 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9304
9305 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9306 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9307 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9308 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9309 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9310 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9311 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9312 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9313 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9314 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9315 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9316 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9317
9318 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9319 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9320 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9321 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9322 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9323 #endif
9324
9325 /*** SPE floating-point extension ***/
9326 #define GEN_SPEFPUOP_CONV_32_32(name) \
9327 static inline void gen_##name(DisasContext *ctx) \
9328 { \
9329 TCGv_i32 t0 = tcg_temp_new_i32(); \
9330 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9331 gen_helper_##name(t0, cpu_env, t0); \
9332 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9333 tcg_temp_free_i32(t0); \
9334 }
9335 #define GEN_SPEFPUOP_CONV_32_64(name) \
9336 static inline void gen_##name(DisasContext *ctx) \
9337 { \
9338 TCGv_i64 t0 = tcg_temp_new_i64(); \
9339 TCGv_i32 t1 = tcg_temp_new_i32(); \
9340 gen_load_gpr64(t0, rB(ctx->opcode)); \
9341 gen_helper_##name(t1, cpu_env, t0); \
9342 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9343 tcg_temp_free_i64(t0); \
9344 tcg_temp_free_i32(t1); \
9345 }
9346 #define GEN_SPEFPUOP_CONV_64_32(name) \
9347 static inline void gen_##name(DisasContext *ctx) \
9348 { \
9349 TCGv_i64 t0 = tcg_temp_new_i64(); \
9350 TCGv_i32 t1 = tcg_temp_new_i32(); \
9351 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9352 gen_helper_##name(t0, cpu_env, t1); \
9353 gen_store_gpr64(rD(ctx->opcode), t0); \
9354 tcg_temp_free_i64(t0); \
9355 tcg_temp_free_i32(t1); \
9356 }
9357 #define GEN_SPEFPUOP_CONV_64_64(name) \
9358 static inline void gen_##name(DisasContext *ctx) \
9359 { \
9360 TCGv_i64 t0 = tcg_temp_new_i64(); \
9361 gen_load_gpr64(t0, rB(ctx->opcode)); \
9362 gen_helper_##name(t0, cpu_env, t0); \
9363 gen_store_gpr64(rD(ctx->opcode), t0); \
9364 tcg_temp_free_i64(t0); \
9365 }
9366 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9367 static inline void gen_##name(DisasContext *ctx) \
9368 { \
9369 TCGv_i32 t0, t1; \
9370 if (unlikely(!ctx->spe_enabled)) { \
9371 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9372 return; \
9373 } \
9374 t0 = tcg_temp_new_i32(); \
9375 t1 = tcg_temp_new_i32(); \
9376 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9377 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9378 gen_helper_##name(t0, cpu_env, t0, t1); \
9379 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9380 \
9381 tcg_temp_free_i32(t0); \
9382 tcg_temp_free_i32(t1); \
9383 }
9384 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9385 static inline void gen_##name(DisasContext *ctx) \
9386 { \
9387 TCGv_i64 t0, t1; \
9388 if (unlikely(!ctx->spe_enabled)) { \
9389 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9390 return; \
9391 } \
9392 t0 = tcg_temp_new_i64(); \
9393 t1 = tcg_temp_new_i64(); \
9394 gen_load_gpr64(t0, rA(ctx->opcode)); \
9395 gen_load_gpr64(t1, rB(ctx->opcode)); \
9396 gen_helper_##name(t0, cpu_env, t0, t1); \
9397 gen_store_gpr64(rD(ctx->opcode), t0); \
9398 tcg_temp_free_i64(t0); \
9399 tcg_temp_free_i64(t1); \
9400 }
9401 #define GEN_SPEFPUOP_COMP_32(name) \
9402 static inline void gen_##name(DisasContext *ctx) \
9403 { \
9404 TCGv_i32 t0, t1; \
9405 if (unlikely(!ctx->spe_enabled)) { \
9406 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9407 return; \
9408 } \
9409 t0 = tcg_temp_new_i32(); \
9410 t1 = tcg_temp_new_i32(); \
9411 \
9412 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9413 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9414 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9415 \
9416 tcg_temp_free_i32(t0); \
9417 tcg_temp_free_i32(t1); \
9418 }
9419 #define GEN_SPEFPUOP_COMP_64(name) \
9420 static inline void gen_##name(DisasContext *ctx) \
9421 { \
9422 TCGv_i64 t0, t1; \
9423 if (unlikely(!ctx->spe_enabled)) { \
9424 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9425 return; \
9426 } \
9427 t0 = tcg_temp_new_i64(); \
9428 t1 = tcg_temp_new_i64(); \
9429 gen_load_gpr64(t0, rA(ctx->opcode)); \
9430 gen_load_gpr64(t1, rB(ctx->opcode)); \
9431 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9432 tcg_temp_free_i64(t0); \
9433 tcg_temp_free_i64(t1); \
9434 }
9435
9436 /* Single precision floating-point vectors operations */
9437 /* Arithmetic */
9438 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9439 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9440 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9441 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9442 static inline void gen_evfsabs(DisasContext *ctx)
9443 {
9444 if (unlikely(!ctx->spe_enabled)) {
9445 gen_exception(ctx, POWERPC_EXCP_SPEU);
9446 return;
9447 }
9448 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9449 ~0x80000000);
9450 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9451 ~0x80000000);
9452 }
9453 static inline void gen_evfsnabs(DisasContext *ctx)
9454 {
9455 if (unlikely(!ctx->spe_enabled)) {
9456 gen_exception(ctx, POWERPC_EXCP_SPEU);
9457 return;
9458 }
9459 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9460 0x80000000);
9461 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9462 0x80000000);
9463 }
9464 static inline void gen_evfsneg(DisasContext *ctx)
9465 {
9466 if (unlikely(!ctx->spe_enabled)) {
9467 gen_exception(ctx, POWERPC_EXCP_SPEU);
9468 return;
9469 }
9470 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9471 0x80000000);
9472 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9473 0x80000000);
9474 }
9475
9476 /* Conversion */
9477 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9478 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9479 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9480 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9481 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9482 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9483 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9484 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9485 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9486 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9487
9488 /* Comparison */
9489 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9490 GEN_SPEFPUOP_COMP_64(evfscmplt);
9491 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9492 GEN_SPEFPUOP_COMP_64(evfststgt);
9493 GEN_SPEFPUOP_COMP_64(evfststlt);
9494 GEN_SPEFPUOP_COMP_64(evfststeq);
9495
9496 /* Opcodes definitions */
9497 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9498 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9499 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9500 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9501 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9502 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9503 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9504 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9505 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9506 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9507 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9508 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9509 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9510 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9511
9512 /* Single precision floating-point operations */
9513 /* Arithmetic */
9514 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9515 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9516 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9517 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9518 static inline void gen_efsabs(DisasContext *ctx)
9519 {
9520 if (unlikely(!ctx->spe_enabled)) {
9521 gen_exception(ctx, POWERPC_EXCP_SPEU);
9522 return;
9523 }
9524 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9525 }
9526 static inline void gen_efsnabs(DisasContext *ctx)
9527 {
9528 if (unlikely(!ctx->spe_enabled)) {
9529 gen_exception(ctx, POWERPC_EXCP_SPEU);
9530 return;
9531 }
9532 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9533 }
9534 static inline void gen_efsneg(DisasContext *ctx)
9535 {
9536 if (unlikely(!ctx->spe_enabled)) {
9537 gen_exception(ctx, POWERPC_EXCP_SPEU);
9538 return;
9539 }
9540 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9541 }
9542
9543 /* Conversion */
9544 GEN_SPEFPUOP_CONV_32_32(efscfui);
9545 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9546 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9547 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9548 GEN_SPEFPUOP_CONV_32_32(efsctui);
9549 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9550 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9551 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9552 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9553 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9554 GEN_SPEFPUOP_CONV_32_64(efscfd);
9555
9556 /* Comparison */
9557 GEN_SPEFPUOP_COMP_32(efscmpgt);
9558 GEN_SPEFPUOP_COMP_32(efscmplt);
9559 GEN_SPEFPUOP_COMP_32(efscmpeq);
9560 GEN_SPEFPUOP_COMP_32(efststgt);
9561 GEN_SPEFPUOP_COMP_32(efststlt);
9562 GEN_SPEFPUOP_COMP_32(efststeq);
9563
9564 /* Opcodes definitions */
9565 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9566 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9567 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9568 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9569 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9570 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9571 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9572 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9573 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9574 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9575 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9576 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9577 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9578 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9579
9580 /* Double precision floating-point operations */
9581 /* Arithmetic */
9582 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9583 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9584 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9585 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9586 static inline void gen_efdabs(DisasContext *ctx)
9587 {
9588 if (unlikely(!ctx->spe_enabled)) {
9589 gen_exception(ctx, POWERPC_EXCP_SPEU);
9590 return;
9591 }
9592 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9593 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9594 ~0x80000000);
9595 }
9596 static inline void gen_efdnabs(DisasContext *ctx)
9597 {
9598 if (unlikely(!ctx->spe_enabled)) {
9599 gen_exception(ctx, POWERPC_EXCP_SPEU);
9600 return;
9601 }
9602 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9603 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9604 0x80000000);
9605 }
9606 static inline void gen_efdneg(DisasContext *ctx)
9607 {
9608 if (unlikely(!ctx->spe_enabled)) {
9609 gen_exception(ctx, POWERPC_EXCP_SPEU);
9610 return;
9611 }
9612 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9613 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9614 0x80000000);
9615 }
9616
9617 /* Conversion */
9618 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9619 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9620 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9621 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9622 GEN_SPEFPUOP_CONV_32_64(efdctui);
9623 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9624 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9625 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9626 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9627 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9628 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9629 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9630 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9631 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9632 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9633
9634 /* Comparison */
9635 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9636 GEN_SPEFPUOP_COMP_64(efdcmplt);
9637 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9638 GEN_SPEFPUOP_COMP_64(efdtstgt);
9639 GEN_SPEFPUOP_COMP_64(efdtstlt);
9640 GEN_SPEFPUOP_COMP_64(efdtsteq);
9641
9642 /* Opcodes definitions */
9643 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9644 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9645 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9646 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9647 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9648 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9649 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9650 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9651 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9652 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9653 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9654 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9655 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9656 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9657 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9658 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9659
9660 static opcode_t opcodes[] = {
9661 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9662 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9663 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9664 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9665 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9666 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9667 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9668 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9669 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9670 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9671 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9672 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9673 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9674 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9675 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9676 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9677 #if defined(TARGET_PPC64)
9678 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9679 #endif
9680 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9681 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9682 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9683 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9684 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9685 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9686 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9687 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9688 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9689 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9690 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9691 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9692 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9693 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9694 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9695 #if defined(TARGET_PPC64)
9696 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9697 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9698 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9699 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9700 #endif
9701 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9702 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9703 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9704 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9705 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9706 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9707 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9708 #if defined(TARGET_PPC64)
9709 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9710 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9711 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9712 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9713 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9714 #endif
9715 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9716 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9717 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9718 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9719 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9720 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9721 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9722 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9723 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9724 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9725 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9726 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9727 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9728 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9729 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9730 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9731 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9732 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9733 #if defined(TARGET_PPC64)
9734 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9735 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9736 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9737 #endif
9738 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9739 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9740 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9741 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9742 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9743 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9744 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9745 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9746 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9747 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9748 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9749 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9750 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9751 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9752 #if defined(TARGET_PPC64)
9753 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9754 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9755 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9756 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9757 #endif
9758 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9759 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9760 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9761 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9762 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9763 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9764 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9765 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9766 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9767 #if defined(TARGET_PPC64)
9768 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9769 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9770 #endif
9771 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9772 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9773 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9774 #if defined(TARGET_PPC64)
9775 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9776 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9777 #endif
9778 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9779 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9780 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9781 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9782 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9783 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9784 #if defined(TARGET_PPC64)
9785 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9786 #endif
9787 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9788 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
9789 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9790 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9791 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9792 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9793 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9794 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
9795 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9796 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9797 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9798 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9799 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9800 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9801 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9802 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9803 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9804 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9805 #if defined(TARGET_PPC64)
9806 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9807 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9808 PPC_SEGMENT_64B),
9809 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9810 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9811 PPC_SEGMENT_64B),
9812 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9813 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9814 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9815 #endif
9816 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9817 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9818 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9819 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9820 #if defined(TARGET_PPC64)
9821 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9822 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9823 #endif
9824 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9825 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9826 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9827 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9828 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9829 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9830 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9831 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9832 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9833 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9834 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9835 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9836 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9837 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9838 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9839 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9840 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9841 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9842 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9843 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9844 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9845 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9846 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9847 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9848 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9849 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9850 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9851 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9852 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9853 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9854 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9855 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9856 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9857 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9858 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9859 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9860 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9861 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9862 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9863 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9864 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9865 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9866 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9867 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9868 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9869 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9870 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9871 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
9872 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
9873 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9874 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9875 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
9876 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
9877 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9878 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9879 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
9880 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
9881 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
9882 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
9883 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
9884 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
9885 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
9886 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
9887 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
9888 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
9889 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
9890 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
9891 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
9892 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
9893 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
9894 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
9895 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
9896 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
9897 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
9898 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
9899 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
9900 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
9901 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
9902 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
9903 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
9904 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
9905 PPC_NONE, PPC2_BOOKE206),
9906 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
9907 PPC_NONE, PPC2_BOOKE206),
9908 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
9909 PPC_NONE, PPC2_BOOKE206),
9910 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
9911 PPC_NONE, PPC2_BOOKE206),
9912 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
9913 PPC_NONE, PPC2_BOOKE206),
9914 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
9915 PPC_NONE, PPC2_PRCNTL),
9916 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
9917 PPC_NONE, PPC2_PRCNTL),
9918 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
9919 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
9920 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
9921 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
9922 PPC_BOOKE, PPC2_BOOKE206),
9923 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
9924 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
9925 PPC_BOOKE, PPC2_BOOKE206),
9926 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
9927 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
9928 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
9929 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
9930 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
9931 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
9932 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
9933 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
9934 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
9935
9936 #undef GEN_INT_ARITH_ADD
9937 #undef GEN_INT_ARITH_ADD_CONST
9938 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
9939 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
9940 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
9941 add_ca, compute_ca, compute_ov) \
9942 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
9943 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
9944 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
9945 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
9946 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
9947 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
9948 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
9949 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
9950 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
9951 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
9952 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
9953
9954 #undef GEN_INT_ARITH_DIVW
9955 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
9956 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
9957 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
9958 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
9959 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
9960 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
9961 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9962 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9963 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9964 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9965
9966 #if defined(TARGET_PPC64)
9967 #undef GEN_INT_ARITH_DIVD
9968 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
9969 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9970 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
9971 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
9972 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
9973 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
9974
9975 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9976 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9977 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9978 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9979
9980 #undef GEN_INT_ARITH_MUL_HELPER
9981 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
9982 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9983 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
9984 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
9985 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
9986 #endif
9987
9988 #undef GEN_INT_ARITH_SUBF
9989 #undef GEN_INT_ARITH_SUBF_CONST
9990 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
9991 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
9992 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
9993 add_ca, compute_ca, compute_ov) \
9994 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
9995 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
9996 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
9997 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
9998 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
9999 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10000 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10001 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10002 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10003 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10004 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10005
10006 #undef GEN_LOGICAL1
10007 #undef GEN_LOGICAL2
10008 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10009 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10010 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10011 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10012 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10013 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10014 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10015 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10016 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10017 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10018 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10019 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10020 #if defined(TARGET_PPC64)
10021 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10022 #endif
10023
10024 #if defined(TARGET_PPC64)
10025 #undef GEN_PPC64_R2
10026 #undef GEN_PPC64_R4
10027 #define GEN_PPC64_R2(name, opc1, opc2) \
10028 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10029 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10030 PPC_64B)
10031 #define GEN_PPC64_R4(name, opc1, opc2) \
10032 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10033 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10034 PPC_64B), \
10035 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10036 PPC_64B), \
10037 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10038 PPC_64B)
10039 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10040 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10041 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10042 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10043 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10044 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10045 #endif
10046
10047 #undef _GEN_FLOAT_ACB
10048 #undef GEN_FLOAT_ACB
10049 #undef _GEN_FLOAT_AB
10050 #undef GEN_FLOAT_AB
10051 #undef _GEN_FLOAT_AC
10052 #undef GEN_FLOAT_AC
10053 #undef GEN_FLOAT_B
10054 #undef GEN_FLOAT_BS
10055 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10056 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10057 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10058 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10059 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10060 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10061 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10062 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10063 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10064 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10065 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10066 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10067 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10068 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10069 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10070 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10071 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10072 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10073 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10074
10075 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10076 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10077 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10078 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10079 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10080 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10081 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10082 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10083 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10084 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10085 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10086 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10087 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10088 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10089 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10090 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10091 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10092 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10093 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10094 #if defined(TARGET_PPC64)
10095 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
10096 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10097 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10098 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10099 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
10100 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10101 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
10102 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10103 #endif
10104 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10105 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10106 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10107 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10108
10109 #undef GEN_LD
10110 #undef GEN_LDU
10111 #undef GEN_LDUX
10112 #undef GEN_LDX_E
10113 #undef GEN_LDS
10114 #define GEN_LD(name, ldop, opc, type) \
10115 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10116 #define GEN_LDU(name, ldop, opc, type) \
10117 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10118 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10119 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10120 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10121 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10122 #define GEN_LDS(name, ldop, op, type) \
10123 GEN_LD(name, ldop, op | 0x20, type) \
10124 GEN_LDU(name, ldop, op | 0x21, type) \
10125 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10126 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10127
10128 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10129 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10130 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10131 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10132 #if defined(TARGET_PPC64)
10133 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10134 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10135 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10136 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10137 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10138 #endif
10139 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10140 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10141
10142 #undef GEN_ST
10143 #undef GEN_STU
10144 #undef GEN_STUX
10145 #undef GEN_STX_E
10146 #undef GEN_STS
10147 #define GEN_ST(name, stop, opc, type) \
10148 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10149 #define GEN_STU(name, stop, opc, type) \
10150 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10151 #define GEN_STUX(name, stop, opc2, opc3, type) \
10152 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10153 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10154 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10155 #define GEN_STS(name, stop, op, type) \
10156 GEN_ST(name, stop, op | 0x20, type) \
10157 GEN_STU(name, stop, op | 0x21, type) \
10158 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10159 GEN_STX(name, stop, 0x17, op | 0x00, type)
10160
10161 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10162 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10163 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10164 #if defined(TARGET_PPC64)
10165 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10166 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10167 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10168 #endif
10169 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10170 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10171
10172 #undef GEN_LDF
10173 #undef GEN_LDUF
10174 #undef GEN_LDUXF
10175 #undef GEN_LDXF
10176 #undef GEN_LDFS
10177 #define GEN_LDF(name, ldop, opc, type) \
10178 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10179 #define GEN_LDUF(name, ldop, opc, type) \
10180 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10181 #define GEN_LDUXF(name, ldop, opc, type) \
10182 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10183 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10184 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10185 #define GEN_LDFS(name, ldop, op, type) \
10186 GEN_LDF(name, ldop, op | 0x20, type) \
10187 GEN_LDUF(name, ldop, op | 0x21, type) \
10188 GEN_LDUXF(name, ldop, op | 0x01, type) \
10189 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10190
10191 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10192 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10193 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10194 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10195 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10196 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10197
10198 #undef GEN_STF
10199 #undef GEN_STUF
10200 #undef GEN_STUXF
10201 #undef GEN_STXF
10202 #undef GEN_STFS
10203 #define GEN_STF(name, stop, opc, type) \
10204 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10205 #define GEN_STUF(name, stop, opc, type) \
10206 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10207 #define GEN_STUXF(name, stop, opc, type) \
10208 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10209 #define GEN_STXF(name, stop, opc2, opc3, type) \
10210 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10211 #define GEN_STFS(name, stop, op, type) \
10212 GEN_STF(name, stop, op | 0x20, type) \
10213 GEN_STUF(name, stop, op | 0x21, type) \
10214 GEN_STUXF(name, stop, op | 0x01, type) \
10215 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10216
10217 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10218 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10219 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10220 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10221 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10222
10223 #undef GEN_CRLOGIC
10224 #define GEN_CRLOGIC(name, tcg_op, opc) \
10225 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10226 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10227 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10228 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10229 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10230 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10231 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10232 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10233 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10234
10235 #undef GEN_MAC_HANDLER
10236 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10237 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10238 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10239 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10240 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10241 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10242 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10243 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10244 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10245 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10246 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10247 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10248 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10249 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10250 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10251 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10252 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10253 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10254 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10255 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10256 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10257 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10258 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10259 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10260 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10261 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10262 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10263 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10264 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10265 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10266 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10267 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10268 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10269 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10270 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10271 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10272 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10273 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10274 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10275 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10276 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10277 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10278 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10279 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10280
10281 #undef GEN_VR_LDX
10282 #undef GEN_VR_STX
10283 #undef GEN_VR_LVE
10284 #undef GEN_VR_STVE
10285 #define GEN_VR_LDX(name, opc2, opc3) \
10286 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10287 #define GEN_VR_STX(name, opc2, opc3) \
10288 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10289 #define GEN_VR_LVE(name, opc2, opc3) \
10290 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10291 #define GEN_VR_STVE(name, opc2, opc3) \
10292 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10293 GEN_VR_LDX(lvx, 0x07, 0x03),
10294 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10295 GEN_VR_LVE(bx, 0x07, 0x00),
10296 GEN_VR_LVE(hx, 0x07, 0x01),
10297 GEN_VR_LVE(wx, 0x07, 0x02),
10298 GEN_VR_STX(svx, 0x07, 0x07),
10299 GEN_VR_STX(svxl, 0x07, 0x0F),
10300 GEN_VR_STVE(bx, 0x07, 0x04),
10301 GEN_VR_STVE(hx, 0x07, 0x05),
10302 GEN_VR_STVE(wx, 0x07, 0x06),
10303
10304 #undef GEN_VX_LOGICAL
10305 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10306 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10307
10308 #undef GEN_VX_LOGICAL_207
10309 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10310 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10311
10312 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10313 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10314 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10315 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10316 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10317 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10318 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10319 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10320
10321 #undef GEN_VXFORM
10322 #define GEN_VXFORM(name, opc2, opc3) \
10323 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10324
10325 #undef GEN_VXFORM_207
10326 #define GEN_VXFORM_207(name, opc2, opc3) \
10327 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10328
10329 #undef GEN_VXFORM_DUAL
10330 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10331 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10332
10333 #undef GEN_VXRFORM_DUAL
10334 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10335 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10336 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10337
10338 GEN_VXFORM(vaddubm, 0, 0),
10339 GEN_VXFORM(vadduhm, 0, 1),
10340 GEN_VXFORM(vadduwm, 0, 2),
10341 GEN_VXFORM_207(vaddudm, 0, 3),
10342 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10343 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10344 GEN_VXFORM(vsubuwm, 0, 18),
10345 GEN_VXFORM_207(vsubudm, 0, 19),
10346 GEN_VXFORM(vmaxub, 1, 0),
10347 GEN_VXFORM(vmaxuh, 1, 1),
10348 GEN_VXFORM(vmaxuw, 1, 2),
10349 GEN_VXFORM_207(vmaxud, 1, 3),
10350 GEN_VXFORM(vmaxsb, 1, 4),
10351 GEN_VXFORM(vmaxsh, 1, 5),
10352 GEN_VXFORM(vmaxsw, 1, 6),
10353 GEN_VXFORM_207(vmaxsd, 1, 7),
10354 GEN_VXFORM(vminub, 1, 8),
10355 GEN_VXFORM(vminuh, 1, 9),
10356 GEN_VXFORM(vminuw, 1, 10),
10357 GEN_VXFORM_207(vminud, 1, 11),
10358 GEN_VXFORM(vminsb, 1, 12),
10359 GEN_VXFORM(vminsh, 1, 13),
10360 GEN_VXFORM(vminsw, 1, 14),
10361 GEN_VXFORM_207(vminsd, 1, 15),
10362 GEN_VXFORM(vavgub, 1, 16),
10363 GEN_VXFORM(vavguh, 1, 17),
10364 GEN_VXFORM(vavguw, 1, 18),
10365 GEN_VXFORM(vavgsb, 1, 20),
10366 GEN_VXFORM(vavgsh, 1, 21),
10367 GEN_VXFORM(vavgsw, 1, 22),
10368 GEN_VXFORM(vmrghb, 6, 0),
10369 GEN_VXFORM(vmrghh, 6, 1),
10370 GEN_VXFORM(vmrghw, 6, 2),
10371 GEN_VXFORM(vmrglb, 6, 4),
10372 GEN_VXFORM(vmrglh, 6, 5),
10373 GEN_VXFORM(vmrglw, 6, 6),
10374 GEN_VXFORM_207(vmrgew, 6, 30),
10375 GEN_VXFORM_207(vmrgow, 6, 26),
10376 GEN_VXFORM(vmuloub, 4, 0),
10377 GEN_VXFORM(vmulouh, 4, 1),
10378 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10379 GEN_VXFORM(vmulosb, 4, 4),
10380 GEN_VXFORM(vmulosh, 4, 5),
10381 GEN_VXFORM_207(vmulosw, 4, 6),
10382 GEN_VXFORM(vmuleub, 4, 8),
10383 GEN_VXFORM(vmuleuh, 4, 9),
10384 GEN_VXFORM_207(vmuleuw, 4, 10),
10385 GEN_VXFORM(vmulesb, 4, 12),
10386 GEN_VXFORM(vmulesh, 4, 13),
10387 GEN_VXFORM_207(vmulesw, 4, 14),
10388 GEN_VXFORM(vslb, 2, 4),
10389 GEN_VXFORM(vslh, 2, 5),
10390 GEN_VXFORM(vslw, 2, 6),
10391 GEN_VXFORM_207(vsld, 2, 23),
10392 GEN_VXFORM(vsrb, 2, 8),
10393 GEN_VXFORM(vsrh, 2, 9),
10394 GEN_VXFORM(vsrw, 2, 10),
10395 GEN_VXFORM_207(vsrd, 2, 27),
10396 GEN_VXFORM(vsrab, 2, 12),
10397 GEN_VXFORM(vsrah, 2, 13),
10398 GEN_VXFORM(vsraw, 2, 14),
10399 GEN_VXFORM_207(vsrad, 2, 15),
10400 GEN_VXFORM(vslo, 6, 16),
10401 GEN_VXFORM(vsro, 6, 17),
10402 GEN_VXFORM(vaddcuw, 0, 6),
10403 GEN_VXFORM(vsubcuw, 0, 22),
10404 GEN_VXFORM(vaddubs, 0, 8),
10405 GEN_VXFORM(vadduhs, 0, 9),
10406 GEN_VXFORM(vadduws, 0, 10),
10407 GEN_VXFORM(vaddsbs, 0, 12),
10408 GEN_VXFORM(vaddshs, 0, 13),
10409 GEN_VXFORM(vaddsws, 0, 14),
10410 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10411 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10412 GEN_VXFORM(vsubuws, 0, 26),
10413 GEN_VXFORM(vsubsbs, 0, 28),
10414 GEN_VXFORM(vsubshs, 0, 29),
10415 GEN_VXFORM(vsubsws, 0, 30),
10416 GEN_VXFORM_207(vadduqm, 0, 4),
10417 GEN_VXFORM_207(vaddcuq, 0, 5),
10418 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10419 GEN_VXFORM_207(vsubuqm, 0, 20),
10420 GEN_VXFORM_207(vsubcuq, 0, 21),
10421 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10422 GEN_VXFORM(vrlb, 2, 0),
10423 GEN_VXFORM(vrlh, 2, 1),
10424 GEN_VXFORM(vrlw, 2, 2),
10425 GEN_VXFORM_207(vrld, 2, 3),
10426 GEN_VXFORM(vsl, 2, 7),
10427 GEN_VXFORM(vsr, 2, 11),
10428 GEN_VXFORM(vpkuhum, 7, 0),
10429 GEN_VXFORM(vpkuwum, 7, 1),
10430 GEN_VXFORM_207(vpkudum, 7, 17),
10431 GEN_VXFORM(vpkuhus, 7, 2),
10432 GEN_VXFORM(vpkuwus, 7, 3),
10433 GEN_VXFORM_207(vpkudus, 7, 19),
10434 GEN_VXFORM(vpkshus, 7, 4),
10435 GEN_VXFORM(vpkswus, 7, 5),
10436 GEN_VXFORM_207(vpksdus, 7, 21),
10437 GEN_VXFORM(vpkshss, 7, 6),
10438 GEN_VXFORM(vpkswss, 7, 7),
10439 GEN_VXFORM_207(vpksdss, 7, 23),
10440 GEN_VXFORM(vpkpx, 7, 12),
10441 GEN_VXFORM(vsum4ubs, 4, 24),
10442 GEN_VXFORM(vsum4sbs, 4, 28),
10443 GEN_VXFORM(vsum4shs, 4, 25),
10444 GEN_VXFORM(vsum2sws, 4, 26),
10445 GEN_VXFORM(vsumsws, 4, 30),
10446 GEN_VXFORM(vaddfp, 5, 0),
10447 GEN_VXFORM(vsubfp, 5, 1),
10448 GEN_VXFORM(vmaxfp, 5, 16),
10449 GEN_VXFORM(vminfp, 5, 17),
10450
10451 #undef GEN_VXRFORM1
10452 #undef GEN_VXRFORM
10453 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10454 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10455 #define GEN_VXRFORM(name, opc2, opc3) \
10456 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10457 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10458 GEN_VXRFORM(vcmpequb, 3, 0)
10459 GEN_VXRFORM(vcmpequh, 3, 1)
10460 GEN_VXRFORM(vcmpequw, 3, 2)
10461 GEN_VXRFORM(vcmpgtsb, 3, 12)
10462 GEN_VXRFORM(vcmpgtsh, 3, 13)
10463 GEN_VXRFORM(vcmpgtsw, 3, 14)
10464 GEN_VXRFORM(vcmpgtub, 3, 8)
10465 GEN_VXRFORM(vcmpgtuh, 3, 9)
10466 GEN_VXRFORM(vcmpgtuw, 3, 10)
10467 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10468 GEN_VXRFORM(vcmpgefp, 3, 7)
10469 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10470 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10471
10472 #undef GEN_VXFORM_SIMM
10473 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10474 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10475 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10476 GEN_VXFORM_SIMM(vspltish, 6, 13),
10477 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10478
10479 #undef GEN_VXFORM_NOA
10480 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10481 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10482 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10483 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10484 GEN_VXFORM_207(vupkhsw, 7, 25),
10485 GEN_VXFORM_NOA(vupklsb, 7, 10),
10486 GEN_VXFORM_NOA(vupklsh, 7, 11),
10487 GEN_VXFORM_207(vupklsw, 7, 27),
10488 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10489 GEN_VXFORM_NOA(vupklpx, 7, 15),
10490 GEN_VXFORM_NOA(vrefp, 5, 4),
10491 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10492 GEN_VXFORM_NOA(vexptefp, 5, 6),
10493 GEN_VXFORM_NOA(vlogefp, 5, 7),
10494 GEN_VXFORM_NOA(vrfim, 5, 8),
10495 GEN_VXFORM_NOA(vrfin, 5, 9),
10496 GEN_VXFORM_NOA(vrfip, 5, 10),
10497 GEN_VXFORM_NOA(vrfiz, 5, 11),
10498
10499 #undef GEN_VXFORM_UIMM
10500 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10501 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10502 GEN_VXFORM_UIMM(vspltb, 6, 8),
10503 GEN_VXFORM_UIMM(vsplth, 6, 9),
10504 GEN_VXFORM_UIMM(vspltw, 6, 10),
10505 GEN_VXFORM_UIMM(vcfux, 5, 12),
10506 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10507 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10508 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10509
10510 #undef GEN_VAFORM_PAIRED
10511 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10512 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10513 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10514 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10515 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10516 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10517 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10518 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10519
10520 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10521 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10522 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10523 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10524
10525 GEN_VXFORM_207(vbpermq, 6, 21),
10526 GEN_VXFORM_207(vgbbd, 6, 20),
10527 GEN_VXFORM_207(vpmsumb, 4, 16),
10528 GEN_VXFORM_207(vpmsumh, 4, 17),
10529 GEN_VXFORM_207(vpmsumw, 4, 18),
10530 GEN_VXFORM_207(vpmsumd, 4, 19),
10531
10532 GEN_VXFORM_207(vsbox, 4, 23),
10533
10534 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10535 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10536
10537 GEN_VXFORM_207(vshasigmaw, 1, 26),
10538 GEN_VXFORM_207(vshasigmad, 1, 27),
10539
10540 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10541
10542 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10543 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10544 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10545 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10546 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10547 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10548 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10549
10550 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10551 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10552 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10553 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10554 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10555
10556 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10557 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10558 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10559 #if defined(TARGET_PPC64)
10560 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10561 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10562 #endif
10563
10564 #undef GEN_XX2FORM
10565 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10566 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10567 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10568
10569 #undef GEN_XX3FORM
10570 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10571 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10572 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10573 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10574 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10575
10576 #undef GEN_XX3_RC_FORM
10577 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10578 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10579 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10580 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10581 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10582 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10583 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10584 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10585 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10586
10587 #undef GEN_XX3FORM_DM
10588 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10589 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10590 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10591 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10592 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10593 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10594 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10595 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10596 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10597 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10598 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10599 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10600 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10601 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10602 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10603 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10604 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10605
10606 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10607 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10608 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10609 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10610
10611 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10612 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10613 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10614 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10615 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10616 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10617 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10618 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10619
10620 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10621 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10622 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10623 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10624 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10625 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10626 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10627 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10628 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10629 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10630 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10631 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10632 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10633 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10634 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10635 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10636 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10637 GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10638 GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10639 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10640 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10641 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10642 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10643 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10644 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10645 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10646 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10647 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10648 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10649 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10650 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10651 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10652 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10653 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10654 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10655 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10656
10657 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10658 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10659 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10660 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10661 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10662 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10663 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10664 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10665 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10666 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10667 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10668 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10669 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10670 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10671 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10672 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10673 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10674 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10675
10676 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10677 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10678 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10679 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10680 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10681 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10682 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10683 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10684 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10685 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10686 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10687 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10688 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10689 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10690 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10691 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10692 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10693 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10694 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10695 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10696 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10697 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10698 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10699 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10700 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10701 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10702 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10703 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10704 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10705 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10706 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10707 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10708 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10709 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10710 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10711 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10712
10713 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10714 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10715 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10716 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10717 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10718 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10719 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10720 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10721 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10722 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10723 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10724 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10725 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10726 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10727 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10728 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10729 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10730 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10731 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10732 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10733 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10734 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10735 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10736 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10737 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10738 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10739 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10740 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10741 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10742 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10743 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10744 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10745 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10746 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10747 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10748 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10749
10750 #undef VSX_LOGICAL
10751 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10752 GEN_XX3FORM(name, opc2, opc3, fl2)
10753
10754 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10755 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10756 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10757 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10758 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10759 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10760 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10761 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10762 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10763 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10764 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10765 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10766
10767 #define GEN_XXSEL_ROW(opc3) \
10768 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10769 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10770 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10771 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10772 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10773 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10774 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10775 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10776
10777 GEN_XXSEL_ROW(0x00)
10778 GEN_XXSEL_ROW(0x01)
10779 GEN_XXSEL_ROW(0x02)
10780 GEN_XXSEL_ROW(0x03)
10781 GEN_XXSEL_ROW(0x04)
10782 GEN_XXSEL_ROW(0x05)
10783 GEN_XXSEL_ROW(0x06)
10784 GEN_XXSEL_ROW(0x07)
10785 GEN_XXSEL_ROW(0x08)
10786 GEN_XXSEL_ROW(0x09)
10787 GEN_XXSEL_ROW(0x0A)
10788 GEN_XXSEL_ROW(0x0B)
10789 GEN_XXSEL_ROW(0x0C)
10790 GEN_XXSEL_ROW(0x0D)
10791 GEN_XXSEL_ROW(0x0E)
10792 GEN_XXSEL_ROW(0x0F)
10793 GEN_XXSEL_ROW(0x10)
10794 GEN_XXSEL_ROW(0x11)
10795 GEN_XXSEL_ROW(0x12)
10796 GEN_XXSEL_ROW(0x13)
10797 GEN_XXSEL_ROW(0x14)
10798 GEN_XXSEL_ROW(0x15)
10799 GEN_XXSEL_ROW(0x16)
10800 GEN_XXSEL_ROW(0x17)
10801 GEN_XXSEL_ROW(0x18)
10802 GEN_XXSEL_ROW(0x19)
10803 GEN_XXSEL_ROW(0x1A)
10804 GEN_XXSEL_ROW(0x1B)
10805 GEN_XXSEL_ROW(0x1C)
10806 GEN_XXSEL_ROW(0x1D)
10807 GEN_XXSEL_ROW(0x1E)
10808 GEN_XXSEL_ROW(0x1F)
10809
10810 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10811
10812 #undef GEN_DFP_T_A_B_Rc
10813 #undef GEN_DFP_BF_A_B
10814 #undef GEN_DFP_BF_A_DCM
10815 #undef GEN_DFP_T_B_U32_U32_Rc
10816 #undef GEN_DFP_T_A_B_I32_Rc
10817 #undef GEN_DFP_T_B_Rc
10818 #undef GEN_DFP_T_FPR_I32_Rc
10819
10820 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10821 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10822
10823 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10824 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10825 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10826
10827 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10828 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10829 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10830 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10831 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10832
10833 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
10834 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10835
10836 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10837 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10838 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10839
10840 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10841 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10842 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10843 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10844 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10845
10846 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10847 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
10848
10849 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10850 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10851
10852 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10853 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10854
10855 #define GEN_DFP_T_B_Rc(name, op1, op2) \
10856 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10857
10858 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
10859 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
10860
10861 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
10862 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
10863
10864 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
10865 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
10866
10867 #define GEN_DFP_BF_A_B(name, op1, op2) \
10868 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
10869
10870 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
10871 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
10872
10873 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
10874 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
10875
10876 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
10877 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
10878
10879 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
10880 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
10881
10882 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
10883 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10884
10885 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
10886 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
10887
10888 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
10889 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
10890
10891 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
10892 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10893
10894 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
10895 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
10896
10897 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
10898 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
10899
10900 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
10901 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
10902
10903 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
10904 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
10905
10906 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
10907 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
10908
10909 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
10910 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
10911
10912 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
10913 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
10914
10915 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
10916 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
10917
10918 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
10919 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
10920
10921 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
10922 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
10923 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
10924 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
10925 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
10926 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
10927 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
10928 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
10929 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
10930 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
10931 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
10932 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
10933 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
10934 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
10935 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
10936 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
10937 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
10938 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
10939 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
10940 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
10941 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
10942 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
10943 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
10944 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
10945 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
10946 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
10947 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
10948 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
10949 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
10950 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
10951 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
10952 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
10953 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
10954 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
10955 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
10956 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
10957 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
10958 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
10959 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
10960 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
10961 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
10962 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
10963 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
10964 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
10965 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
10966 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
10967 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
10968 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
10969 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
10970 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
10971
10972 #undef GEN_SPE
10973 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
10974 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
10975 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10976 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10977 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10978 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10979 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10980 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10981 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10982 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
10983 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
10984 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10985 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10986 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10987 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10988 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10989 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10990 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
10991 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10992 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10993 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10994 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10995 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10996 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10997 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10998 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10999 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11000 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11001 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11002 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11003 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11004
11005 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11006 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11007 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11008 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11009 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11010 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11011 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11012 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11013 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11014 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11015 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11016 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11017 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11018 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11019
11020 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11021 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11022 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11023 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11024 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11025 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11026 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11027 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11028 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11029 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11030 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11031 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11032 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11033 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11034
11035 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11036 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11037 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11038 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11039 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11040 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11041 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11042 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11043 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11044 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11045 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11046 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11047 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11048 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11049 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11050 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11051
11052 #undef GEN_SPEOP_LDST
11053 #define GEN_SPEOP_LDST(name, opc2, sh) \
11054 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11055 GEN_SPEOP_LDST(evldd, 0x00, 3),
11056 GEN_SPEOP_LDST(evldw, 0x01, 3),
11057 GEN_SPEOP_LDST(evldh, 0x02, 3),
11058 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11059 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11060 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11061 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11062 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11063 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11064 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11065 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11066
11067 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11068 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11069 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11070 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11071 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11072 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11073 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11074 };
11075
11076 #include "helper_regs.h"
11077 #include "translate_init.c"
11078
11079 /*****************************************************************************/
11080 /* Misc PowerPC helpers */
11081 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11082 int flags)
11083 {
11084 #define RGPL 4
11085 #define RFPL 4
11086
11087 PowerPCCPU *cpu = POWERPC_CPU(cs);
11088 CPUPPCState *env = &cpu->env;
11089 int i;
11090
11091 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11092 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
11093 env->nip, env->lr, env->ctr, cpu_read_xer(env));
11094 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11095 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11096 env->hflags, env->mmu_idx);
11097 #if !defined(NO_TIMER_DUMP)
11098 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11099 #if !defined(CONFIG_USER_ONLY)
11100 " DECR %08" PRIu32
11101 #endif
11102 "\n",
11103 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11104 #if !defined(CONFIG_USER_ONLY)
11105 , cpu_ppc_load_decr(env)
11106 #endif
11107 );
11108 #endif
11109 for (i = 0; i < 32; i++) {
11110 if ((i & (RGPL - 1)) == 0)
11111 cpu_fprintf(f, "GPR%02d", i);
11112 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11113 if ((i & (RGPL - 1)) == (RGPL - 1))
11114 cpu_fprintf(f, "\n");
11115 }
11116 cpu_fprintf(f, "CR ");
11117 for (i = 0; i < 8; i++)
11118 cpu_fprintf(f, "%01x", env->crf[i]);
11119 cpu_fprintf(f, " [");
11120 for (i = 0; i < 8; i++) {
11121 char a = '-';
11122 if (env->crf[i] & 0x08)
11123 a = 'L';
11124 else if (env->crf[i] & 0x04)
11125 a = 'G';
11126 else if (env->crf[i] & 0x02)
11127 a = 'E';
11128 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11129 }
11130 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11131 env->reserve_addr);
11132 for (i = 0; i < 32; i++) {
11133 if ((i & (RFPL - 1)) == 0)
11134 cpu_fprintf(f, "FPR%02d", i);
11135 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11136 if ((i & (RFPL - 1)) == (RFPL - 1))
11137 cpu_fprintf(f, "\n");
11138 }
11139 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11140 #if !defined(CONFIG_USER_ONLY)
11141 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11142 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11143 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11144 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11145
11146 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11147 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11148 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11149 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11150
11151 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11152 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11153 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11154 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11155
11156 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11157 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11158 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11159 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11160 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11161
11162 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11163 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11164 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11165 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11166
11167 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11168 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11169 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11170 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11171
11172 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11173 " EPR " TARGET_FMT_lx "\n",
11174 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11175 env->spr[SPR_BOOKE_EPR]);
11176
11177 /* FSL-specific */
11178 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11179 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11180 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11181 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11182
11183 /*
11184 * IVORs are left out as they are large and do not change often --
11185 * they can be read with "p $ivor0", "p $ivor1", etc.
11186 */
11187 }
11188
11189 #if defined(TARGET_PPC64)
11190 if (env->flags & POWERPC_FLAG_CFAR) {
11191 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11192 }
11193 #endif
11194
11195 switch (env->mmu_model) {
11196 case POWERPC_MMU_32B:
11197 case POWERPC_MMU_601:
11198 case POWERPC_MMU_SOFT_6xx:
11199 case POWERPC_MMU_SOFT_74xx:
11200 #if defined(TARGET_PPC64)
11201 case POWERPC_MMU_64B:
11202 case POWERPC_MMU_2_06:
11203 case POWERPC_MMU_2_06a:
11204 case POWERPC_MMU_2_06d:
11205 #endif
11206 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11207 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11208 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11209 break;
11210 case POWERPC_MMU_BOOKE206:
11211 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11212 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11213 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11214 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11215
11216 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11217 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11218 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11219 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11220
11221 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11222 " TLB1CFG " TARGET_FMT_lx "\n",
11223 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11224 env->spr[SPR_BOOKE_TLB1CFG]);
11225 break;
11226 default:
11227 break;
11228 }
11229 #endif
11230
11231 #undef RGPL
11232 #undef RFPL
11233 }
11234
11235 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11236 fprintf_function cpu_fprintf, int flags)
11237 {
11238 #if defined(DO_PPC_STATISTICS)
11239 PowerPCCPU *cpu = POWERPC_CPU(cs);
11240 opc_handler_t **t1, **t2, **t3, *handler;
11241 int op1, op2, op3;
11242
11243 t1 = cpu->env.opcodes;
11244 for (op1 = 0; op1 < 64; op1++) {
11245 handler = t1[op1];
11246 if (is_indirect_opcode(handler)) {
11247 t2 = ind_table(handler);
11248 for (op2 = 0; op2 < 32; op2++) {
11249 handler = t2[op2];
11250 if (is_indirect_opcode(handler)) {
11251 t3 = ind_table(handler);
11252 for (op3 = 0; op3 < 32; op3++) {
11253 handler = t3[op3];
11254 if (handler->count == 0)
11255 continue;
11256 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11257 "%016" PRIx64 " %" PRId64 "\n",
11258 op1, op2, op3, op1, (op3 << 5) | op2,
11259 handler->oname,
11260 handler->count, handler->count);
11261 }
11262 } else {
11263 if (handler->count == 0)
11264 continue;
11265 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11266 "%016" PRIx64 " %" PRId64 "\n",
11267 op1, op2, op1, op2, handler->oname,
11268 handler->count, handler->count);
11269 }
11270 }
11271 } else {
11272 if (handler->count == 0)
11273 continue;
11274 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11275 " %" PRId64 "\n",
11276 op1, op1, handler->oname,
11277 handler->count, handler->count);
11278 }
11279 }
11280 #endif
11281 }
11282
11283 /*****************************************************************************/
11284 static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
11285 TranslationBlock *tb,
11286 bool search_pc)
11287 {
11288 CPUState *cs = CPU(cpu);
11289 CPUPPCState *env = &cpu->env;
11290 DisasContext ctx, *ctxp = &ctx;
11291 opc_handler_t **table, *handler;
11292 target_ulong pc_start;
11293 uint16_t *gen_opc_end;
11294 CPUBreakpoint *bp;
11295 int j, lj = -1;
11296 int num_insns;
11297 int max_insns;
11298
11299 pc_start = tb->pc;
11300 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
11301 ctx.nip = pc_start;
11302 ctx.tb = tb;
11303 ctx.exception = POWERPC_EXCP_NONE;
11304 ctx.spr_cb = env->spr_cb;
11305 ctx.mem_idx = env->mmu_idx;
11306 ctx.insns_flags = env->insns_flags;
11307 ctx.insns_flags2 = env->insns_flags2;
11308 ctx.access_type = -1;
11309 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11310 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11311 #if defined(TARGET_PPC64)
11312 ctx.sf_mode = msr_is_64bit(env, env->msr);
11313 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11314 #endif
11315 ctx.fpu_enabled = msr_fp;
11316 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11317 ctx.spe_enabled = msr_spe;
11318 else
11319 ctx.spe_enabled = 0;
11320 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11321 ctx.altivec_enabled = msr_vr;
11322 else
11323 ctx.altivec_enabled = 0;
11324 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11325 ctx.vsx_enabled = msr_vsx;
11326 } else {
11327 ctx.vsx_enabled = 0;
11328 }
11329 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11330 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11331 else
11332 ctx.singlestep_enabled = 0;
11333 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11334 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11335 if (unlikely(cs->singlestep_enabled)) {
11336 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11337 }
11338 #if defined (DO_SINGLE_STEP) && 0
11339 /* Single step trace mode */
11340 msr_se = 1;
11341 #endif
11342 num_insns = 0;
11343 max_insns = tb->cflags & CF_COUNT_MASK;
11344 if (max_insns == 0)
11345 max_insns = CF_COUNT_MASK;
11346
11347 gen_tb_start();
11348 tcg_clear_temp_count();
11349 /* Set env in case of segfault during code fetch */
11350 while (ctx.exception == POWERPC_EXCP_NONE
11351 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
11352 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
11353 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
11354 if (bp->pc == ctx.nip) {
11355 gen_debug_exception(ctxp);
11356 break;
11357 }
11358 }
11359 }
11360 if (unlikely(search_pc)) {
11361 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11362 if (lj < j) {
11363 lj++;
11364 while (lj < j)
11365 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11366 }
11367 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
11368 tcg_ctx.gen_opc_instr_start[lj] = 1;
11369 tcg_ctx.gen_opc_icount[lj] = num_insns;
11370 }
11371 LOG_DISAS("----------------\n");
11372 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11373 ctx.nip, ctx.mem_idx, (int)msr_ir);
11374 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
11375 gen_io_start();
11376 if (unlikely(need_byteswap(&ctx))) {
11377 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11378 } else {
11379 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11380 }
11381 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11382 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11383 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11384 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
11385 tcg_gen_debug_insn_start(ctx.nip);
11386 }
11387 ctx.nip += 4;
11388 table = env->opcodes;
11389 num_insns++;
11390 handler = table[opc1(ctx.opcode)];
11391 if (is_indirect_opcode(handler)) {
11392 table = ind_table(handler);
11393 handler = table[opc2(ctx.opcode)];
11394 if (is_indirect_opcode(handler)) {
11395 table = ind_table(handler);
11396 handler = table[opc3(ctx.opcode)];
11397 }
11398 }
11399 /* Is opcode *REALLY* valid ? */
11400 if (unlikely(handler->handler == &gen_invalid)) {
11401 if (qemu_log_enabled()) {
11402 qemu_log("invalid/unsupported opcode: "
11403 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11404 opc1(ctx.opcode), opc2(ctx.opcode),
11405 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11406 }
11407 } else {
11408 uint32_t inval;
11409
11410 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11411 inval = handler->inval2;
11412 } else {
11413 inval = handler->inval1;
11414 }
11415
11416 if (unlikely((ctx.opcode & inval) != 0)) {
11417 if (qemu_log_enabled()) {
11418 qemu_log("invalid bits: %08x for opcode: "
11419 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11420 ctx.opcode & inval, opc1(ctx.opcode),
11421 opc2(ctx.opcode), opc3(ctx.opcode),
11422 ctx.opcode, ctx.nip - 4);
11423 }
11424 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11425 break;
11426 }
11427 }
11428 (*(handler->handler))(&ctx);
11429 #if defined(DO_PPC_STATISTICS)
11430 handler->count++;
11431 #endif
11432 /* Check trace mode exceptions */
11433 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11434 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11435 ctx.exception != POWERPC_SYSCALL &&
11436 ctx.exception != POWERPC_EXCP_TRAP &&
11437 ctx.exception != POWERPC_EXCP_BRANCH)) {
11438 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11439 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11440 (cs->singlestep_enabled) ||
11441 singlestep ||
11442 num_insns >= max_insns)) {
11443 /* if we reach a page boundary or are single stepping, stop
11444 * generation
11445 */
11446 break;
11447 }
11448 if (tcg_check_temp_count()) {
11449 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11450 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11451 ctx.opcode);
11452 exit(1);
11453 }
11454 }
11455 if (tb->cflags & CF_LAST_IO)
11456 gen_io_end();
11457 if (ctx.exception == POWERPC_EXCP_NONE) {
11458 gen_goto_tb(&ctx, 0, ctx.nip);
11459 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11460 if (unlikely(cs->singlestep_enabled)) {
11461 gen_debug_exception(ctxp);
11462 }
11463 /* Generate the return instruction */
11464 tcg_gen_exit_tb(0);
11465 }
11466 gen_tb_end(tb, num_insns);
11467 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
11468 if (unlikely(search_pc)) {
11469 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11470 lj++;
11471 while (lj <= j)
11472 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11473 } else {
11474 tb->size = ctx.nip - pc_start;
11475 tb->icount = num_insns;
11476 }
11477 #if defined(DEBUG_DISAS)
11478 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11479 int flags;
11480 flags = env->bfd_mach;
11481 flags |= ctx.le_mode << 16;
11482 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11483 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
11484 qemu_log("\n");
11485 }
11486 #endif
11487 }
11488
11489 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
11490 {
11491 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
11492 }
11493
11494 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
11495 {
11496 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
11497 }
11498
11499 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
11500 {
11501 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
11502 }
AR7 emulation for QEMU