target/mips/cpu.c

   1 /*
   2  * QEMU MIPS CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "cpu.h"
  24 #include "internal.h"
  25 #include "kvm_mips.h"
  26 #include "qemu/module.h"
  27 #include "sysemu/kvm.h"
  28 #include "exec/exec-all.h"
  29 #include "hw/qdev-properties.h"
  30 #include "hw/qdev-clock.h"
  31
  32 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
  33 {
  34     MIPSCPU *cpu = MIPS_CPU(cs);
  35     CPUMIPSState *env = &cpu->env;
  36
  37     env->active_tc.PC = value & ~(target_ulong)1;
  38     if (value & 1) {
  39         env->hflags |= MIPS_HFLAG_M16;
  40     } else {
  41         env->hflags &= ~(MIPS_HFLAG_M16);
  42     }
  43 }
  44
  45 static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
  46 {
  47     MIPSCPU *cpu = MIPS_CPU(cs);
  48     CPUMIPSState *env = &cpu->env;
  49
  50     env->active_tc.PC = tb->pc;
  51     env->hflags &= ~MIPS_HFLAG_BMASK;
  52     env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
  53 }
  54
  55 static bool mips_cpu_has_work(CPUState *cs)
  56 {
  57     MIPSCPU *cpu = MIPS_CPU(cs);
  58     CPUMIPSState *env = &cpu->env;
  59     bool has_work = false;
  60
  61     /*
  62      * Prior to MIPS Release 6 it is implementation dependent if non-enabled
  63      * interrupts wake-up the CPU, however most of the implementations only
  64      * check for interrupts that can be taken.
  65      */
  66     if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
  67         cpu_mips_hw_interrupts_pending(env)) {
  68         if (cpu_mips_hw_interrupts_enabled(env) ||
  69             (env->insn_flags & ISA_MIPS32R6)) {
  70             has_work = true;
  71         }
  72     }
  73
  74     /* MIPS-MT has the ability to halt the CPU.  */
  75     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
  76         /*
  77          * The QEMU model will issue an _WAKE request whenever the CPUs
  78          * should be woken up.
  79          */
  80         if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
  81             has_work = true;
  82         }
  83
  84         if (!mips_vpe_active(env)) {
  85             has_work = false;
  86         }
  87     }
  88     /* MIPS Release 6 has the ability to halt the CPU.  */
  89     if (env->CP0_Config5 & (1 << CP0C5_VP)) {
  90         if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
  91             has_work = true;
  92         }
  93         if (!mips_vp_active(env)) {
  94             has_work = false;
  95         }
  96     }
  97     return has_work;
  98 }
  99
 100 static void mips_cpu_reset(DeviceState *dev)
 101 {
 102     CPUState *s = CPU(dev);
 103     MIPSCPU *cpu = MIPS_CPU(s);
 104     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
 105     CPUMIPSState *env = &cpu->env;
 106
 107     mcc->parent_reset(dev);
 108
 109     memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
 110
 111     cpu_state_reset(env);
 112
 113 #ifndef CONFIG_USER_ONLY
 114     if (kvm_enabled()) {
 115         kvm_mips_reset_vcpu(cpu);
 116     }
 117 #endif
 118 }
 119
 120 static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 121 {
 122     MIPSCPU *cpu = MIPS_CPU(s);
 123     CPUMIPSState *env = &cpu->env;
 124
 125     if (!(env->insn_flags & ISA_NANOMIPS32)) {
 126 #ifdef TARGET_WORDS_BIGENDIAN
 127         info->print_insn = print_insn_big_mips;
 128 #else
 129         info->print_insn = print_insn_little_mips;
 130 #endif
 131     } else {
 132 #if defined(CONFIG_NANOMIPS_DIS)
 133         info->print_insn = print_insn_nanomips;
 134 #endif
 135     }
 136 }
 137
 138 /*
 139  * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz.
 140  */
 141 #define CPU_FREQ_HZ_DEFAULT     200000000
 142 #define CP0_COUNT_RATE_DEFAULT  2
 143
 144 static void mips_cp0_period_set(MIPSCPU *cpu)
 145 {
 146     CPUMIPSState *env = &cpu->env;
 147
 148     env->cp0_count_ns = cpu->cp0_count_rate
 149                         * clock_get_ns(MIPS_CPU(cpu)->clock);
 150     assert(env->cp0_count_ns);
 151 }
 152
 153 static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
 154 {
 155     CPUState *cs = CPU(dev);
 156     MIPSCPU *cpu = MIPS_CPU(dev);
 157     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
 158     Error *local_err = NULL;
 159
 160     if (!clock_get(cpu->clock)) {
 161         /* Initialize the frequency in case the clock remains unconnected. */
 162         clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT);
 163     }
 164     mips_cp0_period_set(cpu);
 165
 166     cpu_exec_realizefn(cs, &local_err);
 167     if (local_err != NULL) {
 168         error_propagate(errp, local_err);
 169         return;
 170     }
 171
 172     cpu_mips_realize_env(&cpu->env);
 173
 174     cpu_reset(cs);
 175     qemu_init_vcpu(cs);
 176
 177     mcc->parent_realize(dev, errp);
 178 }
 179
 180 static void mips_cpu_initfn(Object *obj)
 181 {
 182     MIPSCPU *cpu = MIPS_CPU(obj);
 183     CPUMIPSState *env = &cpu->env;
 184     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
 185
 186     cpu_set_cpustate_pointers(cpu);
 187     cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu);
 188     env->cpu_model = mcc->cpu_def;
 189 }
 190
 191 static char *mips_cpu_type_name(const char *cpu_model)
 192 {
 193     return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model);
 194 }
 195
 196 static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)
 197 {
 198     ObjectClass *oc;
 199     char *typename;
 200
 201     typename = mips_cpu_type_name(cpu_model);
 202     oc = object_class_by_name(typename);
 203     g_free(typename);
 204     return oc;
 205 }
 206
 207 static Property mips_cpu_properties[] = {
 208     /* CP0 timer running at half the clock of the CPU */
 209     DEFINE_PROP_UINT32("cp0-count-rate", MIPSCPU, cp0_count_rate,
 210                        CP0_COUNT_RATE_DEFAULT),
 211     DEFINE_PROP_END_OF_LIST()
 212 };
 213
 214 static void mips_cpu_class_init(ObjectClass *c, void *data)
 215 {
 216     MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
 217     CPUClass *cc = CPU_CLASS(c);
 218     DeviceClass *dc = DEVICE_CLASS(c);
 219
 220     device_class_set_parent_realize(dc, mips_cpu_realizefn,
 221                                     &mcc->parent_realize);
 222     device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset);
 223     device_class_set_props(dc, mips_cpu_properties);
 224
 225     cc->class_by_name = mips_cpu_class_by_name;
 226     cc->has_work = mips_cpu_has_work;
 227     cc->do_interrupt = mips_cpu_do_interrupt;
 228     cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
 229     cc->dump_state = mips_cpu_dump_state;
 230     cc->set_pc = mips_cpu_set_pc;
 231     cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
 232     cc->gdb_read_register = mips_cpu_gdb_read_register;
 233     cc->gdb_write_register = mips_cpu_gdb_write_register;
 234 #ifndef CONFIG_USER_ONLY
 235     cc->do_transaction_failed = mips_cpu_do_transaction_failed;
 236     cc->do_unaligned_access = mips_cpu_do_unaligned_access;
 237     cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
 238     cc->vmsd = &vmstate_mips_cpu;
 239 #endif
 240     cc->disas_set_info = mips_cpu_disas_set_info;
 241 #ifdef CONFIG_TCG
 242     cc->tcg_initialize = mips_tcg_init;
 243     cc->tlb_fill = mips_cpu_tlb_fill;
 244 #endif
 245
 246     cc->gdb_num_core_regs = 73;
 247     cc->gdb_stop_before_watchpoint = true;
 248 }
 249
 250 static const TypeInfo mips_cpu_type_info = {
 251     .name = TYPE_MIPS_CPU,
 252     .parent = TYPE_CPU,
 253     .instance_size = sizeof(MIPSCPU),
 254     .instance_init = mips_cpu_initfn,
 255     .abstract = true,
 256     .class_size = sizeof(MIPSCPUClass),
 257     .class_init = mips_cpu_class_init,
 258 };
 259
 260 static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data)
 261 {
 262     MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc);
 263     mcc->cpu_def = data;
 264 }
 265
 266 static void mips_register_cpudef_type(const struct mips_def_t *def)
 267 {
 268     char *typename = mips_cpu_type_name(def->name);
 269     TypeInfo ti = {
 270         .name = typename,
 271         .parent = TYPE_MIPS_CPU,
 272         .class_init = mips_cpu_cpudef_class_init,
 273         .class_data = (void *)def,
 274     };
 275
 276     type_register(&ti);
 277     g_free(typename);
 278 }
 279
 280 static void mips_cpu_register_types(void)
 281 {
 282     int i;
 283
 284     type_register_static(&mips_cpu_type_info);
 285     for (i = 0; i < mips_defs_number; i++) {
 286         mips_register_cpudef_type(&mips_defs[i]);
 287     }
 288 }
 289
 290 type_init(mips_cpu_register_types)
 291
 292 /* Could be used by generic CPU object */
 293 MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
 294 {
 295     DeviceState *cpu;
 296
 297     cpu = DEVICE(object_new(cpu_type));
 298     qdev_connect_clock_in(cpu, "clk-in", cpu_refclk);
 299     qdev_realize(cpu, NULL, &error_abort);
 300
 301     return MIPS_CPU(cpu);
 302 }