hw/mips/cps: Expose input clock and connect it to CPU cores
[qemu/ar7.git] / hw / misc / pvpanic.c
blob598d5471a4203752f8d6adeabeefdebbd17a25e3
1 /*
2 * QEMU simulated pvpanic device.
4 * Copyright Fujitsu, Corp. 2013
6 * Authors:
7 * Wen Congyang <wency@cn.fujitsu.com>
8 * Hu Tao <hutao@cn.fujitsu.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include "qemu/osdep.h"
16 #include "qemu/log.h"
17 #include "qemu/module.h"
18 #include "sysemu/runstate.h"
20 #include "hw/nvram/fw_cfg.h"
21 #include "hw/qdev-properties.h"
22 #include "hw/misc/pvpanic.h"
23 #include "qom/object.h"
25 /* The bit of supported pv event, TODO: include uapi header and remove this */
26 #define PVPANIC_F_PANICKED 0
27 #define PVPANIC_F_CRASHLOADED 1
29 /* The pv event value */
30 #define PVPANIC_PANICKED (1 << PVPANIC_F_PANICKED)
31 #define PVPANIC_CRASHLOADED (1 << PVPANIC_F_CRASHLOADED)
33 typedef struct PVPanicState PVPanicState;
34 DECLARE_INSTANCE_CHECKER(PVPanicState, ISA_PVPANIC_DEVICE,
35 TYPE_PVPANIC)
37 static void handle_event(int event)
39 static bool logged;
41 if (event & ~(PVPANIC_PANICKED | PVPANIC_CRASHLOADED) && !logged) {
42 qemu_log_mask(LOG_GUEST_ERROR, "pvpanic: unknown event %#x.\n", event);
43 logged = true;
46 if (event & PVPANIC_PANICKED) {
47 qemu_system_guest_panicked(NULL);
48 return;
51 if (event & PVPANIC_CRASHLOADED) {
52 qemu_system_guest_crashloaded(NULL);
53 return;
57 #include "hw/isa/isa.h"
59 struct PVPanicState {
60 ISADevice parent_obj;
62 MemoryRegion io;
63 uint16_t ioport;
66 /* return supported events on read */
67 static uint64_t pvpanic_ioport_read(void *opaque, hwaddr addr, unsigned size)
69 return PVPANIC_PANICKED;
72 static void pvpanic_ioport_write(void *opaque, hwaddr addr, uint64_t val,
73 unsigned size)
75 handle_event(val);
78 static const MemoryRegionOps pvpanic_ops = {
79 .read = pvpanic_ioport_read,
80 .write = pvpanic_ioport_write,
81 .impl = {
82 .min_access_size = 1,
83 .max_access_size = 1,
87 static void pvpanic_isa_initfn(Object *obj)
89 PVPanicState *s = ISA_PVPANIC_DEVICE(obj);
91 memory_region_init_io(&s->io, OBJECT(s), &pvpanic_ops, s, "pvpanic", 1);
94 static void pvpanic_isa_realizefn(DeviceState *dev, Error **errp)
96 ISADevice *d = ISA_DEVICE(dev);
97 PVPanicState *s = ISA_PVPANIC_DEVICE(dev);
98 FWCfgState *fw_cfg = fw_cfg_find();
99 uint16_t *pvpanic_port;
101 if (!fw_cfg) {
102 return;
105 pvpanic_port = g_malloc(sizeof(*pvpanic_port));
106 *pvpanic_port = cpu_to_le16(s->ioport);
107 fw_cfg_add_file(fw_cfg, "etc/pvpanic-port", pvpanic_port,
108 sizeof(*pvpanic_port));
110 isa_register_ioport(d, &s->io, s->ioport);
113 static Property pvpanic_isa_properties[] = {
114 DEFINE_PROP_UINT16(PVPANIC_IOPORT_PROP, PVPanicState, ioport, 0x505),
115 DEFINE_PROP_END_OF_LIST(),
118 static void pvpanic_isa_class_init(ObjectClass *klass, void *data)
120 DeviceClass *dc = DEVICE_CLASS(klass);
122 dc->realize = pvpanic_isa_realizefn;
123 device_class_set_props(dc, pvpanic_isa_properties);
124 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
127 static TypeInfo pvpanic_isa_info = {
128 .name = TYPE_PVPANIC,
129 .parent = TYPE_ISA_DEVICE,
130 .instance_size = sizeof(PVPanicState),
131 .instance_init = pvpanic_isa_initfn,
132 .class_init = pvpanic_isa_class_init,
135 static void pvpanic_register_types(void)
137 type_register_static(&pvpanic_isa_info);
140 type_init(pvpanic_register_types)