hw/mips/cps: Expose input clock and connect it to CPU cores

[qemu/ar7.git] / default-configs / targets / riscv32-softmmu.mak

TARGET_ARCH=riscv32
TARGET_BASE_ARCH=riscv
TARGET_SUPPORTS_MTTCG=y
TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-csr.xml gdb-xml/riscv-32bit-virtual.xml
TARGET_NEED_FDT=y