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[qemu/ar7.git] / target / mips / translate_init.c
blob6ae23e476f79b5be471425d8da1ad0874cb43030
1 /*
2 * MIPS emulation for qemu: CPU initialisation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* CPU / CPU family specific config register values. */
22
23 /* Have config1, uncached coherency */
24 #define MIPS_CONFIG0 \
25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
26
27 /* Have config2, no coprocessor2 attached, no MDMX support attached,
28 no performance counters, watch registers present,
29 no code compression, EJTAG present, no FPU */
30 #define MIPS_CONFIG1 \
31 ((1U << CP0C1_M) | \
32 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
34 (0 << CP0C1_FP))
35
36 /* Have config3, no tertiary/secondary caches implemented */
37 #define MIPS_CONFIG2 \
38 ((1U << CP0C2_M))
39
40 /* No config4, no DSP ASE, no large physaddr (PABITS),
41 no external interrupt controller, no vectored interrupts,
42 no 1kb pages, no SmartMIPS ASE, no trace logic */
43 #define MIPS_CONFIG3 \
44 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
46 (0 << CP0C3_SM) | (0 << CP0C3_TL))
47
48 #define MIPS_CONFIG4 \
49 ((0 << CP0C4_M))
50
51 #define MIPS_CONFIG5 \
52 ((0 << CP0C5_M))
53
54 /* MMU types, the first four entries have the same layout as the
55 CP0C0_MT field. */
56 enum mips_mmu_types {
57 MMU_TYPE_NONE,
58 MMU_TYPE_R4000,
59 MMU_TYPE_RESERVED,
60 MMU_TYPE_FMT,
61 MMU_TYPE_R3000,
62 MMU_TYPE_R6000,
63 MMU_TYPE_R8000
64 };
65
66 struct mips_def_t {
67 const char *name;
68 int32_t CP0_PRid;
69 int32_t CP0_Config0;
70 int32_t CP0_Config1;
71 int32_t CP0_Config2;
72 int32_t CP0_Config3;
73 int32_t CP0_Config4;
74 int32_t CP0_Config4_rw_bitmask;
75 int32_t CP0_Config5;
76 int32_t CP0_Config5_rw_bitmask;
77 int32_t CP0_Config6;
78 int32_t CP0_Config7;
79 target_ulong CP0_LLAddr_rw_bitmask;
80 int CP0_LLAddr_shift;
81 int32_t SYNCI_Step;
82 int32_t CCRes;
83 int32_t CP0_Status_rw_bitmask;
84 int32_t CP0_TCStatus_rw_bitmask;
85 int32_t CP0_SRSCtl;
86 int32_t CP1_fcr0;
87 int32_t CP1_fcr31_rw_bitmask;
88 int32_t CP1_fcr31;
89 int32_t MSAIR;
90 int32_t SEGBITS;
91 int32_t PABITS;
92 int32_t CP0_SRSConf0_rw_bitmask;
93 int32_t CP0_SRSConf0;
94 int32_t CP0_SRSConf1_rw_bitmask;
95 int32_t CP0_SRSConf1;
96 int32_t CP0_SRSConf2_rw_bitmask;
97 int32_t CP0_SRSConf2;
98 int32_t CP0_SRSConf3_rw_bitmask;
99 int32_t CP0_SRSConf3;
100 int32_t CP0_SRSConf4_rw_bitmask;
101 int32_t CP0_SRSConf4;
102 int32_t CP0_PageGrain_rw_bitmask;
103 int32_t CP0_PageGrain;
104 int insn_flags;
105 enum mips_mmu_types mmu_type;
106 };
107
108 /*****************************************************************************/
109 /* MIPS CPU definitions */
110 static const mips_def_t mips_defs[] =
111 {
112 {
113 .name = "4Kc",
114 .CP0_PRid = 0x00018000,
115 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
116 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
117 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
118 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
119 (0 << CP0C1_CA),
120 .CP0_Config2 = MIPS_CONFIG2,
121 .CP0_Config3 = MIPS_CONFIG3,
122 .CP0_LLAddr_rw_bitmask = 0,
123 .CP0_LLAddr_shift = 4,
124 .SYNCI_Step = 32,
125 .CCRes = 2,
126 .CP0_Status_rw_bitmask = 0x1278FF17,
127 .SEGBITS = 32,
128 .PABITS = 32,
129 .insn_flags = CPU_MIPS32,
130 .mmu_type = MMU_TYPE_R4000,
131 },
132 {
133 .name = "4Km",
134 .CP0_PRid = 0x00018300,
135 /* Config1 implemented, fixed mapping MMU,
136 no virtual icache, uncached coherency. */
137 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
138 .CP0_Config1 = MIPS_CONFIG1 |
139 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
140 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
141 (1 << CP0C1_CA),
142 .CP0_Config2 = MIPS_CONFIG2,
143 .CP0_Config3 = MIPS_CONFIG3,
144 .CP0_LLAddr_rw_bitmask = 0,
145 .CP0_LLAddr_shift = 4,
146 .SYNCI_Step = 32,
147 .CCRes = 2,
148 .CP0_Status_rw_bitmask = 0x1258FF17,
149 .SEGBITS = 32,
150 .PABITS = 32,
151 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
152 .mmu_type = MMU_TYPE_FMT,
153 },
154 {
155 .name = "4KEcR1",
156 .CP0_PRid = 0x00018400,
157 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
158 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
159 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
160 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
161 (0 << CP0C1_CA),
162 .CP0_Config2 = MIPS_CONFIG2,
163 .CP0_Config3 = MIPS_CONFIG3,
164 .CP0_LLAddr_rw_bitmask = 0,
165 .CP0_LLAddr_shift = 4,
166 .SYNCI_Step = 32,
167 .CCRes = 2,
168 .CP0_Status_rw_bitmask = 0x1278FF17,
169 .SEGBITS = 32,
170 .PABITS = 32,
171 .insn_flags = CPU_MIPS32,
172 .mmu_type = MMU_TYPE_R4000,
173 },
174 {
175 .name = "4KEmR1",
176 .CP0_PRid = 0x00018500,
177 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
178 .CP0_Config1 = MIPS_CONFIG1 |
179 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
180 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
181 (1 << CP0C1_CA),
182 .CP0_Config2 = MIPS_CONFIG2,
183 .CP0_Config3 = MIPS_CONFIG3,
184 .CP0_LLAddr_rw_bitmask = 0,
185 .CP0_LLAddr_shift = 4,
186 .SYNCI_Step = 32,
187 .CCRes = 2,
188 .CP0_Status_rw_bitmask = 0x1258FF17,
189 .SEGBITS = 32,
190 .PABITS = 32,
191 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
192 .mmu_type = MMU_TYPE_FMT,
193 },
194 {
195 .name = "4KEc",
196 .CP0_PRid = 0x00019000,
197 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
198 (MMU_TYPE_R4000 << CP0C0_MT),
199 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
200 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
201 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
202 (0 << CP0C1_CA),
203 .CP0_Config2 = MIPS_CONFIG2,
204 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
205 .CP0_LLAddr_rw_bitmask = 0,
206 .CP0_LLAddr_shift = 4,
207 .SYNCI_Step = 32,
208 .CCRes = 2,
209 .CP0_Status_rw_bitmask = 0x1278FF17,
210 .SEGBITS = 32,
211 .PABITS = 32,
212 .insn_flags = CPU_MIPS32R2,
213 .mmu_type = MMU_TYPE_R4000,
214 },
215 {
216 .name = "4KEm",
217 .CP0_PRid = 0x00019100,
218 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
219 (MMU_TYPE_FMT << CP0C0_MT),
220 .CP0_Config1 = MIPS_CONFIG1 |
221 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
222 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
223 (1 << CP0C1_CA),
224 .CP0_Config2 = MIPS_CONFIG2,
225 .CP0_Config3 = MIPS_CONFIG3,
226 .CP0_LLAddr_rw_bitmask = 0,
227 .CP0_LLAddr_shift = 4,
228 .SYNCI_Step = 32,
229 .CCRes = 2,
230 .CP0_Status_rw_bitmask = 0x1258FF17,
231 .SEGBITS = 32,
232 .PABITS = 32,
233 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
234 .mmu_type = MMU_TYPE_FMT,
235 },
236 {
237 .name = "24Kc",
238 .CP0_PRid = 0x00019300,
239 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
240 (MMU_TYPE_R4000 << CP0C0_MT),
241 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
242 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
243 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
244 (1 << CP0C1_CA),
245 .CP0_Config2 = MIPS_CONFIG2,
246 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
247 .CP0_LLAddr_rw_bitmask = 0,
248 .CP0_LLAddr_shift = 4,
249 .SYNCI_Step = 32,
250 .CCRes = 2,
251 /* No DSP implemented. */
252 .CP0_Status_rw_bitmask = 0x1278FF1F,
253 .SEGBITS = 32,
254 .PABITS = 32,
255 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
256 .mmu_type = MMU_TYPE_R4000,
257 },
258 {
259 .name = "24KEc",
260 .CP0_PRid = 0x00019600,
261 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
262 (MMU_TYPE_R4000 << CP0C0_MT),
263 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
264 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
265 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
266 (1 << CP0C1_CA),
267 .CP0_Config2 = MIPS_CONFIG2,
268 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt),
269 .CP0_LLAddr_rw_bitmask = 0,
270 .CP0_LLAddr_shift = 4,
271 .SYNCI_Step = 32,
272 .CCRes = 2,
273 /* we have a DSP, but no FPU */
274 .CP0_Status_rw_bitmask = 0x1378FF1F,
275 .SEGBITS = 32,
276 .PABITS = 32,
277 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
278 .mmu_type = MMU_TYPE_R4000,
279 },
280 {
281 .name = "24Kf",
282 .CP0_PRid = 0x00019300,
283 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
284 (MMU_TYPE_R4000 << CP0C0_MT),
285 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
286 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
287 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
288 (1 << CP0C1_CA),
289 .CP0_Config2 = MIPS_CONFIG2,
290 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
291 .CP0_LLAddr_rw_bitmask = 0,
292 .CP0_LLAddr_shift = 4,
293 .SYNCI_Step = 32,
294 .CCRes = 2,
295 /* No DSP implemented. */
296 .CP0_Status_rw_bitmask = 0x3678FF1F,
297 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
298 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
299 .CP1_fcr31 = 0,
300 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
301 .SEGBITS = 32,
302 .PABITS = 32,
303 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
304 .mmu_type = MMU_TYPE_R4000,
305 },
306 {
307 .name = "34Kf",
308 .CP0_PRid = 0x00019500,
309 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
310 (MMU_TYPE_R4000 << CP0C0_MT),
311 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
312 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
313 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
314 (1 << CP0C1_CA),
315 .CP0_Config2 = MIPS_CONFIG2,
316 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
317 (1 << CP0C3_DSPP),
318 .CP0_LLAddr_rw_bitmask = 0,
319 .CP0_LLAddr_shift = 0,
320 .SYNCI_Step = 32,
321 .CCRes = 2,
322 .CP0_Status_rw_bitmask = 0x3778FF1F,
323 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
324 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
325 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
326 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
327 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
328 (0xff << CP0TCSt_TASID),
329 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
330 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
331 .CP1_fcr31 = 0,
332 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
333 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
334 .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
335 .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
336 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
337 .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
338 .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
339 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
340 .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
341 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
342 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
343 .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
344 .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
345 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
346 .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
347 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
348 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
349 .SEGBITS = 32,
350 .PABITS = 32,
351 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
352 .mmu_type = MMU_TYPE_R4000,
353 },
354 {
355 .name = "74Kf",
356 .CP0_PRid = 0x00019700,
357 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
358 (MMU_TYPE_R4000 << CP0C0_MT),
359 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
360 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
361 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
362 (1 << CP0C1_CA),
363 .CP0_Config2 = MIPS_CONFIG2,
364 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
365 (1 << CP0C3_VInt),
366 .CP0_LLAddr_rw_bitmask = 0,
367 .CP0_LLAddr_shift = 4,
368 .SYNCI_Step = 32,
369 .CCRes = 2,
370 .CP0_Status_rw_bitmask = 0x3778FF1F,
371 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
372 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
373 .CP1_fcr31 = 0,
374 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
375 .SEGBITS = 32,
376 .PABITS = 32,
377 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
378 .mmu_type = MMU_TYPE_R4000,
379 },
380 {
381 .name = "M14K",
382 .CP0_PRid = 0x00019b00,
383 /* Config1 implemented, fixed mapping MMU,
384 no virtual icache, uncached coherency. */
385 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) |
386 (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
387 .CP0_Config1 = MIPS_CONFIG1,
388 .CP0_Config2 = MIPS_CONFIG2,
389 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt),
390 .CP0_LLAddr_rw_bitmask = 0,
391 .CP0_LLAddr_shift = 4,
392 .SYNCI_Step = 32,
393 .CCRes = 2,
394 .CP0_Status_rw_bitmask = 0x1258FF17,
395 .SEGBITS = 32,
396 .PABITS = 32,
397 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
398 .mmu_type = MMU_TYPE_FMT,
399 },
400 {
401 .name = "M14Kc",
402 /* This is the TLB-based MMU core. */
403 .CP0_PRid = 0x00019c00,
404 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
405 (MMU_TYPE_R4000 << CP0C0_MT),
406 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
407 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
408 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
409 .CP0_Config2 = MIPS_CONFIG2,
410 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt),
411 .CP0_LLAddr_rw_bitmask = 0,
412 .CP0_LLAddr_shift = 4,
413 .SYNCI_Step = 32,
414 .CCRes = 2,
415 .CP0_Status_rw_bitmask = 0x1278FF17,
416 .SEGBITS = 32,
417 .PABITS = 32,
418 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
419 .mmu_type = MMU_TYPE_R4000,
420 },
421 {
422 /* FIXME:
423 * Config3: CMGCR, SC, PW, VZ, CTXTC, CDMM, TL
424 * Config4: MMUExtDef
425 * Config5: EVA, MRP
426 * FIR(FCR0): Has2008
427 * */
428 .name = "P5600",
429 .CP0_PRid = 0x0001A800,
430 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
431 (MMU_TYPE_R4000 << CP0C0_MT),
432 .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
433 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
434 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
435 (1 << CP0C1_PC) | (1 << CP0C1_FP),
436 .CP0_Config2 = MIPS_CONFIG2,
437 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
438 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
439 (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
440 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
441 (0x1c << CP0C4_KScrExist),
442 .CP0_Config4_rw_bitmask = 0,
443 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB) |
444 (1 << CP0C5_MRP),
445 .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
446 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
447 (1 << CP0C5_FRE) | (1 << CP0C5_UFR),
448 .CP0_LLAddr_rw_bitmask = 0,
449 .CP0_LLAddr_shift = 0,
450 .SYNCI_Step = 32,
451 .CCRes = 2,
452 .CP0_Status_rw_bitmask = 0x3C68FF1F,
453 .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
454 (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
455 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) |
456 (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
457 (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
458 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
459 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
460 .SEGBITS = 32,
461 .PABITS = 40,
462 .insn_flags = CPU_MIPS32R5 | ASE_MSA,
463 .mmu_type = MMU_TYPE_R4000,
464 },
465 {
466 /* A generic CPU supporting MIPS32 Release 6 ISA.
467 FIXME: Support IEEE 754-2008 FP.
468 Eventually this should be replaced by a real CPU model. */
469 .name = "mips32r6-generic",
470 .CP0_PRid = 0x00010000,
471 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) |
472 (MMU_TYPE_R4000 << CP0C0_MT),
473 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
474 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
475 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
476 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
477 .CP0_Config2 = MIPS_CONFIG2,
478 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) |
479 (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) |
480 (1 << CP0C3_RXI) | (1U << CP0C3_M),
481 .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
482 (3 << CP0C4_IE) | (1U << CP0C4_M),
483 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
484 .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
485 (1 << CP0C5_UFE),
486 .CP0_LLAddr_rw_bitmask = 0,
487 .CP0_LLAddr_shift = 0,
488 .SYNCI_Step = 32,
489 .CCRes = 2,
490 .CP0_Status_rw_bitmask = 0x3058FF1F,
491 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
492 (1U << CP0PG_RIE),
493 .CP0_PageGrain_rw_bitmask = 0,
494 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
495 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
496 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
497 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
498 .CP1_fcr31_rw_bitmask = 0x0103FFFF,
499 .SEGBITS = 32,
500 .PABITS = 32,
501 .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
502 .mmu_type = MMU_TYPE_R4000,
503 },
504 #if defined(TARGET_MIPS64)
505 {
506 .name = "R4000",
507 .CP0_PRid = 0x00000400,
508 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
509 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
510 /* Note: Config1 is only used internally, the R4000 has only Config0. */
511 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
512 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
513 .CP0_LLAddr_shift = 4,
514 .SYNCI_Step = 16,
515 .CCRes = 2,
516 .CP0_Status_rw_bitmask = 0x3678FFFF,
517 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
518 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
519 .CP1_fcr31 = 0,
520 .CP1_fcr31_rw_bitmask = 0x0183FFFF,
521 .SEGBITS = 40,
522 .PABITS = 36,
523 .insn_flags = CPU_MIPS3,
524 .mmu_type = MMU_TYPE_R4000,
525 },
526 {
527 .name = "VR5432",
528 .CP0_PRid = 0x00005400,
529 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
530 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
531 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
532 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
533 .CP0_LLAddr_shift = 4,
534 .SYNCI_Step = 16,
535 .CCRes = 2,
536 .CP0_Status_rw_bitmask = 0x3678FFFF,
537 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
538 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
539 .CP1_fcr31 = 0,
540 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
541 .SEGBITS = 40,
542 .PABITS = 32,
543 .insn_flags = CPU_VR54XX,
544 .mmu_type = MMU_TYPE_R4000,
545 },
546 {
547 .name = "5Kc",
548 .CP0_PRid = 0x00018100,
549 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
550 (MMU_TYPE_R4000 << CP0C0_MT),
551 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
552 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
553 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
554 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
555 .CP0_Config2 = MIPS_CONFIG2,
556 .CP0_Config3 = MIPS_CONFIG3,
557 .CP0_LLAddr_rw_bitmask = 0,
558 .CP0_LLAddr_shift = 4,
559 .SYNCI_Step = 32,
560 .CCRes = 2,
561 .CP0_Status_rw_bitmask = 0x12F8FFFF,
562 .SEGBITS = 42,
563 .PABITS = 36,
564 .insn_flags = CPU_MIPS64,
565 .mmu_type = MMU_TYPE_R4000,
566 },
567 {
568 .name = "5Kf",
569 .CP0_PRid = 0x00018100,
570 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
571 (MMU_TYPE_R4000 << CP0C0_MT),
572 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
573 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
574 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
575 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
576 .CP0_Config2 = MIPS_CONFIG2,
577 .CP0_Config3 = MIPS_CONFIG3,
578 .CP0_LLAddr_rw_bitmask = 0,
579 .CP0_LLAddr_shift = 4,
580 .SYNCI_Step = 32,
581 .CCRes = 2,
582 .CP0_Status_rw_bitmask = 0x36F8FFFF,
583 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
584 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
585 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
586 .CP1_fcr31 = 0,
587 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
588 .SEGBITS = 42,
589 .PABITS = 36,
590 .insn_flags = CPU_MIPS64,
591 .mmu_type = MMU_TYPE_R4000,
592 },
593 {
594 .name = "20Kc",
595 /* We emulate a later version of the 20Kc, earlier ones had a broken
596 WAIT instruction. */
597 .CP0_PRid = 0x000182a0,
598 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
599 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
600 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
601 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
602 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
603 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
604 .CP0_Config2 = MIPS_CONFIG2,
605 .CP0_Config3 = MIPS_CONFIG3,
606 .CP0_LLAddr_rw_bitmask = 0,
607 .CP0_LLAddr_shift = 0,
608 .SYNCI_Step = 32,
609 .CCRes = 1,
610 .CP0_Status_rw_bitmask = 0x36FBFFFF,
611 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
612 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
613 (1 << FCR0_D) | (1 << FCR0_S) |
614 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
615 .CP1_fcr31 = 0,
616 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
617 .SEGBITS = 40,
618 .PABITS = 36,
619 .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
620 .mmu_type = MMU_TYPE_R4000,
621 },
622 {
623 /* A generic CPU providing MIPS64 Release 2 features.
624 FIXME: Eventually this should be replaced by a real CPU model. */
625 .name = "MIPS64R2-generic",
626 .CP0_PRid = 0x00010000,
627 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
628 (MMU_TYPE_R4000 << CP0C0_MT),
629 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
630 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
631 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
632 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
633 .CP0_Config2 = MIPS_CONFIG2,
634 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
635 .CP0_LLAddr_rw_bitmask = 0,
636 .CP0_LLAddr_shift = 0,
637 .SYNCI_Step = 32,
638 .CCRes = 2,
639 .CP0_Status_rw_bitmask = 0x36FBFFFF,
640 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
641 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
642 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
643 .CP1_fcr31 = 0,
644 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
645 .SEGBITS = 42,
646 .PABITS = 36,
647 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
648 .mmu_type = MMU_TYPE_R4000,
649 },
650 {
651 .name = "5KEc",
652 .CP0_PRid = 0x00018900,
653 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
654 (MMU_TYPE_R4000 << CP0C0_MT),
655 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
656 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
657 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
658 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
659 .CP0_Config2 = MIPS_CONFIG2,
660 .CP0_Config3 = MIPS_CONFIG3,
661 .CP0_LLAddr_rw_bitmask = 0,
662 .CP0_LLAddr_shift = 4,
663 .SYNCI_Step = 32,
664 .CCRes = 2,
665 .CP0_Status_rw_bitmask = 0x12F8FFFF,
666 .SEGBITS = 42,
667 .PABITS = 36,
668 .insn_flags = CPU_MIPS64R2,
669 .mmu_type = MMU_TYPE_R4000,
670 },
671 {
672 .name = "5KEf",
673 .CP0_PRid = 0x00018900,
674 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
675 (MMU_TYPE_R4000 << CP0C0_MT),
676 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
677 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
678 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
679 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
680 .CP0_Config2 = MIPS_CONFIG2,
681 .CP0_Config3 = MIPS_CONFIG3,
682 .CP0_LLAddr_rw_bitmask = 0,
683 .CP0_LLAddr_shift = 4,
684 .SYNCI_Step = 32,
685 .CCRes = 2,
686 .CP0_Status_rw_bitmask = 0x36F8FFFF,
687 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
688 (1 << FCR0_D) | (1 << FCR0_S) |
689 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
690 .SEGBITS = 42,
691 .PABITS = 36,
692 .insn_flags = CPU_MIPS64R2,
693 .mmu_type = MMU_TYPE_R4000,
694 },
695 {
696 .name = "I6400",
697 .CP0_PRid = 0x1A900,
698 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
699 (MMU_TYPE_R4000 << CP0C0_MT),
700 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
701 (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
702 (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
703 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
704 .CP0_Config2 = MIPS_CONFIG2,
705 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
706 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
707 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
708 (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
709 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
710 (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
711 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
712 (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
713 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
714 (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
715 .CP0_LLAddr_rw_bitmask = 0,
716 .CP0_LLAddr_shift = 0,
717 .SYNCI_Step = 32,
718 .CCRes = 2,
719 .CP0_Status_rw_bitmask = 0x30D8FFFF,
720 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
721 (1U << CP0PG_RIE),
722 .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
723 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
724 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
725 (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
726 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
727 .CP1_fcr31_rw_bitmask = 0x0103FFFF,
728 .MSAIR = 0x03 << MSAIR_ProcID,
729 .SEGBITS = 48,
730 .PABITS = 48,
731 .insn_flags = CPU_MIPS64R6 | ASE_MSA,
732 .mmu_type = MMU_TYPE_R4000,
733 },
734 {
735 .name = "Loongson-2E",
736 .CP0_PRid = 0x6302,
737 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
738 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
739 (0x1<<5) | (0x1<<4) | (0x1<<1),
740 /* Note: Config1 is only used internally,
741 Loongson-2E has only Config0. */
742 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
743 .SYNCI_Step = 16,
744 .CCRes = 2,
745 .CP0_Status_rw_bitmask = 0x35D0FFFF,
746 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
747 .CP1_fcr31 = 0,
748 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
749 .SEGBITS = 40,
750 .PABITS = 40,
751 .insn_flags = CPU_LOONGSON2E,
752 .mmu_type = MMU_TYPE_R4000,
753 },
754 {
755 .name = "Loongson-2F",
756 .CP0_PRid = 0x6303,
757 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
758 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
759 (0x1<<5) | (0x1<<4) | (0x1<<1),
760 /* Note: Config1 is only used internally,
761 Loongson-2F has only Config0. */
762 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
763 .SYNCI_Step = 16,
764 .CCRes = 2,
765 .CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */
766 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
767 .CP1_fcr31 = 0,
768 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
769 .SEGBITS = 40,
770 .PABITS = 40,
771 .insn_flags = CPU_LOONGSON2F,
772 .mmu_type = MMU_TYPE_R4000,
773 },
774 {
775 /* A generic CPU providing MIPS64 ASE DSP 2 features.
776 FIXME: Eventually this should be replaced by a real CPU model. */
777 .name = "mips64dspr2",
778 .CP0_PRid = 0x00010000,
779 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
780 (MMU_TYPE_R4000 << CP0C0_MT),
781 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
782 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
783 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
784 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
785 .CP0_Config2 = MIPS_CONFIG2,
786 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
787 (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
788 .CP0_LLAddr_rw_bitmask = 0,
789 .CP0_LLAddr_shift = 0,
790 .SYNCI_Step = 32,
791 .CCRes = 2,
792 .CP0_Status_rw_bitmask = 0x37FBFFFF,
793 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
794 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
795 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
796 .CP1_fcr31 = 0,
797 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
798 .SEGBITS = 42,
799 .PABITS = 36,
800 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
801 .mmu_type = MMU_TYPE_R4000,
802 },
803
804 #endif
805 };
806
807 static const mips_def_t *cpu_mips_find_by_name (const char *name)
808 {
809 int i;
810
811 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
812 if (strcasecmp(name, mips_defs[i].name) == 0) {
813 return &mips_defs[i];
814 }
815 }
816 return NULL;
817 }
818
819 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
820 {
821 int i;
822
823 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
824 (*cpu_fprintf)(f, "MIPS '%s'\n",
825 mips_defs[i].name);
826 }
827 }
828
829 #ifndef CONFIG_USER_ONLY
830 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
831 {
832 env->tlb->nb_tlb = 1;
833 env->tlb->map_address = &no_mmu_map_address;
834 }
835
836 static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
837 {
838 env->tlb->nb_tlb = 1;
839 env->tlb->map_address = &fixed_mmu_map_address;
840 }
841
842 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
843 {
844 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
845 env->tlb->map_address = &r4k_map_address;
846 env->tlb->helper_tlbwi = r4k_helper_tlbwi;
847 env->tlb->helper_tlbwr = r4k_helper_tlbwr;
848 env->tlb->helper_tlbp = r4k_helper_tlbp;
849 env->tlb->helper_tlbr = r4k_helper_tlbr;
850 env->tlb->helper_tlbinv = r4k_helper_tlbinv;
851 env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
852 }
853
854 static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
855 {
856 MIPSCPU *cpu = mips_env_get_cpu(env);
857
858 env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
859
860 switch (def->mmu_type) {
861 case MMU_TYPE_NONE:
862 no_mmu_init(env, def);
863 break;
864 case MMU_TYPE_R4000:
865 r4k_mmu_init(env, def);
866 break;
867 case MMU_TYPE_FMT:
868 fixed_mmu_init(env, def);
869 break;
870 case MMU_TYPE_R3000:
871 case MMU_TYPE_R6000:
872 case MMU_TYPE_R8000:
873 default:
874 cpu_abort(CPU(cpu), "MMU type not supported\n");
875 }
876 }
877 #endif /* CONFIG_USER_ONLY */
878
879 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
880 {
881 int i;
882
883 for (i = 0; i < MIPS_FPU_MAX; i++)
884 env->fpus[i].fcr0 = def->CP1_fcr0;
885
886 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
887 }
888
889 static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
890 {
891 env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
892
893 /* MVPConf1 implemented, TLB sharable, no gating storage support,
894 programmable cache partitioning implemented, number of allocatable
895 and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
896 implemented, 5 TCs implemented. */
897 env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
898 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
899 // TODO: actually do 2 VPEs.
900 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
901 // (0x04 << CP0MVPC0_PTC);
902 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
903 (0x00 << CP0MVPC0_PTC);
904 #if !defined(CONFIG_USER_ONLY)
905 /* Usermode has no TLB support */
906 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
907 #endif
908
909 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
910 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
911 env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
912 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
913 (0x1 << CP0MVPC1_PCP1);
914 }
915
916 static void msa_reset(CPUMIPSState *env)
917 {
918 #ifdef CONFIG_USER_ONLY
919 /* MSA access enabled */
920 env->CP0_Config5 |= 1 << CP0C5_MSAEn;
921 env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
922 #endif
923
924 /* MSA CSR:
925 - non-signaling floating point exception mode off (NX bit is 0)
926 - Cause, Enables, and Flags are all 0
927 - round to nearest / ties to even (RM bits are 0) */
928 env->active_tc.msacsr = 0;
929
930 restore_msa_fp_status(env);
931
932 /* tininess detected after rounding.*/
933 set_float_detect_tininess(float_tininess_after_rounding,
934 &env->active_tc.msa_fp_status);
935
936 /* clear float_status exception flags */
937 set_float_exception_flags(0, &env->active_tc.msa_fp_status);
938
939 /* clear float_status nan mode */
940 set_default_nan_mode(0, &env->active_tc.msa_fp_status);
941
942 /* set proper signanling bit meaning ("1" means "quiet") */
943 set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
944 }
AR7 emulation for QEMU