| blob | c5ae5bb9512d0ef00546972546724575386cb564 |
1 /*
2 * bcm2708 aka bcm2835/2836 aka Raspberry Pi/Pi2 SoC platform defines
3 *
4 <<<<<<< HEAD
5 * These definitions are derived from those in Linux at
6 * arch/arm/mach-{bcm2708,bcm2709}/include/mach/platform.h
7 * where they carry the following notice:
8 */
10 /*
11 * arch/arm/mach-bcm2708/include/mach/platform.h
12 =======
13 * These definitions are derived from those in Raspbian Linux at
14 * arch/arm/mach-{bcm2708,bcm2709}/include/mach/platform.h
15 * where they carry the following notice:
16 >>>>>>> upstreaming-raspi
17 *
18 * Copyright (C) 2010 Broadcom
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 */
35 <<<<<<< HEAD
36 /* Peripheral base address on the VC (GPU) system bus */
37 #define BCM2835_VC_PERI_BASE 0x7e000000
39 /* Peripheral base addresses seen by the CPU: Pi1 and Pi2 differ */
40 #define BCM2835_PERI_BASE 0x20000000
41 #define BCM2836_PERI_BASE 0x3F000000
43 /* "QA7" (Pi2) interrupt controller and mailboxes etc. */
44 #define BCM2836_CONTROL_BASE 0x40000000
46 =======
47 >>>>>>> upstreaming-raspi
48 #define MCORE_OFFSET 0x0000 /* Fake frame buffer device
49 * (the multicore sync block) */
50 #define IC0_OFFSET 0x2000
51 #define ST_OFFSET 0x3000 /* System Timer */
52 #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */
53 #define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
54 #define ARM_OFFSET 0xB000 /* BCM2708 ARM control block */
55 #define ARMCTRL_OFFSET (ARM_OFFSET + 0x000)
56 #define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */
57 #define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */
58 #define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores
59 * Doorbells & Mailboxes */
60 #define PM_OFFSET 0x100000 /* Power Management, Reset controller
61 * and Watchdog registers */
62 <<<<<<< HEAD
63 #define PCM_CLOCK_OFFSET 0x101098 /* PCM Clock */
64 #define RNG_OFFSET 0x104000 /* Hardware RNG */
65 #define GPIO_OFFSET 0x200000 /* GPIO */
66 #define UART0_OFFSET 0x201000 /* Uart 0 */
67 #define MMCI0_OFFSET 0x202000 /* MMC interface */
68 #define I2S_OFFSET 0x203000 /* I2S */
69 #define SPI0_OFFSET 0x204000 /* SPI0 */
70 #define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */
71 #define UART1_OFFSET 0x215000 /* Uart 1 */
72 #define EMMC_OFFSET 0x300000 /* eMMC interface */
73 #define SMI_OFFSET 0x600000 /* SMI */
74 =======
75 #define PCM_CLOCK_OFFSET 0x101098
76 #define RNG_OFFSET 0x104000
77 #define GPIO_OFFSET 0x200000
78 #define UART0_OFFSET 0x201000
79 #define MMCI0_OFFSET 0x202000
80 #define I2S_OFFSET 0x203000
81 #define SPI0_OFFSET 0x204000
82 #define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */
83 #define UART1_OFFSET 0x215000
84 #define EMMC_OFFSET 0x300000
85 #define SMI_OFFSET 0x600000
86 >>>>>>> upstreaming-raspi
87 #define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */
88 #define USB_OFFSET 0x980000 /* DTC_OTG USB controller */
89 #define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */
91 <<<<<<< HEAD
92 /*
93 * Interrupt assignments
94 */
96 #define ARM_IRQ1_BASE 0
97 #define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0)
98 #define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1)
99 #define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2)
100 #define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3)
101 #define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4)
102 #define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5)
103 #define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6)
104 #define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7)
105 #define INTERRUPT_ISP (ARM_IRQ1_BASE + 8)
106 #define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9)
107 #define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10)
108 #define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11)
109 #define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12)
110 #define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13)
111 #define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14)
112 #define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15)
113 #define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16)
114 #define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17)
115 #define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18)
116 #define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19)
117 #define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20)
118 #define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21)
119 #define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22)
120 #define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23)
121 #define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24)
122 #define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25)
123 #define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26)
124 #define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27)
125 #define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28)
126 #define INTERRUPT_AUX (ARM_IRQ1_BASE + 29)
127 #define INTERRUPT_ARM (ARM_IRQ1_BASE + 30)
128 #define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31)
130 #define ARM_IRQ2_BASE 32
131 #define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0)
132 #define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1)
133 #define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2)
134 #define INTERRUPT_SDC (ARM_IRQ2_BASE + 3)
135 #define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4)
136 #define INTERRUPT_AVE (ARM_IRQ2_BASE + 5)
137 #define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6)
138 #define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7)
139 #define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8)
140 #define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9)
141 #define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10)
142 #define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11)
143 #define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12)
144 #define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13)
145 #define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14)
146 #define INTERRUPT_CPR (ARM_IRQ2_BASE + 15)
147 #define INTERRUPT_SMI (ARM_IRQ2_BASE + 16)
148 #define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17)
149 #define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18)
150 #define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19)
151 #define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20)
152 #define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21)
153 #define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22)
154 #define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23)
155 #define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24)
156 #define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25)
157 #define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26)
158 #define INTERRUPT_VEC (ARM_IRQ2_BASE + 27)
159 #define INTERRUPT_CPG (ARM_IRQ2_BASE + 28)
160 #define INTERRUPT_RNG (ARM_IRQ2_BASE + 29)
161 #define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30)
162 #define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31)
164 #define ARM_IRQ0_BASE 64
165 #define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0)
166 #define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1)
167 #define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2)
168 #define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3)
169 #define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4)
170 #define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5)
171 #define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6)
172 #define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7)
173 #define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8)
174 #define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9)
175 #define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10)
176 #define INTERRUPT_USB (ARM_IRQ0_BASE + 11)
177 #define INTERRUPT_3D (ARM_IRQ0_BASE + 12)
178 #define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13)
179 #define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14)
180 #define INTERRUPT_I2C (ARM_IRQ0_BASE + 15)
181 #define INTERRUPT_SPI (ARM_IRQ0_BASE + 16)
182 #define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17)
183 #define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18)
184 #define INTERRUPT_UART (ARM_IRQ0_BASE + 19)
185 #define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20)
186 =======
187 /* GPU interrupts */
188 #define INTERRUPT_TIMER0 0
189 #define INTERRUPT_TIMER1 1
190 #define INTERRUPT_TIMER2 2
191 #define INTERRUPT_TIMER3 3
192 #define INTERRUPT_CODEC0 4
193 #define INTERRUPT_CODEC1 5
194 #define INTERRUPT_CODEC2 6
195 #define INTERRUPT_JPEG 7
196 #define INTERRUPT_ISP 8
197 #define INTERRUPT_USB 9
198 #define INTERRUPT_3D 10
199 #define INTERRUPT_TRANSPOSER 11
200 #define INTERRUPT_MULTICORESYNC0 12
201 #define INTERRUPT_MULTICORESYNC1 13
202 #define INTERRUPT_MULTICORESYNC2 14
203 #define INTERRUPT_MULTICORESYNC3 15
204 #define INTERRUPT_DMA0 16
205 #define INTERRUPT_DMA1 17
206 #define INTERRUPT_DMA2 18
207 #define INTERRUPT_DMA3 19
208 #define INTERRUPT_DMA4 20
209 #define INTERRUPT_DMA5 21
210 #define INTERRUPT_DMA6 22
211 #define INTERRUPT_DMA7 23
212 #define INTERRUPT_DMA8 24
213 #define INTERRUPT_DMA9 25
214 #define INTERRUPT_DMA10 26
215 #define INTERRUPT_DMA11 27
216 #define INTERRUPT_DMA12 28
217 #define INTERRUPT_AUX 29
218 #define INTERRUPT_ARM 30
219 #define INTERRUPT_VPUDMA 31
220 #define INTERRUPT_HOSTPORT 32
221 #define INTERRUPT_VIDEOSCALER 33
222 #define INTERRUPT_CCP2TX 34
223 #define INTERRUPT_SDC 35
224 #define INTERRUPT_DSI0 36
225 #define INTERRUPT_AVE 37
226 #define INTERRUPT_CAM0 38
227 #define INTERRUPT_CAM1 39
228 #define INTERRUPT_HDMI0 40
229 #define INTERRUPT_HDMI1 41
230 #define INTERRUPT_PIXELVALVE1 42
231 #define INTERRUPT_I2CSPISLV 43
232 #define INTERRUPT_DSI1 44
233 #define INTERRUPT_PWA0 45
234 #define INTERRUPT_PWA1 46
235 #define INTERRUPT_CPR 47
236 #define INTERRUPT_SMI 48
237 #define INTERRUPT_GPIO0 49
238 #define INTERRUPT_GPIO1 50
239 #define INTERRUPT_GPIO2 51
240 #define INTERRUPT_GPIO3 52
241 #define INTERRUPT_I2C 53
242 #define INTERRUPT_SPI 54
243 #define INTERRUPT_I2SPCM 55
244 #define INTERRUPT_SDIO 56
245 #define INTERRUPT_UART 57
246 #define INTERRUPT_SLIMBUS 58
247 #define INTERRUPT_VEC 59
248 #define INTERRUPT_CPG 60
249 #define INTERRUPT_RNG 61
250 #define INTERRUPT_ARASANSDIO 62
251 #define INTERRUPT_AVSPMON 63
253 /* ARM CPU IRQs use a private number space */
254 #define INTERRUPT_ARM_TIMER 0
255 #define INTERRUPT_ARM_MAILBOX 1
256 #define INTERRUPT_ARM_DOORBELL_0 2
257 #define INTERRUPT_ARM_DOORBELL_1 3
258 #define INTERRUPT_VPU0_HALTED 4
259 #define INTERRUPT_VPU1_HALTED 5
260 #define INTERRUPT_ILLEGAL_TYPE0 6
261 #define INTERRUPT_ILLEGAL_TYPE1 7
262 >>>>>>> upstreaming-raspi