Merge remote-tracking branch 'remotes/riku/tags/pull-linux-user-20150323' into staging
[qemu/ar7.git] / target-m68k / cpu.h
blob5f165da90dc9250084e1d57789f60c644ea2cdb9
1 /*
2 * m68k virtual CPU header
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #ifndef CPU_M68K_H
21 #define CPU_M68K_H
23 #define TARGET_LONG_BITS 32
25 #define CPUArchState struct CPUM68KState
27 #include "config.h"
28 #include "qemu-common.h"
29 #include "exec/cpu-defs.h"
31 #include "fpu/softfloat.h"
33 #define MAX_QREGS 32
35 #define ELF_MACHINE EM_68K
37 #define EXCP_ACCESS 2 /* Access (MMU) error. */
38 #define EXCP_ADDRESS 3 /* Address error. */
39 #define EXCP_ILLEGAL 4 /* Illegal instruction. */
40 #define EXCP_DIV0 5 /* Divide by zero */
41 #define EXCP_PRIVILEGE 8 /* Privilege violation. */
42 #define EXCP_TRACE 9
43 #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */
44 #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */
45 #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */
46 #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */
47 #define EXCP_FORMAT 14 /* RTE format error. */
48 #define EXCP_UNINITIALIZED 15
49 #define EXCP_TRAP0 32 /* User trap #0. */
50 #define EXCP_TRAP15 47 /* User trap #15. */
51 #define EXCP_UNSUPPORTED 61
52 #define EXCP_ICE 13
54 #define EXCP_RTE 0x100
55 #define EXCP_HALT_INSN 0x101
57 #define NB_MMU_MODES 2
59 typedef struct CPUM68KState {
60 uint32_t dregs[8];
61 uint32_t aregs[8];
62 uint32_t pc;
63 uint32_t sr;
65 /* SSP and USP. The current_sp is stored in aregs[7], the other here. */
66 int current_sp;
67 uint32_t sp[2];
69 /* Condition flags. */
70 uint32_t cc_op;
71 uint32_t cc_dest;
72 uint32_t cc_src;
73 uint32_t cc_x;
75 float64 fregs[8];
76 float64 fp_result;
77 uint32_t fpcr;
78 uint32_t fpsr;
79 float_status fp_status;
81 uint64_t mactmp;
82 /* EMAC Hardware deals with 48-bit values composed of one 32-bit and
83 two 8-bit parts. We store a single 64-bit value and
84 rearrange/extend this when changing modes. */
85 uint64_t macc[4];
86 uint32_t macsr;
87 uint32_t mac_mask;
89 /* Temporary storage for DIV helpers. */
90 uint32_t div1;
91 uint32_t div2;
93 /* MMU status. */
94 struct {
95 uint32_t ar;
96 } mmu;
98 /* Control registers. */
99 uint32_t vbr;
100 uint32_t mbar;
101 uint32_t rambar0;
102 uint32_t cacr;
104 int pending_vector;
105 int pending_level;
107 uint32_t qregs[MAX_QREGS];
109 CPU_COMMON
111 /* Fields from here on are preserved across CPU reset. */
112 uint32_t features;
113 } CPUM68KState;
115 #include "cpu-qom.h"
117 void m68k_tcg_init(void);
118 void m68k_cpu_init_gdb(M68kCPU *cpu);
119 M68kCPU *cpu_m68k_init(const char *cpu_model);
120 int cpu_m68k_exec(CPUM68KState *s);
121 /* you can call this signal handler from your SIGBUS and SIGSEGV
122 signal handlers to inform the virtual CPU of exceptions. non zero
123 is returned if the signal was handled by the virtual CPU. */
124 int cpu_m68k_signal_handler(int host_signum, void *pinfo,
125 void *puc);
126 void cpu_m68k_flush_flags(CPUM68KState *, int);
128 enum {
129 CC_OP_DYNAMIC, /* Use env->cc_op */
130 CC_OP_FLAGS, /* CC_DEST = CVZN, CC_SRC = unused */
131 CC_OP_LOGIC, /* CC_DEST = result, CC_SRC = unused */
132 CC_OP_ADD, /* CC_DEST = result, CC_SRC = source */
133 CC_OP_SUB, /* CC_DEST = result, CC_SRC = source */
134 CC_OP_CMPB, /* CC_DEST = result, CC_SRC = source */
135 CC_OP_CMPW, /* CC_DEST = result, CC_SRC = source */
136 CC_OP_ADDX, /* CC_DEST = result, CC_SRC = source */
137 CC_OP_SUBX, /* CC_DEST = result, CC_SRC = source */
138 CC_OP_SHIFT, /* CC_DEST = result, CC_SRC = carry */
141 #define CCF_C 0x01
142 #define CCF_V 0x02
143 #define CCF_Z 0x04
144 #define CCF_N 0x08
145 #define CCF_X 0x10
147 #define SR_I_SHIFT 8
148 #define SR_I 0x0700
149 #define SR_M 0x1000
150 #define SR_S 0x2000
151 #define SR_T 0x8000
153 #define M68K_SSP 0
154 #define M68K_USP 1
156 /* CACR fields are implementation defined, but some bits are common. */
157 #define M68K_CACR_EUSP 0x10
159 #define MACSR_PAV0 0x100
160 #define MACSR_OMC 0x080
161 #define MACSR_SU 0x040
162 #define MACSR_FI 0x020
163 #define MACSR_RT 0x010
164 #define MACSR_N 0x008
165 #define MACSR_Z 0x004
166 #define MACSR_V 0x002
167 #define MACSR_EV 0x001
169 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
170 void m68k_set_macsr(CPUM68KState *env, uint32_t val);
171 void m68k_switch_sp(CPUM68KState *env);
173 #define M68K_FPCR_PREC (1 << 6)
175 void do_m68k_semihosting(CPUM68KState *env, int nr);
177 /* There are 4 ColdFire core ISA revisions: A, A+, B and C.
178 Each feature covers the subset of instructions common to the
179 ISA revisions mentioned. */
181 enum m68k_features {
182 M68K_FEATURE_CF_ISA_A,
183 M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */
184 M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
185 M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */
186 M68K_FEATURE_CF_FPU,
187 M68K_FEATURE_CF_MAC,
188 M68K_FEATURE_CF_EMAC,
189 M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */
190 M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */
191 M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */
192 M68K_FEATURE_WORD_INDEX /* word sized address index registers. */
195 static inline int m68k_feature(CPUM68KState *env, int feature)
197 return (env->features & (1u << feature)) != 0;
200 void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf);
202 void register_m68k_insns (CPUM68KState *env);
204 #ifdef CONFIG_USER_ONLY
205 /* Linux uses 8k pages. */
206 #define TARGET_PAGE_BITS 13
207 #else
208 /* Smallest TLB entry size is 1k. */
209 #define TARGET_PAGE_BITS 10
210 #endif
212 #define TARGET_PHYS_ADDR_SPACE_BITS 32
213 #define TARGET_VIRT_ADDR_SPACE_BITS 32
215 #define cpu_init(cpu_model) CPU(cpu_m68k_init(cpu_model))
217 #define cpu_exec cpu_m68k_exec
218 #define cpu_gen_code cpu_m68k_gen_code
219 #define cpu_signal_handler cpu_m68k_signal_handler
220 #define cpu_list m68k_cpu_list
222 /* MMU modes definitions */
223 #define MMU_MODE0_SUFFIX _kernel
224 #define MMU_MODE1_SUFFIX _user
225 #define MMU_USER_IDX 1
226 static inline int cpu_mmu_index (CPUM68KState *env)
228 return (env->sr & SR_S) == 0 ? 1 : 0;
231 int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
232 int mmu_idx);
234 #include "exec/cpu-all.h"
236 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
237 target_ulong *cs_base, int *flags)
239 *pc = env->pc;
240 *cs_base = 0;
241 *flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
242 | (env->sr & SR_S) /* Bit 13 */
243 | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
246 #include "exec/exec-all.h"
248 #endif