2 * QEMU IDE Emulation: MacIO support.
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "hw/ppc/mac.h"
27 #include "hw/ppc/mac_dbdma.h"
28 #include "sysemu/block-backend.h"
29 #include "sysemu/dma.h"
31 #include <hw/ide/internal.h>
34 // #define DEBUG_MACIO
37 static const int debug_macio
= 1;
39 static const int debug_macio
= 0;
42 #define MACIO_DPRINTF(fmt, ...) do { \
44 printf(fmt , ## __VA_ARGS__); \
49 /***********************************************************/
50 /* MacIO based PowerPC IDE */
52 #define MACIO_PAGE_SIZE 4096
55 * Unaligned DMA read/write access functions required for OS X/Darwin which
56 * don't perform DMA transactions on sector boundaries. These functions are
57 * modelled on bdrv_co_do_preadv()/bdrv_co_do_pwritev() and so should be
58 * easy to remove if the unaligned block APIs are ever exposed.
61 static void pmac_dma_read(BlockBackend
*blk
,
62 int64_t offset
, unsigned int bytes
,
63 void (*cb
)(void *opaque
, int ret
), void *opaque
)
65 DBDMA_io
*io
= opaque
;
66 MACIOIDEState
*m
= io
->opaque
;
67 IDEState
*s
= idebus_active_if(&m
->bus
);
68 dma_addr_t dma_addr
, dma_len
;
72 uint64_t align
= BDRV_SECTOR_SIZE
;
73 size_t head_bytes
, tail_bytes
;
75 qemu_iovec_destroy(&io
->iov
);
76 qemu_iovec_init(&io
->iov
, io
->len
/ MACIO_PAGE_SIZE
+ 1);
78 sector_num
= (offset
>> 9);
79 nsector
= (io
->len
>> 9);
81 MACIO_DPRINTF("--- DMA read transfer (0x%" HWADDR_PRIx
",0x%x): "
82 "sector_num: %" PRId64
", nsector: %d\n", io
->addr
, io
->len
,
87 mem
= dma_memory_map(&address_space_memory
, dma_addr
, &dma_len
,
88 DMA_DIRECTION_FROM_DEVICE
);
90 if (offset
& (align
- 1)) {
91 head_bytes
= offset
& (align
- 1);
93 MACIO_DPRINTF("--- DMA unaligned head: sector %" PRId64
", "
94 "discarding %zu bytes\n", sector_num
, head_bytes
);
96 qemu_iovec_add(&io
->iov
, &io
->head_remainder
, head_bytes
);
98 bytes
+= offset
& (align
- 1);
99 offset
= offset
& ~(align
- 1);
102 qemu_iovec_add(&io
->iov
, mem
, io
->len
);
104 if ((offset
+ bytes
) & (align
- 1)) {
105 tail_bytes
= (offset
+ bytes
) & (align
- 1);
107 MACIO_DPRINTF("--- DMA unaligned tail: sector %" PRId64
", "
108 "discarding bytes %zu\n", sector_num
, tail_bytes
);
110 qemu_iovec_add(&io
->iov
, &io
->tail_remainder
, align
- tail_bytes
);
111 bytes
= ROUND_UP(bytes
, align
);
114 s
->io_buffer_size
-= io
->len
;
115 s
->io_buffer_index
+= io
->len
;
119 MACIO_DPRINTF("--- Block read transfer - sector_num: %" PRIx64
" "
120 "nsector: %x\n", (offset
>> 9), (bytes
>> 9));
122 m
->aiocb
= blk_aio_readv(blk
, (offset
>> 9), &io
->iov
, (bytes
>> 9),
126 static void pmac_dma_write(BlockBackend
*blk
,
127 int64_t offset
, int bytes
,
128 void (*cb
)(void *opaque
, int ret
), void *opaque
)
130 DBDMA_io
*io
= opaque
;
131 MACIOIDEState
*m
= io
->opaque
;
132 IDEState
*s
= idebus_active_if(&m
->bus
);
133 dma_addr_t dma_addr
, dma_len
;
137 uint64_t align
= BDRV_SECTOR_SIZE
;
138 size_t head_bytes
, tail_bytes
;
139 bool unaligned_head
= false, unaligned_tail
= false;
141 qemu_iovec_destroy(&io
->iov
);
142 qemu_iovec_init(&io
->iov
, io
->len
/ MACIO_PAGE_SIZE
+ 1);
144 sector_num
= (offset
>> 9);
145 nsector
= (io
->len
>> 9);
147 MACIO_DPRINTF("--- DMA write transfer (0x%" HWADDR_PRIx
",0x%x): "
148 "sector_num: %" PRId64
", nsector: %d\n", io
->addr
, io
->len
,
149 sector_num
, nsector
);
153 mem
= dma_memory_map(&address_space_memory
, dma_addr
, &dma_len
,
154 DMA_DIRECTION_TO_DEVICE
);
156 if (offset
& (align
- 1)) {
157 head_bytes
= offset
& (align
- 1);
158 sector_num
= ((offset
& ~(align
- 1)) >> 9);
160 MACIO_DPRINTF("--- DMA unaligned head: pre-reading head sector %"
161 PRId64
"\n", sector_num
);
163 blk_pread(s
->blk
, (sector_num
<< 9), &io
->head_remainder
, align
);
165 qemu_iovec_add(&io
->iov
, &io
->head_remainder
, head_bytes
);
166 qemu_iovec_add(&io
->iov
, mem
, io
->len
);
168 bytes
+= offset
& (align
- 1);
169 offset
= offset
& ~(align
- 1);
171 unaligned_head
= true;
174 if ((offset
+ bytes
) & (align
- 1)) {
175 tail_bytes
= (offset
+ bytes
) & (align
- 1);
176 sector_num
= (((offset
+ bytes
) & ~(align
- 1)) >> 9);
178 MACIO_DPRINTF("--- DMA unaligned tail: pre-reading tail sector %"
179 PRId64
"\n", sector_num
);
181 blk_pread(s
->blk
, (sector_num
<< 9), &io
->tail_remainder
, align
);
183 if (!unaligned_head
) {
184 qemu_iovec_add(&io
->iov
, mem
, io
->len
);
187 qemu_iovec_add(&io
->iov
, &io
->tail_remainder
+ tail_bytes
,
190 bytes
= ROUND_UP(bytes
, align
);
192 unaligned_tail
= true;
195 if (!unaligned_head
&& !unaligned_tail
) {
196 qemu_iovec_add(&io
->iov
, mem
, io
->len
);
199 s
->io_buffer_size
-= io
->len
;
200 s
->io_buffer_index
+= io
->len
;
204 MACIO_DPRINTF("--- Block write transfer - sector_num: %" PRIx64
" "
205 "nsector: %x\n", (offset
>> 9), (bytes
>> 9));
207 m
->aiocb
= blk_aio_writev(blk
, (offset
>> 9), &io
->iov
, (bytes
>> 9),
211 static void pmac_ide_atapi_transfer_cb(void *opaque
, int ret
)
213 DBDMA_io
*io
= opaque
;
214 MACIOIDEState
*m
= io
->opaque
;
215 IDEState
*s
= idebus_active_if(&m
->bus
);
218 MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
221 MACIO_DPRINTF("DMA error: %d\n", ret
);
222 ide_atapi_io_error(s
, ret
);
226 if (!m
->dma_active
) {
227 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
228 s
->nsector
, io
->len
, s
->status
);
229 /* data not ready yet, wait for the channel to get restarted */
230 io
->processing
= false;
234 if (s
->io_buffer_size
<= 0) {
235 MACIO_DPRINTF("End of IDE transfer\n");
237 m
->dma_active
= false;
242 MACIO_DPRINTF("End of DMA transfer\n");
247 /* Non-block ATAPI transfer - just copy to RAM */
248 s
->io_buffer_size
= MIN(s
->io_buffer_size
, io
->len
);
249 cpu_physical_memory_write(io
->addr
, s
->io_buffer
, s
->io_buffer_size
);
251 m
->dma_active
= false;
255 /* Calculate current offset */
256 offset
= (int64_t)(s
->lba
<< 11) + s
->io_buffer_index
;
258 pmac_dma_read(s
->blk
, offset
, io
->len
, pmac_ide_atapi_transfer_cb
, io
);
262 block_acct_done(blk_get_stats(s
->blk
), &s
->acct
);
268 static void pmac_ide_transfer_cb(void *opaque
, int ret
)
270 DBDMA_io
*io
= opaque
;
271 MACIOIDEState
*m
= io
->opaque
;
272 IDEState
*s
= idebus_active_if(&m
->bus
);
275 MACIO_DPRINTF("pmac_ide_transfer_cb\n");
278 MACIO_DPRINTF("DMA error: %d\n", ret
);
284 if (!m
->dma_active
) {
285 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
286 s
->nsector
, io
->len
, s
->status
);
287 /* data not ready yet, wait for the channel to get restarted */
288 io
->processing
= false;
292 if (s
->io_buffer_size
<= 0) {
293 MACIO_DPRINTF("End of IDE transfer\n");
294 s
->status
= READY_STAT
| SEEK_STAT
;
296 m
->dma_active
= false;
301 MACIO_DPRINTF("End of DMA transfer\n");
305 /* Calculate number of sectors */
306 offset
= (ide_get_sector(s
) << 9) + s
->io_buffer_index
;
308 switch (s
->dma_cmd
) {
310 pmac_dma_read(s
->blk
, offset
, io
->len
, pmac_ide_transfer_cb
, io
);
313 pmac_dma_write(s
->blk
, offset
, io
->len
, pmac_ide_transfer_cb
, io
);
322 if (s
->dma_cmd
== IDE_DMA_READ
|| s
->dma_cmd
== IDE_DMA_WRITE
) {
323 block_acct_done(blk_get_stats(s
->blk
), &s
->acct
);
328 static void pmac_ide_transfer(DBDMA_io
*io
)
330 MACIOIDEState
*m
= io
->opaque
;
331 IDEState
*s
= idebus_active_if(&m
->bus
);
335 if (s
->drive_kind
== IDE_CD
) {
336 block_acct_start(blk_get_stats(s
->blk
), &s
->acct
, io
->len
,
339 pmac_ide_atapi_transfer_cb(io
, 0);
343 switch (s
->dma_cmd
) {
345 block_acct_start(blk_get_stats(s
->blk
), &s
->acct
, io
->len
,
349 block_acct_start(blk_get_stats(s
->blk
), &s
->acct
, io
->len
,
356 pmac_ide_transfer_cb(io
, 0);
359 static void pmac_ide_flush(DBDMA_io
*io
)
361 MACIOIDEState
*m
= io
->opaque
;
368 /* PowerMac IDE memory IO */
369 static void pmac_ide_writeb (void *opaque
,
370 hwaddr addr
, uint32_t val
)
372 MACIOIDEState
*d
= opaque
;
374 addr
= (addr
& 0xFFF) >> 4;
377 ide_ioport_write(&d
->bus
, addr
, val
);
381 ide_cmd_write(&d
->bus
, 0, val
);
388 static uint32_t pmac_ide_readb (void *opaque
,hwaddr addr
)
391 MACIOIDEState
*d
= opaque
;
393 addr
= (addr
& 0xFFF) >> 4;
396 retval
= ide_ioport_read(&d
->bus
, addr
);
400 retval
= ide_status_read(&d
->bus
, 0);
409 static void pmac_ide_writew (void *opaque
,
410 hwaddr addr
, uint32_t val
)
412 MACIOIDEState
*d
= opaque
;
414 addr
= (addr
& 0xFFF) >> 4;
417 ide_data_writew(&d
->bus
, 0, val
);
421 static uint32_t pmac_ide_readw (void *opaque
,hwaddr addr
)
424 MACIOIDEState
*d
= opaque
;
426 addr
= (addr
& 0xFFF) >> 4;
428 retval
= ide_data_readw(&d
->bus
, 0);
432 retval
= bswap16(retval
);
436 static void pmac_ide_writel (void *opaque
,
437 hwaddr addr
, uint32_t val
)
439 MACIOIDEState
*d
= opaque
;
441 addr
= (addr
& 0xFFF) >> 4;
444 ide_data_writel(&d
->bus
, 0, val
);
448 static uint32_t pmac_ide_readl (void *opaque
,hwaddr addr
)
451 MACIOIDEState
*d
= opaque
;
453 addr
= (addr
& 0xFFF) >> 4;
455 retval
= ide_data_readl(&d
->bus
, 0);
459 retval
= bswap32(retval
);
463 static const MemoryRegionOps pmac_ide_ops
= {
476 .endianness
= DEVICE_NATIVE_ENDIAN
,
479 static const VMStateDescription vmstate_pmac
= {
482 .minimum_version_id
= 0,
483 .fields
= (VMStateField
[]) {
484 VMSTATE_IDE_BUS(bus
, MACIOIDEState
),
485 VMSTATE_IDE_DRIVES(bus
.ifs
, MACIOIDEState
),
486 VMSTATE_END_OF_LIST()
490 static void macio_ide_reset(DeviceState
*dev
)
492 MACIOIDEState
*d
= MACIO_IDE(dev
);
494 ide_bus_reset(&d
->bus
);
497 static int ide_nop_int(IDEDMA
*dma
, int x
)
502 static int32_t ide_nop_int32(IDEDMA
*dma
, int x
)
507 static void ide_dbdma_start(IDEDMA
*dma
, IDEState
*s
,
508 BlockCompletionFunc
*cb
)
510 MACIOIDEState
*m
= container_of(dma
, MACIOIDEState
, dma
);
512 s
->io_buffer_index
= 0;
513 if (s
->drive_kind
== IDE_CD
) {
514 s
->io_buffer_size
= s
->packet_transfer_size
;
516 s
->io_buffer_size
= s
->nsector
* BDRV_SECTOR_SIZE
;
519 MACIO_DPRINTF("\n\n------------ IDE transfer\n");
520 MACIO_DPRINTF("buffer_size: %x buffer_index: %x\n",
521 s
->io_buffer_size
, s
->io_buffer_index
);
522 MACIO_DPRINTF("lba: %x size: %x\n", s
->lba
, s
->io_buffer_size
);
523 MACIO_DPRINTF("-------------------------\n");
525 m
->dma_active
= true;
526 DBDMA_kick(m
->dbdma
);
529 static const IDEDMAOps dbdma_ops
= {
530 .start_dma
= ide_dbdma_start
,
531 .prepare_buf
= ide_nop_int32
,
532 .rw_buf
= ide_nop_int
,
535 static void macio_ide_realizefn(DeviceState
*dev
, Error
**errp
)
537 MACIOIDEState
*s
= MACIO_IDE(dev
);
539 ide_init2(&s
->bus
, s
->irq
);
541 /* Register DMA callbacks */
542 s
->dma
.ops
= &dbdma_ops
;
543 s
->bus
.dma
= &s
->dma
;
546 static void macio_ide_initfn(Object
*obj
)
548 SysBusDevice
*d
= SYS_BUS_DEVICE(obj
);
549 MACIOIDEState
*s
= MACIO_IDE(obj
);
551 ide_bus_new(&s
->bus
, sizeof(s
->bus
), DEVICE(obj
), 0, 2);
552 memory_region_init_io(&s
->mem
, obj
, &pmac_ide_ops
, s
, "pmac-ide", 0x1000);
553 sysbus_init_mmio(d
, &s
->mem
);
554 sysbus_init_irq(d
, &s
->irq
);
555 sysbus_init_irq(d
, &s
->dma_irq
);
558 static void macio_ide_class_init(ObjectClass
*oc
, void *data
)
560 DeviceClass
*dc
= DEVICE_CLASS(oc
);
562 dc
->realize
= macio_ide_realizefn
;
563 dc
->reset
= macio_ide_reset
;
564 dc
->vmsd
= &vmstate_pmac
;
567 static const TypeInfo macio_ide_type_info
= {
568 .name
= TYPE_MACIO_IDE
,
569 .parent
= TYPE_SYS_BUS_DEVICE
,
570 .instance_size
= sizeof(MACIOIDEState
),
571 .instance_init
= macio_ide_initfn
,
572 .class_init
= macio_ide_class_init
,
575 static void macio_ide_register_types(void)
577 type_register_static(&macio_ide_type_info
);
580 /* hd_table must contain 2 block drivers */
581 void macio_ide_init_drives(MACIOIDEState
*s
, DriveInfo
**hd_table
)
585 for (i
= 0; i
< 2; i
++) {
587 ide_create_drive(&s
->bus
, i
, hd_table
[i
]);
592 void macio_ide_register_dma(MACIOIDEState
*s
, void *dbdma
, int channel
)
595 DBDMA_register_channel(dbdma
, channel
, s
->dma_irq
,
596 pmac_ide_transfer
, pmac_ide_flush
, s
);
599 type_init(macio_ide_register_types
)